1#![allow(improper_ctypes)]
9
10#[cfg(test)]
11use stdarch_test::assert_instr;
12
13use super::*;
14
15#[doc = "CRC32 single round checksum for bytes (8 bits)."]
16#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"]
17#[inline]
18#[target_feature(enable = "crc")]
19#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
20#[cfg_attr(test, assert_instr(crc32b))]
21#[cfg_attr(
22 target_arch = "arm",
23 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
24)]
25#[cfg_attr(
26 not(target_arch = "arm"),
27 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
28)]
29pub fn __crc32b(crc: u32, data: u8) -> u32 {
30 unsafe extern "unadjusted" {
31 #[cfg_attr(
32 any(target_arch = "aarch64", target_arch = "arm64ec"),
33 link_name = "llvm.aarch64.crc32b"
34 )]
35 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
36 fn ___crc32b(crc: u32, data: u32) -> u32;
37 }
38 unsafe { ___crc32b(crc, data as u32) }
39}
40#[doc = "CRC32-C single round checksum for bytes (8 bits)."]
41#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"]
42#[inline]
43#[target_feature(enable = "crc")]
44#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
45#[cfg_attr(test, assert_instr(crc32cb))]
46#[cfg_attr(
47 target_arch = "arm",
48 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
49)]
50#[cfg_attr(
51 not(target_arch = "arm"),
52 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
53)]
54pub fn __crc32cb(crc: u32, data: u8) -> u32 {
55 unsafe extern "unadjusted" {
56 #[cfg_attr(
57 any(target_arch = "aarch64", target_arch = "arm64ec"),
58 link_name = "llvm.aarch64.crc32cb"
59 )]
60 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
61 fn ___crc32cb(crc: u32, data: u32) -> u32;
62 }
63 unsafe { ___crc32cb(crc, data as u32) }
64}
65#[doc = "CRC32-C single round checksum for quad words (64 bits)."]
66#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
67#[inline]
68#[target_feature(enable = "crc")]
69#[cfg(target_arch = "arm")]
70#[cfg_attr(test, assert_instr(crc32cw))]
71#[cfg_attr(
72 target_arch = "arm",
73 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
74)]
75pub fn __crc32cd(crc: u32, data: u64) -> u32 {
76 let b: u32 = (data & 0xFFFFFFFF) as u32;
77 let c: u32 = (data >> 32) as u32;
78 unsafe extern "unadjusted" {
79 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
80 fn ___crc32cw(crc: u32, data: u32) -> u32;
81 }
82 unsafe { ___crc32cw(___crc32cw(crc, b), c) }
83}
84#[doc = "CRC32-C single round checksum for bytes (16 bits)."]
85#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"]
86#[inline]
87#[target_feature(enable = "crc")]
88#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
89#[cfg_attr(test, assert_instr(crc32ch))]
90#[cfg_attr(
91 target_arch = "arm",
92 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
93)]
94#[cfg_attr(
95 not(target_arch = "arm"),
96 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
97)]
98pub fn __crc32ch(crc: u32, data: u16) -> u32 {
99 unsafe extern "unadjusted" {
100 #[cfg_attr(
101 any(target_arch = "aarch64", target_arch = "arm64ec"),
102 link_name = "llvm.aarch64.crc32ch"
103 )]
104 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
105 fn ___crc32ch(crc: u32, data: u32) -> u32;
106 }
107 unsafe { ___crc32ch(crc, data as u32) }
108}
109#[doc = "CRC32-C single round checksum for bytes (32 bits)."]
110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"]
111#[inline]
112#[target_feature(enable = "crc")]
113#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
114#[cfg_attr(test, assert_instr(crc32cw))]
115#[cfg_attr(
116 target_arch = "arm",
117 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
118)]
119#[cfg_attr(
120 not(target_arch = "arm"),
121 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
122)]
123pub fn __crc32cw(crc: u32, data: u32) -> u32 {
124 unsafe extern "unadjusted" {
125 #[cfg_attr(
126 any(target_arch = "aarch64", target_arch = "arm64ec"),
127 link_name = "llvm.aarch64.crc32cw"
128 )]
129 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
130 fn ___crc32cw(crc: u32, data: u32) -> u32;
131 }
132 unsafe { ___crc32cw(crc, data) }
133}
134#[doc = "CRC32 single round checksum for quad words (64 bits)."]
135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
136#[inline]
137#[target_feature(enable = "crc")]
138#[cfg(target_arch = "arm")]
139#[cfg_attr(test, assert_instr(crc32w))]
140#[cfg_attr(
141 target_arch = "arm",
142 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
143)]
144pub fn __crc32d(crc: u32, data: u64) -> u32 {
145 let b: u32 = (data & 0xFFFFFFFF) as u32;
146 let c: u32 = (data >> 32) as u32;
147 unsafe extern "unadjusted" {
148 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
149 fn ___crc32w(crc: u32, data: u32) -> u32;
150 }
151 unsafe { ___crc32w(___crc32w(crc, b), c) }
152}
153#[doc = "CRC32 single round checksum for bytes (16 bits)."]
154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"]
155#[inline]
156#[target_feature(enable = "crc")]
157#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
158#[cfg_attr(test, assert_instr(crc32h))]
159#[cfg_attr(
160 target_arch = "arm",
161 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
162)]
163#[cfg_attr(
164 not(target_arch = "arm"),
165 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
166)]
167pub fn __crc32h(crc: u32, data: u16) -> u32 {
168 unsafe extern "unadjusted" {
169 #[cfg_attr(
170 any(target_arch = "aarch64", target_arch = "arm64ec"),
171 link_name = "llvm.aarch64.crc32h"
172 )]
173 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
174 fn ___crc32h(crc: u32, data: u32) -> u32;
175 }
176 unsafe { ___crc32h(crc, data as u32) }
177}
178#[doc = "CRC32 single round checksum for bytes (32 bits)."]
179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"]
180#[inline]
181#[target_feature(enable = "crc")]
182#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
183#[cfg_attr(test, assert_instr(crc32w))]
184#[cfg_attr(
185 target_arch = "arm",
186 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
187)]
188#[cfg_attr(
189 not(target_arch = "arm"),
190 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
191)]
192pub fn __crc32w(crc: u32, data: u32) -> u32 {
193 unsafe extern "unadjusted" {
194 #[cfg_attr(
195 any(target_arch = "aarch64", target_arch = "arm64ec"),
196 link_name = "llvm.aarch64.crc32w"
197 )]
198 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
199 fn ___crc32w(crc: u32, data: u32) -> u32;
200 }
201 unsafe { ___crc32w(crc, data) }
202}
203#[doc = "Signed Add and Accumulate Long Pairwise."]
204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"]
205#[inline]
206#[target_feature(enable = "neon")]
207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
208#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
209#[cfg_attr(
210 target_arch = "arm",
211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
212)]
213fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
214 unsafe extern "unadjusted" {
215 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i16.v8i8")]
216 fn _priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t;
217 }
218 unsafe { _priv_vpadal_s8(a, b) }
219}
220#[doc = "Signed Add and Accumulate Long Pairwise."]
221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"]
222#[inline]
223#[target_feature(enable = "neon")]
224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
225#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
226#[cfg_attr(
227 target_arch = "arm",
228 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
229)]
230fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
231 unsafe extern "unadjusted" {
232 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v8i16.v16i8")]
233 fn _priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t;
234 }
235 unsafe { _priv_vpadalq_s8(a, b) }
236}
237#[doc = "Signed Add and Accumulate Long Pairwise."]
238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"]
239#[inline]
240#[target_feature(enable = "neon")]
241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
242#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
243#[cfg_attr(
244 target_arch = "arm",
245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
246)]
247fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
248 unsafe extern "unadjusted" {
249 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i32.v4i16")]
250 fn _priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t;
251 }
252 unsafe { _priv_vpadal_s16(a, b) }
253}
254#[doc = "Signed Add and Accumulate Long Pairwise."]
255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"]
256#[inline]
257#[target_feature(enable = "neon")]
258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
259#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
260#[cfg_attr(
261 target_arch = "arm",
262 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
263)]
264fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
265 unsafe extern "unadjusted" {
266 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i32.v8i16")]
267 fn _priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t;
268 }
269 unsafe { _priv_vpadalq_s16(a, b) }
270}
271#[doc = "Signed Add and Accumulate Long Pairwise."]
272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"]
273#[inline]
274#[target_feature(enable = "neon")]
275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
276#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
277#[cfg_attr(
278 target_arch = "arm",
279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
280)]
281fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
282 unsafe extern "unadjusted" {
283 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v1i64.v2i32")]
284 fn _priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t;
285 }
286 unsafe { _priv_vpadal_s32(a, b) }
287}
288#[doc = "Signed Add and Accumulate Long Pairwise."]
289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"]
290#[inline]
291#[target_feature(enable = "neon")]
292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
293#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
294#[cfg_attr(
295 target_arch = "arm",
296 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
297)]
298fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
299 unsafe extern "unadjusted" {
300 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i64.v4i32")]
301 fn _priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t;
302 }
303 unsafe { _priv_vpadalq_s32(a, b) }
304}
305#[doc = "Signed Add and Accumulate Long Pairwise."]
306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"]
307#[inline]
308#[target_feature(enable = "neon")]
309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
310#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
311#[cfg_attr(
312 target_arch = "arm",
313 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
314)]
315fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
316 unsafe extern "unadjusted" {
317 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i16.v8i8")]
318 fn _priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t;
319 }
320 unsafe { _priv_vpadal_u8(a, b) }
321}
322#[doc = "Signed Add and Accumulate Long Pairwise."]
323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"]
324#[inline]
325#[target_feature(enable = "neon")]
326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
327#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
328#[cfg_attr(
329 target_arch = "arm",
330 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
331)]
332fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
333 unsafe extern "unadjusted" {
334 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v8i16.v16i8")]
335 fn _priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t;
336 }
337 unsafe { _priv_vpadalq_u8(a, b) }
338}
339#[doc = "Signed Add and Accumulate Long Pairwise."]
340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"]
341#[inline]
342#[target_feature(enable = "neon")]
343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
344#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
345#[cfg_attr(
346 target_arch = "arm",
347 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
348)]
349fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
350 unsafe extern "unadjusted" {
351 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i32.v4i16")]
352 fn _priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t;
353 }
354 unsafe { _priv_vpadal_u16(a, b) }
355}
356#[doc = "Signed Add and Accumulate Long Pairwise."]
357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"]
358#[inline]
359#[target_feature(enable = "neon")]
360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
361#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
362#[cfg_attr(
363 target_arch = "arm",
364 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
365)]
366fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
367 unsafe extern "unadjusted" {
368 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i32.v8i16")]
369 fn _priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t;
370 }
371 unsafe { _priv_vpadalq_u16(a, b) }
372}
373#[doc = "Signed Add and Accumulate Long Pairwise."]
374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"]
375#[inline]
376#[target_feature(enable = "neon")]
377#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
378#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
379#[cfg_attr(
380 target_arch = "arm",
381 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
382)]
383fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
384 unsafe extern "unadjusted" {
385 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v1i64.v2i32")]
386 fn _priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t;
387 }
388 unsafe { _priv_vpadal_u32(a, b) }
389}
390#[doc = "Signed Add and Accumulate Long Pairwise."]
391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"]
392#[inline]
393#[target_feature(enable = "neon")]
394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
395#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
396#[cfg_attr(
397 target_arch = "arm",
398 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
399)]
400fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
401 unsafe extern "unadjusted" {
402 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i64.v4i32")]
403 fn _priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t;
404 }
405 unsafe { _priv_vpadalq_u32(a, b) }
406}
407#[doc = "Absolute difference and accumulate (64-bit)"]
408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s16)"]
409#[inline]
410#[target_feature(enable = "neon")]
411#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
412#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
413#[cfg_attr(
414 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
415 assert_instr(saba)
416)]
417#[cfg_attr(
418 not(target_arch = "arm"),
419 stable(feature = "neon_intrinsics", since = "1.59.0")
420)]
421#[cfg_attr(
422 target_arch = "arm",
423 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
424)]
425pub fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
426 unsafe { simd_add(a, vabd_s16(b, c)) }
427}
428#[doc = "Absolute difference and accumulate (64-bit)"]
429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s32)"]
430#[inline]
431#[target_feature(enable = "neon")]
432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
433#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
434#[cfg_attr(
435 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
436 assert_instr(saba)
437)]
438#[cfg_attr(
439 not(target_arch = "arm"),
440 stable(feature = "neon_intrinsics", since = "1.59.0")
441)]
442#[cfg_attr(
443 target_arch = "arm",
444 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
445)]
446pub fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
447 unsafe { simd_add(a, vabd_s32(b, c)) }
448}
449#[doc = "Absolute difference and accumulate (64-bit)"]
450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s8)"]
451#[inline]
452#[target_feature(enable = "neon")]
453#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
454#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
455#[cfg_attr(
456 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
457 assert_instr(saba)
458)]
459#[cfg_attr(
460 not(target_arch = "arm"),
461 stable(feature = "neon_intrinsics", since = "1.59.0")
462)]
463#[cfg_attr(
464 target_arch = "arm",
465 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
466)]
467pub fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
468 unsafe { simd_add(a, vabd_s8(b, c)) }
469}
470#[doc = "Absolute difference and accumulate (64-bit)"]
471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u16)"]
472#[inline]
473#[target_feature(enable = "neon")]
474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
475#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
476#[cfg_attr(
477 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
478 assert_instr(uaba)
479)]
480#[cfg_attr(
481 not(target_arch = "arm"),
482 stable(feature = "neon_intrinsics", since = "1.59.0")
483)]
484#[cfg_attr(
485 target_arch = "arm",
486 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
487)]
488pub fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
489 unsafe { simd_add(a, vabd_u16(b, c)) }
490}
491#[doc = "Absolute difference and accumulate (64-bit)"]
492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u32)"]
493#[inline]
494#[target_feature(enable = "neon")]
495#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
496#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
497#[cfg_attr(
498 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
499 assert_instr(uaba)
500)]
501#[cfg_attr(
502 not(target_arch = "arm"),
503 stable(feature = "neon_intrinsics", since = "1.59.0")
504)]
505#[cfg_attr(
506 target_arch = "arm",
507 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
508)]
509pub fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
510 unsafe { simd_add(a, vabd_u32(b, c)) }
511}
512#[doc = "Absolute difference and accumulate (64-bit)"]
513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u8)"]
514#[inline]
515#[target_feature(enable = "neon")]
516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
517#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
518#[cfg_attr(
519 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
520 assert_instr(uaba)
521)]
522#[cfg_attr(
523 not(target_arch = "arm"),
524 stable(feature = "neon_intrinsics", since = "1.59.0")
525)]
526#[cfg_attr(
527 target_arch = "arm",
528 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
529)]
530pub fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
531 unsafe { simd_add(a, vabd_u8(b, c)) }
532}
533#[doc = "Signed Absolute difference and Accumulate Long"]
534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"]
535#[inline]
536#[target_feature(enable = "neon")]
537#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
538#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))]
539#[cfg_attr(
540 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
541 assert_instr(sabal)
542)]
543#[cfg_attr(
544 not(target_arch = "arm"),
545 stable(feature = "neon_intrinsics", since = "1.59.0")
546)]
547#[cfg_attr(
548 target_arch = "arm",
549 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
550)]
551pub fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
552 let d: int8x8_t = vabd_s8(b, c);
553 unsafe {
554 let e: uint8x8_t = simd_cast(d);
555 simd_add(a, simd_cast(e))
556 }
557}
558#[doc = "Signed Absolute difference and Accumulate Long"]
559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"]
560#[inline]
561#[target_feature(enable = "neon")]
562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
563#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))]
564#[cfg_attr(
565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
566 assert_instr(sabal)
567)]
568#[cfg_attr(
569 not(target_arch = "arm"),
570 stable(feature = "neon_intrinsics", since = "1.59.0")
571)]
572#[cfg_attr(
573 target_arch = "arm",
574 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
575)]
576pub fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
577 let d: int16x4_t = vabd_s16(b, c);
578 unsafe {
579 let e: uint16x4_t = simd_cast(d);
580 simd_add(a, simd_cast(e))
581 }
582}
583#[doc = "Signed Absolute difference and Accumulate Long"]
584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"]
585#[inline]
586#[target_feature(enable = "neon")]
587#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
588#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))]
589#[cfg_attr(
590 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
591 assert_instr(sabal)
592)]
593#[cfg_attr(
594 not(target_arch = "arm"),
595 stable(feature = "neon_intrinsics", since = "1.59.0")
596)]
597#[cfg_attr(
598 target_arch = "arm",
599 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
600)]
601pub fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
602 let d: int32x2_t = vabd_s32(b, c);
603 unsafe {
604 let e: uint32x2_t = simd_cast(d);
605 simd_add(a, simd_cast(e))
606 }
607}
608#[doc = "Unsigned Absolute difference and Accumulate Long"]
609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"]
610#[inline]
611#[target_feature(enable = "neon")]
612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
613#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))]
614#[cfg_attr(
615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
616 assert_instr(uabal)
617)]
618#[cfg_attr(
619 not(target_arch = "arm"),
620 stable(feature = "neon_intrinsics", since = "1.59.0")
621)]
622#[cfg_attr(
623 target_arch = "arm",
624 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
625)]
626pub fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
627 let d: uint8x8_t = vabd_u8(b, c);
628 unsafe { simd_add(a, simd_cast(d)) }
629}
630#[doc = "Unsigned Absolute difference and Accumulate Long"]
631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"]
632#[inline]
633#[target_feature(enable = "neon")]
634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
635#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))]
636#[cfg_attr(
637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
638 assert_instr(uabal)
639)]
640#[cfg_attr(
641 not(target_arch = "arm"),
642 stable(feature = "neon_intrinsics", since = "1.59.0")
643)]
644#[cfg_attr(
645 target_arch = "arm",
646 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
647)]
648pub fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
649 let d: uint16x4_t = vabd_u16(b, c);
650 unsafe { simd_add(a, simd_cast(d)) }
651}
652#[doc = "Unsigned Absolute difference and Accumulate Long"]
653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"]
654#[inline]
655#[target_feature(enable = "neon")]
656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
657#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))]
658#[cfg_attr(
659 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
660 assert_instr(uabal)
661)]
662#[cfg_attr(
663 not(target_arch = "arm"),
664 stable(feature = "neon_intrinsics", since = "1.59.0")
665)]
666#[cfg_attr(
667 target_arch = "arm",
668 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
669)]
670pub fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
671 let d: uint32x2_t = vabd_u32(b, c);
672 unsafe { simd_add(a, simd_cast(d)) }
673}
674#[doc = "Absolute difference and accumulate (128-bit)"]
675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s16)"]
676#[inline]
677#[target_feature(enable = "neon")]
678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
679#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
680#[cfg_attr(
681 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
682 assert_instr(saba)
683)]
684#[cfg_attr(
685 not(target_arch = "arm"),
686 stable(feature = "neon_intrinsics", since = "1.59.0")
687)]
688#[cfg_attr(
689 target_arch = "arm",
690 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
691)]
692pub fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
693 unsafe { simd_add(a, vabdq_s16(b, c)) }
694}
695#[doc = "Absolute difference and accumulate (128-bit)"]
696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s32)"]
697#[inline]
698#[target_feature(enable = "neon")]
699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
700#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
701#[cfg_attr(
702 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
703 assert_instr(saba)
704)]
705#[cfg_attr(
706 not(target_arch = "arm"),
707 stable(feature = "neon_intrinsics", since = "1.59.0")
708)]
709#[cfg_attr(
710 target_arch = "arm",
711 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
712)]
713pub fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
714 unsafe { simd_add(a, vabdq_s32(b, c)) }
715}
716#[doc = "Absolute difference and accumulate (128-bit)"]
717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s8)"]
718#[inline]
719#[target_feature(enable = "neon")]
720#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
721#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
722#[cfg_attr(
723 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
724 assert_instr(saba)
725)]
726#[cfg_attr(
727 not(target_arch = "arm"),
728 stable(feature = "neon_intrinsics", since = "1.59.0")
729)]
730#[cfg_attr(
731 target_arch = "arm",
732 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
733)]
734pub fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
735 unsafe { simd_add(a, vabdq_s8(b, c)) }
736}
737#[doc = "Absolute difference and accumulate (128-bit)"]
738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u16)"]
739#[inline]
740#[target_feature(enable = "neon")]
741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
742#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
743#[cfg_attr(
744 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
745 assert_instr(uaba)
746)]
747#[cfg_attr(
748 not(target_arch = "arm"),
749 stable(feature = "neon_intrinsics", since = "1.59.0")
750)]
751#[cfg_attr(
752 target_arch = "arm",
753 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
754)]
755pub fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
756 unsafe { simd_add(a, vabdq_u16(b, c)) }
757}
758#[doc = "Absolute difference and accumulate (128-bit)"]
759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u32)"]
760#[inline]
761#[target_feature(enable = "neon")]
762#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
763#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
764#[cfg_attr(
765 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
766 assert_instr(uaba)
767)]
768#[cfg_attr(
769 not(target_arch = "arm"),
770 stable(feature = "neon_intrinsics", since = "1.59.0")
771)]
772#[cfg_attr(
773 target_arch = "arm",
774 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
775)]
776pub fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
777 unsafe { simd_add(a, vabdq_u32(b, c)) }
778}
779#[doc = "Absolute difference and accumulate (128-bit)"]
780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u8)"]
781#[inline]
782#[target_feature(enable = "neon")]
783#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
784#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
785#[cfg_attr(
786 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
787 assert_instr(uaba)
788)]
789#[cfg_attr(
790 not(target_arch = "arm"),
791 stable(feature = "neon_intrinsics", since = "1.59.0")
792)]
793#[cfg_attr(
794 target_arch = "arm",
795 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
796)]
797pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
798 unsafe { simd_add(a, vabdq_u8(b, c)) }
799}
800#[doc = "Absolute difference between the arguments of Floating"]
801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f16)"]
802#[inline]
803#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
804#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
805#[cfg_attr(
806 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
807 assert_instr(fabd)
808)]
809#[target_feature(enable = "neon,fp16")]
810#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
811pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
812 unsafe extern "unadjusted" {
813 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f16")]
814 #[cfg_attr(
815 any(target_arch = "aarch64", target_arch = "arm64ec"),
816 link_name = "llvm.aarch64.neon.fabd.v4f16"
817 )]
818 fn _vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
819 }
820 unsafe { _vabd_f16(a, b) }
821}
822#[doc = "Absolute difference between the arguments of Floating"]
823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f16)"]
824#[inline]
825#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
826#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
827#[cfg_attr(
828 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
829 assert_instr(fabd)
830)]
831#[target_feature(enable = "neon,fp16")]
832#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
833pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
834 unsafe extern "unadjusted" {
835 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8f16")]
836 #[cfg_attr(
837 any(target_arch = "aarch64", target_arch = "arm64ec"),
838 link_name = "llvm.aarch64.neon.fabd.v8f16"
839 )]
840 fn _vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
841 }
842 unsafe { _vabdq_f16(a, b) }
843}
844#[doc = "Absolute difference between the arguments of Floating"]
845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"]
846#[inline]
847#[target_feature(enable = "neon")]
848#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
849#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
850#[cfg_attr(
851 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
852 assert_instr(fabd)
853)]
854#[cfg_attr(
855 not(target_arch = "arm"),
856 stable(feature = "neon_intrinsics", since = "1.59.0")
857)]
858#[cfg_attr(
859 target_arch = "arm",
860 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
861)]
862pub fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
863 unsafe extern "unadjusted" {
864 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2f32")]
865 #[cfg_attr(
866 any(target_arch = "aarch64", target_arch = "arm64ec"),
867 link_name = "llvm.aarch64.neon.fabd.v2f32"
868 )]
869 fn _vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
870 }
871 unsafe { _vabd_f32(a, b) }
872}
873#[doc = "Absolute difference between the arguments of Floating"]
874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"]
875#[inline]
876#[target_feature(enable = "neon")]
877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
878#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
879#[cfg_attr(
880 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
881 assert_instr(fabd)
882)]
883#[cfg_attr(
884 not(target_arch = "arm"),
885 stable(feature = "neon_intrinsics", since = "1.59.0")
886)]
887#[cfg_attr(
888 target_arch = "arm",
889 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
890)]
891pub fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
892 unsafe extern "unadjusted" {
893 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f32")]
894 #[cfg_attr(
895 any(target_arch = "aarch64", target_arch = "arm64ec"),
896 link_name = "llvm.aarch64.neon.fabd.v4f32"
897 )]
898 fn _vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
899 }
900 unsafe { _vabdq_f32(a, b) }
901}
902#[doc = "Absolute difference between the arguments"]
903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"]
904#[inline]
905#[target_feature(enable = "neon")]
906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
907#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
908#[cfg_attr(
909 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
910 assert_instr(sabd)
911)]
912#[cfg_attr(
913 not(target_arch = "arm"),
914 stable(feature = "neon_intrinsics", since = "1.59.0")
915)]
916#[cfg_attr(
917 target_arch = "arm",
918 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
919)]
920pub fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
921 unsafe extern "unadjusted" {
922 #[cfg_attr(
923 any(target_arch = "aarch64", target_arch = "arm64ec"),
924 link_name = "llvm.aarch64.neon.sabd.v8i8"
925 )]
926 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i8")]
927 fn _vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
928 }
929 unsafe { _vabd_s8(a, b) }
930}
931#[doc = "Absolute difference between the arguments"]
932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"]
933#[inline]
934#[target_feature(enable = "neon")]
935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
936#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
937#[cfg_attr(
938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
939 assert_instr(sabd)
940)]
941#[cfg_attr(
942 not(target_arch = "arm"),
943 stable(feature = "neon_intrinsics", since = "1.59.0")
944)]
945#[cfg_attr(
946 target_arch = "arm",
947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
948)]
949pub fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
950 unsafe extern "unadjusted" {
951 #[cfg_attr(
952 any(target_arch = "aarch64", target_arch = "arm64ec"),
953 link_name = "llvm.aarch64.neon.sabd.v16i8"
954 )]
955 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v16i8")]
956 fn _vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
957 }
958 unsafe { _vabdq_s8(a, b) }
959}
960#[doc = "Absolute difference between the arguments"]
961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"]
962#[inline]
963#[target_feature(enable = "neon")]
964#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
965#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
966#[cfg_attr(
967 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
968 assert_instr(sabd)
969)]
970#[cfg_attr(
971 not(target_arch = "arm"),
972 stable(feature = "neon_intrinsics", since = "1.59.0")
973)]
974#[cfg_attr(
975 target_arch = "arm",
976 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
977)]
978pub fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
979 unsafe extern "unadjusted" {
980 #[cfg_attr(
981 any(target_arch = "aarch64", target_arch = "arm64ec"),
982 link_name = "llvm.aarch64.neon.sabd.v4i16"
983 )]
984 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i16")]
985 fn _vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
986 }
987 unsafe { _vabd_s16(a, b) }
988}
989#[doc = "Absolute difference between the arguments"]
990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"]
991#[inline]
992#[target_feature(enable = "neon")]
993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
994#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
995#[cfg_attr(
996 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
997 assert_instr(sabd)
998)]
999#[cfg_attr(
1000 not(target_arch = "arm"),
1001 stable(feature = "neon_intrinsics", since = "1.59.0")
1002)]
1003#[cfg_attr(
1004 target_arch = "arm",
1005 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1006)]
1007pub fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
1008 unsafe extern "unadjusted" {
1009 #[cfg_attr(
1010 any(target_arch = "aarch64", target_arch = "arm64ec"),
1011 link_name = "llvm.aarch64.neon.sabd.v8i16"
1012 )]
1013 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i16")]
1014 fn _vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
1015 }
1016 unsafe { _vabdq_s16(a, b) }
1017}
1018#[doc = "Absolute difference between the arguments"]
1019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"]
1020#[inline]
1021#[target_feature(enable = "neon")]
1022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1023#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
1024#[cfg_attr(
1025 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1026 assert_instr(sabd)
1027)]
1028#[cfg_attr(
1029 not(target_arch = "arm"),
1030 stable(feature = "neon_intrinsics", since = "1.59.0")
1031)]
1032#[cfg_attr(
1033 target_arch = "arm",
1034 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1035)]
1036pub fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
1037 unsafe extern "unadjusted" {
1038 #[cfg_attr(
1039 any(target_arch = "aarch64", target_arch = "arm64ec"),
1040 link_name = "llvm.aarch64.neon.sabd.v2i32"
1041 )]
1042 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2i32")]
1043 fn _vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
1044 }
1045 unsafe { _vabd_s32(a, b) }
1046}
1047#[doc = "Absolute difference between the arguments"]
1048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"]
1049#[inline]
1050#[target_feature(enable = "neon")]
1051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1052#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
1053#[cfg_attr(
1054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1055 assert_instr(sabd)
1056)]
1057#[cfg_attr(
1058 not(target_arch = "arm"),
1059 stable(feature = "neon_intrinsics", since = "1.59.0")
1060)]
1061#[cfg_attr(
1062 target_arch = "arm",
1063 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1064)]
1065pub fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
1066 unsafe extern "unadjusted" {
1067 #[cfg_attr(
1068 any(target_arch = "aarch64", target_arch = "arm64ec"),
1069 link_name = "llvm.aarch64.neon.sabd.v4i32"
1070 )]
1071 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i32")]
1072 fn _vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
1073 }
1074 unsafe { _vabdq_s32(a, b) }
1075}
1076#[doc = "Absolute difference between the arguments"]
1077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"]
1078#[inline]
1079#[target_feature(enable = "neon")]
1080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1081#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
1082#[cfg_attr(
1083 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1084 assert_instr(uabd)
1085)]
1086#[cfg_attr(
1087 not(target_arch = "arm"),
1088 stable(feature = "neon_intrinsics", since = "1.59.0")
1089)]
1090#[cfg_attr(
1091 target_arch = "arm",
1092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1093)]
1094pub fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
1095 unsafe extern "unadjusted" {
1096 #[cfg_attr(
1097 any(target_arch = "aarch64", target_arch = "arm64ec"),
1098 link_name = "llvm.aarch64.neon.uabd.v8i8"
1099 )]
1100 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i8")]
1101 fn _vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
1102 }
1103 unsafe { _vabd_u8(a, b) }
1104}
1105#[doc = "Absolute difference between the arguments"]
1106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"]
1107#[inline]
1108#[target_feature(enable = "neon")]
1109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1110#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
1111#[cfg_attr(
1112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1113 assert_instr(uabd)
1114)]
1115#[cfg_attr(
1116 not(target_arch = "arm"),
1117 stable(feature = "neon_intrinsics", since = "1.59.0")
1118)]
1119#[cfg_attr(
1120 target_arch = "arm",
1121 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1122)]
1123pub fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
1124 unsafe extern "unadjusted" {
1125 #[cfg_attr(
1126 any(target_arch = "aarch64", target_arch = "arm64ec"),
1127 link_name = "llvm.aarch64.neon.uabd.v16i8"
1128 )]
1129 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v16i8")]
1130 fn _vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
1131 }
1132 unsafe { _vabdq_u8(a, b) }
1133}
1134#[doc = "Absolute difference between the arguments"]
1135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"]
1136#[inline]
1137#[target_feature(enable = "neon")]
1138#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1139#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
1140#[cfg_attr(
1141 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1142 assert_instr(uabd)
1143)]
1144#[cfg_attr(
1145 not(target_arch = "arm"),
1146 stable(feature = "neon_intrinsics", since = "1.59.0")
1147)]
1148#[cfg_attr(
1149 target_arch = "arm",
1150 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1151)]
1152pub fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
1153 unsafe extern "unadjusted" {
1154 #[cfg_attr(
1155 any(target_arch = "aarch64", target_arch = "arm64ec"),
1156 link_name = "llvm.aarch64.neon.uabd.v4i16"
1157 )]
1158 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i16")]
1159 fn _vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
1160 }
1161 unsafe { _vabd_u16(a, b) }
1162}
1163#[doc = "Absolute difference between the arguments"]
1164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"]
1165#[inline]
1166#[target_feature(enable = "neon")]
1167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1168#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
1169#[cfg_attr(
1170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1171 assert_instr(uabd)
1172)]
1173#[cfg_attr(
1174 not(target_arch = "arm"),
1175 stable(feature = "neon_intrinsics", since = "1.59.0")
1176)]
1177#[cfg_attr(
1178 target_arch = "arm",
1179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1180)]
1181pub fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
1182 unsafe extern "unadjusted" {
1183 #[cfg_attr(
1184 any(target_arch = "aarch64", target_arch = "arm64ec"),
1185 link_name = "llvm.aarch64.neon.uabd.v8i16"
1186 )]
1187 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i16")]
1188 fn _vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
1189 }
1190 unsafe { _vabdq_u16(a, b) }
1191}
1192#[doc = "Absolute difference between the arguments"]
1193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"]
1194#[inline]
1195#[target_feature(enable = "neon")]
1196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1197#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
1198#[cfg_attr(
1199 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1200 assert_instr(uabd)
1201)]
1202#[cfg_attr(
1203 not(target_arch = "arm"),
1204 stable(feature = "neon_intrinsics", since = "1.59.0")
1205)]
1206#[cfg_attr(
1207 target_arch = "arm",
1208 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1209)]
1210pub fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
1211 unsafe extern "unadjusted" {
1212 #[cfg_attr(
1213 any(target_arch = "aarch64", target_arch = "arm64ec"),
1214 link_name = "llvm.aarch64.neon.uabd.v2i32"
1215 )]
1216 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v2i32")]
1217 fn _vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
1218 }
1219 unsafe { _vabd_u32(a, b) }
1220}
1221#[doc = "Absolute difference between the arguments"]
1222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"]
1223#[inline]
1224#[target_feature(enable = "neon")]
1225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1226#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
1227#[cfg_attr(
1228 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1229 assert_instr(uabd)
1230)]
1231#[cfg_attr(
1232 not(target_arch = "arm"),
1233 stable(feature = "neon_intrinsics", since = "1.59.0")
1234)]
1235#[cfg_attr(
1236 target_arch = "arm",
1237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1238)]
1239pub fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
1240 unsafe extern "unadjusted" {
1241 #[cfg_attr(
1242 any(target_arch = "aarch64", target_arch = "arm64ec"),
1243 link_name = "llvm.aarch64.neon.uabd.v4i32"
1244 )]
1245 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i32")]
1246 fn _vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
1247 }
1248 unsafe { _vabdq_u32(a, b) }
1249}
1250#[doc = "Signed Absolute difference Long"]
1251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"]
1252#[inline]
1253#[target_feature(enable = "neon")]
1254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1255#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))]
1256#[cfg_attr(
1257 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1258 assert_instr(sabdl)
1259)]
1260#[cfg_attr(
1261 not(target_arch = "arm"),
1262 stable(feature = "neon_intrinsics", since = "1.59.0")
1263)]
1264#[cfg_attr(
1265 target_arch = "arm",
1266 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1267)]
1268pub fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
1269 unsafe {
1270 let c: uint8x8_t = simd_cast(vabd_s8(a, b));
1271 simd_cast(c)
1272 }
1273}
1274#[doc = "Signed Absolute difference Long"]
1275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"]
1276#[inline]
1277#[target_feature(enable = "neon")]
1278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1279#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))]
1280#[cfg_attr(
1281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1282 assert_instr(sabdl)
1283)]
1284#[cfg_attr(
1285 not(target_arch = "arm"),
1286 stable(feature = "neon_intrinsics", since = "1.59.0")
1287)]
1288#[cfg_attr(
1289 target_arch = "arm",
1290 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1291)]
1292pub fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
1293 unsafe {
1294 let c: uint16x4_t = simd_cast(vabd_s16(a, b));
1295 simd_cast(c)
1296 }
1297}
1298#[doc = "Signed Absolute difference Long"]
1299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"]
1300#[inline]
1301#[target_feature(enable = "neon")]
1302#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1303#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))]
1304#[cfg_attr(
1305 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1306 assert_instr(sabdl)
1307)]
1308#[cfg_attr(
1309 not(target_arch = "arm"),
1310 stable(feature = "neon_intrinsics", since = "1.59.0")
1311)]
1312#[cfg_attr(
1313 target_arch = "arm",
1314 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1315)]
1316pub fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
1317 unsafe {
1318 let c: uint32x2_t = simd_cast(vabd_s32(a, b));
1319 simd_cast(c)
1320 }
1321}
1322#[doc = "Unsigned Absolute difference Long"]
1323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"]
1324#[inline]
1325#[target_feature(enable = "neon")]
1326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1327#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))]
1328#[cfg_attr(
1329 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1330 assert_instr(uabdl)
1331)]
1332#[cfg_attr(
1333 not(target_arch = "arm"),
1334 stable(feature = "neon_intrinsics", since = "1.59.0")
1335)]
1336#[cfg_attr(
1337 target_arch = "arm",
1338 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1339)]
1340pub fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
1341 unsafe { simd_cast(vabd_u8(a, b)) }
1342}
1343#[doc = "Unsigned Absolute difference Long"]
1344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"]
1345#[inline]
1346#[target_feature(enable = "neon")]
1347#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1348#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))]
1349#[cfg_attr(
1350 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1351 assert_instr(uabdl)
1352)]
1353#[cfg_attr(
1354 not(target_arch = "arm"),
1355 stable(feature = "neon_intrinsics", since = "1.59.0")
1356)]
1357#[cfg_attr(
1358 target_arch = "arm",
1359 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1360)]
1361pub fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
1362 unsafe { simd_cast(vabd_u16(a, b)) }
1363}
1364#[doc = "Unsigned Absolute difference Long"]
1365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"]
1366#[inline]
1367#[target_feature(enable = "neon")]
1368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1369#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))]
1370#[cfg_attr(
1371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1372 assert_instr(uabdl)
1373)]
1374#[cfg_attr(
1375 not(target_arch = "arm"),
1376 stable(feature = "neon_intrinsics", since = "1.59.0")
1377)]
1378#[cfg_attr(
1379 target_arch = "arm",
1380 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1381)]
1382pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
1383 unsafe { simd_cast(vabd_u32(a, b)) }
1384}
1385#[doc = "Floating-point absolute value"]
1386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f16)"]
1387#[inline]
1388#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1390#[cfg_attr(
1391 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1392 assert_instr(fabs)
1393)]
1394#[target_feature(enable = "neon,fp16")]
1395#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1396pub fn vabs_f16(a: float16x4_t) -> float16x4_t {
1397 unsafe { simd_fabs(a) }
1398}
1399#[doc = "Floating-point absolute value"]
1400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f16)"]
1401#[inline]
1402#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1404#[cfg_attr(
1405 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1406 assert_instr(fabs)
1407)]
1408#[target_feature(enable = "neon,fp16")]
1409#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1410pub fn vabsq_f16(a: float16x8_t) -> float16x8_t {
1411 unsafe { simd_fabs(a) }
1412}
1413#[doc = "Floating-point absolute value"]
1414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"]
1415#[inline]
1416#[target_feature(enable = "neon")]
1417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1419#[cfg_attr(
1420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1421 assert_instr(fabs)
1422)]
1423#[cfg_attr(
1424 not(target_arch = "arm"),
1425 stable(feature = "neon_intrinsics", since = "1.59.0")
1426)]
1427#[cfg_attr(
1428 target_arch = "arm",
1429 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1430)]
1431pub fn vabs_f32(a: float32x2_t) -> float32x2_t {
1432 unsafe { simd_fabs(a) }
1433}
1434#[doc = "Floating-point absolute value"]
1435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"]
1436#[inline]
1437#[target_feature(enable = "neon")]
1438#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1439#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1440#[cfg_attr(
1441 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1442 assert_instr(fabs)
1443)]
1444#[cfg_attr(
1445 not(target_arch = "arm"),
1446 stable(feature = "neon_intrinsics", since = "1.59.0")
1447)]
1448#[cfg_attr(
1449 target_arch = "arm",
1450 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1451)]
1452pub fn vabsq_f32(a: float32x4_t) -> float32x4_t {
1453 unsafe { simd_fabs(a) }
1454}
1455#[doc = "Absolute value (wrapping)."]
1456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)"]
1457#[inline]
1458#[target_feature(enable = "neon")]
1459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1461#[cfg_attr(
1462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1463 assert_instr(abs)
1464)]
1465#[cfg_attr(
1466 not(target_arch = "arm"),
1467 stable(feature = "neon_intrinsics", since = "1.59.0")
1468)]
1469#[cfg_attr(
1470 target_arch = "arm",
1471 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1472)]
1473pub fn vabs_s8(a: int8x8_t) -> int8x8_t {
1474 unsafe extern "unadjusted" {
1475 #[cfg_attr(
1476 any(target_arch = "aarch64", target_arch = "arm64ec"),
1477 link_name = "llvm.aarch64.neon.abs.v8i8"
1478 )]
1479 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i8")]
1480 fn _vabs_s8(a: int8x8_t) -> int8x8_t;
1481 }
1482 unsafe { _vabs_s8(a) }
1483}
1484#[doc = "Absolute value (wrapping)."]
1485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"]
1486#[inline]
1487#[target_feature(enable = "neon")]
1488#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1489#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1490#[cfg_attr(
1491 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1492 assert_instr(abs)
1493)]
1494#[cfg_attr(
1495 not(target_arch = "arm"),
1496 stable(feature = "neon_intrinsics", since = "1.59.0")
1497)]
1498#[cfg_attr(
1499 target_arch = "arm",
1500 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1501)]
1502pub fn vabsq_s8(a: int8x16_t) -> int8x16_t {
1503 unsafe extern "unadjusted" {
1504 #[cfg_attr(
1505 any(target_arch = "aarch64", target_arch = "arm64ec"),
1506 link_name = "llvm.aarch64.neon.abs.v16i8"
1507 )]
1508 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v16i8")]
1509 fn _vabsq_s8(a: int8x16_t) -> int8x16_t;
1510 }
1511 unsafe { _vabsq_s8(a) }
1512}
1513#[doc = "Absolute value (wrapping)."]
1514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"]
1515#[inline]
1516#[target_feature(enable = "neon")]
1517#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1518#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1519#[cfg_attr(
1520 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1521 assert_instr(abs)
1522)]
1523#[cfg_attr(
1524 not(target_arch = "arm"),
1525 stable(feature = "neon_intrinsics", since = "1.59.0")
1526)]
1527#[cfg_attr(
1528 target_arch = "arm",
1529 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1530)]
1531pub fn vabs_s16(a: int16x4_t) -> int16x4_t {
1532 unsafe extern "unadjusted" {
1533 #[cfg_attr(
1534 any(target_arch = "aarch64", target_arch = "arm64ec"),
1535 link_name = "llvm.aarch64.neon.abs.v4i16"
1536 )]
1537 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i16")]
1538 fn _vabs_s16(a: int16x4_t) -> int16x4_t;
1539 }
1540 unsafe { _vabs_s16(a) }
1541}
1542#[doc = "Absolute value (wrapping)."]
1543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"]
1544#[inline]
1545#[target_feature(enable = "neon")]
1546#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1547#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1548#[cfg_attr(
1549 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1550 assert_instr(abs)
1551)]
1552#[cfg_attr(
1553 not(target_arch = "arm"),
1554 stable(feature = "neon_intrinsics", since = "1.59.0")
1555)]
1556#[cfg_attr(
1557 target_arch = "arm",
1558 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1559)]
1560pub fn vabsq_s16(a: int16x8_t) -> int16x8_t {
1561 unsafe extern "unadjusted" {
1562 #[cfg_attr(
1563 any(target_arch = "aarch64", target_arch = "arm64ec"),
1564 link_name = "llvm.aarch64.neon.abs.v8i16"
1565 )]
1566 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i16")]
1567 fn _vabsq_s16(a: int16x8_t) -> int16x8_t;
1568 }
1569 unsafe { _vabsq_s16(a) }
1570}
1571#[doc = "Absolute value (wrapping)."]
1572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"]
1573#[inline]
1574#[target_feature(enable = "neon")]
1575#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1576#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1577#[cfg_attr(
1578 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1579 assert_instr(abs)
1580)]
1581#[cfg_attr(
1582 not(target_arch = "arm"),
1583 stable(feature = "neon_intrinsics", since = "1.59.0")
1584)]
1585#[cfg_attr(
1586 target_arch = "arm",
1587 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1588)]
1589pub fn vabs_s32(a: int32x2_t) -> int32x2_t {
1590 unsafe extern "unadjusted" {
1591 #[cfg_attr(
1592 any(target_arch = "aarch64", target_arch = "arm64ec"),
1593 link_name = "llvm.aarch64.neon.abs.v2i32"
1594 )]
1595 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v2i32")]
1596 fn _vabs_s32(a: int32x2_t) -> int32x2_t;
1597 }
1598 unsafe { _vabs_s32(a) }
1599}
1600#[doc = "Absolute value (wrapping)."]
1601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"]
1602#[inline]
1603#[target_feature(enable = "neon")]
1604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1606#[cfg_attr(
1607 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1608 assert_instr(abs)
1609)]
1610#[cfg_attr(
1611 not(target_arch = "arm"),
1612 stable(feature = "neon_intrinsics", since = "1.59.0")
1613)]
1614#[cfg_attr(
1615 target_arch = "arm",
1616 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1617)]
1618pub fn vabsq_s32(a: int32x4_t) -> int32x4_t {
1619 unsafe extern "unadjusted" {
1620 #[cfg_attr(
1621 any(target_arch = "aarch64", target_arch = "arm64ec"),
1622 link_name = "llvm.aarch64.neon.abs.v4i32"
1623 )]
1624 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i32")]
1625 fn _vabsq_s32(a: int32x4_t) -> int32x4_t;
1626 }
1627 unsafe { _vabsq_s32(a) }
1628}
1629#[doc = "Floating-point absolute value"]
1630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"]
1631#[inline]
1632#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1633#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1634#[cfg_attr(
1635 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1636 assert_instr(fabs)
1637)]
1638#[target_feature(enable = "neon,fp16")]
1639#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1640pub fn vabsh_f16(a: f16) -> f16 {
1641 unsafe { simd_extract!(vabs_f16(vdup_n_f16(a)), 0) }
1642}
1643#[doc = "Floating-point Add (vector)."]
1644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"]
1645#[inline]
1646#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1647#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
1648#[cfg_attr(
1649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1650 assert_instr(fadd)
1651)]
1652#[target_feature(enable = "neon,fp16")]
1653#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1654pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
1655 unsafe { simd_add(a, b) }
1656}
1657#[doc = "Floating-point Add (vector)."]
1658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f16)"]
1659#[inline]
1660#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1661#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
1662#[cfg_attr(
1663 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1664 assert_instr(fadd)
1665)]
1666#[target_feature(enable = "neon,fp16")]
1667#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1668pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
1669 unsafe { simd_add(a, b) }
1670}
1671#[doc = "Vector add."]
1672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f32)"]
1673#[inline]
1674#[target_feature(enable = "neon")]
1675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1676#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1677#[cfg_attr(
1678 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1679 assert_instr(fadd)
1680)]
1681#[cfg_attr(
1682 not(target_arch = "arm"),
1683 stable(feature = "neon_intrinsics", since = "1.59.0")
1684)]
1685#[cfg_attr(
1686 target_arch = "arm",
1687 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1688)]
1689pub fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
1690 unsafe { simd_add(a, b) }
1691}
1692#[doc = "Vector add."]
1693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s16)"]
1694#[inline]
1695#[target_feature(enable = "neon")]
1696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1697#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1698#[cfg_attr(
1699 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1700 assert_instr(add)
1701)]
1702#[cfg_attr(
1703 not(target_arch = "arm"),
1704 stable(feature = "neon_intrinsics", since = "1.59.0")
1705)]
1706#[cfg_attr(
1707 target_arch = "arm",
1708 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1709)]
1710pub fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
1711 unsafe { simd_add(a, b) }
1712}
1713#[doc = "Vector add."]
1714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s32)"]
1715#[inline]
1716#[target_feature(enable = "neon")]
1717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1718#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1719#[cfg_attr(
1720 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1721 assert_instr(add)
1722)]
1723#[cfg_attr(
1724 not(target_arch = "arm"),
1725 stable(feature = "neon_intrinsics", since = "1.59.0")
1726)]
1727#[cfg_attr(
1728 target_arch = "arm",
1729 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1730)]
1731pub fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
1732 unsafe { simd_add(a, b) }
1733}
1734#[doc = "Vector add."]
1735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s8)"]
1736#[inline]
1737#[target_feature(enable = "neon")]
1738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1739#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1740#[cfg_attr(
1741 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1742 assert_instr(add)
1743)]
1744#[cfg_attr(
1745 not(target_arch = "arm"),
1746 stable(feature = "neon_intrinsics", since = "1.59.0")
1747)]
1748#[cfg_attr(
1749 target_arch = "arm",
1750 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1751)]
1752pub fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
1753 unsafe { simd_add(a, b) }
1754}
1755#[doc = "Vector add."]
1756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u16)"]
1757#[inline]
1758#[target_feature(enable = "neon")]
1759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1761#[cfg_attr(
1762 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1763 assert_instr(add)
1764)]
1765#[cfg_attr(
1766 not(target_arch = "arm"),
1767 stable(feature = "neon_intrinsics", since = "1.59.0")
1768)]
1769#[cfg_attr(
1770 target_arch = "arm",
1771 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1772)]
1773pub fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
1774 unsafe { simd_add(a, b) }
1775}
1776#[doc = "Vector add."]
1777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u32)"]
1778#[inline]
1779#[target_feature(enable = "neon")]
1780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1782#[cfg_attr(
1783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1784 assert_instr(add)
1785)]
1786#[cfg_attr(
1787 not(target_arch = "arm"),
1788 stable(feature = "neon_intrinsics", since = "1.59.0")
1789)]
1790#[cfg_attr(
1791 target_arch = "arm",
1792 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1793)]
1794pub fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
1795 unsafe { simd_add(a, b) }
1796}
1797#[doc = "Vector add."]
1798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u8)"]
1799#[inline]
1800#[target_feature(enable = "neon")]
1801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1802#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1803#[cfg_attr(
1804 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1805 assert_instr(add)
1806)]
1807#[cfg_attr(
1808 not(target_arch = "arm"),
1809 stable(feature = "neon_intrinsics", since = "1.59.0")
1810)]
1811#[cfg_attr(
1812 target_arch = "arm",
1813 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1814)]
1815pub fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
1816 unsafe { simd_add(a, b) }
1817}
1818#[doc = "Vector add."]
1819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f32)"]
1820#[inline]
1821#[target_feature(enable = "neon")]
1822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1823#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1824#[cfg_attr(
1825 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1826 assert_instr(fadd)
1827)]
1828#[cfg_attr(
1829 not(target_arch = "arm"),
1830 stable(feature = "neon_intrinsics", since = "1.59.0")
1831)]
1832#[cfg_attr(
1833 target_arch = "arm",
1834 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1835)]
1836pub fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
1837 unsafe { simd_add(a, b) }
1838}
1839#[doc = "Vector add."]
1840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s16)"]
1841#[inline]
1842#[target_feature(enable = "neon")]
1843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1845#[cfg_attr(
1846 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1847 assert_instr(add)
1848)]
1849#[cfg_attr(
1850 not(target_arch = "arm"),
1851 stable(feature = "neon_intrinsics", since = "1.59.0")
1852)]
1853#[cfg_attr(
1854 target_arch = "arm",
1855 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1856)]
1857pub fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
1858 unsafe { simd_add(a, b) }
1859}
1860#[doc = "Vector add."]
1861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s32)"]
1862#[inline]
1863#[target_feature(enable = "neon")]
1864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1865#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1866#[cfg_attr(
1867 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1868 assert_instr(add)
1869)]
1870#[cfg_attr(
1871 not(target_arch = "arm"),
1872 stable(feature = "neon_intrinsics", since = "1.59.0")
1873)]
1874#[cfg_attr(
1875 target_arch = "arm",
1876 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1877)]
1878pub fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
1879 unsafe { simd_add(a, b) }
1880}
1881#[doc = "Vector add."]
1882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s64)"]
1883#[inline]
1884#[target_feature(enable = "neon")]
1885#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1886#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1887#[cfg_attr(
1888 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1889 assert_instr(add)
1890)]
1891#[cfg_attr(
1892 not(target_arch = "arm"),
1893 stable(feature = "neon_intrinsics", since = "1.59.0")
1894)]
1895#[cfg_attr(
1896 target_arch = "arm",
1897 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1898)]
1899pub fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
1900 unsafe { simd_add(a, b) }
1901}
1902#[doc = "Vector add."]
1903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s8)"]
1904#[inline]
1905#[target_feature(enable = "neon")]
1906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1907#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1908#[cfg_attr(
1909 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1910 assert_instr(add)
1911)]
1912#[cfg_attr(
1913 not(target_arch = "arm"),
1914 stable(feature = "neon_intrinsics", since = "1.59.0")
1915)]
1916#[cfg_attr(
1917 target_arch = "arm",
1918 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1919)]
1920pub fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
1921 unsafe { simd_add(a, b) }
1922}
1923#[doc = "Vector add."]
1924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u16)"]
1925#[inline]
1926#[target_feature(enable = "neon")]
1927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1929#[cfg_attr(
1930 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1931 assert_instr(add)
1932)]
1933#[cfg_attr(
1934 not(target_arch = "arm"),
1935 stable(feature = "neon_intrinsics", since = "1.59.0")
1936)]
1937#[cfg_attr(
1938 target_arch = "arm",
1939 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1940)]
1941pub fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
1942 unsafe { simd_add(a, b) }
1943}
1944#[doc = "Vector add."]
1945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u32)"]
1946#[inline]
1947#[target_feature(enable = "neon")]
1948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1949#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1950#[cfg_attr(
1951 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1952 assert_instr(add)
1953)]
1954#[cfg_attr(
1955 not(target_arch = "arm"),
1956 stable(feature = "neon_intrinsics", since = "1.59.0")
1957)]
1958#[cfg_attr(
1959 target_arch = "arm",
1960 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1961)]
1962pub fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
1963 unsafe { simd_add(a, b) }
1964}
1965#[doc = "Vector add."]
1966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u64)"]
1967#[inline]
1968#[target_feature(enable = "neon")]
1969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1971#[cfg_attr(
1972 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1973 assert_instr(add)
1974)]
1975#[cfg_attr(
1976 not(target_arch = "arm"),
1977 stable(feature = "neon_intrinsics", since = "1.59.0")
1978)]
1979#[cfg_attr(
1980 target_arch = "arm",
1981 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1982)]
1983pub fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
1984 unsafe { simd_add(a, b) }
1985}
1986#[doc = "Vector add."]
1987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u8)"]
1988#[inline]
1989#[target_feature(enable = "neon")]
1990#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1991#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1992#[cfg_attr(
1993 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1994 assert_instr(add)
1995)]
1996#[cfg_attr(
1997 not(target_arch = "arm"),
1998 stable(feature = "neon_intrinsics", since = "1.59.0")
1999)]
2000#[cfg_attr(
2001 target_arch = "arm",
2002 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2003)]
2004pub fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
2005 unsafe { simd_add(a, b) }
2006}
2007#[doc = "Bitwise exclusive OR"]
2008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"]
2009#[inline]
2010#[target_feature(enable = "neon")]
2011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2013#[cfg_attr(
2014 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2015 assert_instr(nop)
2016)]
2017#[cfg_attr(
2018 not(target_arch = "arm"),
2019 stable(feature = "neon_intrinsics", since = "1.59.0")
2020)]
2021#[cfg_attr(
2022 target_arch = "arm",
2023 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2024)]
2025pub fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
2026 unsafe { simd_xor(a, b) }
2027}
2028#[doc = "Bitwise exclusive OR"]
2029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"]
2030#[inline]
2031#[target_feature(enable = "neon")]
2032#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2033#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2034#[cfg_attr(
2035 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2036 assert_instr(nop)
2037)]
2038#[cfg_attr(
2039 not(target_arch = "arm"),
2040 stable(feature = "neon_intrinsics", since = "1.59.0")
2041)]
2042#[cfg_attr(
2043 target_arch = "arm",
2044 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2045)]
2046pub fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
2047 unsafe { simd_xor(a, b) }
2048}
2049#[doc = "Bitwise exclusive OR"]
2050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"]
2051#[inline]
2052#[target_feature(enable = "neon")]
2053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2055#[cfg_attr(
2056 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2057 assert_instr(nop)
2058)]
2059#[cfg_attr(
2060 not(target_arch = "arm"),
2061 stable(feature = "neon_intrinsics", since = "1.59.0")
2062)]
2063#[cfg_attr(
2064 target_arch = "arm",
2065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2066)]
2067pub fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
2068 unsafe { simd_xor(a, b) }
2069}
2070#[doc = "Bitwise exclusive OR"]
2071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"]
2072#[inline]
2073#[target_feature(enable = "neon")]
2074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2076#[cfg_attr(
2077 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2078 assert_instr(nop)
2079)]
2080#[cfg_attr(
2081 not(target_arch = "arm"),
2082 stable(feature = "neon_intrinsics", since = "1.59.0")
2083)]
2084#[cfg_attr(
2085 target_arch = "arm",
2086 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2087)]
2088pub fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
2089 unsafe { simd_xor(a, b) }
2090}
2091#[doc = "Bitwise exclusive OR"]
2092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"]
2093#[inline]
2094#[target_feature(enable = "neon")]
2095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2097#[cfg_attr(
2098 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2099 assert_instr(nop)
2100)]
2101#[cfg_attr(
2102 not(target_arch = "arm"),
2103 stable(feature = "neon_intrinsics", since = "1.59.0")
2104)]
2105#[cfg_attr(
2106 target_arch = "arm",
2107 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2108)]
2109pub fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
2110 unsafe { simd_xor(a, b) }
2111}
2112#[doc = "Bitwise exclusive OR"]
2113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"]
2114#[inline]
2115#[target_feature(enable = "neon")]
2116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2118#[cfg_attr(
2119 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2120 assert_instr(nop)
2121)]
2122#[cfg_attr(
2123 not(target_arch = "arm"),
2124 stable(feature = "neon_intrinsics", since = "1.59.0")
2125)]
2126#[cfg_attr(
2127 target_arch = "arm",
2128 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2129)]
2130pub fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
2131 unsafe { simd_xor(a, b) }
2132}
2133#[doc = "Add"]
2134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddh_f16)"]
2135#[inline]
2136#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2137#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
2138#[cfg_attr(
2139 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2140 assert_instr(fadd)
2141)]
2142#[target_feature(enable = "neon,fp16")]
2143#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2144pub fn vaddh_f16(a: f16, b: f16) -> f16 {
2145 a + b
2146}
2147#[doc = "Add returning High Narrow (high half)."]
2148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s16)"]
2149#[inline]
2150#[target_feature(enable = "neon")]
2151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2153#[cfg_attr(
2154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2155 assert_instr(addhn2)
2156)]
2157#[cfg_attr(
2158 not(target_arch = "arm"),
2159 stable(feature = "neon_intrinsics", since = "1.59.0")
2160)]
2161#[cfg_attr(
2162 target_arch = "arm",
2163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2164)]
2165pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t {
2166 unsafe {
2167 let x = simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8)));
2168 simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
2169 }
2170}
2171#[doc = "Add returning High Narrow (high half)."]
2172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s32)"]
2173#[inline]
2174#[target_feature(enable = "neon")]
2175#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2176#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2177#[cfg_attr(
2178 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2179 assert_instr(addhn2)
2180)]
2181#[cfg_attr(
2182 not(target_arch = "arm"),
2183 stable(feature = "neon_intrinsics", since = "1.59.0")
2184)]
2185#[cfg_attr(
2186 target_arch = "arm",
2187 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2188)]
2189pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t {
2190 unsafe {
2191 let x = simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16)));
2192 simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7])
2193 }
2194}
2195#[doc = "Add returning High Narrow (high half)."]
2196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s64)"]
2197#[inline]
2198#[target_feature(enable = "neon")]
2199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2201#[cfg_attr(
2202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2203 assert_instr(addhn2)
2204)]
2205#[cfg_attr(
2206 not(target_arch = "arm"),
2207 stable(feature = "neon_intrinsics", since = "1.59.0")
2208)]
2209#[cfg_attr(
2210 target_arch = "arm",
2211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2212)]
2213pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t {
2214 unsafe {
2215 let x = simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32)));
2216 simd_shuffle!(r, x, [0, 1, 2, 3])
2217 }
2218}
2219#[doc = "Add returning High Narrow (high half)."]
2220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u16)"]
2221#[inline]
2222#[target_feature(enable = "neon")]
2223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2224#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2225#[cfg_attr(
2226 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2227 assert_instr(addhn2)
2228)]
2229#[cfg_attr(
2230 not(target_arch = "arm"),
2231 stable(feature = "neon_intrinsics", since = "1.59.0")
2232)]
2233#[cfg_attr(
2234 target_arch = "arm",
2235 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2236)]
2237pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t {
2238 unsafe {
2239 let x = simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8)));
2240 simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
2241 }
2242}
2243#[doc = "Add returning High Narrow (high half)."]
2244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u32)"]
2245#[inline]
2246#[target_feature(enable = "neon")]
2247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2249#[cfg_attr(
2250 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2251 assert_instr(addhn2)
2252)]
2253#[cfg_attr(
2254 not(target_arch = "arm"),
2255 stable(feature = "neon_intrinsics", since = "1.59.0")
2256)]
2257#[cfg_attr(
2258 target_arch = "arm",
2259 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2260)]
2261pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_t {
2262 unsafe {
2263 let x = simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16)));
2264 simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7])
2265 }
2266}
2267#[doc = "Add returning High Narrow (high half)."]
2268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u64)"]
2269#[inline]
2270#[target_feature(enable = "neon")]
2271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2272#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2273#[cfg_attr(
2274 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2275 assert_instr(addhn2)
2276)]
2277#[cfg_attr(
2278 not(target_arch = "arm"),
2279 stable(feature = "neon_intrinsics", since = "1.59.0")
2280)]
2281#[cfg_attr(
2282 target_arch = "arm",
2283 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2284)]
2285pub fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_t {
2286 unsafe {
2287 let x = simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32)));
2288 simd_shuffle!(r, x, [0, 1, 2, 3])
2289 }
2290}
2291#[doc = "Add returning High Narrow."]
2292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s16)"]
2293#[inline]
2294#[target_feature(enable = "neon")]
2295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2297#[cfg_attr(
2298 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2299 assert_instr(addhn)
2300)]
2301#[cfg_attr(
2302 not(target_arch = "arm"),
2303 stable(feature = "neon_intrinsics", since = "1.59.0")
2304)]
2305#[cfg_attr(
2306 target_arch = "arm",
2307 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2308)]
2309pub fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
2310 unsafe { simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8))) }
2311}
2312#[doc = "Add returning High Narrow."]
2313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s32)"]
2314#[inline]
2315#[target_feature(enable = "neon")]
2316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2318#[cfg_attr(
2319 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2320 assert_instr(addhn)
2321)]
2322#[cfg_attr(
2323 not(target_arch = "arm"),
2324 stable(feature = "neon_intrinsics", since = "1.59.0")
2325)]
2326#[cfg_attr(
2327 target_arch = "arm",
2328 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2329)]
2330pub fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
2331 unsafe { simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16))) }
2332}
2333#[doc = "Add returning High Narrow."]
2334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s64)"]
2335#[inline]
2336#[target_feature(enable = "neon")]
2337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2339#[cfg_attr(
2340 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2341 assert_instr(addhn)
2342)]
2343#[cfg_attr(
2344 not(target_arch = "arm"),
2345 stable(feature = "neon_intrinsics", since = "1.59.0")
2346)]
2347#[cfg_attr(
2348 target_arch = "arm",
2349 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2350)]
2351pub fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
2352 unsafe { simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32))) }
2353}
2354#[doc = "Add returning High Narrow."]
2355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u16)"]
2356#[inline]
2357#[target_feature(enable = "neon")]
2358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2360#[cfg_attr(
2361 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2362 assert_instr(addhn)
2363)]
2364#[cfg_attr(
2365 not(target_arch = "arm"),
2366 stable(feature = "neon_intrinsics", since = "1.59.0")
2367)]
2368#[cfg_attr(
2369 target_arch = "arm",
2370 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2371)]
2372pub fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
2373 unsafe { simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8))) }
2374}
2375#[doc = "Add returning High Narrow."]
2376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u32)"]
2377#[inline]
2378#[target_feature(enable = "neon")]
2379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2380#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2381#[cfg_attr(
2382 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2383 assert_instr(addhn)
2384)]
2385#[cfg_attr(
2386 not(target_arch = "arm"),
2387 stable(feature = "neon_intrinsics", since = "1.59.0")
2388)]
2389#[cfg_attr(
2390 target_arch = "arm",
2391 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2392)]
2393pub fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
2394 unsafe { simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16))) }
2395}
2396#[doc = "Add returning High Narrow."]
2397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u64)"]
2398#[inline]
2399#[target_feature(enable = "neon")]
2400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2402#[cfg_attr(
2403 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2404 assert_instr(addhn)
2405)]
2406#[cfg_attr(
2407 not(target_arch = "arm"),
2408 stable(feature = "neon_intrinsics", since = "1.59.0")
2409)]
2410#[cfg_attr(
2411 target_arch = "arm",
2412 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2413)]
2414pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
2415 unsafe { simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32))) }
2416}
2417#[doc = "Signed Add Long (vector, high half)."]
2418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s16)"]
2419#[inline]
2420#[target_feature(enable = "neon")]
2421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2423#[cfg_attr(
2424 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2425 assert_instr(saddl2)
2426)]
2427#[cfg_attr(
2428 not(target_arch = "arm"),
2429 stable(feature = "neon_intrinsics", since = "1.59.0")
2430)]
2431#[cfg_attr(
2432 target_arch = "arm",
2433 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2434)]
2435pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
2436 unsafe {
2437 let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
2438 let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2439 let a: int32x4_t = simd_cast(a);
2440 let b: int32x4_t = simd_cast(b);
2441 simd_add(a, b)
2442 }
2443}
2444#[doc = "Signed Add Long (vector, high half)."]
2445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s32)"]
2446#[inline]
2447#[target_feature(enable = "neon")]
2448#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2449#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2450#[cfg_attr(
2451 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2452 assert_instr(saddl2)
2453)]
2454#[cfg_attr(
2455 not(target_arch = "arm"),
2456 stable(feature = "neon_intrinsics", since = "1.59.0")
2457)]
2458#[cfg_attr(
2459 target_arch = "arm",
2460 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2461)]
2462pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
2463 unsafe {
2464 let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
2465 let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
2466 let a: int64x2_t = simd_cast(a);
2467 let b: int64x2_t = simd_cast(b);
2468 simd_add(a, b)
2469 }
2470}
2471#[doc = "Signed Add Long (vector, high half)."]
2472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s8)"]
2473#[inline]
2474#[target_feature(enable = "neon")]
2475#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2476#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2477#[cfg_attr(
2478 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2479 assert_instr(saddl2)
2480)]
2481#[cfg_attr(
2482 not(target_arch = "arm"),
2483 stable(feature = "neon_intrinsics", since = "1.59.0")
2484)]
2485#[cfg_attr(
2486 target_arch = "arm",
2487 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2488)]
2489pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
2490 unsafe {
2491 let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
2492 let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2493 let a: int16x8_t = simd_cast(a);
2494 let b: int16x8_t = simd_cast(b);
2495 simd_add(a, b)
2496 }
2497}
2498#[doc = "Signed Add Long (vector, high half)."]
2499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u16)"]
2500#[inline]
2501#[target_feature(enable = "neon")]
2502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2504#[cfg_attr(
2505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2506 assert_instr(uaddl2)
2507)]
2508#[cfg_attr(
2509 not(target_arch = "arm"),
2510 stable(feature = "neon_intrinsics", since = "1.59.0")
2511)]
2512#[cfg_attr(
2513 target_arch = "arm",
2514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2515)]
2516pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
2517 unsafe {
2518 let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
2519 let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2520 let a: uint32x4_t = simd_cast(a);
2521 let b: uint32x4_t = simd_cast(b);
2522 simd_add(a, b)
2523 }
2524}
2525#[doc = "Signed Add Long (vector, high half)."]
2526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u32)"]
2527#[inline]
2528#[target_feature(enable = "neon")]
2529#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2530#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2531#[cfg_attr(
2532 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2533 assert_instr(uaddl2)
2534)]
2535#[cfg_attr(
2536 not(target_arch = "arm"),
2537 stable(feature = "neon_intrinsics", since = "1.59.0")
2538)]
2539#[cfg_attr(
2540 target_arch = "arm",
2541 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2542)]
2543pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
2544 unsafe {
2545 let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
2546 let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
2547 let a: uint64x2_t = simd_cast(a);
2548 let b: uint64x2_t = simd_cast(b);
2549 simd_add(a, b)
2550 }
2551}
2552#[doc = "Signed Add Long (vector, high half)."]
2553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u8)"]
2554#[inline]
2555#[target_feature(enable = "neon")]
2556#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2558#[cfg_attr(
2559 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2560 assert_instr(uaddl2)
2561)]
2562#[cfg_attr(
2563 not(target_arch = "arm"),
2564 stable(feature = "neon_intrinsics", since = "1.59.0")
2565)]
2566#[cfg_attr(
2567 target_arch = "arm",
2568 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2569)]
2570pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
2571 unsafe {
2572 let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
2573 let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2574 let a: uint16x8_t = simd_cast(a);
2575 let b: uint16x8_t = simd_cast(b);
2576 simd_add(a, b)
2577 }
2578}
2579#[doc = "Add Long (vector)."]
2580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s16)"]
2581#[inline]
2582#[target_feature(enable = "neon")]
2583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2585#[cfg_attr(
2586 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2587 assert_instr(saddl)
2588)]
2589#[cfg_attr(
2590 not(target_arch = "arm"),
2591 stable(feature = "neon_intrinsics", since = "1.59.0")
2592)]
2593#[cfg_attr(
2594 target_arch = "arm",
2595 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2596)]
2597pub fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
2598 unsafe {
2599 let a: int32x4_t = simd_cast(a);
2600 let b: int32x4_t = simd_cast(b);
2601 simd_add(a, b)
2602 }
2603}
2604#[doc = "Add Long (vector)."]
2605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s32)"]
2606#[inline]
2607#[target_feature(enable = "neon")]
2608#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2609#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2610#[cfg_attr(
2611 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2612 assert_instr(saddl)
2613)]
2614#[cfg_attr(
2615 not(target_arch = "arm"),
2616 stable(feature = "neon_intrinsics", since = "1.59.0")
2617)]
2618#[cfg_attr(
2619 target_arch = "arm",
2620 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2621)]
2622pub fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
2623 unsafe {
2624 let a: int64x2_t = simd_cast(a);
2625 let b: int64x2_t = simd_cast(b);
2626 simd_add(a, b)
2627 }
2628}
2629#[doc = "Add Long (vector)."]
2630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s8)"]
2631#[inline]
2632#[target_feature(enable = "neon")]
2633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2634#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2635#[cfg_attr(
2636 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2637 assert_instr(saddl)
2638)]
2639#[cfg_attr(
2640 not(target_arch = "arm"),
2641 stable(feature = "neon_intrinsics", since = "1.59.0")
2642)]
2643#[cfg_attr(
2644 target_arch = "arm",
2645 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2646)]
2647pub fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
2648 unsafe {
2649 let a: int16x8_t = simd_cast(a);
2650 let b: int16x8_t = simd_cast(b);
2651 simd_add(a, b)
2652 }
2653}
2654#[doc = "Add Long (vector)."]
2655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u16)"]
2656#[inline]
2657#[target_feature(enable = "neon")]
2658#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2659#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2660#[cfg_attr(
2661 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2662 assert_instr(uaddl)
2663)]
2664#[cfg_attr(
2665 not(target_arch = "arm"),
2666 stable(feature = "neon_intrinsics", since = "1.59.0")
2667)]
2668#[cfg_attr(
2669 target_arch = "arm",
2670 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2671)]
2672pub fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
2673 unsafe {
2674 let a: uint32x4_t = simd_cast(a);
2675 let b: uint32x4_t = simd_cast(b);
2676 simd_add(a, b)
2677 }
2678}
2679#[doc = "Add Long (vector)."]
2680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u32)"]
2681#[inline]
2682#[target_feature(enable = "neon")]
2683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2685#[cfg_attr(
2686 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2687 assert_instr(uaddl)
2688)]
2689#[cfg_attr(
2690 not(target_arch = "arm"),
2691 stable(feature = "neon_intrinsics", since = "1.59.0")
2692)]
2693#[cfg_attr(
2694 target_arch = "arm",
2695 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2696)]
2697pub fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
2698 unsafe {
2699 let a: uint64x2_t = simd_cast(a);
2700 let b: uint64x2_t = simd_cast(b);
2701 simd_add(a, b)
2702 }
2703}
2704#[doc = "Add Long (vector)."]
2705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u8)"]
2706#[inline]
2707#[target_feature(enable = "neon")]
2708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2710#[cfg_attr(
2711 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2712 assert_instr(uaddl)
2713)]
2714#[cfg_attr(
2715 not(target_arch = "arm"),
2716 stable(feature = "neon_intrinsics", since = "1.59.0")
2717)]
2718#[cfg_attr(
2719 target_arch = "arm",
2720 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2721)]
2722pub fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
2723 unsafe {
2724 let a: uint16x8_t = simd_cast(a);
2725 let b: uint16x8_t = simd_cast(b);
2726 simd_add(a, b)
2727 }
2728}
2729#[doc = "Bitwise exclusive OR"]
2730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"]
2731#[inline]
2732#[target_feature(enable = "neon")]
2733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2734#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2735#[cfg_attr(
2736 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2737 assert_instr(nop)
2738)]
2739#[cfg_attr(
2740 not(target_arch = "arm"),
2741 stable(feature = "neon_intrinsics", since = "1.59.0")
2742)]
2743#[cfg_attr(
2744 target_arch = "arm",
2745 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2746)]
2747pub fn vaddq_p128(a: p128, b: p128) -> p128 {
2748 a ^ b
2749}
2750#[doc = "Add Wide (high half)."]
2751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s16)"]
2752#[inline]
2753#[target_feature(enable = "neon")]
2754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2755#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2756#[cfg_attr(
2757 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2758 assert_instr(saddw2)
2759)]
2760#[cfg_attr(
2761 not(target_arch = "arm"),
2762 stable(feature = "neon_intrinsics", since = "1.59.0")
2763)]
2764#[cfg_attr(
2765 target_arch = "arm",
2766 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2767)]
2768pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
2769 unsafe {
2770 let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2771 let b: int32x4_t = simd_cast(b);
2772 simd_add(a, b)
2773 }
2774}
2775#[doc = "Add Wide (high half)."]
2776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s32)"]
2777#[inline]
2778#[target_feature(enable = "neon")]
2779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2781#[cfg_attr(
2782 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2783 assert_instr(saddw2)
2784)]
2785#[cfg_attr(
2786 not(target_arch = "arm"),
2787 stable(feature = "neon_intrinsics", since = "1.59.0")
2788)]
2789#[cfg_attr(
2790 target_arch = "arm",
2791 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2792)]
2793pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
2794 unsafe {
2795 let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
2796 let b: int64x2_t = simd_cast(b);
2797 simd_add(a, b)
2798 }
2799}
2800#[doc = "Add Wide (high half)."]
2801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s8)"]
2802#[inline]
2803#[target_feature(enable = "neon")]
2804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2805#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2806#[cfg_attr(
2807 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2808 assert_instr(saddw2)
2809)]
2810#[cfg_attr(
2811 not(target_arch = "arm"),
2812 stable(feature = "neon_intrinsics", since = "1.59.0")
2813)]
2814#[cfg_attr(
2815 target_arch = "arm",
2816 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2817)]
2818pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
2819 unsafe {
2820 let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2821 let b: int16x8_t = simd_cast(b);
2822 simd_add(a, b)
2823 }
2824}
2825#[doc = "Add Wide (high half)."]
2826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u16)"]
2827#[inline]
2828#[target_feature(enable = "neon")]
2829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2831#[cfg_attr(
2832 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2833 assert_instr(uaddw2)
2834)]
2835#[cfg_attr(
2836 not(target_arch = "arm"),
2837 stable(feature = "neon_intrinsics", since = "1.59.0")
2838)]
2839#[cfg_attr(
2840 target_arch = "arm",
2841 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2842)]
2843pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
2844 unsafe {
2845 let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2846 let b: uint32x4_t = simd_cast(b);
2847 simd_add(a, b)
2848 }
2849}
2850#[doc = "Add Wide (high half)."]
2851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u32)"]
2852#[inline]
2853#[target_feature(enable = "neon")]
2854#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2855#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2856#[cfg_attr(
2857 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2858 assert_instr(uaddw2)
2859)]
2860#[cfg_attr(
2861 not(target_arch = "arm"),
2862 stable(feature = "neon_intrinsics", since = "1.59.0")
2863)]
2864#[cfg_attr(
2865 target_arch = "arm",
2866 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2867)]
2868pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
2869 unsafe {
2870 let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
2871 let b: uint64x2_t = simd_cast(b);
2872 simd_add(a, b)
2873 }
2874}
2875#[doc = "Add Wide (high half)."]
2876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u8)"]
2877#[inline]
2878#[target_feature(enable = "neon")]
2879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2881#[cfg_attr(
2882 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2883 assert_instr(uaddw2)
2884)]
2885#[cfg_attr(
2886 not(target_arch = "arm"),
2887 stable(feature = "neon_intrinsics", since = "1.59.0")
2888)]
2889#[cfg_attr(
2890 target_arch = "arm",
2891 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2892)]
2893pub fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
2894 unsafe {
2895 let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2896 let b: uint16x8_t = simd_cast(b);
2897 simd_add(a, b)
2898 }
2899}
2900#[doc = "Add Wide"]
2901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s16)"]
2902#[inline]
2903#[target_feature(enable = "neon")]
2904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2905#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2906#[cfg_attr(
2907 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2908 assert_instr(saddw)
2909)]
2910#[cfg_attr(
2911 not(target_arch = "arm"),
2912 stable(feature = "neon_intrinsics", since = "1.59.0")
2913)]
2914#[cfg_attr(
2915 target_arch = "arm",
2916 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2917)]
2918pub fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
2919 unsafe {
2920 let b: int32x4_t = simd_cast(b);
2921 simd_add(a, b)
2922 }
2923}
2924#[doc = "Add Wide"]
2925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s32)"]
2926#[inline]
2927#[target_feature(enable = "neon")]
2928#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2929#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2930#[cfg_attr(
2931 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2932 assert_instr(saddw)
2933)]
2934#[cfg_attr(
2935 not(target_arch = "arm"),
2936 stable(feature = "neon_intrinsics", since = "1.59.0")
2937)]
2938#[cfg_attr(
2939 target_arch = "arm",
2940 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2941)]
2942pub fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
2943 unsafe {
2944 let b: int64x2_t = simd_cast(b);
2945 simd_add(a, b)
2946 }
2947}
2948#[doc = "Add Wide"]
2949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s8)"]
2950#[inline]
2951#[target_feature(enable = "neon")]
2952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2953#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2954#[cfg_attr(
2955 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2956 assert_instr(saddw)
2957)]
2958#[cfg_attr(
2959 not(target_arch = "arm"),
2960 stable(feature = "neon_intrinsics", since = "1.59.0")
2961)]
2962#[cfg_attr(
2963 target_arch = "arm",
2964 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2965)]
2966pub fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
2967 unsafe {
2968 let b: int16x8_t = simd_cast(b);
2969 simd_add(a, b)
2970 }
2971}
2972#[doc = "Add Wide"]
2973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u16)"]
2974#[inline]
2975#[target_feature(enable = "neon")]
2976#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2977#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2978#[cfg_attr(
2979 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2980 assert_instr(uaddw)
2981)]
2982#[cfg_attr(
2983 not(target_arch = "arm"),
2984 stable(feature = "neon_intrinsics", since = "1.59.0")
2985)]
2986#[cfg_attr(
2987 target_arch = "arm",
2988 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2989)]
2990pub fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
2991 unsafe {
2992 let b: uint32x4_t = simd_cast(b);
2993 simd_add(a, b)
2994 }
2995}
2996#[doc = "Add Wide"]
2997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u32)"]
2998#[inline]
2999#[target_feature(enable = "neon")]
3000#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3001#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
3002#[cfg_attr(
3003 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3004 assert_instr(uaddw)
3005)]
3006#[cfg_attr(
3007 not(target_arch = "arm"),
3008 stable(feature = "neon_intrinsics", since = "1.59.0")
3009)]
3010#[cfg_attr(
3011 target_arch = "arm",
3012 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3013)]
3014pub fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
3015 unsafe {
3016 let b: uint64x2_t = simd_cast(b);
3017 simd_add(a, b)
3018 }
3019}
3020#[doc = "Add Wide"]
3021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u8)"]
3022#[inline]
3023#[target_feature(enable = "neon")]
3024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3025#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
3026#[cfg_attr(
3027 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3028 assert_instr(uaddw)
3029)]
3030#[cfg_attr(
3031 not(target_arch = "arm"),
3032 stable(feature = "neon_intrinsics", since = "1.59.0")
3033)]
3034#[cfg_attr(
3035 target_arch = "arm",
3036 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3037)]
3038pub fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
3039 unsafe {
3040 let b: uint16x8_t = simd_cast(b);
3041 simd_add(a, b)
3042 }
3043}
3044#[doc = "AES single round encryption."]
3045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"]
3046#[inline]
3047#[target_feature(enable = "aes")]
3048#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3049#[cfg_attr(test, assert_instr(aesd))]
3050#[cfg_attr(
3051 target_arch = "arm",
3052 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3053)]
3054#[cfg_attr(
3055 not(target_arch = "arm"),
3056 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3057)]
3058pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
3059 unsafe extern "unadjusted" {
3060 #[cfg_attr(
3061 any(target_arch = "aarch64", target_arch = "arm64ec"),
3062 link_name = "llvm.aarch64.crypto.aesd"
3063 )]
3064 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")]
3065 fn _vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
3066 }
3067 unsafe { _vaesdq_u8(data, key) }
3068}
3069#[doc = "AES single round encryption."]
3070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"]
3071#[inline]
3072#[target_feature(enable = "aes")]
3073#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3074#[cfg_attr(test, assert_instr(aese))]
3075#[cfg_attr(
3076 target_arch = "arm",
3077 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3078)]
3079#[cfg_attr(
3080 not(target_arch = "arm"),
3081 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3082)]
3083pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
3084 unsafe extern "unadjusted" {
3085 #[cfg_attr(
3086 any(target_arch = "aarch64", target_arch = "arm64ec"),
3087 link_name = "llvm.aarch64.crypto.aese"
3088 )]
3089 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")]
3090 fn _vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
3091 }
3092 unsafe { _vaeseq_u8(data, key) }
3093}
3094#[doc = "AES inverse mix columns."]
3095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"]
3096#[inline]
3097#[target_feature(enable = "aes")]
3098#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3099#[cfg_attr(test, assert_instr(aesimc))]
3100#[cfg_attr(
3101 target_arch = "arm",
3102 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3103)]
3104#[cfg_attr(
3105 not(target_arch = "arm"),
3106 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3107)]
3108pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
3109 unsafe extern "unadjusted" {
3110 #[cfg_attr(
3111 any(target_arch = "aarch64", target_arch = "arm64ec"),
3112 link_name = "llvm.aarch64.crypto.aesimc"
3113 )]
3114 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")]
3115 fn _vaesimcq_u8(data: uint8x16_t) -> uint8x16_t;
3116 }
3117 unsafe { _vaesimcq_u8(data) }
3118}
3119#[doc = "AES mix columns."]
3120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"]
3121#[inline]
3122#[target_feature(enable = "aes")]
3123#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3124#[cfg_attr(test, assert_instr(aesmc))]
3125#[cfg_attr(
3126 target_arch = "arm",
3127 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3128)]
3129#[cfg_attr(
3130 not(target_arch = "arm"),
3131 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3132)]
3133pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
3134 unsafe extern "unadjusted" {
3135 #[cfg_attr(
3136 any(target_arch = "aarch64", target_arch = "arm64ec"),
3137 link_name = "llvm.aarch64.crypto.aesmc"
3138 )]
3139 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")]
3140 fn _vaesmcq_u8(data: uint8x16_t) -> uint8x16_t;
3141 }
3142 unsafe { _vaesmcq_u8(data) }
3143}
3144#[doc = "Vector bitwise and"]
3145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"]
3146#[inline]
3147#[target_feature(enable = "neon")]
3148#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3149#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3150#[cfg_attr(
3151 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3152 assert_instr(and)
3153)]
3154#[cfg_attr(
3155 not(target_arch = "arm"),
3156 stable(feature = "neon_intrinsics", since = "1.59.0")
3157)]
3158#[cfg_attr(
3159 target_arch = "arm",
3160 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3161)]
3162pub fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
3163 unsafe { simd_and(a, b) }
3164}
3165#[doc = "Vector bitwise and"]
3166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"]
3167#[inline]
3168#[target_feature(enable = "neon")]
3169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3171#[cfg_attr(
3172 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3173 assert_instr(and)
3174)]
3175#[cfg_attr(
3176 not(target_arch = "arm"),
3177 stable(feature = "neon_intrinsics", since = "1.59.0")
3178)]
3179#[cfg_attr(
3180 target_arch = "arm",
3181 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3182)]
3183pub fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
3184 unsafe { simd_and(a, b) }
3185}
3186#[doc = "Vector bitwise and"]
3187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"]
3188#[inline]
3189#[target_feature(enable = "neon")]
3190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3191#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3192#[cfg_attr(
3193 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3194 assert_instr(and)
3195)]
3196#[cfg_attr(
3197 not(target_arch = "arm"),
3198 stable(feature = "neon_intrinsics", since = "1.59.0")
3199)]
3200#[cfg_attr(
3201 target_arch = "arm",
3202 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3203)]
3204pub fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
3205 unsafe { simd_and(a, b) }
3206}
3207#[doc = "Vector bitwise and"]
3208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"]
3209#[inline]
3210#[target_feature(enable = "neon")]
3211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3213#[cfg_attr(
3214 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3215 assert_instr(and)
3216)]
3217#[cfg_attr(
3218 not(target_arch = "arm"),
3219 stable(feature = "neon_intrinsics", since = "1.59.0")
3220)]
3221#[cfg_attr(
3222 target_arch = "arm",
3223 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3224)]
3225pub fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
3226 unsafe { simd_and(a, b) }
3227}
3228#[doc = "Vector bitwise and"]
3229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"]
3230#[inline]
3231#[target_feature(enable = "neon")]
3232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3233#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3234#[cfg_attr(
3235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3236 assert_instr(and)
3237)]
3238#[cfg_attr(
3239 not(target_arch = "arm"),
3240 stable(feature = "neon_intrinsics", since = "1.59.0")
3241)]
3242#[cfg_attr(
3243 target_arch = "arm",
3244 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3245)]
3246pub fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
3247 unsafe { simd_and(a, b) }
3248}
3249#[doc = "Vector bitwise and"]
3250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"]
3251#[inline]
3252#[target_feature(enable = "neon")]
3253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3254#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3255#[cfg_attr(
3256 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3257 assert_instr(and)
3258)]
3259#[cfg_attr(
3260 not(target_arch = "arm"),
3261 stable(feature = "neon_intrinsics", since = "1.59.0")
3262)]
3263#[cfg_attr(
3264 target_arch = "arm",
3265 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3266)]
3267pub fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
3268 unsafe { simd_and(a, b) }
3269}
3270#[doc = "Vector bitwise and"]
3271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"]
3272#[inline]
3273#[target_feature(enable = "neon")]
3274#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3275#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3276#[cfg_attr(
3277 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3278 assert_instr(and)
3279)]
3280#[cfg_attr(
3281 not(target_arch = "arm"),
3282 stable(feature = "neon_intrinsics", since = "1.59.0")
3283)]
3284#[cfg_attr(
3285 target_arch = "arm",
3286 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3287)]
3288pub fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
3289 unsafe { simd_and(a, b) }
3290}
3291#[doc = "Vector bitwise and"]
3292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"]
3293#[inline]
3294#[target_feature(enable = "neon")]
3295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3297#[cfg_attr(
3298 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3299 assert_instr(and)
3300)]
3301#[cfg_attr(
3302 not(target_arch = "arm"),
3303 stable(feature = "neon_intrinsics", since = "1.59.0")
3304)]
3305#[cfg_attr(
3306 target_arch = "arm",
3307 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3308)]
3309pub fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
3310 unsafe { simd_and(a, b) }
3311}
3312#[doc = "Vector bitwise and"]
3313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"]
3314#[inline]
3315#[target_feature(enable = "neon")]
3316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3318#[cfg_attr(
3319 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3320 assert_instr(and)
3321)]
3322#[cfg_attr(
3323 not(target_arch = "arm"),
3324 stable(feature = "neon_intrinsics", since = "1.59.0")
3325)]
3326#[cfg_attr(
3327 target_arch = "arm",
3328 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3329)]
3330pub fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
3331 unsafe { simd_and(a, b) }
3332}
3333#[doc = "Vector bitwise and"]
3334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"]
3335#[inline]
3336#[target_feature(enable = "neon")]
3337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3339#[cfg_attr(
3340 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3341 assert_instr(and)
3342)]
3343#[cfg_attr(
3344 not(target_arch = "arm"),
3345 stable(feature = "neon_intrinsics", since = "1.59.0")
3346)]
3347#[cfg_attr(
3348 target_arch = "arm",
3349 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3350)]
3351pub fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
3352 unsafe { simd_and(a, b) }
3353}
3354#[doc = "Vector bitwise and"]
3355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"]
3356#[inline]
3357#[target_feature(enable = "neon")]
3358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3360#[cfg_attr(
3361 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3362 assert_instr(and)
3363)]
3364#[cfg_attr(
3365 not(target_arch = "arm"),
3366 stable(feature = "neon_intrinsics", since = "1.59.0")
3367)]
3368#[cfg_attr(
3369 target_arch = "arm",
3370 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3371)]
3372pub fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
3373 unsafe { simd_and(a, b) }
3374}
3375#[doc = "Vector bitwise and"]
3376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"]
3377#[inline]
3378#[target_feature(enable = "neon")]
3379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3380#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3381#[cfg_attr(
3382 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3383 assert_instr(and)
3384)]
3385#[cfg_attr(
3386 not(target_arch = "arm"),
3387 stable(feature = "neon_intrinsics", since = "1.59.0")
3388)]
3389#[cfg_attr(
3390 target_arch = "arm",
3391 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3392)]
3393pub fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
3394 unsafe { simd_and(a, b) }
3395}
3396#[doc = "Vector bitwise and"]
3397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"]
3398#[inline]
3399#[target_feature(enable = "neon")]
3400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3402#[cfg_attr(
3403 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3404 assert_instr(and)
3405)]
3406#[cfg_attr(
3407 not(target_arch = "arm"),
3408 stable(feature = "neon_intrinsics", since = "1.59.0")
3409)]
3410#[cfg_attr(
3411 target_arch = "arm",
3412 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3413)]
3414pub fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
3415 unsafe { simd_and(a, b) }
3416}
3417#[doc = "Vector bitwise and"]
3418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"]
3419#[inline]
3420#[target_feature(enable = "neon")]
3421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3423#[cfg_attr(
3424 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3425 assert_instr(and)
3426)]
3427#[cfg_attr(
3428 not(target_arch = "arm"),
3429 stable(feature = "neon_intrinsics", since = "1.59.0")
3430)]
3431#[cfg_attr(
3432 target_arch = "arm",
3433 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3434)]
3435pub fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
3436 unsafe { simd_and(a, b) }
3437}
3438#[doc = "Vector bitwise and"]
3439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"]
3440#[inline]
3441#[target_feature(enable = "neon")]
3442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3444#[cfg_attr(
3445 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3446 assert_instr(and)
3447)]
3448#[cfg_attr(
3449 not(target_arch = "arm"),
3450 stable(feature = "neon_intrinsics", since = "1.59.0")
3451)]
3452#[cfg_attr(
3453 target_arch = "arm",
3454 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3455)]
3456pub fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
3457 unsafe { simd_and(a, b) }
3458}
3459#[doc = "Vector bitwise and"]
3460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"]
3461#[inline]
3462#[target_feature(enable = "neon")]
3463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3465#[cfg_attr(
3466 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3467 assert_instr(and)
3468)]
3469#[cfg_attr(
3470 not(target_arch = "arm"),
3471 stable(feature = "neon_intrinsics", since = "1.59.0")
3472)]
3473#[cfg_attr(
3474 target_arch = "arm",
3475 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3476)]
3477pub fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
3478 unsafe { simd_and(a, b) }
3479}
3480#[doc = "Vector bitwise bit clear."]
3481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s16)"]
3482#[inline]
3483#[target_feature(enable = "neon")]
3484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3486#[cfg_attr(
3487 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3488 assert_instr(bic)
3489)]
3490#[cfg_attr(
3491 not(target_arch = "arm"),
3492 stable(feature = "neon_intrinsics", since = "1.59.0")
3493)]
3494#[cfg_attr(
3495 target_arch = "arm",
3496 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3497)]
3498pub fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
3499 let c = int16x4_t::splat(-1);
3500 unsafe { simd_and(simd_xor(b, c), a) }
3501}
3502#[doc = "Vector bitwise bit clear."]
3503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s32)"]
3504#[inline]
3505#[target_feature(enable = "neon")]
3506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3508#[cfg_attr(
3509 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3510 assert_instr(bic)
3511)]
3512#[cfg_attr(
3513 not(target_arch = "arm"),
3514 stable(feature = "neon_intrinsics", since = "1.59.0")
3515)]
3516#[cfg_attr(
3517 target_arch = "arm",
3518 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3519)]
3520pub fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
3521 let c = int32x2_t::splat(-1);
3522 unsafe { simd_and(simd_xor(b, c), a) }
3523}
3524#[doc = "Vector bitwise bit clear."]
3525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s64)"]
3526#[inline]
3527#[target_feature(enable = "neon")]
3528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3530#[cfg_attr(
3531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3532 assert_instr(bic)
3533)]
3534#[cfg_attr(
3535 not(target_arch = "arm"),
3536 stable(feature = "neon_intrinsics", since = "1.59.0")
3537)]
3538#[cfg_attr(
3539 target_arch = "arm",
3540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3541)]
3542pub fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
3543 let c = int64x1_t::splat(-1);
3544 unsafe { simd_and(simd_xor(b, c), a) }
3545}
3546#[doc = "Vector bitwise bit clear."]
3547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s8)"]
3548#[inline]
3549#[target_feature(enable = "neon")]
3550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3552#[cfg_attr(
3553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3554 assert_instr(bic)
3555)]
3556#[cfg_attr(
3557 not(target_arch = "arm"),
3558 stable(feature = "neon_intrinsics", since = "1.59.0")
3559)]
3560#[cfg_attr(
3561 target_arch = "arm",
3562 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3563)]
3564pub fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
3565 let c = int8x8_t::splat(-1);
3566 unsafe { simd_and(simd_xor(b, c), a) }
3567}
3568#[doc = "Vector bitwise bit clear."]
3569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s16)"]
3570#[inline]
3571#[target_feature(enable = "neon")]
3572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3573#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3574#[cfg_attr(
3575 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3576 assert_instr(bic)
3577)]
3578#[cfg_attr(
3579 not(target_arch = "arm"),
3580 stable(feature = "neon_intrinsics", since = "1.59.0")
3581)]
3582#[cfg_attr(
3583 target_arch = "arm",
3584 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3585)]
3586pub fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
3587 let c = int16x8_t::splat(-1);
3588 unsafe { simd_and(simd_xor(b, c), a) }
3589}
3590#[doc = "Vector bitwise bit clear."]
3591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s32)"]
3592#[inline]
3593#[target_feature(enable = "neon")]
3594#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3595#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3596#[cfg_attr(
3597 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3598 assert_instr(bic)
3599)]
3600#[cfg_attr(
3601 not(target_arch = "arm"),
3602 stable(feature = "neon_intrinsics", since = "1.59.0")
3603)]
3604#[cfg_attr(
3605 target_arch = "arm",
3606 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3607)]
3608pub fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
3609 let c = int32x4_t::splat(-1);
3610 unsafe { simd_and(simd_xor(b, c), a) }
3611}
3612#[doc = "Vector bitwise bit clear."]
3613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s64)"]
3614#[inline]
3615#[target_feature(enable = "neon")]
3616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3618#[cfg_attr(
3619 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3620 assert_instr(bic)
3621)]
3622#[cfg_attr(
3623 not(target_arch = "arm"),
3624 stable(feature = "neon_intrinsics", since = "1.59.0")
3625)]
3626#[cfg_attr(
3627 target_arch = "arm",
3628 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3629)]
3630pub fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
3631 let c = int64x2_t::splat(-1);
3632 unsafe { simd_and(simd_xor(b, c), a) }
3633}
3634#[doc = "Vector bitwise bit clear."]
3635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s8)"]
3636#[inline]
3637#[target_feature(enable = "neon")]
3638#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3639#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3640#[cfg_attr(
3641 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3642 assert_instr(bic)
3643)]
3644#[cfg_attr(
3645 not(target_arch = "arm"),
3646 stable(feature = "neon_intrinsics", since = "1.59.0")
3647)]
3648#[cfg_attr(
3649 target_arch = "arm",
3650 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3651)]
3652pub fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
3653 let c = int8x16_t::splat(-1);
3654 unsafe { simd_and(simd_xor(b, c), a) }
3655}
3656#[doc = "Vector bitwise bit clear."]
3657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u16)"]
3658#[inline]
3659#[target_feature(enable = "neon")]
3660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3661#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3662#[cfg_attr(
3663 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3664 assert_instr(bic)
3665)]
3666#[cfg_attr(
3667 not(target_arch = "arm"),
3668 stable(feature = "neon_intrinsics", since = "1.59.0")
3669)]
3670#[cfg_attr(
3671 target_arch = "arm",
3672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3673)]
3674pub fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
3675 let c = int16x4_t::splat(-1);
3676 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3677}
3678#[doc = "Vector bitwise bit clear."]
3679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u32)"]
3680#[inline]
3681#[target_feature(enable = "neon")]
3682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3683#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3684#[cfg_attr(
3685 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3686 assert_instr(bic)
3687)]
3688#[cfg_attr(
3689 not(target_arch = "arm"),
3690 stable(feature = "neon_intrinsics", since = "1.59.0")
3691)]
3692#[cfg_attr(
3693 target_arch = "arm",
3694 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3695)]
3696pub fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
3697 let c = int32x2_t::splat(-1);
3698 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3699}
3700#[doc = "Vector bitwise bit clear."]
3701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u64)"]
3702#[inline]
3703#[target_feature(enable = "neon")]
3704#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3706#[cfg_attr(
3707 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3708 assert_instr(bic)
3709)]
3710#[cfg_attr(
3711 not(target_arch = "arm"),
3712 stable(feature = "neon_intrinsics", since = "1.59.0")
3713)]
3714#[cfg_attr(
3715 target_arch = "arm",
3716 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3717)]
3718pub fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
3719 let c = int64x1_t::splat(-1);
3720 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3721}
3722#[doc = "Vector bitwise bit clear."]
3723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u8)"]
3724#[inline]
3725#[target_feature(enable = "neon")]
3726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3727#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3728#[cfg_attr(
3729 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3730 assert_instr(bic)
3731)]
3732#[cfg_attr(
3733 not(target_arch = "arm"),
3734 stable(feature = "neon_intrinsics", since = "1.59.0")
3735)]
3736#[cfg_attr(
3737 target_arch = "arm",
3738 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3739)]
3740pub fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
3741 let c = int8x8_t::splat(-1);
3742 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3743}
3744#[doc = "Vector bitwise bit clear."]
3745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u16)"]
3746#[inline]
3747#[target_feature(enable = "neon")]
3748#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3749#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3750#[cfg_attr(
3751 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3752 assert_instr(bic)
3753)]
3754#[cfg_attr(
3755 not(target_arch = "arm"),
3756 stable(feature = "neon_intrinsics", since = "1.59.0")
3757)]
3758#[cfg_attr(
3759 target_arch = "arm",
3760 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3761)]
3762pub fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
3763 let c = int16x8_t::splat(-1);
3764 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3765}
3766#[doc = "Vector bitwise bit clear."]
3767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u32)"]
3768#[inline]
3769#[target_feature(enable = "neon")]
3770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3771#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3772#[cfg_attr(
3773 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3774 assert_instr(bic)
3775)]
3776#[cfg_attr(
3777 not(target_arch = "arm"),
3778 stable(feature = "neon_intrinsics", since = "1.59.0")
3779)]
3780#[cfg_attr(
3781 target_arch = "arm",
3782 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3783)]
3784pub fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
3785 let c = int32x4_t::splat(-1);
3786 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3787}
3788#[doc = "Vector bitwise bit clear."]
3789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u64)"]
3790#[inline]
3791#[target_feature(enable = "neon")]
3792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3793#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3794#[cfg_attr(
3795 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3796 assert_instr(bic)
3797)]
3798#[cfg_attr(
3799 not(target_arch = "arm"),
3800 stable(feature = "neon_intrinsics", since = "1.59.0")
3801)]
3802#[cfg_attr(
3803 target_arch = "arm",
3804 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3805)]
3806pub fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
3807 let c = int64x2_t::splat(-1);
3808 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3809}
3810#[doc = "Vector bitwise bit clear."]
3811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u8)"]
3812#[inline]
3813#[target_feature(enable = "neon")]
3814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3815#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3816#[cfg_attr(
3817 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3818 assert_instr(bic)
3819)]
3820#[cfg_attr(
3821 not(target_arch = "arm"),
3822 stable(feature = "neon_intrinsics", since = "1.59.0")
3823)]
3824#[cfg_attr(
3825 target_arch = "arm",
3826 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3827)]
3828pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
3829 let c = int8x16_t::splat(-1);
3830 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3831}
3832#[doc = "Bitwise Select."]
3833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f16)"]
3834#[inline]
3835#[target_feature(enable = "neon,fp16")]
3836#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3837#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3838#[cfg_attr(
3839 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3840 assert_instr(bsl)
3841)]
3842#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3843pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
3844 let not = int16x4_t::splat(-1);
3845 unsafe {
3846 transmute(simd_or(
3847 simd_and(a, transmute(b)),
3848 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3849 ))
3850 }
3851}
3852#[doc = "Bitwise Select."]
3853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f16)"]
3854#[inline]
3855#[target_feature(enable = "neon,fp16")]
3856#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3857#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3858#[cfg_attr(
3859 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3860 assert_instr(bsl)
3861)]
3862#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3863pub fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
3864 let not = int16x8_t::splat(-1);
3865 unsafe {
3866 transmute(simd_or(
3867 simd_and(a, transmute(b)),
3868 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3869 ))
3870 }
3871}
3872#[doc = "Bitwise Select."]
3873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f32)"]
3874#[inline]
3875#[target_feature(enable = "neon")]
3876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3877#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3878#[cfg_attr(
3879 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3880 assert_instr(bsl)
3881)]
3882#[cfg_attr(
3883 not(target_arch = "arm"),
3884 stable(feature = "neon_intrinsics", since = "1.59.0")
3885)]
3886#[cfg_attr(
3887 target_arch = "arm",
3888 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3889)]
3890pub fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
3891 let not = int32x2_t::splat(-1);
3892 unsafe {
3893 transmute(simd_or(
3894 simd_and(a, transmute(b)),
3895 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3896 ))
3897 }
3898}
3899#[doc = "Bitwise Select."]
3900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p16)"]
3901#[inline]
3902#[target_feature(enable = "neon")]
3903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3904#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3905#[cfg_attr(
3906 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3907 assert_instr(bsl)
3908)]
3909#[cfg_attr(
3910 not(target_arch = "arm"),
3911 stable(feature = "neon_intrinsics", since = "1.59.0")
3912)]
3913#[cfg_attr(
3914 target_arch = "arm",
3915 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3916)]
3917pub fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_t {
3918 let not = int16x4_t::splat(-1);
3919 unsafe {
3920 transmute(simd_or(
3921 simd_and(a, transmute(b)),
3922 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3923 ))
3924 }
3925}
3926#[doc = "Bitwise Select."]
3927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p8)"]
3928#[inline]
3929#[target_feature(enable = "neon")]
3930#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3931#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3932#[cfg_attr(
3933 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3934 assert_instr(bsl)
3935)]
3936#[cfg_attr(
3937 not(target_arch = "arm"),
3938 stable(feature = "neon_intrinsics", since = "1.59.0")
3939)]
3940#[cfg_attr(
3941 target_arch = "arm",
3942 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3943)]
3944pub fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t {
3945 let not = int8x8_t::splat(-1);
3946 unsafe {
3947 transmute(simd_or(
3948 simd_and(a, transmute(b)),
3949 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3950 ))
3951 }
3952}
3953#[doc = "Bitwise Select."]
3954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s16)"]
3955#[inline]
3956#[target_feature(enable = "neon")]
3957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3959#[cfg_attr(
3960 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3961 assert_instr(bsl)
3962)]
3963#[cfg_attr(
3964 not(target_arch = "arm"),
3965 stable(feature = "neon_intrinsics", since = "1.59.0")
3966)]
3967#[cfg_attr(
3968 target_arch = "arm",
3969 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3970)]
3971pub fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
3972 let not = int16x4_t::splat(-1);
3973 unsafe {
3974 transmute(simd_or(
3975 simd_and(a, transmute(b)),
3976 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3977 ))
3978 }
3979}
3980#[doc = "Bitwise Select."]
3981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s32)"]
3982#[inline]
3983#[target_feature(enable = "neon")]
3984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3986#[cfg_attr(
3987 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3988 assert_instr(bsl)
3989)]
3990#[cfg_attr(
3991 not(target_arch = "arm"),
3992 stable(feature = "neon_intrinsics", since = "1.59.0")
3993)]
3994#[cfg_attr(
3995 target_arch = "arm",
3996 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3997)]
3998pub fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
3999 let not = int32x2_t::splat(-1);
4000 unsafe {
4001 transmute(simd_or(
4002 simd_and(a, transmute(b)),
4003 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4004 ))
4005 }
4006}
4007#[doc = "Bitwise Select."]
4008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s64)"]
4009#[inline]
4010#[target_feature(enable = "neon")]
4011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4013#[cfg_attr(
4014 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4015 assert_instr(bsl)
4016)]
4017#[cfg_attr(
4018 not(target_arch = "arm"),
4019 stable(feature = "neon_intrinsics", since = "1.59.0")
4020)]
4021#[cfg_attr(
4022 target_arch = "arm",
4023 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4024)]
4025pub fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
4026 let not = int64x1_t::splat(-1);
4027 unsafe {
4028 transmute(simd_or(
4029 simd_and(a, transmute(b)),
4030 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4031 ))
4032 }
4033}
4034#[doc = "Bitwise Select."]
4035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s8)"]
4036#[inline]
4037#[target_feature(enable = "neon")]
4038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4040#[cfg_attr(
4041 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4042 assert_instr(bsl)
4043)]
4044#[cfg_attr(
4045 not(target_arch = "arm"),
4046 stable(feature = "neon_intrinsics", since = "1.59.0")
4047)]
4048#[cfg_attr(
4049 target_arch = "arm",
4050 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4051)]
4052pub fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
4053 let not = int8x8_t::splat(-1);
4054 unsafe {
4055 transmute(simd_or(
4056 simd_and(a, transmute(b)),
4057 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4058 ))
4059 }
4060}
4061#[doc = "Bitwise Select."]
4062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f32)"]
4063#[inline]
4064#[target_feature(enable = "neon")]
4065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4067#[cfg_attr(
4068 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4069 assert_instr(bsl)
4070)]
4071#[cfg_attr(
4072 not(target_arch = "arm"),
4073 stable(feature = "neon_intrinsics", since = "1.59.0")
4074)]
4075#[cfg_attr(
4076 target_arch = "arm",
4077 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4078)]
4079pub fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
4080 let not = int32x4_t::splat(-1);
4081 unsafe {
4082 transmute(simd_or(
4083 simd_and(a, transmute(b)),
4084 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4085 ))
4086 }
4087}
4088#[doc = "Bitwise Select."]
4089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p16)"]
4090#[inline]
4091#[target_feature(enable = "neon")]
4092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4093#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4094#[cfg_attr(
4095 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4096 assert_instr(bsl)
4097)]
4098#[cfg_attr(
4099 not(target_arch = "arm"),
4100 stable(feature = "neon_intrinsics", since = "1.59.0")
4101)]
4102#[cfg_attr(
4103 target_arch = "arm",
4104 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4105)]
4106pub fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8_t {
4107 let not = int16x8_t::splat(-1);
4108 unsafe {
4109 transmute(simd_or(
4110 simd_and(a, transmute(b)),
4111 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4112 ))
4113 }
4114}
4115#[doc = "Bitwise Select."]
4116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p8)"]
4117#[inline]
4118#[target_feature(enable = "neon")]
4119#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4120#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4121#[cfg_attr(
4122 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4123 assert_instr(bsl)
4124)]
4125#[cfg_attr(
4126 not(target_arch = "arm"),
4127 stable(feature = "neon_intrinsics", since = "1.59.0")
4128)]
4129#[cfg_attr(
4130 target_arch = "arm",
4131 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4132)]
4133pub fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_t {
4134 let not = int8x16_t::splat(-1);
4135 unsafe {
4136 transmute(simd_or(
4137 simd_and(a, transmute(b)),
4138 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4139 ))
4140 }
4141}
4142#[doc = "Bitwise Select."]
4143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s16)"]
4144#[inline]
4145#[target_feature(enable = "neon")]
4146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4147#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4148#[cfg_attr(
4149 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4150 assert_instr(bsl)
4151)]
4152#[cfg_attr(
4153 not(target_arch = "arm"),
4154 stable(feature = "neon_intrinsics", since = "1.59.0")
4155)]
4156#[cfg_attr(
4157 target_arch = "arm",
4158 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4159)]
4160pub fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
4161 let not = int16x8_t::splat(-1);
4162 unsafe {
4163 transmute(simd_or(
4164 simd_and(a, transmute(b)),
4165 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4166 ))
4167 }
4168}
4169#[doc = "Bitwise Select."]
4170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s32)"]
4171#[inline]
4172#[target_feature(enable = "neon")]
4173#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4174#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4175#[cfg_attr(
4176 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4177 assert_instr(bsl)
4178)]
4179#[cfg_attr(
4180 not(target_arch = "arm"),
4181 stable(feature = "neon_intrinsics", since = "1.59.0")
4182)]
4183#[cfg_attr(
4184 target_arch = "arm",
4185 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4186)]
4187pub fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
4188 let not = int32x4_t::splat(-1);
4189 unsafe {
4190 transmute(simd_or(
4191 simd_and(a, transmute(b)),
4192 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4193 ))
4194 }
4195}
4196#[doc = "Bitwise Select."]
4197#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s64)"]
4198#[inline]
4199#[target_feature(enable = "neon")]
4200#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4201#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4202#[cfg_attr(
4203 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4204 assert_instr(bsl)
4205)]
4206#[cfg_attr(
4207 not(target_arch = "arm"),
4208 stable(feature = "neon_intrinsics", since = "1.59.0")
4209)]
4210#[cfg_attr(
4211 target_arch = "arm",
4212 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4213)]
4214pub fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
4215 let not = int64x2_t::splat(-1);
4216 unsafe {
4217 transmute(simd_or(
4218 simd_and(a, transmute(b)),
4219 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4220 ))
4221 }
4222}
4223#[doc = "Bitwise Select."]
4224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s8)"]
4225#[inline]
4226#[target_feature(enable = "neon")]
4227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4229#[cfg_attr(
4230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4231 assert_instr(bsl)
4232)]
4233#[cfg_attr(
4234 not(target_arch = "arm"),
4235 stable(feature = "neon_intrinsics", since = "1.59.0")
4236)]
4237#[cfg_attr(
4238 target_arch = "arm",
4239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4240)]
4241pub fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
4242 let not = int8x16_t::splat(-1);
4243 unsafe {
4244 transmute(simd_or(
4245 simd_and(a, transmute(b)),
4246 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4247 ))
4248 }
4249}
4250#[doc = "Bitwise Select."]
4251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u16)"]
4252#[inline]
4253#[target_feature(enable = "neon")]
4254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4255#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4256#[cfg_attr(
4257 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4258 assert_instr(bsl)
4259)]
4260#[cfg_attr(
4261 not(target_arch = "arm"),
4262 stable(feature = "neon_intrinsics", since = "1.59.0")
4263)]
4264#[cfg_attr(
4265 target_arch = "arm",
4266 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4267)]
4268pub fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
4269 let not = int16x4_t::splat(-1);
4270 unsafe {
4271 transmute(simd_or(
4272 simd_and(a, b),
4273 simd_and(simd_xor(a, transmute(not)), c),
4274 ))
4275 }
4276}
4277#[doc = "Bitwise Select."]
4278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u32)"]
4279#[inline]
4280#[target_feature(enable = "neon")]
4281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4283#[cfg_attr(
4284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4285 assert_instr(bsl)
4286)]
4287#[cfg_attr(
4288 not(target_arch = "arm"),
4289 stable(feature = "neon_intrinsics", since = "1.59.0")
4290)]
4291#[cfg_attr(
4292 target_arch = "arm",
4293 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4294)]
4295pub fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
4296 let not = int32x2_t::splat(-1);
4297 unsafe {
4298 transmute(simd_or(
4299 simd_and(a, b),
4300 simd_and(simd_xor(a, transmute(not)), c),
4301 ))
4302 }
4303}
4304#[doc = "Bitwise Select."]
4305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u64)"]
4306#[inline]
4307#[target_feature(enable = "neon")]
4308#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4309#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4310#[cfg_attr(
4311 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4312 assert_instr(bsl)
4313)]
4314#[cfg_attr(
4315 not(target_arch = "arm"),
4316 stable(feature = "neon_intrinsics", since = "1.59.0")
4317)]
4318#[cfg_attr(
4319 target_arch = "arm",
4320 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4321)]
4322pub fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_t {
4323 let not = int64x1_t::splat(-1);
4324 unsafe {
4325 transmute(simd_or(
4326 simd_and(a, b),
4327 simd_and(simd_xor(a, transmute(not)), c),
4328 ))
4329 }
4330}
4331#[doc = "Bitwise Select."]
4332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u8)"]
4333#[inline]
4334#[target_feature(enable = "neon")]
4335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4336#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4337#[cfg_attr(
4338 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4339 assert_instr(bsl)
4340)]
4341#[cfg_attr(
4342 not(target_arch = "arm"),
4343 stable(feature = "neon_intrinsics", since = "1.59.0")
4344)]
4345#[cfg_attr(
4346 target_arch = "arm",
4347 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4348)]
4349pub fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
4350 let not = int8x8_t::splat(-1);
4351 unsafe {
4352 transmute(simd_or(
4353 simd_and(a, b),
4354 simd_and(simd_xor(a, transmute(not)), c),
4355 ))
4356 }
4357}
4358#[doc = "Bitwise Select."]
4359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u16)"]
4360#[inline]
4361#[target_feature(enable = "neon")]
4362#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4363#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4364#[cfg_attr(
4365 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4366 assert_instr(bsl)
4367)]
4368#[cfg_attr(
4369 not(target_arch = "arm"),
4370 stable(feature = "neon_intrinsics", since = "1.59.0")
4371)]
4372#[cfg_attr(
4373 target_arch = "arm",
4374 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4375)]
4376pub fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
4377 let not = int16x8_t::splat(-1);
4378 unsafe {
4379 transmute(simd_or(
4380 simd_and(a, b),
4381 simd_and(simd_xor(a, transmute(not)), c),
4382 ))
4383 }
4384}
4385#[doc = "Bitwise Select."]
4386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u32)"]
4387#[inline]
4388#[target_feature(enable = "neon")]
4389#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4390#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4391#[cfg_attr(
4392 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4393 assert_instr(bsl)
4394)]
4395#[cfg_attr(
4396 not(target_arch = "arm"),
4397 stable(feature = "neon_intrinsics", since = "1.59.0")
4398)]
4399#[cfg_attr(
4400 target_arch = "arm",
4401 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4402)]
4403pub fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
4404 let not = int32x4_t::splat(-1);
4405 unsafe {
4406 transmute(simd_or(
4407 simd_and(a, b),
4408 simd_and(simd_xor(a, transmute(not)), c),
4409 ))
4410 }
4411}
4412#[doc = "Bitwise Select."]
4413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u64)"]
4414#[inline]
4415#[target_feature(enable = "neon")]
4416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4417#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4418#[cfg_attr(
4419 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4420 assert_instr(bsl)
4421)]
4422#[cfg_attr(
4423 not(target_arch = "arm"),
4424 stable(feature = "neon_intrinsics", since = "1.59.0")
4425)]
4426#[cfg_attr(
4427 target_arch = "arm",
4428 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4429)]
4430pub fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
4431 let not = int64x2_t::splat(-1);
4432 unsafe {
4433 transmute(simd_or(
4434 simd_and(a, b),
4435 simd_and(simd_xor(a, transmute(not)), c),
4436 ))
4437 }
4438}
4439#[doc = "Bitwise Select."]
4440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u8)"]
4441#[inline]
4442#[target_feature(enable = "neon")]
4443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4445#[cfg_attr(
4446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4447 assert_instr(bsl)
4448)]
4449#[cfg_attr(
4450 not(target_arch = "arm"),
4451 stable(feature = "neon_intrinsics", since = "1.59.0")
4452)]
4453#[cfg_attr(
4454 target_arch = "arm",
4455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4456)]
4457pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
4458 let not = int8x16_t::splat(-1);
4459 unsafe {
4460 transmute(simd_or(
4461 simd_and(a, b),
4462 simd_and(simd_xor(a, transmute(not)), c),
4463 ))
4464 }
4465}
4466#[doc = "Floating-point absolute compare greater than or equal"]
4467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f16)"]
4468#[inline]
4469#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4470#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4471#[cfg_attr(
4472 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4473 assert_instr(facge)
4474)]
4475#[target_feature(enable = "neon,fp16")]
4476#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4477pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4478 unsafe extern "unadjusted" {
4479 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i16.v4f16")]
4480 #[cfg_attr(
4481 any(target_arch = "aarch64", target_arch = "arm64ec"),
4482 link_name = "llvm.aarch64.neon.facge.v4i16.v4f16"
4483 )]
4484 fn _vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t;
4485 }
4486 unsafe { _vcage_f16(a, b) }
4487}
4488#[doc = "Floating-point absolute compare greater than or equal"]
4489#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f16)"]
4490#[inline]
4491#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4492#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4493#[cfg_attr(
4494 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4495 assert_instr(facge)
4496)]
4497#[target_feature(enable = "neon,fp16")]
4498#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4499pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4500 unsafe extern "unadjusted" {
4501 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v8i16.v8f16")]
4502 #[cfg_attr(
4503 any(target_arch = "aarch64", target_arch = "arm64ec"),
4504 link_name = "llvm.aarch64.neon.facge.v8i16.v8f16"
4505 )]
4506 fn _vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t;
4507 }
4508 unsafe { _vcageq_f16(a, b) }
4509}
4510#[doc = "Floating-point absolute compare greater than or equal"]
4511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"]
4512#[inline]
4513#[target_feature(enable = "neon")]
4514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4515#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4516#[cfg_attr(
4517 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4518 assert_instr(facge)
4519)]
4520#[cfg_attr(
4521 not(target_arch = "arm"),
4522 stable(feature = "neon_intrinsics", since = "1.59.0")
4523)]
4524#[cfg_attr(
4525 target_arch = "arm",
4526 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4527)]
4528pub fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4529 unsafe extern "unadjusted" {
4530 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v2i32.v2f32")]
4531 #[cfg_attr(
4532 any(target_arch = "aarch64", target_arch = "arm64ec"),
4533 link_name = "llvm.aarch64.neon.facge.v2i32.v2f32"
4534 )]
4535 fn _vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t;
4536 }
4537 unsafe { _vcage_f32(a, b) }
4538}
4539#[doc = "Floating-point absolute compare greater than or equal"]
4540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"]
4541#[inline]
4542#[target_feature(enable = "neon")]
4543#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4544#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4545#[cfg_attr(
4546 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4547 assert_instr(facge)
4548)]
4549#[cfg_attr(
4550 not(target_arch = "arm"),
4551 stable(feature = "neon_intrinsics", since = "1.59.0")
4552)]
4553#[cfg_attr(
4554 target_arch = "arm",
4555 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4556)]
4557pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4558 unsafe extern "unadjusted" {
4559 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i32.v4f32")]
4560 #[cfg_attr(
4561 any(target_arch = "aarch64", target_arch = "arm64ec"),
4562 link_name = "llvm.aarch64.neon.facge.v4i32.v4f32"
4563 )]
4564 fn _vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t;
4565 }
4566 unsafe { _vcageq_f32(a, b) }
4567}
4568#[doc = "Floating-point absolute compare greater than"]
4569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f16)"]
4570#[inline]
4571#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4572#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4573#[cfg_attr(
4574 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4575 assert_instr(facgt)
4576)]
4577#[target_feature(enable = "neon,fp16")]
4578#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4579pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4580 unsafe extern "unadjusted" {
4581 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i16.v4f16")]
4582 #[cfg_attr(
4583 any(target_arch = "aarch64", target_arch = "arm64ec"),
4584 link_name = "llvm.aarch64.neon.facgt.v4i16.v4f16"
4585 )]
4586 fn _vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t;
4587 }
4588 unsafe { _vcagt_f16(a, b) }
4589}
4590#[doc = "Floating-point absolute compare greater than"]
4591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f16)"]
4592#[inline]
4593#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4594#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4595#[cfg_attr(
4596 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4597 assert_instr(facgt)
4598)]
4599#[target_feature(enable = "neon,fp16")]
4600#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4601pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4602 unsafe extern "unadjusted" {
4603 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v8i16.v8f16")]
4604 #[cfg_attr(
4605 any(target_arch = "aarch64", target_arch = "arm64ec"),
4606 link_name = "llvm.aarch64.neon.facgt.v8i16.v8f16"
4607 )]
4608 fn _vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t;
4609 }
4610 unsafe { _vcagtq_f16(a, b) }
4611}
4612#[doc = "Floating-point absolute compare greater than"]
4613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"]
4614#[inline]
4615#[target_feature(enable = "neon")]
4616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4617#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4618#[cfg_attr(
4619 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4620 assert_instr(facgt)
4621)]
4622#[cfg_attr(
4623 not(target_arch = "arm"),
4624 stable(feature = "neon_intrinsics", since = "1.59.0")
4625)]
4626#[cfg_attr(
4627 target_arch = "arm",
4628 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4629)]
4630pub fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4631 unsafe extern "unadjusted" {
4632 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v2i32.v2f32")]
4633 #[cfg_attr(
4634 any(target_arch = "aarch64", target_arch = "arm64ec"),
4635 link_name = "llvm.aarch64.neon.facgt.v2i32.v2f32"
4636 )]
4637 fn _vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t;
4638 }
4639 unsafe { _vcagt_f32(a, b) }
4640}
4641#[doc = "Floating-point absolute compare greater than"]
4642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"]
4643#[inline]
4644#[target_feature(enable = "neon")]
4645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4646#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4647#[cfg_attr(
4648 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4649 assert_instr(facgt)
4650)]
4651#[cfg_attr(
4652 not(target_arch = "arm"),
4653 stable(feature = "neon_intrinsics", since = "1.59.0")
4654)]
4655#[cfg_attr(
4656 target_arch = "arm",
4657 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4658)]
4659pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4660 unsafe extern "unadjusted" {
4661 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i32.v4f32")]
4662 #[cfg_attr(
4663 any(target_arch = "aarch64", target_arch = "arm64ec"),
4664 link_name = "llvm.aarch64.neon.facgt.v4i32.v4f32"
4665 )]
4666 fn _vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t;
4667 }
4668 unsafe { _vcagtq_f32(a, b) }
4669}
4670#[doc = "Floating-point absolute compare less than or equal"]
4671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f16)"]
4672#[inline]
4673#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4674#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4675#[cfg_attr(
4676 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4677 assert_instr(facge)
4678)]
4679#[target_feature(enable = "neon,fp16")]
4680#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4681pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4682 vcage_f16(b, a)
4683}
4684#[doc = "Floating-point absolute compare less than or equal"]
4685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f16)"]
4686#[inline]
4687#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4688#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4689#[cfg_attr(
4690 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4691 assert_instr(facge)
4692)]
4693#[target_feature(enable = "neon,fp16")]
4694#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4695pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4696 vcageq_f16(b, a)
4697}
4698#[doc = "Floating-point absolute compare less than or equal"]
4699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"]
4700#[inline]
4701#[target_feature(enable = "neon")]
4702#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4703#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4704#[cfg_attr(
4705 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4706 assert_instr(facge)
4707)]
4708#[cfg_attr(
4709 not(target_arch = "arm"),
4710 stable(feature = "neon_intrinsics", since = "1.59.0")
4711)]
4712#[cfg_attr(
4713 target_arch = "arm",
4714 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4715)]
4716pub fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4717 vcage_f32(b, a)
4718}
4719#[doc = "Floating-point absolute compare less than or equal"]
4720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"]
4721#[inline]
4722#[target_feature(enable = "neon")]
4723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4724#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4725#[cfg_attr(
4726 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4727 assert_instr(facge)
4728)]
4729#[cfg_attr(
4730 not(target_arch = "arm"),
4731 stable(feature = "neon_intrinsics", since = "1.59.0")
4732)]
4733#[cfg_attr(
4734 target_arch = "arm",
4735 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4736)]
4737pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4738 vcageq_f32(b, a)
4739}
4740#[doc = "Floating-point absolute compare less than"]
4741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f16)"]
4742#[inline]
4743#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4744#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4745#[cfg_attr(
4746 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4747 assert_instr(facgt)
4748)]
4749#[target_feature(enable = "neon,fp16")]
4750#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4751pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4752 vcagt_f16(b, a)
4753}
4754#[doc = "Floating-point absolute compare less than"]
4755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f16)"]
4756#[inline]
4757#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4758#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4759#[cfg_attr(
4760 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4761 assert_instr(facgt)
4762)]
4763#[target_feature(enable = "neon,fp16")]
4764#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4765pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4766 vcagtq_f16(b, a)
4767}
4768#[doc = "Floating-point absolute compare less than"]
4769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"]
4770#[inline]
4771#[target_feature(enable = "neon")]
4772#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4773#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4774#[cfg_attr(
4775 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4776 assert_instr(facgt)
4777)]
4778#[cfg_attr(
4779 not(target_arch = "arm"),
4780 stable(feature = "neon_intrinsics", since = "1.59.0")
4781)]
4782#[cfg_attr(
4783 target_arch = "arm",
4784 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4785)]
4786pub fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4787 vcagt_f32(b, a)
4788}
4789#[doc = "Floating-point absolute compare less than"]
4790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"]
4791#[inline]
4792#[target_feature(enable = "neon")]
4793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4794#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4795#[cfg_attr(
4796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4797 assert_instr(facgt)
4798)]
4799#[cfg_attr(
4800 not(target_arch = "arm"),
4801 stable(feature = "neon_intrinsics", since = "1.59.0")
4802)]
4803#[cfg_attr(
4804 target_arch = "arm",
4805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4806)]
4807pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4808 vcagtq_f32(b, a)
4809}
4810#[doc = "Floating-point compare equal"]
4811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f16)"]
4812#[inline]
4813#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4814#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
4815#[cfg_attr(
4816 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4817 assert_instr(fcmeq)
4818)]
4819#[target_feature(enable = "neon,fp16")]
4820#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4821pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4822 unsafe { simd_eq(a, b) }
4823}
4824#[doc = "Floating-point compare equal"]
4825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f16)"]
4826#[inline]
4827#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4828#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
4829#[cfg_attr(
4830 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4831 assert_instr(fcmeq)
4832)]
4833#[target_feature(enable = "neon,fp16")]
4834#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4835pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4836 unsafe { simd_eq(a, b) }
4837}
4838#[doc = "Floating-point compare equal"]
4839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"]
4840#[inline]
4841#[target_feature(enable = "neon")]
4842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4843#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
4844#[cfg_attr(
4845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4846 assert_instr(fcmeq)
4847)]
4848#[cfg_attr(
4849 not(target_arch = "arm"),
4850 stable(feature = "neon_intrinsics", since = "1.59.0")
4851)]
4852#[cfg_attr(
4853 target_arch = "arm",
4854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4855)]
4856pub fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4857 unsafe { simd_eq(a, b) }
4858}
4859#[doc = "Floating-point compare equal"]
4860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"]
4861#[inline]
4862#[target_feature(enable = "neon")]
4863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4864#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
4865#[cfg_attr(
4866 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4867 assert_instr(fcmeq)
4868)]
4869#[cfg_attr(
4870 not(target_arch = "arm"),
4871 stable(feature = "neon_intrinsics", since = "1.59.0")
4872)]
4873#[cfg_attr(
4874 target_arch = "arm",
4875 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4876)]
4877pub fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4878 unsafe { simd_eq(a, b) }
4879}
4880#[doc = "Compare bitwise Equal (vector)"]
4881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"]
4882#[inline]
4883#[target_feature(enable = "neon")]
4884#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4885#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
4886#[cfg_attr(
4887 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4888 assert_instr(cmeq)
4889)]
4890#[cfg_attr(
4891 not(target_arch = "arm"),
4892 stable(feature = "neon_intrinsics", since = "1.59.0")
4893)]
4894#[cfg_attr(
4895 target_arch = "arm",
4896 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4897)]
4898pub fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
4899 unsafe { simd_eq(a, b) }
4900}
4901#[doc = "Compare bitwise Equal (vector)"]
4902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"]
4903#[inline]
4904#[target_feature(enable = "neon")]
4905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4906#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
4907#[cfg_attr(
4908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4909 assert_instr(cmeq)
4910)]
4911#[cfg_attr(
4912 not(target_arch = "arm"),
4913 stable(feature = "neon_intrinsics", since = "1.59.0")
4914)]
4915#[cfg_attr(
4916 target_arch = "arm",
4917 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4918)]
4919pub fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
4920 unsafe { simd_eq(a, b) }
4921}
4922#[doc = "Compare bitwise Equal (vector)"]
4923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"]
4924#[inline]
4925#[target_feature(enable = "neon")]
4926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4927#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
4928#[cfg_attr(
4929 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4930 assert_instr(cmeq)
4931)]
4932#[cfg_attr(
4933 not(target_arch = "arm"),
4934 stable(feature = "neon_intrinsics", since = "1.59.0")
4935)]
4936#[cfg_attr(
4937 target_arch = "arm",
4938 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4939)]
4940pub fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
4941 unsafe { simd_eq(a, b) }
4942}
4943#[doc = "Compare bitwise Equal (vector)"]
4944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"]
4945#[inline]
4946#[target_feature(enable = "neon")]
4947#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4948#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
4949#[cfg_attr(
4950 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4951 assert_instr(cmeq)
4952)]
4953#[cfg_attr(
4954 not(target_arch = "arm"),
4955 stable(feature = "neon_intrinsics", since = "1.59.0")
4956)]
4957#[cfg_attr(
4958 target_arch = "arm",
4959 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4960)]
4961pub fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
4962 unsafe { simd_eq(a, b) }
4963}
4964#[doc = "Compare bitwise Equal (vector)"]
4965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"]
4966#[inline]
4967#[target_feature(enable = "neon")]
4968#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4969#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
4970#[cfg_attr(
4971 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4972 assert_instr(cmeq)
4973)]
4974#[cfg_attr(
4975 not(target_arch = "arm"),
4976 stable(feature = "neon_intrinsics", since = "1.59.0")
4977)]
4978#[cfg_attr(
4979 target_arch = "arm",
4980 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4981)]
4982pub fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
4983 unsafe { simd_eq(a, b) }
4984}
4985#[doc = "Compare bitwise Equal (vector)"]
4986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"]
4987#[inline]
4988#[target_feature(enable = "neon")]
4989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4990#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
4991#[cfg_attr(
4992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4993 assert_instr(cmeq)
4994)]
4995#[cfg_attr(
4996 not(target_arch = "arm"),
4997 stable(feature = "neon_intrinsics", since = "1.59.0")
4998)]
4999#[cfg_attr(
5000 target_arch = "arm",
5001 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5002)]
5003pub fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
5004 unsafe { simd_eq(a, b) }
5005}
5006#[doc = "Compare bitwise Equal (vector)"]
5007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"]
5008#[inline]
5009#[target_feature(enable = "neon")]
5010#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5011#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5012#[cfg_attr(
5013 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5014 assert_instr(cmeq)
5015)]
5016#[cfg_attr(
5017 not(target_arch = "arm"),
5018 stable(feature = "neon_intrinsics", since = "1.59.0")
5019)]
5020#[cfg_attr(
5021 target_arch = "arm",
5022 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5023)]
5024pub fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5025 unsafe { simd_eq(a, b) }
5026}
5027#[doc = "Compare bitwise Equal (vector)"]
5028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"]
5029#[inline]
5030#[target_feature(enable = "neon")]
5031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5032#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5033#[cfg_attr(
5034 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5035 assert_instr(cmeq)
5036)]
5037#[cfg_attr(
5038 not(target_arch = "arm"),
5039 stable(feature = "neon_intrinsics", since = "1.59.0")
5040)]
5041#[cfg_attr(
5042 target_arch = "arm",
5043 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5044)]
5045pub fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5046 unsafe { simd_eq(a, b) }
5047}
5048#[doc = "Compare bitwise Equal (vector)"]
5049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"]
5050#[inline]
5051#[target_feature(enable = "neon")]
5052#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5053#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
5054#[cfg_attr(
5055 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5056 assert_instr(cmeq)
5057)]
5058#[cfg_attr(
5059 not(target_arch = "arm"),
5060 stable(feature = "neon_intrinsics", since = "1.59.0")
5061)]
5062#[cfg_attr(
5063 target_arch = "arm",
5064 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5065)]
5066pub fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5067 unsafe { simd_eq(a, b) }
5068}
5069#[doc = "Compare bitwise Equal (vector)"]
5070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"]
5071#[inline]
5072#[target_feature(enable = "neon")]
5073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5074#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
5075#[cfg_attr(
5076 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5077 assert_instr(cmeq)
5078)]
5079#[cfg_attr(
5080 not(target_arch = "arm"),
5081 stable(feature = "neon_intrinsics", since = "1.59.0")
5082)]
5083#[cfg_attr(
5084 target_arch = "arm",
5085 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5086)]
5087pub fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5088 unsafe { simd_eq(a, b) }
5089}
5090#[doc = "Compare bitwise Equal (vector)"]
5091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"]
5092#[inline]
5093#[target_feature(enable = "neon")]
5094#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5095#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
5096#[cfg_attr(
5097 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5098 assert_instr(cmeq)
5099)]
5100#[cfg_attr(
5101 not(target_arch = "arm"),
5102 stable(feature = "neon_intrinsics", since = "1.59.0")
5103)]
5104#[cfg_attr(
5105 target_arch = "arm",
5106 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5107)]
5108pub fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5109 unsafe { simd_eq(a, b) }
5110}
5111#[doc = "Compare bitwise Equal (vector)"]
5112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"]
5113#[inline]
5114#[target_feature(enable = "neon")]
5115#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5116#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
5117#[cfg_attr(
5118 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5119 assert_instr(cmeq)
5120)]
5121#[cfg_attr(
5122 not(target_arch = "arm"),
5123 stable(feature = "neon_intrinsics", since = "1.59.0")
5124)]
5125#[cfg_attr(
5126 target_arch = "arm",
5127 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5128)]
5129pub fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5130 unsafe { simd_eq(a, b) }
5131}
5132#[doc = "Compare bitwise Equal (vector)"]
5133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"]
5134#[inline]
5135#[target_feature(enable = "neon")]
5136#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5137#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5138#[cfg_attr(
5139 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5140 assert_instr(cmeq)
5141)]
5142#[cfg_attr(
5143 not(target_arch = "arm"),
5144 stable(feature = "neon_intrinsics", since = "1.59.0")
5145)]
5146#[cfg_attr(
5147 target_arch = "arm",
5148 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5149)]
5150pub fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
5151 unsafe { simd_eq(a, b) }
5152}
5153#[doc = "Compare bitwise Equal (vector)"]
5154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"]
5155#[inline]
5156#[target_feature(enable = "neon")]
5157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5158#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5159#[cfg_attr(
5160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5161 assert_instr(cmeq)
5162)]
5163#[cfg_attr(
5164 not(target_arch = "arm"),
5165 stable(feature = "neon_intrinsics", since = "1.59.0")
5166)]
5167#[cfg_attr(
5168 target_arch = "arm",
5169 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5170)]
5171pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
5172 unsafe { simd_eq(a, b) }
5173}
5174#[doc = "Floating-point compare greater than or equal"]
5175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f16)"]
5176#[inline]
5177#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5178#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5179#[cfg_attr(
5180 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5181 assert_instr(fcmge)
5182)]
5183#[target_feature(enable = "neon,fp16")]
5184#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5185pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5186 unsafe { simd_ge(a, b) }
5187}
5188#[doc = "Floating-point compare greater than or equal"]
5189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f16)"]
5190#[inline]
5191#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5192#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5193#[cfg_attr(
5194 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5195 assert_instr(fcmge)
5196)]
5197#[target_feature(enable = "neon,fp16")]
5198#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5199pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5200 unsafe { simd_ge(a, b) }
5201}
5202#[doc = "Floating-point compare greater than or equal"]
5203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"]
5204#[inline]
5205#[target_feature(enable = "neon")]
5206#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5207#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5208#[cfg_attr(
5209 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5210 assert_instr(fcmge)
5211)]
5212#[cfg_attr(
5213 not(target_arch = "arm"),
5214 stable(feature = "neon_intrinsics", since = "1.59.0")
5215)]
5216#[cfg_attr(
5217 target_arch = "arm",
5218 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5219)]
5220pub fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5221 unsafe { simd_ge(a, b) }
5222}
5223#[doc = "Floating-point compare greater than or equal"]
5224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"]
5225#[inline]
5226#[target_feature(enable = "neon")]
5227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5228#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5229#[cfg_attr(
5230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5231 assert_instr(fcmge)
5232)]
5233#[cfg_attr(
5234 not(target_arch = "arm"),
5235 stable(feature = "neon_intrinsics", since = "1.59.0")
5236)]
5237#[cfg_attr(
5238 target_arch = "arm",
5239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5240)]
5241pub fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5242 unsafe { simd_ge(a, b) }
5243}
5244#[doc = "Compare signed greater than or equal"]
5245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"]
5246#[inline]
5247#[target_feature(enable = "neon")]
5248#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5249#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5250#[cfg_attr(
5251 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5252 assert_instr(cmge)
5253)]
5254#[cfg_attr(
5255 not(target_arch = "arm"),
5256 stable(feature = "neon_intrinsics", since = "1.59.0")
5257)]
5258#[cfg_attr(
5259 target_arch = "arm",
5260 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5261)]
5262pub fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5263 unsafe { simd_ge(a, b) }
5264}
5265#[doc = "Compare signed greater than or equal"]
5266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"]
5267#[inline]
5268#[target_feature(enable = "neon")]
5269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5270#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5271#[cfg_attr(
5272 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5273 assert_instr(cmge)
5274)]
5275#[cfg_attr(
5276 not(target_arch = "arm"),
5277 stable(feature = "neon_intrinsics", since = "1.59.0")
5278)]
5279#[cfg_attr(
5280 target_arch = "arm",
5281 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5282)]
5283pub fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
5284 unsafe { simd_ge(a, b) }
5285}
5286#[doc = "Compare signed greater than or equal"]
5287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"]
5288#[inline]
5289#[target_feature(enable = "neon")]
5290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5291#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
5292#[cfg_attr(
5293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5294 assert_instr(cmge)
5295)]
5296#[cfg_attr(
5297 not(target_arch = "arm"),
5298 stable(feature = "neon_intrinsics", since = "1.59.0")
5299)]
5300#[cfg_attr(
5301 target_arch = "arm",
5302 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5303)]
5304pub fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
5305 unsafe { simd_ge(a, b) }
5306}
5307#[doc = "Compare signed greater than or equal"]
5308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"]
5309#[inline]
5310#[target_feature(enable = "neon")]
5311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5312#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
5313#[cfg_attr(
5314 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5315 assert_instr(cmge)
5316)]
5317#[cfg_attr(
5318 not(target_arch = "arm"),
5319 stable(feature = "neon_intrinsics", since = "1.59.0")
5320)]
5321#[cfg_attr(
5322 target_arch = "arm",
5323 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5324)]
5325pub fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
5326 unsafe { simd_ge(a, b) }
5327}
5328#[doc = "Compare signed greater than or equal"]
5329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"]
5330#[inline]
5331#[target_feature(enable = "neon")]
5332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5333#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
5334#[cfg_attr(
5335 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5336 assert_instr(cmge)
5337)]
5338#[cfg_attr(
5339 not(target_arch = "arm"),
5340 stable(feature = "neon_intrinsics", since = "1.59.0")
5341)]
5342#[cfg_attr(
5343 target_arch = "arm",
5344 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5345)]
5346pub fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
5347 unsafe { simd_ge(a, b) }
5348}
5349#[doc = "Compare signed greater than or equal"]
5350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"]
5351#[inline]
5352#[target_feature(enable = "neon")]
5353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5354#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
5355#[cfg_attr(
5356 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5357 assert_instr(cmge)
5358)]
5359#[cfg_attr(
5360 not(target_arch = "arm"),
5361 stable(feature = "neon_intrinsics", since = "1.59.0")
5362)]
5363#[cfg_attr(
5364 target_arch = "arm",
5365 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5366)]
5367pub fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
5368 unsafe { simd_ge(a, b) }
5369}
5370#[doc = "Compare unsigned greater than or equal"]
5371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"]
5372#[inline]
5373#[target_feature(enable = "neon")]
5374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5375#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
5376#[cfg_attr(
5377 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5378 assert_instr(cmhs)
5379)]
5380#[cfg_attr(
5381 not(target_arch = "arm"),
5382 stable(feature = "neon_intrinsics", since = "1.59.0")
5383)]
5384#[cfg_attr(
5385 target_arch = "arm",
5386 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5387)]
5388pub fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5389 unsafe { simd_ge(a, b) }
5390}
5391#[doc = "Compare unsigned greater than or equal"]
5392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"]
5393#[inline]
5394#[target_feature(enable = "neon")]
5395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5396#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
5397#[cfg_attr(
5398 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5399 assert_instr(cmhs)
5400)]
5401#[cfg_attr(
5402 not(target_arch = "arm"),
5403 stable(feature = "neon_intrinsics", since = "1.59.0")
5404)]
5405#[cfg_attr(
5406 target_arch = "arm",
5407 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5408)]
5409pub fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5410 unsafe { simd_ge(a, b) }
5411}
5412#[doc = "Compare unsigned greater than or equal"]
5413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"]
5414#[inline]
5415#[target_feature(enable = "neon")]
5416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5417#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
5418#[cfg_attr(
5419 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5420 assert_instr(cmhs)
5421)]
5422#[cfg_attr(
5423 not(target_arch = "arm"),
5424 stable(feature = "neon_intrinsics", since = "1.59.0")
5425)]
5426#[cfg_attr(
5427 target_arch = "arm",
5428 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5429)]
5430pub fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5431 unsafe { simd_ge(a, b) }
5432}
5433#[doc = "Compare unsigned greater than or equal"]
5434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"]
5435#[inline]
5436#[target_feature(enable = "neon")]
5437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5438#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
5439#[cfg_attr(
5440 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5441 assert_instr(cmhs)
5442)]
5443#[cfg_attr(
5444 not(target_arch = "arm"),
5445 stable(feature = "neon_intrinsics", since = "1.59.0")
5446)]
5447#[cfg_attr(
5448 target_arch = "arm",
5449 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5450)]
5451pub fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5452 unsafe { simd_ge(a, b) }
5453}
5454#[doc = "Compare unsigned greater than or equal"]
5455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"]
5456#[inline]
5457#[target_feature(enable = "neon")]
5458#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5459#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
5460#[cfg_attr(
5461 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5462 assert_instr(cmhs)
5463)]
5464#[cfg_attr(
5465 not(target_arch = "arm"),
5466 stable(feature = "neon_intrinsics", since = "1.59.0")
5467)]
5468#[cfg_attr(
5469 target_arch = "arm",
5470 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5471)]
5472pub fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5473 unsafe { simd_ge(a, b) }
5474}
5475#[doc = "Compare unsigned greater than or equal"]
5476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"]
5477#[inline]
5478#[target_feature(enable = "neon")]
5479#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5480#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
5481#[cfg_attr(
5482 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5483 assert_instr(cmhs)
5484)]
5485#[cfg_attr(
5486 not(target_arch = "arm"),
5487 stable(feature = "neon_intrinsics", since = "1.59.0")
5488)]
5489#[cfg_attr(
5490 target_arch = "arm",
5491 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5492)]
5493pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5494 unsafe { simd_ge(a, b) }
5495}
5496#[doc = "Floating-point compare greater than or equal to zero"]
5497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f16)"]
5498#[inline]
5499#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5500#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5501#[cfg_attr(
5502 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5503 assert_instr(fcmge)
5504)]
5505#[target_feature(enable = "neon,fp16")]
5506#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5507pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t {
5508 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
5509 unsafe { simd_ge(a, transmute(b)) }
5510}
5511#[doc = "Floating-point compare greater than or equal to zero"]
5512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f16)"]
5513#[inline]
5514#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5515#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5516#[cfg_attr(
5517 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5518 assert_instr(fcmge)
5519)]
5520#[target_feature(enable = "neon,fp16")]
5521#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5522pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t {
5523 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
5524 unsafe { simd_ge(a, transmute(b)) }
5525}
5526#[doc = "Floating-point compare greater than"]
5527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f16)"]
5528#[inline]
5529#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5530#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5531#[cfg_attr(
5532 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5533 assert_instr(fcmgt)
5534)]
5535#[target_feature(enable = "neon,fp16")]
5536#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5537pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5538 unsafe { simd_gt(a, b) }
5539}
5540#[doc = "Floating-point compare greater than"]
5541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f16)"]
5542#[inline]
5543#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5544#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5545#[cfg_attr(
5546 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5547 assert_instr(fcmgt)
5548)]
5549#[target_feature(enable = "neon,fp16")]
5550#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5551pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5552 unsafe { simd_gt(a, b) }
5553}
5554#[doc = "Floating-point compare greater than"]
5555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"]
5556#[inline]
5557#[target_feature(enable = "neon")]
5558#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5559#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
5560#[cfg_attr(
5561 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5562 assert_instr(fcmgt)
5563)]
5564#[cfg_attr(
5565 not(target_arch = "arm"),
5566 stable(feature = "neon_intrinsics", since = "1.59.0")
5567)]
5568#[cfg_attr(
5569 target_arch = "arm",
5570 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5571)]
5572pub fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5573 unsafe { simd_gt(a, b) }
5574}
5575#[doc = "Floating-point compare greater than"]
5576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"]
5577#[inline]
5578#[target_feature(enable = "neon")]
5579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5580#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
5581#[cfg_attr(
5582 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5583 assert_instr(fcmgt)
5584)]
5585#[cfg_attr(
5586 not(target_arch = "arm"),
5587 stable(feature = "neon_intrinsics", since = "1.59.0")
5588)]
5589#[cfg_attr(
5590 target_arch = "arm",
5591 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5592)]
5593pub fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5594 unsafe { simd_gt(a, b) }
5595}
5596#[doc = "Compare signed greater than"]
5597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"]
5598#[inline]
5599#[target_feature(enable = "neon")]
5600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5601#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
5602#[cfg_attr(
5603 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5604 assert_instr(cmgt)
5605)]
5606#[cfg_attr(
5607 not(target_arch = "arm"),
5608 stable(feature = "neon_intrinsics", since = "1.59.0")
5609)]
5610#[cfg_attr(
5611 target_arch = "arm",
5612 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5613)]
5614pub fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5615 unsafe { simd_gt(a, b) }
5616}
5617#[doc = "Compare signed greater than"]
5618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"]
5619#[inline]
5620#[target_feature(enable = "neon")]
5621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5622#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
5623#[cfg_attr(
5624 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5625 assert_instr(cmgt)
5626)]
5627#[cfg_attr(
5628 not(target_arch = "arm"),
5629 stable(feature = "neon_intrinsics", since = "1.59.0")
5630)]
5631#[cfg_attr(
5632 target_arch = "arm",
5633 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5634)]
5635pub fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
5636 unsafe { simd_gt(a, b) }
5637}
5638#[doc = "Compare signed greater than"]
5639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"]
5640#[inline]
5641#[target_feature(enable = "neon")]
5642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5643#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
5644#[cfg_attr(
5645 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5646 assert_instr(cmgt)
5647)]
5648#[cfg_attr(
5649 not(target_arch = "arm"),
5650 stable(feature = "neon_intrinsics", since = "1.59.0")
5651)]
5652#[cfg_attr(
5653 target_arch = "arm",
5654 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5655)]
5656pub fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
5657 unsafe { simd_gt(a, b) }
5658}
5659#[doc = "Compare signed greater than"]
5660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"]
5661#[inline]
5662#[target_feature(enable = "neon")]
5663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5664#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
5665#[cfg_attr(
5666 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5667 assert_instr(cmgt)
5668)]
5669#[cfg_attr(
5670 not(target_arch = "arm"),
5671 stable(feature = "neon_intrinsics", since = "1.59.0")
5672)]
5673#[cfg_attr(
5674 target_arch = "arm",
5675 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5676)]
5677pub fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
5678 unsafe { simd_gt(a, b) }
5679}
5680#[doc = "Compare signed greater than"]
5681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"]
5682#[inline]
5683#[target_feature(enable = "neon")]
5684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5685#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
5686#[cfg_attr(
5687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5688 assert_instr(cmgt)
5689)]
5690#[cfg_attr(
5691 not(target_arch = "arm"),
5692 stable(feature = "neon_intrinsics", since = "1.59.0")
5693)]
5694#[cfg_attr(
5695 target_arch = "arm",
5696 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5697)]
5698pub fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
5699 unsafe { simd_gt(a, b) }
5700}
5701#[doc = "Compare signed greater than"]
5702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"]
5703#[inline]
5704#[target_feature(enable = "neon")]
5705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5706#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
5707#[cfg_attr(
5708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5709 assert_instr(cmgt)
5710)]
5711#[cfg_attr(
5712 not(target_arch = "arm"),
5713 stable(feature = "neon_intrinsics", since = "1.59.0")
5714)]
5715#[cfg_attr(
5716 target_arch = "arm",
5717 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5718)]
5719pub fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
5720 unsafe { simd_gt(a, b) }
5721}
5722#[doc = "Compare unsigned greater than"]
5723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"]
5724#[inline]
5725#[target_feature(enable = "neon")]
5726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5727#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
5728#[cfg_attr(
5729 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5730 assert_instr(cmhi)
5731)]
5732#[cfg_attr(
5733 not(target_arch = "arm"),
5734 stable(feature = "neon_intrinsics", since = "1.59.0")
5735)]
5736#[cfg_attr(
5737 target_arch = "arm",
5738 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5739)]
5740pub fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5741 unsafe { simd_gt(a, b) }
5742}
5743#[doc = "Compare unsigned greater than"]
5744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"]
5745#[inline]
5746#[target_feature(enable = "neon")]
5747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5748#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
5749#[cfg_attr(
5750 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5751 assert_instr(cmhi)
5752)]
5753#[cfg_attr(
5754 not(target_arch = "arm"),
5755 stable(feature = "neon_intrinsics", since = "1.59.0")
5756)]
5757#[cfg_attr(
5758 target_arch = "arm",
5759 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5760)]
5761pub fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5762 unsafe { simd_gt(a, b) }
5763}
5764#[doc = "Compare unsigned greater than"]
5765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"]
5766#[inline]
5767#[target_feature(enable = "neon")]
5768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5769#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
5770#[cfg_attr(
5771 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5772 assert_instr(cmhi)
5773)]
5774#[cfg_attr(
5775 not(target_arch = "arm"),
5776 stable(feature = "neon_intrinsics", since = "1.59.0")
5777)]
5778#[cfg_attr(
5779 target_arch = "arm",
5780 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5781)]
5782pub fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5783 unsafe { simd_gt(a, b) }
5784}
5785#[doc = "Compare unsigned greater than"]
5786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"]
5787#[inline]
5788#[target_feature(enable = "neon")]
5789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5790#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
5791#[cfg_attr(
5792 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5793 assert_instr(cmhi)
5794)]
5795#[cfg_attr(
5796 not(target_arch = "arm"),
5797 stable(feature = "neon_intrinsics", since = "1.59.0")
5798)]
5799#[cfg_attr(
5800 target_arch = "arm",
5801 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5802)]
5803pub fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5804 unsafe { simd_gt(a, b) }
5805}
5806#[doc = "Compare unsigned greater than"]
5807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"]
5808#[inline]
5809#[target_feature(enable = "neon")]
5810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5811#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
5812#[cfg_attr(
5813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5814 assert_instr(cmhi)
5815)]
5816#[cfg_attr(
5817 not(target_arch = "arm"),
5818 stable(feature = "neon_intrinsics", since = "1.59.0")
5819)]
5820#[cfg_attr(
5821 target_arch = "arm",
5822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5823)]
5824pub fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5825 unsafe { simd_gt(a, b) }
5826}
5827#[doc = "Compare unsigned greater than"]
5828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"]
5829#[inline]
5830#[target_feature(enable = "neon")]
5831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5832#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
5833#[cfg_attr(
5834 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5835 assert_instr(cmhi)
5836)]
5837#[cfg_attr(
5838 not(target_arch = "arm"),
5839 stable(feature = "neon_intrinsics", since = "1.59.0")
5840)]
5841#[cfg_attr(
5842 target_arch = "arm",
5843 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5844)]
5845pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5846 unsafe { simd_gt(a, b) }
5847}
5848#[doc = "Floating-point compare greater than zero"]
5849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f16)"]
5850#[inline]
5851#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5852#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5853#[cfg_attr(
5854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5855 assert_instr(fcmgt)
5856)]
5857#[target_feature(enable = "neon,fp16")]
5858#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5859pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t {
5860 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
5861 unsafe { simd_gt(a, transmute(b)) }
5862}
5863#[doc = "Floating-point compare greater than zero"]
5864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f16)"]
5865#[inline]
5866#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5867#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5868#[cfg_attr(
5869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5870 assert_instr(fcmgt)
5871)]
5872#[target_feature(enable = "neon,fp16")]
5873#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5874pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t {
5875 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
5876 unsafe { simd_gt(a, transmute(b)) }
5877}
5878#[doc = "Floating-point compare less than or equal"]
5879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f16)"]
5880#[inline]
5881#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5882#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5883#[cfg_attr(
5884 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5885 assert_instr(fcmge)
5886)]
5887#[target_feature(enable = "neon,fp16")]
5888#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5889pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5890 unsafe { simd_le(a, b) }
5891}
5892#[doc = "Floating-point compare less than or equal"]
5893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f16)"]
5894#[inline]
5895#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5896#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5897#[cfg_attr(
5898 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5899 assert_instr(fcmge)
5900)]
5901#[target_feature(enable = "neon,fp16")]
5902#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5903pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5904 unsafe { simd_le(a, b) }
5905}
5906#[doc = "Floating-point compare less than or equal"]
5907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"]
5908#[inline]
5909#[target_feature(enable = "neon")]
5910#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5911#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5912#[cfg_attr(
5913 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5914 assert_instr(fcmge)
5915)]
5916#[cfg_attr(
5917 not(target_arch = "arm"),
5918 stable(feature = "neon_intrinsics", since = "1.59.0")
5919)]
5920#[cfg_attr(
5921 target_arch = "arm",
5922 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5923)]
5924pub fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5925 unsafe { simd_le(a, b) }
5926}
5927#[doc = "Floating-point compare less than or equal"]
5928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"]
5929#[inline]
5930#[target_feature(enable = "neon")]
5931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5932#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5933#[cfg_attr(
5934 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5935 assert_instr(fcmge)
5936)]
5937#[cfg_attr(
5938 not(target_arch = "arm"),
5939 stable(feature = "neon_intrinsics", since = "1.59.0")
5940)]
5941#[cfg_attr(
5942 target_arch = "arm",
5943 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5944)]
5945pub fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5946 unsafe { simd_le(a, b) }
5947}
5948#[doc = "Compare signed less than or equal"]
5949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"]
5950#[inline]
5951#[target_feature(enable = "neon")]
5952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5953#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5954#[cfg_attr(
5955 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5956 assert_instr(cmge)
5957)]
5958#[cfg_attr(
5959 not(target_arch = "arm"),
5960 stable(feature = "neon_intrinsics", since = "1.59.0")
5961)]
5962#[cfg_attr(
5963 target_arch = "arm",
5964 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5965)]
5966pub fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5967 unsafe { simd_le(a, b) }
5968}
5969#[doc = "Compare signed less than or equal"]
5970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"]
5971#[inline]
5972#[target_feature(enable = "neon")]
5973#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5974#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5975#[cfg_attr(
5976 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5977 assert_instr(cmge)
5978)]
5979#[cfg_attr(
5980 not(target_arch = "arm"),
5981 stable(feature = "neon_intrinsics", since = "1.59.0")
5982)]
5983#[cfg_attr(
5984 target_arch = "arm",
5985 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5986)]
5987pub fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
5988 unsafe { simd_le(a, b) }
5989}
5990#[doc = "Compare signed less than or equal"]
5991#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"]
5992#[inline]
5993#[target_feature(enable = "neon")]
5994#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5995#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
5996#[cfg_attr(
5997 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5998 assert_instr(cmge)
5999)]
6000#[cfg_attr(
6001 not(target_arch = "arm"),
6002 stable(feature = "neon_intrinsics", since = "1.59.0")
6003)]
6004#[cfg_attr(
6005 target_arch = "arm",
6006 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6007)]
6008pub fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
6009 unsafe { simd_le(a, b) }
6010}
6011#[doc = "Compare signed less than or equal"]
6012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"]
6013#[inline]
6014#[target_feature(enable = "neon")]
6015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6016#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
6017#[cfg_attr(
6018 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6019 assert_instr(cmge)
6020)]
6021#[cfg_attr(
6022 not(target_arch = "arm"),
6023 stable(feature = "neon_intrinsics", since = "1.59.0")
6024)]
6025#[cfg_attr(
6026 target_arch = "arm",
6027 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6028)]
6029pub fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
6030 unsafe { simd_le(a, b) }
6031}
6032#[doc = "Compare signed less than or equal"]
6033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"]
6034#[inline]
6035#[target_feature(enable = "neon")]
6036#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6037#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
6038#[cfg_attr(
6039 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6040 assert_instr(cmge)
6041)]
6042#[cfg_attr(
6043 not(target_arch = "arm"),
6044 stable(feature = "neon_intrinsics", since = "1.59.0")
6045)]
6046#[cfg_attr(
6047 target_arch = "arm",
6048 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6049)]
6050pub fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
6051 unsafe { simd_le(a, b) }
6052}
6053#[doc = "Compare signed less than or equal"]
6054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"]
6055#[inline]
6056#[target_feature(enable = "neon")]
6057#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6058#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
6059#[cfg_attr(
6060 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6061 assert_instr(cmge)
6062)]
6063#[cfg_attr(
6064 not(target_arch = "arm"),
6065 stable(feature = "neon_intrinsics", since = "1.59.0")
6066)]
6067#[cfg_attr(
6068 target_arch = "arm",
6069 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6070)]
6071pub fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
6072 unsafe { simd_le(a, b) }
6073}
6074#[doc = "Compare unsigned less than or equal"]
6075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"]
6076#[inline]
6077#[target_feature(enable = "neon")]
6078#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6079#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
6080#[cfg_attr(
6081 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6082 assert_instr(cmhs)
6083)]
6084#[cfg_attr(
6085 not(target_arch = "arm"),
6086 stable(feature = "neon_intrinsics", since = "1.59.0")
6087)]
6088#[cfg_attr(
6089 target_arch = "arm",
6090 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6091)]
6092pub fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
6093 unsafe { simd_le(a, b) }
6094}
6095#[doc = "Compare unsigned less than or equal"]
6096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"]
6097#[inline]
6098#[target_feature(enable = "neon")]
6099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6100#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
6101#[cfg_attr(
6102 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6103 assert_instr(cmhs)
6104)]
6105#[cfg_attr(
6106 not(target_arch = "arm"),
6107 stable(feature = "neon_intrinsics", since = "1.59.0")
6108)]
6109#[cfg_attr(
6110 target_arch = "arm",
6111 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6112)]
6113pub fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
6114 unsafe { simd_le(a, b) }
6115}
6116#[doc = "Compare unsigned less than or equal"]
6117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"]
6118#[inline]
6119#[target_feature(enable = "neon")]
6120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6121#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
6122#[cfg_attr(
6123 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6124 assert_instr(cmhs)
6125)]
6126#[cfg_attr(
6127 not(target_arch = "arm"),
6128 stable(feature = "neon_intrinsics", since = "1.59.0")
6129)]
6130#[cfg_attr(
6131 target_arch = "arm",
6132 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6133)]
6134pub fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
6135 unsafe { simd_le(a, b) }
6136}
6137#[doc = "Compare unsigned less than or equal"]
6138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"]
6139#[inline]
6140#[target_feature(enable = "neon")]
6141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6142#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
6143#[cfg_attr(
6144 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6145 assert_instr(cmhs)
6146)]
6147#[cfg_attr(
6148 not(target_arch = "arm"),
6149 stable(feature = "neon_intrinsics", since = "1.59.0")
6150)]
6151#[cfg_attr(
6152 target_arch = "arm",
6153 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6154)]
6155pub fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
6156 unsafe { simd_le(a, b) }
6157}
6158#[doc = "Compare unsigned less than or equal"]
6159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"]
6160#[inline]
6161#[target_feature(enable = "neon")]
6162#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6163#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
6164#[cfg_attr(
6165 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6166 assert_instr(cmhs)
6167)]
6168#[cfg_attr(
6169 not(target_arch = "arm"),
6170 stable(feature = "neon_intrinsics", since = "1.59.0")
6171)]
6172#[cfg_attr(
6173 target_arch = "arm",
6174 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6175)]
6176pub fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
6177 unsafe { simd_le(a, b) }
6178}
6179#[doc = "Compare unsigned less than or equal"]
6180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"]
6181#[inline]
6182#[target_feature(enable = "neon")]
6183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6184#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
6185#[cfg_attr(
6186 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6187 assert_instr(cmhs)
6188)]
6189#[cfg_attr(
6190 not(target_arch = "arm"),
6191 stable(feature = "neon_intrinsics", since = "1.59.0")
6192)]
6193#[cfg_attr(
6194 target_arch = "arm",
6195 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6196)]
6197pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
6198 unsafe { simd_le(a, b) }
6199}
6200#[doc = "Floating-point compare less than or equal to zero"]
6201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f16)"]
6202#[inline]
6203#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6204#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
6205#[cfg_attr(
6206 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6207 assert_instr(fcmle)
6208)]
6209#[target_feature(enable = "neon,fp16")]
6210#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6211pub fn vclez_f16(a: float16x4_t) -> uint16x4_t {
6212 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
6213 unsafe { simd_le(a, transmute(b)) }
6214}
6215#[doc = "Floating-point compare less than or equal to zero"]
6216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f16)"]
6217#[inline]
6218#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6219#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
6220#[cfg_attr(
6221 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6222 assert_instr(fcmle)
6223)]
6224#[target_feature(enable = "neon,fp16")]
6225#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6226pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t {
6227 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
6228 unsafe { simd_le(a, transmute(b)) }
6229}
6230#[doc = "Count leading sign bits"]
6231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"]
6232#[inline]
6233#[target_feature(enable = "neon")]
6234#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6235#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
6236#[cfg_attr(
6237 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6238 assert_instr(cls)
6239)]
6240#[cfg_attr(
6241 not(target_arch = "arm"),
6242 stable(feature = "neon_intrinsics", since = "1.59.0")
6243)]
6244#[cfg_attr(
6245 target_arch = "arm",
6246 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6247)]
6248pub fn vcls_s8(a: int8x8_t) -> int8x8_t {
6249 unsafe extern "unadjusted" {
6250 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i8")]
6251 #[cfg_attr(
6252 any(target_arch = "aarch64", target_arch = "arm64ec"),
6253 link_name = "llvm.aarch64.neon.cls.v8i8"
6254 )]
6255 fn _vcls_s8(a: int8x8_t) -> int8x8_t;
6256 }
6257 unsafe { _vcls_s8(a) }
6258}
6259#[doc = "Count leading sign bits"]
6260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"]
6261#[inline]
6262#[target_feature(enable = "neon")]
6263#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6264#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
6265#[cfg_attr(
6266 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6267 assert_instr(cls)
6268)]
6269#[cfg_attr(
6270 not(target_arch = "arm"),
6271 stable(feature = "neon_intrinsics", since = "1.59.0")
6272)]
6273#[cfg_attr(
6274 target_arch = "arm",
6275 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6276)]
6277pub fn vclsq_s8(a: int8x16_t) -> int8x16_t {
6278 unsafe extern "unadjusted" {
6279 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v16i8")]
6280 #[cfg_attr(
6281 any(target_arch = "aarch64", target_arch = "arm64ec"),
6282 link_name = "llvm.aarch64.neon.cls.v16i8"
6283 )]
6284 fn _vclsq_s8(a: int8x16_t) -> int8x16_t;
6285 }
6286 unsafe { _vclsq_s8(a) }
6287}
6288#[doc = "Count leading sign bits"]
6289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"]
6290#[inline]
6291#[target_feature(enable = "neon")]
6292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6293#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
6294#[cfg_attr(
6295 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6296 assert_instr(cls)
6297)]
6298#[cfg_attr(
6299 not(target_arch = "arm"),
6300 stable(feature = "neon_intrinsics", since = "1.59.0")
6301)]
6302#[cfg_attr(
6303 target_arch = "arm",
6304 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6305)]
6306pub fn vcls_s16(a: int16x4_t) -> int16x4_t {
6307 unsafe extern "unadjusted" {
6308 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i16")]
6309 #[cfg_attr(
6310 any(target_arch = "aarch64", target_arch = "arm64ec"),
6311 link_name = "llvm.aarch64.neon.cls.v4i16"
6312 )]
6313 fn _vcls_s16(a: int16x4_t) -> int16x4_t;
6314 }
6315 unsafe { _vcls_s16(a) }
6316}
6317#[doc = "Count leading sign bits"]
6318#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"]
6319#[inline]
6320#[target_feature(enable = "neon")]
6321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6322#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
6323#[cfg_attr(
6324 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6325 assert_instr(cls)
6326)]
6327#[cfg_attr(
6328 not(target_arch = "arm"),
6329 stable(feature = "neon_intrinsics", since = "1.59.0")
6330)]
6331#[cfg_attr(
6332 target_arch = "arm",
6333 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6334)]
6335pub fn vclsq_s16(a: int16x8_t) -> int16x8_t {
6336 unsafe extern "unadjusted" {
6337 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i16")]
6338 #[cfg_attr(
6339 any(target_arch = "aarch64", target_arch = "arm64ec"),
6340 link_name = "llvm.aarch64.neon.cls.v8i16"
6341 )]
6342 fn _vclsq_s16(a: int16x8_t) -> int16x8_t;
6343 }
6344 unsafe { _vclsq_s16(a) }
6345}
6346#[doc = "Count leading sign bits"]
6347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"]
6348#[inline]
6349#[target_feature(enable = "neon")]
6350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6351#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
6352#[cfg_attr(
6353 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6354 assert_instr(cls)
6355)]
6356#[cfg_attr(
6357 not(target_arch = "arm"),
6358 stable(feature = "neon_intrinsics", since = "1.59.0")
6359)]
6360#[cfg_attr(
6361 target_arch = "arm",
6362 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6363)]
6364pub fn vcls_s32(a: int32x2_t) -> int32x2_t {
6365 unsafe extern "unadjusted" {
6366 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v2i32")]
6367 #[cfg_attr(
6368 any(target_arch = "aarch64", target_arch = "arm64ec"),
6369 link_name = "llvm.aarch64.neon.cls.v2i32"
6370 )]
6371 fn _vcls_s32(a: int32x2_t) -> int32x2_t;
6372 }
6373 unsafe { _vcls_s32(a) }
6374}
6375#[doc = "Count leading sign bits"]
6376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"]
6377#[inline]
6378#[target_feature(enable = "neon")]
6379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6380#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
6381#[cfg_attr(
6382 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6383 assert_instr(cls)
6384)]
6385#[cfg_attr(
6386 not(target_arch = "arm"),
6387 stable(feature = "neon_intrinsics", since = "1.59.0")
6388)]
6389#[cfg_attr(
6390 target_arch = "arm",
6391 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6392)]
6393pub fn vclsq_s32(a: int32x4_t) -> int32x4_t {
6394 unsafe extern "unadjusted" {
6395 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i32")]
6396 #[cfg_attr(
6397 any(target_arch = "aarch64", target_arch = "arm64ec"),
6398 link_name = "llvm.aarch64.neon.cls.v4i32"
6399 )]
6400 fn _vclsq_s32(a: int32x4_t) -> int32x4_t;
6401 }
6402 unsafe { _vclsq_s32(a) }
6403}
6404#[doc = "Count leading sign bits"]
6405#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"]
6406#[inline]
6407#[target_feature(enable = "neon")]
6408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6410#[cfg_attr(
6411 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6412 assert_instr(cls)
6413)]
6414#[cfg_attr(
6415 not(target_arch = "arm"),
6416 stable(feature = "neon_intrinsics", since = "1.59.0")
6417)]
6418#[cfg_attr(
6419 target_arch = "arm",
6420 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6421)]
6422pub fn vcls_u8(a: uint8x8_t) -> int8x8_t {
6423 unsafe { vcls_s8(transmute(a)) }
6424}
6425#[doc = "Count leading sign bits"]
6426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"]
6427#[inline]
6428#[target_feature(enable = "neon")]
6429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6431#[cfg_attr(
6432 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6433 assert_instr(cls)
6434)]
6435#[cfg_attr(
6436 not(target_arch = "arm"),
6437 stable(feature = "neon_intrinsics", since = "1.59.0")
6438)]
6439#[cfg_attr(
6440 target_arch = "arm",
6441 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6442)]
6443pub fn vclsq_u8(a: uint8x16_t) -> int8x16_t {
6444 unsafe { vclsq_s8(transmute(a)) }
6445}
6446#[doc = "Count leading sign bits"]
6447#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"]
6448#[inline]
6449#[target_feature(enable = "neon")]
6450#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6451#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6452#[cfg_attr(
6453 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6454 assert_instr(cls)
6455)]
6456#[cfg_attr(
6457 not(target_arch = "arm"),
6458 stable(feature = "neon_intrinsics", since = "1.59.0")
6459)]
6460#[cfg_attr(
6461 target_arch = "arm",
6462 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6463)]
6464pub fn vcls_u16(a: uint16x4_t) -> int16x4_t {
6465 unsafe { vcls_s16(transmute(a)) }
6466}
6467#[doc = "Count leading sign bits"]
6468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"]
6469#[inline]
6470#[target_feature(enable = "neon")]
6471#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6472#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6473#[cfg_attr(
6474 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6475 assert_instr(cls)
6476)]
6477#[cfg_attr(
6478 not(target_arch = "arm"),
6479 stable(feature = "neon_intrinsics", since = "1.59.0")
6480)]
6481#[cfg_attr(
6482 target_arch = "arm",
6483 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6484)]
6485pub fn vclsq_u16(a: uint16x8_t) -> int16x8_t {
6486 unsafe { vclsq_s16(transmute(a)) }
6487}
6488#[doc = "Count leading sign bits"]
6489#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"]
6490#[inline]
6491#[target_feature(enable = "neon")]
6492#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6493#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6494#[cfg_attr(
6495 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6496 assert_instr(cls)
6497)]
6498#[cfg_attr(
6499 not(target_arch = "arm"),
6500 stable(feature = "neon_intrinsics", since = "1.59.0")
6501)]
6502#[cfg_attr(
6503 target_arch = "arm",
6504 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6505)]
6506pub fn vcls_u32(a: uint32x2_t) -> int32x2_t {
6507 unsafe { vcls_s32(transmute(a)) }
6508}
6509#[doc = "Count leading sign bits"]
6510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"]
6511#[inline]
6512#[target_feature(enable = "neon")]
6513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6515#[cfg_attr(
6516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6517 assert_instr(cls)
6518)]
6519#[cfg_attr(
6520 not(target_arch = "arm"),
6521 stable(feature = "neon_intrinsics", since = "1.59.0")
6522)]
6523#[cfg_attr(
6524 target_arch = "arm",
6525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6526)]
6527pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t {
6528 unsafe { vclsq_s32(transmute(a)) }
6529}
6530#[doc = "Floating-point compare less than"]
6531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f16)"]
6532#[inline]
6533#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6534#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
6535#[cfg_attr(
6536 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6537 assert_instr(fcmgt)
6538)]
6539#[target_feature(enable = "neon,fp16")]
6540#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6541pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
6542 unsafe { simd_lt(a, b) }
6543}
6544#[doc = "Floating-point compare less than"]
6545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f16)"]
6546#[inline]
6547#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6548#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
6549#[cfg_attr(
6550 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6551 assert_instr(fcmgt)
6552)]
6553#[target_feature(enable = "neon,fp16")]
6554#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6555pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
6556 unsafe { simd_lt(a, b) }
6557}
6558#[doc = "Floating-point compare less than"]
6559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"]
6560#[inline]
6561#[target_feature(enable = "neon")]
6562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6563#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
6564#[cfg_attr(
6565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6566 assert_instr(fcmgt)
6567)]
6568#[cfg_attr(
6569 not(target_arch = "arm"),
6570 stable(feature = "neon_intrinsics", since = "1.59.0")
6571)]
6572#[cfg_attr(
6573 target_arch = "arm",
6574 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6575)]
6576pub fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
6577 unsafe { simd_lt(a, b) }
6578}
6579#[doc = "Floating-point compare less than"]
6580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"]
6581#[inline]
6582#[target_feature(enable = "neon")]
6583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6584#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
6585#[cfg_attr(
6586 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6587 assert_instr(fcmgt)
6588)]
6589#[cfg_attr(
6590 not(target_arch = "arm"),
6591 stable(feature = "neon_intrinsics", since = "1.59.0")
6592)]
6593#[cfg_attr(
6594 target_arch = "arm",
6595 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6596)]
6597pub fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
6598 unsafe { simd_lt(a, b) }
6599}
6600#[doc = "Compare signed less than"]
6601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"]
6602#[inline]
6603#[target_feature(enable = "neon")]
6604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6605#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
6606#[cfg_attr(
6607 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6608 assert_instr(cmgt)
6609)]
6610#[cfg_attr(
6611 not(target_arch = "arm"),
6612 stable(feature = "neon_intrinsics", since = "1.59.0")
6613)]
6614#[cfg_attr(
6615 target_arch = "arm",
6616 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6617)]
6618pub fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
6619 unsafe { simd_lt(a, b) }
6620}
6621#[doc = "Compare signed less than"]
6622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"]
6623#[inline]
6624#[target_feature(enable = "neon")]
6625#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6626#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
6627#[cfg_attr(
6628 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6629 assert_instr(cmgt)
6630)]
6631#[cfg_attr(
6632 not(target_arch = "arm"),
6633 stable(feature = "neon_intrinsics", since = "1.59.0")
6634)]
6635#[cfg_attr(
6636 target_arch = "arm",
6637 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6638)]
6639pub fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
6640 unsafe { simd_lt(a, b) }
6641}
6642#[doc = "Compare signed less than"]
6643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"]
6644#[inline]
6645#[target_feature(enable = "neon")]
6646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6647#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
6648#[cfg_attr(
6649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6650 assert_instr(cmgt)
6651)]
6652#[cfg_attr(
6653 not(target_arch = "arm"),
6654 stable(feature = "neon_intrinsics", since = "1.59.0")
6655)]
6656#[cfg_attr(
6657 target_arch = "arm",
6658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6659)]
6660pub fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
6661 unsafe { simd_lt(a, b) }
6662}
6663#[doc = "Compare signed less than"]
6664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"]
6665#[inline]
6666#[target_feature(enable = "neon")]
6667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6668#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
6669#[cfg_attr(
6670 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6671 assert_instr(cmgt)
6672)]
6673#[cfg_attr(
6674 not(target_arch = "arm"),
6675 stable(feature = "neon_intrinsics", since = "1.59.0")
6676)]
6677#[cfg_attr(
6678 target_arch = "arm",
6679 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6680)]
6681pub fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
6682 unsafe { simd_lt(a, b) }
6683}
6684#[doc = "Compare signed less than"]
6685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"]
6686#[inline]
6687#[target_feature(enable = "neon")]
6688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6689#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
6690#[cfg_attr(
6691 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6692 assert_instr(cmgt)
6693)]
6694#[cfg_attr(
6695 not(target_arch = "arm"),
6696 stable(feature = "neon_intrinsics", since = "1.59.0")
6697)]
6698#[cfg_attr(
6699 target_arch = "arm",
6700 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6701)]
6702pub fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
6703 unsafe { simd_lt(a, b) }
6704}
6705#[doc = "Compare signed less than"]
6706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"]
6707#[inline]
6708#[target_feature(enable = "neon")]
6709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6710#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
6711#[cfg_attr(
6712 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6713 assert_instr(cmgt)
6714)]
6715#[cfg_attr(
6716 not(target_arch = "arm"),
6717 stable(feature = "neon_intrinsics", since = "1.59.0")
6718)]
6719#[cfg_attr(
6720 target_arch = "arm",
6721 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6722)]
6723pub fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
6724 unsafe { simd_lt(a, b) }
6725}
6726#[doc = "Compare unsigned less than"]
6727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"]
6728#[inline]
6729#[target_feature(enable = "neon")]
6730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6731#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
6732#[cfg_attr(
6733 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6734 assert_instr(cmhi)
6735)]
6736#[cfg_attr(
6737 not(target_arch = "arm"),
6738 stable(feature = "neon_intrinsics", since = "1.59.0")
6739)]
6740#[cfg_attr(
6741 target_arch = "arm",
6742 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6743)]
6744pub fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
6745 unsafe { simd_lt(a, b) }
6746}
6747#[doc = "Compare unsigned less than"]
6748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"]
6749#[inline]
6750#[target_feature(enable = "neon")]
6751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6752#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
6753#[cfg_attr(
6754 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6755 assert_instr(cmhi)
6756)]
6757#[cfg_attr(
6758 not(target_arch = "arm"),
6759 stable(feature = "neon_intrinsics", since = "1.59.0")
6760)]
6761#[cfg_attr(
6762 target_arch = "arm",
6763 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6764)]
6765pub fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
6766 unsafe { simd_lt(a, b) }
6767}
6768#[doc = "Compare unsigned less than"]
6769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"]
6770#[inline]
6771#[target_feature(enable = "neon")]
6772#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6773#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
6774#[cfg_attr(
6775 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6776 assert_instr(cmhi)
6777)]
6778#[cfg_attr(
6779 not(target_arch = "arm"),
6780 stable(feature = "neon_intrinsics", since = "1.59.0")
6781)]
6782#[cfg_attr(
6783 target_arch = "arm",
6784 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6785)]
6786pub fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
6787 unsafe { simd_lt(a, b) }
6788}
6789#[doc = "Compare unsigned less than"]
6790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"]
6791#[inline]
6792#[target_feature(enable = "neon")]
6793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6794#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
6795#[cfg_attr(
6796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6797 assert_instr(cmhi)
6798)]
6799#[cfg_attr(
6800 not(target_arch = "arm"),
6801 stable(feature = "neon_intrinsics", since = "1.59.0")
6802)]
6803#[cfg_attr(
6804 target_arch = "arm",
6805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6806)]
6807pub fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
6808 unsafe { simd_lt(a, b) }
6809}
6810#[doc = "Compare unsigned less than"]
6811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"]
6812#[inline]
6813#[target_feature(enable = "neon")]
6814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6815#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
6816#[cfg_attr(
6817 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6818 assert_instr(cmhi)
6819)]
6820#[cfg_attr(
6821 not(target_arch = "arm"),
6822 stable(feature = "neon_intrinsics", since = "1.59.0")
6823)]
6824#[cfg_attr(
6825 target_arch = "arm",
6826 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6827)]
6828pub fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
6829 unsafe { simd_lt(a, b) }
6830}
6831#[doc = "Compare unsigned less than"]
6832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"]
6833#[inline]
6834#[target_feature(enable = "neon")]
6835#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6836#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
6837#[cfg_attr(
6838 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6839 assert_instr(cmhi)
6840)]
6841#[cfg_attr(
6842 not(target_arch = "arm"),
6843 stable(feature = "neon_intrinsics", since = "1.59.0")
6844)]
6845#[cfg_attr(
6846 target_arch = "arm",
6847 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6848)]
6849pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
6850 unsafe { simd_lt(a, b) }
6851}
6852#[doc = "Floating-point compare less than"]
6853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f16)"]
6854#[inline]
6855#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6856#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
6857#[cfg_attr(
6858 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6859 assert_instr(fcmlt)
6860)]
6861#[target_feature(enable = "neon,fp16")]
6862#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6863pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t {
6864 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
6865 unsafe { simd_lt(a, transmute(b)) }
6866}
6867#[doc = "Floating-point compare less than"]
6868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f16)"]
6869#[inline]
6870#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6871#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
6872#[cfg_attr(
6873 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6874 assert_instr(fcmlt)
6875)]
6876#[target_feature(enable = "neon,fp16")]
6877#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6878pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t {
6879 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
6880 unsafe { simd_lt(a, transmute(b)) }
6881}
6882#[doc = "Count leading zero bits"]
6883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"]
6884#[inline]
6885#[target_feature(enable = "neon")]
6886#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6887#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
6888#[cfg_attr(
6889 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6890 assert_instr(clz)
6891)]
6892#[cfg_attr(
6893 not(target_arch = "arm"),
6894 stable(feature = "neon_intrinsics", since = "1.59.0")
6895)]
6896#[cfg_attr(
6897 target_arch = "arm",
6898 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6899)]
6900pub fn vclz_s8(a: int8x8_t) -> int8x8_t {
6901 unsafe extern "unadjusted" {
6902 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v8i8")]
6903 #[cfg_attr(
6904 any(target_arch = "aarch64", target_arch = "arm64ec"),
6905 link_name = "llvm.ctlz.v8i8"
6906 )]
6907 fn _vclz_s8(a: int8x8_t) -> int8x8_t;
6908 }
6909 unsafe { _vclz_s8(a) }
6910}
6911#[doc = "Count leading zero bits"]
6912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"]
6913#[inline]
6914#[target_feature(enable = "neon")]
6915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6916#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
6917#[cfg_attr(
6918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6919 assert_instr(clz)
6920)]
6921#[cfg_attr(
6922 not(target_arch = "arm"),
6923 stable(feature = "neon_intrinsics", since = "1.59.0")
6924)]
6925#[cfg_attr(
6926 target_arch = "arm",
6927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6928)]
6929pub fn vclzq_s8(a: int8x16_t) -> int8x16_t {
6930 unsafe extern "unadjusted" {
6931 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v16i8")]
6932 #[cfg_attr(
6933 any(target_arch = "aarch64", target_arch = "arm64ec"),
6934 link_name = "llvm.ctlz.v16i8"
6935 )]
6936 fn _vclzq_s8(a: int8x16_t) -> int8x16_t;
6937 }
6938 unsafe { _vclzq_s8(a) }
6939}
6940#[doc = "Count leading zero bits"]
6941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"]
6942#[inline]
6943#[target_feature(enable = "neon")]
6944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6945#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
6946#[cfg_attr(
6947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6948 assert_instr(clz)
6949)]
6950#[cfg_attr(
6951 not(target_arch = "arm"),
6952 stable(feature = "neon_intrinsics", since = "1.59.0")
6953)]
6954#[cfg_attr(
6955 target_arch = "arm",
6956 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6957)]
6958pub fn vclz_s16(a: int16x4_t) -> int16x4_t {
6959 unsafe extern "unadjusted" {
6960 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v4i16")]
6961 #[cfg_attr(
6962 any(target_arch = "aarch64", target_arch = "arm64ec"),
6963 link_name = "llvm.ctlz.v4i16"
6964 )]
6965 fn _vclz_s16(a: int16x4_t) -> int16x4_t;
6966 }
6967 unsafe { _vclz_s16(a) }
6968}
6969#[doc = "Count leading zero bits"]
6970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"]
6971#[inline]
6972#[target_feature(enable = "neon")]
6973#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6974#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
6975#[cfg_attr(
6976 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6977 assert_instr(clz)
6978)]
6979#[cfg_attr(
6980 not(target_arch = "arm"),
6981 stable(feature = "neon_intrinsics", since = "1.59.0")
6982)]
6983#[cfg_attr(
6984 target_arch = "arm",
6985 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6986)]
6987pub fn vclzq_s16(a: int16x8_t) -> int16x8_t {
6988 unsafe extern "unadjusted" {
6989 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v8i16")]
6990 #[cfg_attr(
6991 any(target_arch = "aarch64", target_arch = "arm64ec"),
6992 link_name = "llvm.ctlz.v8i16"
6993 )]
6994 fn _vclzq_s16(a: int16x8_t) -> int16x8_t;
6995 }
6996 unsafe { _vclzq_s16(a) }
6997}
6998#[doc = "Count leading zero bits"]
6999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"]
7000#[inline]
7001#[target_feature(enable = "neon")]
7002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7003#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7004#[cfg_attr(
7005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7006 assert_instr(clz)
7007)]
7008#[cfg_attr(
7009 not(target_arch = "arm"),
7010 stable(feature = "neon_intrinsics", since = "1.59.0")
7011)]
7012#[cfg_attr(
7013 target_arch = "arm",
7014 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7015)]
7016pub fn vclz_s32(a: int32x2_t) -> int32x2_t {
7017 unsafe extern "unadjusted" {
7018 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v2i32")]
7019 #[cfg_attr(
7020 any(target_arch = "aarch64", target_arch = "arm64ec"),
7021 link_name = "llvm.ctlz.v2i32"
7022 )]
7023 fn _vclz_s32(a: int32x2_t) -> int32x2_t;
7024 }
7025 unsafe { _vclz_s32(a) }
7026}
7027#[doc = "Count leading zero bits"]
7028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"]
7029#[inline]
7030#[target_feature(enable = "neon")]
7031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7032#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7033#[cfg_attr(
7034 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7035 assert_instr(clz)
7036)]
7037#[cfg_attr(
7038 not(target_arch = "arm"),
7039 stable(feature = "neon_intrinsics", since = "1.59.0")
7040)]
7041#[cfg_attr(
7042 target_arch = "arm",
7043 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7044)]
7045pub fn vclzq_s32(a: int32x4_t) -> int32x4_t {
7046 unsafe extern "unadjusted" {
7047 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctlz.v4i32")]
7048 #[cfg_attr(
7049 any(target_arch = "aarch64", target_arch = "arm64ec"),
7050 link_name = "llvm.ctlz.v4i32"
7051 )]
7052 fn _vclzq_s32(a: int32x4_t) -> int32x4_t;
7053 }
7054 unsafe { _vclzq_s32(a) }
7055}
7056#[doc = "Count leading zero bits"]
7057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
7058#[inline]
7059#[cfg(target_endian = "little")]
7060#[target_feature(enable = "neon")]
7061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7062#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7063#[cfg_attr(
7064 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7065 assert_instr(clz)
7066)]
7067#[cfg_attr(
7068 not(target_arch = "arm"),
7069 stable(feature = "neon_intrinsics", since = "1.59.0")
7070)]
7071#[cfg_attr(
7072 target_arch = "arm",
7073 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7074)]
7075pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
7076 unsafe { transmute(vclz_s16(transmute(a))) }
7077}
7078#[doc = "Count leading zero bits"]
7079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
7080#[inline]
7081#[cfg(target_endian = "big")]
7082#[target_feature(enable = "neon")]
7083#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7084#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7085#[cfg_attr(
7086 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7087 assert_instr(clz)
7088)]
7089#[cfg_attr(
7090 not(target_arch = "arm"),
7091 stable(feature = "neon_intrinsics", since = "1.59.0")
7092)]
7093#[cfg_attr(
7094 target_arch = "arm",
7095 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7096)]
7097pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
7098 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
7099 unsafe {
7100 let ret_val: uint16x4_t = transmute(vclz_s16(transmute(a)));
7101 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7102 }
7103}
7104#[doc = "Count leading zero bits"]
7105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
7106#[inline]
7107#[cfg(target_endian = "little")]
7108#[target_feature(enable = "neon")]
7109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7110#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7111#[cfg_attr(
7112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7113 assert_instr(clz)
7114)]
7115#[cfg_attr(
7116 not(target_arch = "arm"),
7117 stable(feature = "neon_intrinsics", since = "1.59.0")
7118)]
7119#[cfg_attr(
7120 target_arch = "arm",
7121 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7122)]
7123pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
7124 unsafe { transmute(vclzq_s16(transmute(a))) }
7125}
7126#[doc = "Count leading zero bits"]
7127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
7128#[inline]
7129#[cfg(target_endian = "big")]
7130#[target_feature(enable = "neon")]
7131#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7132#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7133#[cfg_attr(
7134 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7135 assert_instr(clz)
7136)]
7137#[cfg_attr(
7138 not(target_arch = "arm"),
7139 stable(feature = "neon_intrinsics", since = "1.59.0")
7140)]
7141#[cfg_attr(
7142 target_arch = "arm",
7143 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7144)]
7145pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
7146 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7147 unsafe {
7148 let ret_val: uint16x8_t = transmute(vclzq_s16(transmute(a)));
7149 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7150 }
7151}
7152#[doc = "Count leading zero bits"]
7153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
7154#[inline]
7155#[cfg(target_endian = "little")]
7156#[target_feature(enable = "neon")]
7157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7158#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7159#[cfg_attr(
7160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7161 assert_instr(clz)
7162)]
7163#[cfg_attr(
7164 not(target_arch = "arm"),
7165 stable(feature = "neon_intrinsics", since = "1.59.0")
7166)]
7167#[cfg_attr(
7168 target_arch = "arm",
7169 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7170)]
7171pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
7172 unsafe { transmute(vclz_s32(transmute(a))) }
7173}
7174#[doc = "Count leading zero bits"]
7175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
7176#[inline]
7177#[cfg(target_endian = "big")]
7178#[target_feature(enable = "neon")]
7179#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7180#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7181#[cfg_attr(
7182 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7183 assert_instr(clz)
7184)]
7185#[cfg_attr(
7186 not(target_arch = "arm"),
7187 stable(feature = "neon_intrinsics", since = "1.59.0")
7188)]
7189#[cfg_attr(
7190 target_arch = "arm",
7191 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7192)]
7193pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
7194 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
7195 unsafe {
7196 let ret_val: uint32x2_t = transmute(vclz_s32(transmute(a)));
7197 simd_shuffle!(ret_val, ret_val, [1, 0])
7198 }
7199}
7200#[doc = "Count leading zero bits"]
7201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
7202#[inline]
7203#[cfg(target_endian = "little")]
7204#[target_feature(enable = "neon")]
7205#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7206#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7207#[cfg_attr(
7208 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7209 assert_instr(clz)
7210)]
7211#[cfg_attr(
7212 not(target_arch = "arm"),
7213 stable(feature = "neon_intrinsics", since = "1.59.0")
7214)]
7215#[cfg_attr(
7216 target_arch = "arm",
7217 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7218)]
7219pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
7220 unsafe { transmute(vclzq_s32(transmute(a))) }
7221}
7222#[doc = "Count leading zero bits"]
7223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
7224#[inline]
7225#[cfg(target_endian = "big")]
7226#[target_feature(enable = "neon")]
7227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7228#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7229#[cfg_attr(
7230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7231 assert_instr(clz)
7232)]
7233#[cfg_attr(
7234 not(target_arch = "arm"),
7235 stable(feature = "neon_intrinsics", since = "1.59.0")
7236)]
7237#[cfg_attr(
7238 target_arch = "arm",
7239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7240)]
7241pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
7242 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
7243 unsafe {
7244 let ret_val: uint32x4_t = transmute(vclzq_s32(transmute(a)));
7245 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7246 }
7247}
7248#[doc = "Count leading zero bits"]
7249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
7250#[inline]
7251#[cfg(target_endian = "little")]
7252#[target_feature(enable = "neon")]
7253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7254#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7255#[cfg_attr(
7256 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7257 assert_instr(clz)
7258)]
7259#[cfg_attr(
7260 not(target_arch = "arm"),
7261 stable(feature = "neon_intrinsics", since = "1.59.0")
7262)]
7263#[cfg_attr(
7264 target_arch = "arm",
7265 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7266)]
7267pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
7268 unsafe { transmute(vclz_s8(transmute(a))) }
7269}
7270#[doc = "Count leading zero bits"]
7271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
7272#[inline]
7273#[cfg(target_endian = "big")]
7274#[target_feature(enable = "neon")]
7275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7276#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7277#[cfg_attr(
7278 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7279 assert_instr(clz)
7280)]
7281#[cfg_attr(
7282 not(target_arch = "arm"),
7283 stable(feature = "neon_intrinsics", since = "1.59.0")
7284)]
7285#[cfg_attr(
7286 target_arch = "arm",
7287 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7288)]
7289pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
7290 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7291 unsafe {
7292 let ret_val: uint8x8_t = transmute(vclz_s8(transmute(a)));
7293 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7294 }
7295}
7296#[doc = "Count leading zero bits"]
7297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
7298#[inline]
7299#[cfg(target_endian = "little")]
7300#[target_feature(enable = "neon")]
7301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7302#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7303#[cfg_attr(
7304 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7305 assert_instr(clz)
7306)]
7307#[cfg_attr(
7308 not(target_arch = "arm"),
7309 stable(feature = "neon_intrinsics", since = "1.59.0")
7310)]
7311#[cfg_attr(
7312 target_arch = "arm",
7313 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7314)]
7315pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
7316 unsafe { transmute(vclzq_s8(transmute(a))) }
7317}
7318#[doc = "Count leading zero bits"]
7319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
7320#[inline]
7321#[cfg(target_endian = "big")]
7322#[target_feature(enable = "neon")]
7323#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7324#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7325#[cfg_attr(
7326 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7327 assert_instr(clz)
7328)]
7329#[cfg_attr(
7330 not(target_arch = "arm"),
7331 stable(feature = "neon_intrinsics", since = "1.59.0")
7332)]
7333#[cfg_attr(
7334 target_arch = "arm",
7335 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7336)]
7337pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
7338 let a: uint8x16_t =
7339 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7340 unsafe {
7341 let ret_val: uint8x16_t = transmute(vclzq_s8(transmute(a)));
7342 simd_shuffle!(
7343 ret_val,
7344 ret_val,
7345 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7346 )
7347 }
7348}
7349#[doc = "Population count per byte."]
7350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"]
7351#[inline]
7352#[target_feature(enable = "neon")]
7353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7354#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7355#[cfg_attr(
7356 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7357 assert_instr(cnt)
7358)]
7359#[cfg_attr(
7360 not(target_arch = "arm"),
7361 stable(feature = "neon_intrinsics", since = "1.59.0")
7362)]
7363#[cfg_attr(
7364 target_arch = "arm",
7365 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7366)]
7367pub fn vcnt_s8(a: int8x8_t) -> int8x8_t {
7368 unsafe extern "unadjusted" {
7369 #[cfg_attr(
7370 any(target_arch = "aarch64", target_arch = "arm64ec"),
7371 link_name = "llvm.ctpop.v8i8"
7372 )]
7373 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctpop.v8i8")]
7374 fn _vcnt_s8(a: int8x8_t) -> int8x8_t;
7375 }
7376 unsafe { _vcnt_s8(a) }
7377}
7378#[doc = "Population count per byte."]
7379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)"]
7380#[inline]
7381#[target_feature(enable = "neon")]
7382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7383#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7384#[cfg_attr(
7385 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7386 assert_instr(cnt)
7387)]
7388#[cfg_attr(
7389 not(target_arch = "arm"),
7390 stable(feature = "neon_intrinsics", since = "1.59.0")
7391)]
7392#[cfg_attr(
7393 target_arch = "arm",
7394 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7395)]
7396pub fn vcntq_s8(a: int8x16_t) -> int8x16_t {
7397 unsafe extern "unadjusted" {
7398 #[cfg_attr(
7399 any(target_arch = "aarch64", target_arch = "arm64ec"),
7400 link_name = "llvm.ctpop.v16i8"
7401 )]
7402 #[cfg_attr(target_arch = "arm", link_name = "llvm.ctpop.v16i8")]
7403 fn _vcntq_s8(a: int8x16_t) -> int8x16_t;
7404 }
7405 unsafe { _vcntq_s8(a) }
7406}
7407#[doc = "Population count per byte."]
7408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
7409#[inline]
7410#[cfg(target_endian = "little")]
7411#[target_feature(enable = "neon")]
7412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7413#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7414#[cfg_attr(
7415 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7416 assert_instr(cnt)
7417)]
7418#[cfg_attr(
7419 not(target_arch = "arm"),
7420 stable(feature = "neon_intrinsics", since = "1.59.0")
7421)]
7422#[cfg_attr(
7423 target_arch = "arm",
7424 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7425)]
7426pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
7427 unsafe { transmute(vcnt_s8(transmute(a))) }
7428}
7429#[doc = "Population count per byte."]
7430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
7431#[inline]
7432#[cfg(target_endian = "big")]
7433#[target_feature(enable = "neon")]
7434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7435#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7436#[cfg_attr(
7437 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7438 assert_instr(cnt)
7439)]
7440#[cfg_attr(
7441 not(target_arch = "arm"),
7442 stable(feature = "neon_intrinsics", since = "1.59.0")
7443)]
7444#[cfg_attr(
7445 target_arch = "arm",
7446 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7447)]
7448pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
7449 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7450 unsafe {
7451 let ret_val: uint8x8_t = transmute(vcnt_s8(transmute(a)));
7452 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7453 }
7454}
7455#[doc = "Population count per byte."]
7456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
7457#[inline]
7458#[cfg(target_endian = "little")]
7459#[target_feature(enable = "neon")]
7460#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7461#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7462#[cfg_attr(
7463 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7464 assert_instr(cnt)
7465)]
7466#[cfg_attr(
7467 not(target_arch = "arm"),
7468 stable(feature = "neon_intrinsics", since = "1.59.0")
7469)]
7470#[cfg_attr(
7471 target_arch = "arm",
7472 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7473)]
7474pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
7475 unsafe { transmute(vcntq_s8(transmute(a))) }
7476}
7477#[doc = "Population count per byte."]
7478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
7479#[inline]
7480#[cfg(target_endian = "big")]
7481#[target_feature(enable = "neon")]
7482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7483#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7484#[cfg_attr(
7485 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7486 assert_instr(cnt)
7487)]
7488#[cfg_attr(
7489 not(target_arch = "arm"),
7490 stable(feature = "neon_intrinsics", since = "1.59.0")
7491)]
7492#[cfg_attr(
7493 target_arch = "arm",
7494 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7495)]
7496pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
7497 let a: uint8x16_t =
7498 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7499 unsafe {
7500 let ret_val: uint8x16_t = transmute(vcntq_s8(transmute(a)));
7501 simd_shuffle!(
7502 ret_val,
7503 ret_val,
7504 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7505 )
7506 }
7507}
7508#[doc = "Population count per byte."]
7509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
7510#[inline]
7511#[cfg(target_endian = "little")]
7512#[target_feature(enable = "neon")]
7513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7515#[cfg_attr(
7516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7517 assert_instr(cnt)
7518)]
7519#[cfg_attr(
7520 not(target_arch = "arm"),
7521 stable(feature = "neon_intrinsics", since = "1.59.0")
7522)]
7523#[cfg_attr(
7524 target_arch = "arm",
7525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7526)]
7527pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
7528 unsafe { transmute(vcnt_s8(transmute(a))) }
7529}
7530#[doc = "Population count per byte."]
7531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
7532#[inline]
7533#[cfg(target_endian = "big")]
7534#[target_feature(enable = "neon")]
7535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7536#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7537#[cfg_attr(
7538 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7539 assert_instr(cnt)
7540)]
7541#[cfg_attr(
7542 not(target_arch = "arm"),
7543 stable(feature = "neon_intrinsics", since = "1.59.0")
7544)]
7545#[cfg_attr(
7546 target_arch = "arm",
7547 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7548)]
7549pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
7550 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7551 unsafe {
7552 let ret_val: poly8x8_t = transmute(vcnt_s8(transmute(a)));
7553 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7554 }
7555}
7556#[doc = "Population count per byte."]
7557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
7558#[inline]
7559#[cfg(target_endian = "little")]
7560#[target_feature(enable = "neon")]
7561#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7562#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7563#[cfg_attr(
7564 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7565 assert_instr(cnt)
7566)]
7567#[cfg_attr(
7568 not(target_arch = "arm"),
7569 stable(feature = "neon_intrinsics", since = "1.59.0")
7570)]
7571#[cfg_attr(
7572 target_arch = "arm",
7573 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7574)]
7575pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
7576 unsafe { transmute(vcntq_s8(transmute(a))) }
7577}
7578#[doc = "Population count per byte."]
7579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
7580#[inline]
7581#[cfg(target_endian = "big")]
7582#[target_feature(enable = "neon")]
7583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7585#[cfg_attr(
7586 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7587 assert_instr(cnt)
7588)]
7589#[cfg_attr(
7590 not(target_arch = "arm"),
7591 stable(feature = "neon_intrinsics", since = "1.59.0")
7592)]
7593#[cfg_attr(
7594 target_arch = "arm",
7595 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7596)]
7597pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
7598 let a: poly8x16_t =
7599 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7600 unsafe {
7601 let ret_val: poly8x16_t = transmute(vcntq_s8(transmute(a)));
7602 simd_shuffle!(
7603 ret_val,
7604 ret_val,
7605 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7606 )
7607 }
7608}
7609#[doc = "Join two smaller vectors into a single larger vector"]
7610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"]
7611#[inline]
7612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7613#[target_feature(enable = "neon,fp16")]
7614#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7615#[cfg_attr(test, assert_instr(nop))]
7616pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t {
7617 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7618}
7619#[doc = "Join two smaller vectors into a single larger vector"]
7620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"]
7621#[inline]
7622#[target_feature(enable = "neon")]
7623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7624#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7625#[cfg_attr(
7626 not(target_arch = "arm"),
7627 stable(feature = "neon_intrinsics", since = "1.59.0")
7628)]
7629#[cfg_attr(
7630 target_arch = "arm",
7631 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7632)]
7633pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t {
7634 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7635}
7636#[doc = "Join two smaller vectors into a single larger vector"]
7637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"]
7638#[inline]
7639#[target_feature(enable = "neon")]
7640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7642#[cfg_attr(
7643 not(target_arch = "arm"),
7644 stable(feature = "neon_intrinsics", since = "1.59.0")
7645)]
7646#[cfg_attr(
7647 target_arch = "arm",
7648 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7649)]
7650pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t {
7651 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7652}
7653#[doc = "Join two smaller vectors into a single larger vector"]
7654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"]
7655#[inline]
7656#[target_feature(enable = "neon")]
7657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7659#[cfg_attr(
7660 not(target_arch = "arm"),
7661 stable(feature = "neon_intrinsics", since = "1.59.0")
7662)]
7663#[cfg_attr(
7664 target_arch = "arm",
7665 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7666)]
7667pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t {
7668 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7669}
7670#[doc = "Join two smaller vectors into a single larger vector"]
7671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"]
7672#[inline]
7673#[target_feature(enable = "neon")]
7674#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7675#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7676#[cfg_attr(
7677 not(target_arch = "arm"),
7678 stable(feature = "neon_intrinsics", since = "1.59.0")
7679)]
7680#[cfg_attr(
7681 target_arch = "arm",
7682 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7683)]
7684pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t {
7685 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7686}
7687#[doc = "Join two smaller vectors into a single larger vector"]
7688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"]
7689#[inline]
7690#[target_feature(enable = "neon")]
7691#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7692#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7693#[cfg_attr(
7694 not(target_arch = "arm"),
7695 stable(feature = "neon_intrinsics", since = "1.59.0")
7696)]
7697#[cfg_attr(
7698 target_arch = "arm",
7699 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7700)]
7701pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t {
7702 unsafe { simd_shuffle!(a, b, [0, 1]) }
7703}
7704#[doc = "Join two smaller vectors into a single larger vector"]
7705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"]
7706#[inline]
7707#[target_feature(enable = "neon")]
7708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7710#[cfg_attr(
7711 not(target_arch = "arm"),
7712 stable(feature = "neon_intrinsics", since = "1.59.0")
7713)]
7714#[cfg_attr(
7715 target_arch = "arm",
7716 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7717)]
7718pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
7719 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7720}
7721#[doc = "Join two smaller vectors into a single larger vector"]
7722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"]
7723#[inline]
7724#[target_feature(enable = "neon")]
7725#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7726#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7727#[cfg_attr(
7728 not(target_arch = "arm"),
7729 stable(feature = "neon_intrinsics", since = "1.59.0")
7730)]
7731#[cfg_attr(
7732 target_arch = "arm",
7733 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7734)]
7735pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t {
7736 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7737}
7738#[doc = "Join two smaller vectors into a single larger vector"]
7739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"]
7740#[inline]
7741#[target_feature(enable = "neon")]
7742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7743#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7744#[cfg_attr(
7745 not(target_arch = "arm"),
7746 stable(feature = "neon_intrinsics", since = "1.59.0")
7747)]
7748#[cfg_attr(
7749 target_arch = "arm",
7750 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7751)]
7752pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t {
7753 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7754}
7755#[doc = "Join two smaller vectors into a single larger vector"]
7756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"]
7757#[inline]
7758#[target_feature(enable = "neon")]
7759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7761#[cfg_attr(
7762 not(target_arch = "arm"),
7763 stable(feature = "neon_intrinsics", since = "1.59.0")
7764)]
7765#[cfg_attr(
7766 target_arch = "arm",
7767 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7768)]
7769pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t {
7770 unsafe { simd_shuffle!(a, b, [0, 1]) }
7771}
7772#[doc = "Join two smaller vectors into a single larger vector"]
7773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"]
7774#[inline]
7775#[target_feature(enable = "neon")]
7776#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7777#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7778#[cfg_attr(
7779 not(target_arch = "arm"),
7780 stable(feature = "neon_intrinsics", since = "1.59.0")
7781)]
7782#[cfg_attr(
7783 target_arch = "arm",
7784 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7785)]
7786pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t {
7787 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7788}
7789#[doc = "Join two smaller vectors into a single larger vector"]
7790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"]
7791#[inline]
7792#[target_feature(enable = "neon")]
7793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7795#[cfg_attr(
7796 not(target_arch = "arm"),
7797 stable(feature = "neon_intrinsics", since = "1.59.0")
7798)]
7799#[cfg_attr(
7800 target_arch = "arm",
7801 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7802)]
7803pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t {
7804 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7805}
7806#[doc = "Join two smaller vectors into a single larger vector"]
7807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"]
7808#[inline]
7809#[target_feature(enable = "neon")]
7810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7812#[cfg_attr(
7813 not(target_arch = "arm"),
7814 stable(feature = "neon_intrinsics", since = "1.59.0")
7815)]
7816#[cfg_attr(
7817 target_arch = "arm",
7818 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7819)]
7820pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t {
7821 unsafe { simd_shuffle!(a, b, [0, 1]) }
7822}
7823#[doc = "Insert vector element from another vector element"]
7824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
7825#[inline]
7826#[cfg(target_endian = "little")]
7827#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7828#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7829#[cfg_attr(
7830 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7831 assert_instr(nop)
7832)]
7833#[target_feature(enable = "neon,fp16")]
7834#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7835pub fn vcreate_f16(a: u64) -> float16x4_t {
7836 unsafe { transmute(a) }
7837}
7838#[doc = "Insert vector element from another vector element"]
7839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
7840#[inline]
7841#[cfg(target_endian = "big")]
7842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7844#[cfg_attr(
7845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7846 assert_instr(nop)
7847)]
7848#[target_feature(enable = "neon,fp16")]
7849#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7850pub fn vcreate_f16(a: u64) -> float16x4_t {
7851 unsafe {
7852 let ret_val: float16x4_t = transmute(a);
7853 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7854 }
7855}
7856#[doc = "Insert vector element from another vector element"]
7857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
7858#[inline]
7859#[cfg(target_endian = "little")]
7860#[target_feature(enable = "neon")]
7861#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7862#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7863#[cfg_attr(
7864 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7865 assert_instr(nop)
7866)]
7867#[cfg_attr(
7868 not(target_arch = "arm"),
7869 stable(feature = "neon_intrinsics", since = "1.59.0")
7870)]
7871#[cfg_attr(
7872 target_arch = "arm",
7873 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7874)]
7875pub fn vcreate_f32(a: u64) -> float32x2_t {
7876 unsafe { transmute(a) }
7877}
7878#[doc = "Insert vector element from another vector element"]
7879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
7880#[inline]
7881#[cfg(target_endian = "big")]
7882#[target_feature(enable = "neon")]
7883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7885#[cfg_attr(
7886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7887 assert_instr(nop)
7888)]
7889#[cfg_attr(
7890 not(target_arch = "arm"),
7891 stable(feature = "neon_intrinsics", since = "1.59.0")
7892)]
7893#[cfg_attr(
7894 target_arch = "arm",
7895 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7896)]
7897pub fn vcreate_f32(a: u64) -> float32x2_t {
7898 unsafe {
7899 let ret_val: float32x2_t = transmute(a);
7900 simd_shuffle!(ret_val, ret_val, [1, 0])
7901 }
7902}
7903#[doc = "Insert vector element from another vector element"]
7904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
7905#[inline]
7906#[cfg(target_endian = "little")]
7907#[target_feature(enable = "neon")]
7908#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7909#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7910#[cfg_attr(
7911 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7912 assert_instr(nop)
7913)]
7914#[cfg_attr(
7915 not(target_arch = "arm"),
7916 stable(feature = "neon_intrinsics", since = "1.59.0")
7917)]
7918#[cfg_attr(
7919 target_arch = "arm",
7920 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7921)]
7922pub fn vcreate_s8(a: u64) -> int8x8_t {
7923 unsafe { transmute(a) }
7924}
7925#[doc = "Insert vector element from another vector element"]
7926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
7927#[inline]
7928#[cfg(target_endian = "big")]
7929#[target_feature(enable = "neon")]
7930#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7931#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7932#[cfg_attr(
7933 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7934 assert_instr(nop)
7935)]
7936#[cfg_attr(
7937 not(target_arch = "arm"),
7938 stable(feature = "neon_intrinsics", since = "1.59.0")
7939)]
7940#[cfg_attr(
7941 target_arch = "arm",
7942 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7943)]
7944pub fn vcreate_s8(a: u64) -> int8x8_t {
7945 unsafe {
7946 let ret_val: int8x8_t = transmute(a);
7947 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7948 }
7949}
7950#[doc = "Insert vector element from another vector element"]
7951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
7952#[inline]
7953#[cfg(target_endian = "little")]
7954#[target_feature(enable = "neon")]
7955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7957#[cfg_attr(
7958 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7959 assert_instr(nop)
7960)]
7961#[cfg_attr(
7962 not(target_arch = "arm"),
7963 stable(feature = "neon_intrinsics", since = "1.59.0")
7964)]
7965#[cfg_attr(
7966 target_arch = "arm",
7967 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7968)]
7969pub fn vcreate_s16(a: u64) -> int16x4_t {
7970 unsafe { transmute(a) }
7971}
7972#[doc = "Insert vector element from another vector element"]
7973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
7974#[inline]
7975#[cfg(target_endian = "big")]
7976#[target_feature(enable = "neon")]
7977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7978#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7979#[cfg_attr(
7980 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7981 assert_instr(nop)
7982)]
7983#[cfg_attr(
7984 not(target_arch = "arm"),
7985 stable(feature = "neon_intrinsics", since = "1.59.0")
7986)]
7987#[cfg_attr(
7988 target_arch = "arm",
7989 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7990)]
7991pub fn vcreate_s16(a: u64) -> int16x4_t {
7992 unsafe {
7993 let ret_val: int16x4_t = transmute(a);
7994 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7995 }
7996}
7997#[doc = "Insert vector element from another vector element"]
7998#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
7999#[inline]
8000#[cfg(target_endian = "little")]
8001#[target_feature(enable = "neon")]
8002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8003#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8004#[cfg_attr(
8005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8006 assert_instr(nop)
8007)]
8008#[cfg_attr(
8009 not(target_arch = "arm"),
8010 stable(feature = "neon_intrinsics", since = "1.59.0")
8011)]
8012#[cfg_attr(
8013 target_arch = "arm",
8014 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8015)]
8016pub fn vcreate_s32(a: u64) -> int32x2_t {
8017 unsafe { transmute(a) }
8018}
8019#[doc = "Insert vector element from another vector element"]
8020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
8021#[inline]
8022#[cfg(target_endian = "big")]
8023#[target_feature(enable = "neon")]
8024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8025#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8026#[cfg_attr(
8027 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8028 assert_instr(nop)
8029)]
8030#[cfg_attr(
8031 not(target_arch = "arm"),
8032 stable(feature = "neon_intrinsics", since = "1.59.0")
8033)]
8034#[cfg_attr(
8035 target_arch = "arm",
8036 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8037)]
8038pub fn vcreate_s32(a: u64) -> int32x2_t {
8039 unsafe {
8040 let ret_val: int32x2_t = transmute(a);
8041 simd_shuffle!(ret_val, ret_val, [1, 0])
8042 }
8043}
8044#[doc = "Insert vector element from another vector element"]
8045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"]
8046#[inline]
8047#[target_feature(enable = "neon")]
8048#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8049#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8050#[cfg_attr(
8051 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8052 assert_instr(nop)
8053)]
8054#[cfg_attr(
8055 not(target_arch = "arm"),
8056 stable(feature = "neon_intrinsics", since = "1.59.0")
8057)]
8058#[cfg_attr(
8059 target_arch = "arm",
8060 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8061)]
8062pub fn vcreate_s64(a: u64) -> int64x1_t {
8063 unsafe { transmute(a) }
8064}
8065#[doc = "Insert vector element from another vector element"]
8066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
8067#[inline]
8068#[cfg(target_endian = "little")]
8069#[target_feature(enable = "neon")]
8070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8071#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8072#[cfg_attr(
8073 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8074 assert_instr(nop)
8075)]
8076#[cfg_attr(
8077 not(target_arch = "arm"),
8078 stable(feature = "neon_intrinsics", since = "1.59.0")
8079)]
8080#[cfg_attr(
8081 target_arch = "arm",
8082 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8083)]
8084pub fn vcreate_u8(a: u64) -> uint8x8_t {
8085 unsafe { transmute(a) }
8086}
8087#[doc = "Insert vector element from another vector element"]
8088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
8089#[inline]
8090#[cfg(target_endian = "big")]
8091#[target_feature(enable = "neon")]
8092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8093#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8094#[cfg_attr(
8095 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8096 assert_instr(nop)
8097)]
8098#[cfg_attr(
8099 not(target_arch = "arm"),
8100 stable(feature = "neon_intrinsics", since = "1.59.0")
8101)]
8102#[cfg_attr(
8103 target_arch = "arm",
8104 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8105)]
8106pub fn vcreate_u8(a: u64) -> uint8x8_t {
8107 unsafe {
8108 let ret_val: uint8x8_t = transmute(a);
8109 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
8110 }
8111}
8112#[doc = "Insert vector element from another vector element"]
8113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
8114#[inline]
8115#[cfg(target_endian = "little")]
8116#[target_feature(enable = "neon")]
8117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8118#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8119#[cfg_attr(
8120 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8121 assert_instr(nop)
8122)]
8123#[cfg_attr(
8124 not(target_arch = "arm"),
8125 stable(feature = "neon_intrinsics", since = "1.59.0")
8126)]
8127#[cfg_attr(
8128 target_arch = "arm",
8129 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8130)]
8131pub fn vcreate_u16(a: u64) -> uint16x4_t {
8132 unsafe { transmute(a) }
8133}
8134#[doc = "Insert vector element from another vector element"]
8135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
8136#[inline]
8137#[cfg(target_endian = "big")]
8138#[target_feature(enable = "neon")]
8139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8140#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8141#[cfg_attr(
8142 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8143 assert_instr(nop)
8144)]
8145#[cfg_attr(
8146 not(target_arch = "arm"),
8147 stable(feature = "neon_intrinsics", since = "1.59.0")
8148)]
8149#[cfg_attr(
8150 target_arch = "arm",
8151 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8152)]
8153pub fn vcreate_u16(a: u64) -> uint16x4_t {
8154 unsafe {
8155 let ret_val: uint16x4_t = transmute(a);
8156 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
8157 }
8158}
8159#[doc = "Insert vector element from another vector element"]
8160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
8161#[inline]
8162#[cfg(target_endian = "little")]
8163#[target_feature(enable = "neon")]
8164#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8165#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8166#[cfg_attr(
8167 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8168 assert_instr(nop)
8169)]
8170#[cfg_attr(
8171 not(target_arch = "arm"),
8172 stable(feature = "neon_intrinsics", since = "1.59.0")
8173)]
8174#[cfg_attr(
8175 target_arch = "arm",
8176 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8177)]
8178pub fn vcreate_u32(a: u64) -> uint32x2_t {
8179 unsafe { transmute(a) }
8180}
8181#[doc = "Insert vector element from another vector element"]
8182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
8183#[inline]
8184#[cfg(target_endian = "big")]
8185#[target_feature(enable = "neon")]
8186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8187#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8188#[cfg_attr(
8189 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8190 assert_instr(nop)
8191)]
8192#[cfg_attr(
8193 not(target_arch = "arm"),
8194 stable(feature = "neon_intrinsics", since = "1.59.0")
8195)]
8196#[cfg_attr(
8197 target_arch = "arm",
8198 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8199)]
8200pub fn vcreate_u32(a: u64) -> uint32x2_t {
8201 unsafe {
8202 let ret_val: uint32x2_t = transmute(a);
8203 simd_shuffle!(ret_val, ret_val, [1, 0])
8204 }
8205}
8206#[doc = "Insert vector element from another vector element"]
8207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"]
8208#[inline]
8209#[target_feature(enable = "neon")]
8210#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8211#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8212#[cfg_attr(
8213 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8214 assert_instr(nop)
8215)]
8216#[cfg_attr(
8217 not(target_arch = "arm"),
8218 stable(feature = "neon_intrinsics", since = "1.59.0")
8219)]
8220#[cfg_attr(
8221 target_arch = "arm",
8222 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8223)]
8224pub fn vcreate_u64(a: u64) -> uint64x1_t {
8225 unsafe { transmute(a) }
8226}
8227#[doc = "Insert vector element from another vector element"]
8228#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
8229#[inline]
8230#[cfg(target_endian = "little")]
8231#[target_feature(enable = "neon")]
8232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8233#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8234#[cfg_attr(
8235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8236 assert_instr(nop)
8237)]
8238#[cfg_attr(
8239 not(target_arch = "arm"),
8240 stable(feature = "neon_intrinsics", since = "1.59.0")
8241)]
8242#[cfg_attr(
8243 target_arch = "arm",
8244 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8245)]
8246pub fn vcreate_p8(a: u64) -> poly8x8_t {
8247 unsafe { transmute(a) }
8248}
8249#[doc = "Insert vector element from another vector element"]
8250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
8251#[inline]
8252#[cfg(target_endian = "big")]
8253#[target_feature(enable = "neon")]
8254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8255#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8256#[cfg_attr(
8257 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8258 assert_instr(nop)
8259)]
8260#[cfg_attr(
8261 not(target_arch = "arm"),
8262 stable(feature = "neon_intrinsics", since = "1.59.0")
8263)]
8264#[cfg_attr(
8265 target_arch = "arm",
8266 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8267)]
8268pub fn vcreate_p8(a: u64) -> poly8x8_t {
8269 unsafe {
8270 let ret_val: poly8x8_t = transmute(a);
8271 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
8272 }
8273}
8274#[doc = "Insert vector element from another vector element"]
8275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
8276#[inline]
8277#[cfg(target_endian = "little")]
8278#[target_feature(enable = "neon")]
8279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8281#[cfg_attr(
8282 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8283 assert_instr(nop)
8284)]
8285#[cfg_attr(
8286 not(target_arch = "arm"),
8287 stable(feature = "neon_intrinsics", since = "1.59.0")
8288)]
8289#[cfg_attr(
8290 target_arch = "arm",
8291 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8292)]
8293pub fn vcreate_p16(a: u64) -> poly16x4_t {
8294 unsafe { transmute(a) }
8295}
8296#[doc = "Insert vector element from another vector element"]
8297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
8298#[inline]
8299#[cfg(target_endian = "big")]
8300#[target_feature(enable = "neon")]
8301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8302#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8303#[cfg_attr(
8304 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8305 assert_instr(nop)
8306)]
8307#[cfg_attr(
8308 not(target_arch = "arm"),
8309 stable(feature = "neon_intrinsics", since = "1.59.0")
8310)]
8311#[cfg_attr(
8312 target_arch = "arm",
8313 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8314)]
8315pub fn vcreate_p16(a: u64) -> poly16x4_t {
8316 unsafe {
8317 let ret_val: poly16x4_t = transmute(a);
8318 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
8319 }
8320}
8321#[doc = "Insert vector element from another vector element"]
8322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"]
8323#[inline]
8324#[target_feature(enable = "neon,aes")]
8325#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8327#[cfg_attr(
8328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8329 assert_instr(nop)
8330)]
8331#[cfg_attr(
8332 not(target_arch = "arm"),
8333 stable(feature = "neon_intrinsics", since = "1.59.0")
8334)]
8335#[cfg_attr(
8336 target_arch = "arm",
8337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8338)]
8339pub fn vcreate_p64(a: u64) -> poly64x1_t {
8340 unsafe { transmute(a) }
8341}
8342#[doc = "Floating-point convert to lower precision narrow"]
8343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"]
8344#[inline]
8345#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8346# [cfg_attr (all (test , target_arch = "arm") , assert_instr (vcvt . f16 . f32))]
8347#[cfg_attr(
8348 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8349 assert_instr(fcvtn)
8350)]
8351#[target_feature(enable = "neon,fp16")]
8352#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8353pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
8354 unsafe { simd_cast(a) }
8355}
8356#[doc = "Fixed-point convert to floating-point"]
8357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_s16)"]
8358#[inline]
8359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8360#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8361#[cfg_attr(
8362 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8363 assert_instr(scvtf)
8364)]
8365#[target_feature(enable = "neon,fp16")]
8366#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8367pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t {
8368 unsafe { simd_cast(a) }
8369}
8370#[doc = "Fixed-point convert to floating-point"]
8371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_s16)"]
8372#[inline]
8373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8375#[cfg_attr(
8376 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8377 assert_instr(scvtf)
8378)]
8379#[target_feature(enable = "neon,fp16")]
8380#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8381pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t {
8382 unsafe { simd_cast(a) }
8383}
8384#[doc = "Fixed-point convert to floating-point"]
8385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_u16)"]
8386#[inline]
8387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8389#[cfg_attr(
8390 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8391 assert_instr(ucvtf)
8392)]
8393#[target_feature(enable = "neon,fp16")]
8394#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8395pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t {
8396 unsafe { simd_cast(a) }
8397}
8398#[doc = "Fixed-point convert to floating-point"]
8399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_u16)"]
8400#[inline]
8401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8403#[cfg_attr(
8404 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8405 assert_instr(ucvtf)
8406)]
8407#[target_feature(enable = "neon,fp16")]
8408#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8409pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
8410 unsafe { simd_cast(a) }
8411}
8412#[doc = "Floating-point convert to higher precision long"]
8413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"]
8414#[inline]
8415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8417#[cfg_attr(
8418 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8419 assert_instr(fcvtl)
8420)]
8421#[target_feature(enable = "neon,fp16")]
8422#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8423pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t {
8424 unsafe { simd_cast(a) }
8425}
8426#[doc = "Fixed-point convert to floating-point"]
8427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"]
8428#[inline]
8429#[target_feature(enable = "neon")]
8430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8431#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8432#[cfg_attr(
8433 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8434 assert_instr(scvtf)
8435)]
8436#[cfg_attr(
8437 not(target_arch = "arm"),
8438 stable(feature = "neon_intrinsics", since = "1.59.0")
8439)]
8440#[cfg_attr(
8441 target_arch = "arm",
8442 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8443)]
8444pub fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t {
8445 unsafe { simd_cast(a) }
8446}
8447#[doc = "Fixed-point convert to floating-point"]
8448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"]
8449#[inline]
8450#[target_feature(enable = "neon")]
8451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8453#[cfg_attr(
8454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8455 assert_instr(scvtf)
8456)]
8457#[cfg_attr(
8458 not(target_arch = "arm"),
8459 stable(feature = "neon_intrinsics", since = "1.59.0")
8460)]
8461#[cfg_attr(
8462 target_arch = "arm",
8463 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8464)]
8465pub fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t {
8466 unsafe { simd_cast(a) }
8467}
8468#[doc = "Fixed-point convert to floating-point"]
8469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"]
8470#[inline]
8471#[target_feature(enable = "neon")]
8472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8474#[cfg_attr(
8475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8476 assert_instr(ucvtf)
8477)]
8478#[cfg_attr(
8479 not(target_arch = "arm"),
8480 stable(feature = "neon_intrinsics", since = "1.59.0")
8481)]
8482#[cfg_attr(
8483 target_arch = "arm",
8484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8485)]
8486pub fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t {
8487 unsafe { simd_cast(a) }
8488}
8489#[doc = "Fixed-point convert to floating-point"]
8490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"]
8491#[inline]
8492#[target_feature(enable = "neon")]
8493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8494#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8495#[cfg_attr(
8496 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8497 assert_instr(ucvtf)
8498)]
8499#[cfg_attr(
8500 not(target_arch = "arm"),
8501 stable(feature = "neon_intrinsics", since = "1.59.0")
8502)]
8503#[cfg_attr(
8504 target_arch = "arm",
8505 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8506)]
8507pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t {
8508 unsafe { simd_cast(a) }
8509}
8510#[doc = "Fixed-point convert to floating-point"]
8511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_s16)"]
8512#[inline]
8513#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8514#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8515#[cfg_attr(
8516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8517 assert_instr(scvtf, N = 1)
8518)]
8519#[rustc_legacy_const_generics(1)]
8520#[target_feature(enable = "neon,fp16")]
8521#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8522pub fn vcvt_n_f16_s16<const N: i32>(a: int16x4_t) -> float16x4_t {
8523 static_assert!(N >= 1 && N <= 16);
8524 unsafe extern "unadjusted" {
8525 #[cfg_attr(
8526 target_arch = "arm",
8527 link_name = "llvm.arm.neon.vcvtfxs2fp.v4f16.v4i16"
8528 )]
8529 #[cfg_attr(
8530 any(target_arch = "aarch64", target_arch = "arm64ec"),
8531 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f16.v4i16"
8532 )]
8533 fn _vcvt_n_f16_s16(a: int16x4_t, n: i32) -> float16x4_t;
8534 }
8535 unsafe { _vcvt_n_f16_s16(a, N) }
8536}
8537#[doc = "Fixed-point convert to floating-point"]
8538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_s16)"]
8539#[inline]
8540#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8541#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8542#[cfg_attr(
8543 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8544 assert_instr(scvtf, N = 1)
8545)]
8546#[rustc_legacy_const_generics(1)]
8547#[target_feature(enable = "neon,fp16")]
8548#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8549pub fn vcvtq_n_f16_s16<const N: i32>(a: int16x8_t) -> float16x8_t {
8550 static_assert!(N >= 1 && N <= 16);
8551 unsafe extern "unadjusted" {
8552 #[cfg_attr(
8553 target_arch = "arm",
8554 link_name = "llvm.arm.neon.vcvtfxs2fp.v8f16.v8i16"
8555 )]
8556 #[cfg_attr(
8557 any(target_arch = "aarch64", target_arch = "arm64ec"),
8558 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v8f16.v8i16"
8559 )]
8560 fn _vcvtq_n_f16_s16(a: int16x8_t, n: i32) -> float16x8_t;
8561 }
8562 unsafe { _vcvtq_n_f16_s16(a, N) }
8563}
8564#[doc = "Fixed-point convert to floating-point"]
8565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_u16)"]
8566#[inline]
8567#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8568#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8569#[cfg_attr(
8570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8571 assert_instr(ucvtf, N = 1)
8572)]
8573#[rustc_legacy_const_generics(1)]
8574#[target_feature(enable = "neon,fp16")]
8575#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8576pub fn vcvt_n_f16_u16<const N: i32>(a: uint16x4_t) -> float16x4_t {
8577 static_assert!(N >= 1 && N <= 16);
8578 unsafe extern "unadjusted" {
8579 #[cfg_attr(
8580 target_arch = "arm",
8581 link_name = "llvm.arm.neon.vcvtfxu2fp.v4f16.v4i16"
8582 )]
8583 #[cfg_attr(
8584 any(target_arch = "aarch64", target_arch = "arm64ec"),
8585 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f16.v4i16"
8586 )]
8587 fn _vcvt_n_f16_u16(a: uint16x4_t, n: i32) -> float16x4_t;
8588 }
8589 unsafe { _vcvt_n_f16_u16(a, N) }
8590}
8591#[doc = "Fixed-point convert to floating-point"]
8592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_u16)"]
8593#[inline]
8594#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8595#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8596#[cfg_attr(
8597 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8598 assert_instr(ucvtf, N = 1)
8599)]
8600#[rustc_legacy_const_generics(1)]
8601#[target_feature(enable = "neon,fp16")]
8602#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8603pub fn vcvtq_n_f16_u16<const N: i32>(a: uint16x8_t) -> float16x8_t {
8604 static_assert!(N >= 1 && N <= 16);
8605 unsafe extern "unadjusted" {
8606 #[cfg_attr(
8607 target_arch = "arm",
8608 link_name = "llvm.arm.neon.vcvtfxu2fp.v8f16.v8i16"
8609 )]
8610 #[cfg_attr(
8611 any(target_arch = "aarch64", target_arch = "arm64ec"),
8612 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v8f16.v8i16"
8613 )]
8614 fn _vcvtq_n_f16_u16(a: uint16x8_t, n: i32) -> float16x8_t;
8615 }
8616 unsafe { _vcvtq_n_f16_u16(a, N) }
8617}
8618#[doc = "Fixed-point convert to floating-point"]
8619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
8620#[inline]
8621#[cfg(target_arch = "arm")]
8622#[target_feature(enable = "neon,v7")]
8623#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8624#[rustc_legacy_const_generics(1)]
8625#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8626pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
8627 static_assert!(N >= 1 && N <= 32);
8628 unsafe extern "unadjusted" {
8629 #[cfg_attr(
8630 target_arch = "arm",
8631 link_name = "llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32"
8632 )]
8633 fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t;
8634 }
8635 unsafe { _vcvt_n_f32_s32(a, N) }
8636}
8637#[doc = "Fixed-point convert to floating-point"]
8638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
8639#[inline]
8640#[cfg(target_arch = "arm")]
8641#[target_feature(enable = "neon,v7")]
8642#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8643#[rustc_legacy_const_generics(1)]
8644#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8645pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
8646 static_assert!(N >= 1 && N <= 32);
8647 unsafe extern "unadjusted" {
8648 #[cfg_attr(
8649 target_arch = "arm",
8650 link_name = "llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32"
8651 )]
8652 fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t;
8653 }
8654 unsafe { _vcvtq_n_f32_s32(a, N) }
8655}
8656#[doc = "Fixed-point convert to floating-point"]
8657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
8658#[inline]
8659#[target_feature(enable = "neon")]
8660#[cfg(not(target_arch = "arm"))]
8661#[cfg_attr(test, assert_instr(scvtf, N = 2))]
8662#[rustc_legacy_const_generics(1)]
8663#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8664pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
8665 static_assert!(N >= 1 && N <= 32);
8666 unsafe extern "unadjusted" {
8667 #[cfg_attr(
8668 any(target_arch = "aarch64", target_arch = "arm64ec"),
8669 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32"
8670 )]
8671 fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t;
8672 }
8673 unsafe { _vcvt_n_f32_s32(a, N) }
8674}
8675#[doc = "Fixed-point convert to floating-point"]
8676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
8677#[inline]
8678#[target_feature(enable = "neon")]
8679#[cfg(not(target_arch = "arm"))]
8680#[cfg_attr(test, assert_instr(scvtf, N = 2))]
8681#[rustc_legacy_const_generics(1)]
8682#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8683pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
8684 static_assert!(N >= 1 && N <= 32);
8685 unsafe extern "unadjusted" {
8686 #[cfg_attr(
8687 any(target_arch = "aarch64", target_arch = "arm64ec"),
8688 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32"
8689 )]
8690 fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t;
8691 }
8692 unsafe { _vcvtq_n_f32_s32(a, N) }
8693}
8694#[doc = "Fixed-point convert to floating-point"]
8695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
8696#[inline]
8697#[cfg(target_arch = "arm")]
8698#[target_feature(enable = "neon,v7")]
8699#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8700#[rustc_legacy_const_generics(1)]
8701#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8702pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
8703 static_assert!(N >= 1 && N <= 32);
8704 unsafe extern "unadjusted" {
8705 #[cfg_attr(
8706 target_arch = "arm",
8707 link_name = "llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32"
8708 )]
8709 fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t;
8710 }
8711 unsafe { _vcvt_n_f32_u32(a, N) }
8712}
8713#[doc = "Fixed-point convert to floating-point"]
8714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
8715#[inline]
8716#[cfg(target_arch = "arm")]
8717#[target_feature(enable = "neon,v7")]
8718#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8719#[rustc_legacy_const_generics(1)]
8720#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8721pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
8722 static_assert!(N >= 1 && N <= 32);
8723 unsafe extern "unadjusted" {
8724 #[cfg_attr(
8725 target_arch = "arm",
8726 link_name = "llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32"
8727 )]
8728 fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t;
8729 }
8730 unsafe { _vcvtq_n_f32_u32(a, N) }
8731}
8732#[doc = "Fixed-point convert to floating-point"]
8733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
8734#[inline]
8735#[target_feature(enable = "neon")]
8736#[cfg(not(target_arch = "arm"))]
8737#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
8738#[rustc_legacy_const_generics(1)]
8739#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8740pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
8741 static_assert!(N >= 1 && N <= 32);
8742 unsafe extern "unadjusted" {
8743 #[cfg_attr(
8744 any(target_arch = "aarch64", target_arch = "arm64ec"),
8745 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32"
8746 )]
8747 fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t;
8748 }
8749 unsafe { _vcvt_n_f32_u32(a, N) }
8750}
8751#[doc = "Fixed-point convert to floating-point"]
8752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
8753#[inline]
8754#[target_feature(enable = "neon")]
8755#[cfg(not(target_arch = "arm"))]
8756#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
8757#[rustc_legacy_const_generics(1)]
8758#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8759pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
8760 static_assert!(N >= 1 && N <= 32);
8761 unsafe extern "unadjusted" {
8762 #[cfg_attr(
8763 any(target_arch = "aarch64", target_arch = "arm64ec"),
8764 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32"
8765 )]
8766 fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t;
8767 }
8768 unsafe { _vcvtq_n_f32_u32(a, N) }
8769}
8770#[doc = "Floating-point convert to signed fixed-point"]
8771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s16_f16)"]
8772#[inline]
8773#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8774#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8775#[cfg_attr(
8776 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8777 assert_instr(fcvtzs, N = 1)
8778)]
8779#[rustc_legacy_const_generics(1)]
8780#[target_feature(enable = "neon,fp16")]
8781#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8782pub fn vcvt_n_s16_f16<const N: i32>(a: float16x4_t) -> int16x4_t {
8783 static_assert!(N >= 1 && N <= 16);
8784 unsafe extern "unadjusted" {
8785 #[cfg_attr(
8786 target_arch = "arm",
8787 link_name = "llvm.arm.neon.vcvtfp2fxs.v4i16.v4f16"
8788 )]
8789 #[cfg_attr(
8790 any(target_arch = "aarch64", target_arch = "arm64ec"),
8791 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i16.v4f16"
8792 )]
8793 fn _vcvt_n_s16_f16(a: float16x4_t, n: i32) -> int16x4_t;
8794 }
8795 unsafe { _vcvt_n_s16_f16(a, N) }
8796}
8797#[doc = "Floating-point convert to signed fixed-point"]
8798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s16_f16)"]
8799#[inline]
8800#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8801#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8802#[cfg_attr(
8803 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8804 assert_instr(fcvtzs, N = 1)
8805)]
8806#[rustc_legacy_const_generics(1)]
8807#[target_feature(enable = "neon,fp16")]
8808#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8809pub fn vcvtq_n_s16_f16<const N: i32>(a: float16x8_t) -> int16x8_t {
8810 static_assert!(N >= 1 && N <= 16);
8811 unsafe extern "unadjusted" {
8812 #[cfg_attr(
8813 target_arch = "arm",
8814 link_name = "llvm.arm.neon.vcvtfp2fxs.v8i16.v8f16"
8815 )]
8816 #[cfg_attr(
8817 any(target_arch = "aarch64", target_arch = "arm64ec"),
8818 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v8i16.v8f16"
8819 )]
8820 fn _vcvtq_n_s16_f16(a: float16x8_t, n: i32) -> int16x8_t;
8821 }
8822 unsafe { _vcvtq_n_s16_f16(a, N) }
8823}
8824#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
8826#[inline]
8827#[cfg(target_arch = "arm")]
8828#[target_feature(enable = "neon,v7")]
8829#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8830#[rustc_legacy_const_generics(1)]
8831#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8832pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
8833 static_assert!(N >= 1 && N <= 32);
8834 unsafe extern "unadjusted" {
8835 #[cfg_attr(
8836 target_arch = "arm",
8837 link_name = "llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32"
8838 )]
8839 fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t;
8840 }
8841 unsafe { _vcvt_n_s32_f32(a, N) }
8842}
8843#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
8845#[inline]
8846#[cfg(target_arch = "arm")]
8847#[target_feature(enable = "neon,v7")]
8848#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8849#[rustc_legacy_const_generics(1)]
8850#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8851pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
8852 static_assert!(N >= 1 && N <= 32);
8853 unsafe extern "unadjusted" {
8854 #[cfg_attr(
8855 target_arch = "arm",
8856 link_name = "llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32"
8857 )]
8858 fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t;
8859 }
8860 unsafe { _vcvtq_n_s32_f32(a, N) }
8861}
8862#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
8864#[inline]
8865#[target_feature(enable = "neon")]
8866#[cfg(not(target_arch = "arm"))]
8867#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
8868#[rustc_legacy_const_generics(1)]
8869#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8870pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
8871 static_assert!(N >= 1 && N <= 32);
8872 unsafe extern "unadjusted" {
8873 #[cfg_attr(
8874 any(target_arch = "aarch64", target_arch = "arm64ec"),
8875 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32"
8876 )]
8877 fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t;
8878 }
8879 unsafe { _vcvt_n_s32_f32(a, N) }
8880}
8881#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
8883#[inline]
8884#[target_feature(enable = "neon")]
8885#[cfg(not(target_arch = "arm"))]
8886#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
8887#[rustc_legacy_const_generics(1)]
8888#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8889pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
8890 static_assert!(N >= 1 && N <= 32);
8891 unsafe extern "unadjusted" {
8892 #[cfg_attr(
8893 any(target_arch = "aarch64", target_arch = "arm64ec"),
8894 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32"
8895 )]
8896 fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t;
8897 }
8898 unsafe { _vcvtq_n_s32_f32(a, N) }
8899}
8900#[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
8901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u16_f16)"]
8902#[inline]
8903#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8904#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8905#[cfg_attr(
8906 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8907 assert_instr(fcvtzu, N = 1)
8908)]
8909#[rustc_legacy_const_generics(1)]
8910#[target_feature(enable = "neon,fp16")]
8911#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8912pub fn vcvt_n_u16_f16<const N: i32>(a: float16x4_t) -> uint16x4_t {
8913 static_assert!(N >= 1 && N <= 16);
8914 unsafe extern "unadjusted" {
8915 #[cfg_attr(
8916 target_arch = "arm",
8917 link_name = "llvm.arm.neon.vcvtfp2fxu.v4i16.v4f16"
8918 )]
8919 #[cfg_attr(
8920 any(target_arch = "aarch64", target_arch = "arm64ec"),
8921 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i16.v4f16"
8922 )]
8923 fn _vcvt_n_u16_f16(a: float16x4_t, n: i32) -> uint16x4_t;
8924 }
8925 unsafe { _vcvt_n_u16_f16(a, N) }
8926}
8927#[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
8928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u16_f16)"]
8929#[inline]
8930#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8931#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8932#[cfg_attr(
8933 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8934 assert_instr(fcvtzu, N = 1)
8935)]
8936#[rustc_legacy_const_generics(1)]
8937#[target_feature(enable = "neon,fp16")]
8938#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8939pub fn vcvtq_n_u16_f16<const N: i32>(a: float16x8_t) -> uint16x8_t {
8940 static_assert!(N >= 1 && N <= 16);
8941 unsafe extern "unadjusted" {
8942 #[cfg_attr(
8943 target_arch = "arm",
8944 link_name = "llvm.arm.neon.vcvtfp2fxu.v8i16.v8f16"
8945 )]
8946 #[cfg_attr(
8947 any(target_arch = "aarch64", target_arch = "arm64ec"),
8948 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v8i16.v8f16"
8949 )]
8950 fn _vcvtq_n_u16_f16(a: float16x8_t, n: i32) -> uint16x8_t;
8951 }
8952 unsafe { _vcvtq_n_u16_f16(a, N) }
8953}
8954#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
8956#[inline]
8957#[cfg(target_arch = "arm")]
8958#[target_feature(enable = "neon,v7")]
8959#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8960#[rustc_legacy_const_generics(1)]
8961#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8962pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
8963 static_assert!(N >= 1 && N <= 32);
8964 unsafe extern "unadjusted" {
8965 #[cfg_attr(
8966 target_arch = "arm",
8967 link_name = "llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32"
8968 )]
8969 fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t;
8970 }
8971 unsafe { _vcvt_n_u32_f32(a, N) }
8972}
8973#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
8975#[inline]
8976#[cfg(target_arch = "arm")]
8977#[target_feature(enable = "neon,v7")]
8978#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8979#[rustc_legacy_const_generics(1)]
8980#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8981pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
8982 static_assert!(N >= 1 && N <= 32);
8983 unsafe extern "unadjusted" {
8984 #[cfg_attr(
8985 target_arch = "arm",
8986 link_name = "llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32"
8987 )]
8988 fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t;
8989 }
8990 unsafe { _vcvtq_n_u32_f32(a, N) }
8991}
8992#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
8994#[inline]
8995#[target_feature(enable = "neon")]
8996#[cfg(not(target_arch = "arm"))]
8997#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
8998#[rustc_legacy_const_generics(1)]
8999#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9000pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
9001 static_assert!(N >= 1 && N <= 32);
9002 unsafe extern "unadjusted" {
9003 #[cfg_attr(
9004 any(target_arch = "aarch64", target_arch = "arm64ec"),
9005 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32"
9006 )]
9007 fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t;
9008 }
9009 unsafe { _vcvt_n_u32_f32(a, N) }
9010}
9011#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
9012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
9013#[inline]
9014#[target_feature(enable = "neon")]
9015#[cfg(not(target_arch = "arm"))]
9016#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
9017#[rustc_legacy_const_generics(1)]
9018#[stable(feature = "neon_intrinsics", since = "1.59.0")]
9019pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
9020 static_assert!(N >= 1 && N <= 32);
9021 unsafe extern "unadjusted" {
9022 #[cfg_attr(
9023 any(target_arch = "aarch64", target_arch = "arm64ec"),
9024 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32"
9025 )]
9026 fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t;
9027 }
9028 unsafe { _vcvtq_n_u32_f32(a, N) }
9029}
9030#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
9031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s16_f16)"]
9032#[inline]
9033#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9034#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9035#[cfg_attr(
9036 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9037 assert_instr(fcvtzs)
9038)]
9039#[target_feature(enable = "neon,fp16")]
9040#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9041pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t {
9042 unsafe { simd_cast(a) }
9043}
9044#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
9045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s16_f16)"]
9046#[inline]
9047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9048#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9049#[cfg_attr(
9050 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9051 assert_instr(fcvtzs)
9052)]
9053#[target_feature(enable = "neon,fp16")]
9054#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9055pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t {
9056 unsafe { simd_cast(a) }
9057}
9058#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
9059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"]
9060#[inline]
9061#[target_feature(enable = "neon")]
9062#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9063#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9064#[cfg_attr(
9065 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9066 assert_instr(fcvtzs)
9067)]
9068#[cfg_attr(
9069 not(target_arch = "arm"),
9070 stable(feature = "neon_intrinsics", since = "1.59.0")
9071)]
9072#[cfg_attr(
9073 target_arch = "arm",
9074 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9075)]
9076pub fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t {
9077 unsafe extern "unadjusted" {
9078 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v2i32.v2f32")]
9079 #[cfg_attr(
9080 any(target_arch = "aarch64", target_arch = "arm64ec"),
9081 link_name = "llvm.fptosi.sat.v2i32.v2f32"
9082 )]
9083 fn _vcvt_s32_f32(a: float32x2_t) -> int32x2_t;
9084 }
9085 unsafe { _vcvt_s32_f32(a) }
9086}
9087#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
9088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"]
9089#[inline]
9090#[target_feature(enable = "neon")]
9091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9093#[cfg_attr(
9094 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9095 assert_instr(fcvtzs)
9096)]
9097#[cfg_attr(
9098 not(target_arch = "arm"),
9099 stable(feature = "neon_intrinsics", since = "1.59.0")
9100)]
9101#[cfg_attr(
9102 target_arch = "arm",
9103 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9104)]
9105pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
9106 unsafe extern "unadjusted" {
9107 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v4i32.v4f32")]
9108 #[cfg_attr(
9109 any(target_arch = "aarch64", target_arch = "arm64ec"),
9110 link_name = "llvm.fptosi.sat.v4i32.v4f32"
9111 )]
9112 fn _vcvtq_s32_f32(a: float32x4_t) -> int32x4_t;
9113 }
9114 unsafe { _vcvtq_s32_f32(a) }
9115}
9116#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u16_f16)"]
9118#[inline]
9119#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9120#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9121#[cfg_attr(
9122 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9123 assert_instr(fcvtzu)
9124)]
9125#[target_feature(enable = "neon,fp16")]
9126#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9127pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t {
9128 unsafe { simd_cast(a) }
9129}
9130#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u16_f16)"]
9132#[inline]
9133#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9135#[cfg_attr(
9136 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9137 assert_instr(fcvtzu)
9138)]
9139#[target_feature(enable = "neon,fp16")]
9140#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9141pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t {
9142 unsafe { simd_cast(a) }
9143}
9144#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"]
9146#[inline]
9147#[target_feature(enable = "neon")]
9148#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9149#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9150#[cfg_attr(
9151 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9152 assert_instr(fcvtzu)
9153)]
9154#[cfg_attr(
9155 not(target_arch = "arm"),
9156 stable(feature = "neon_intrinsics", since = "1.59.0")
9157)]
9158#[cfg_attr(
9159 target_arch = "arm",
9160 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9161)]
9162pub fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t {
9163 unsafe extern "unadjusted" {
9164 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v2i32.v2f32")]
9165 #[cfg_attr(
9166 any(target_arch = "aarch64", target_arch = "arm64ec"),
9167 link_name = "llvm.fptoui.sat.v2i32.v2f32"
9168 )]
9169 fn _vcvt_u32_f32(a: float32x2_t) -> uint32x2_t;
9170 }
9171 unsafe { _vcvt_u32_f32(a) }
9172}
9173#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"]
9175#[inline]
9176#[target_feature(enable = "neon")]
9177#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9178#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9179#[cfg_attr(
9180 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9181 assert_instr(fcvtzu)
9182)]
9183#[cfg_attr(
9184 not(target_arch = "arm"),
9185 stable(feature = "neon_intrinsics", since = "1.59.0")
9186)]
9187#[cfg_attr(
9188 target_arch = "arm",
9189 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9190)]
9191pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
9192 unsafe extern "unadjusted" {
9193 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v4i32.v4f32")]
9194 #[cfg_attr(
9195 any(target_arch = "aarch64", target_arch = "arm64ec"),
9196 link_name = "llvm.fptoui.sat.v4i32.v4f32"
9197 )]
9198 fn _vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t;
9199 }
9200 unsafe { _vcvtq_u32_f32(a) }
9201}
9202#[doc = "Dot product arithmetic (indexed)"]
9203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
9204#[inline]
9205#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9206#[target_feature(enable = "neon,dotprod")]
9207#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
9208#[cfg_attr(
9209 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9210 assert_instr(sdot, LANE = 0)
9211)]
9212#[rustc_legacy_const_generics(3)]
9213#[cfg_attr(
9214 not(target_arch = "arm"),
9215 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9216)]
9217#[cfg_attr(
9218 target_arch = "arm",
9219 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9220)]
9221pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
9222 static_assert_uimm_bits!(LANE, 1);
9223 unsafe {
9224 let c: int32x2_t = transmute(c);
9225 let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
9226 vdot_s32(a, b, transmute(c))
9227 }
9228}
9229#[doc = "Dot product arithmetic (indexed)"]
9230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
9231#[inline]
9232#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9233#[target_feature(enable = "neon,dotprod")]
9234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
9235#[cfg_attr(
9236 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9237 assert_instr(sdot, LANE = 0)
9238)]
9239#[rustc_legacy_const_generics(3)]
9240#[cfg_attr(
9241 not(target_arch = "arm"),
9242 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9243)]
9244#[cfg_attr(
9245 target_arch = "arm",
9246 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9247)]
9248pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
9249 static_assert_uimm_bits!(LANE, 1);
9250 unsafe {
9251 let c: int32x2_t = transmute(c);
9252 let c: int32x4_t =
9253 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
9254 vdotq_s32(a, b, transmute(c))
9255 }
9256}
9257#[doc = "Dot product arithmetic (indexed)"]
9258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
9259#[inline]
9260#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9261#[target_feature(enable = "neon,dotprod")]
9262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
9263#[cfg_attr(
9264 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9265 assert_instr(udot, LANE = 0)
9266)]
9267#[rustc_legacy_const_generics(3)]
9268#[cfg_attr(
9269 not(target_arch = "arm"),
9270 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9271)]
9272#[cfg_attr(
9273 target_arch = "arm",
9274 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9275)]
9276pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
9277 static_assert_uimm_bits!(LANE, 1);
9278 unsafe {
9279 let c: uint32x2_t = transmute(c);
9280 let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
9281 vdot_u32(a, b, transmute(c))
9282 }
9283}
9284#[doc = "Dot product arithmetic (indexed)"]
9285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
9286#[inline]
9287#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9288#[target_feature(enable = "neon,dotprod")]
9289#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
9290#[cfg_attr(
9291 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9292 assert_instr(udot, LANE = 0)
9293)]
9294#[rustc_legacy_const_generics(3)]
9295#[cfg_attr(
9296 not(target_arch = "arm"),
9297 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9298)]
9299#[cfg_attr(
9300 target_arch = "arm",
9301 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9302)]
9303pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
9304 static_assert_uimm_bits!(LANE, 1);
9305 unsafe {
9306 let c: uint32x2_t = transmute(c);
9307 let c: uint32x4_t =
9308 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
9309 vdotq_u32(a, b, transmute(c))
9310 }
9311}
9312#[doc = "Dot product arithmetic (vector)"]
9313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
9314#[inline]
9315#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9316#[target_feature(enable = "neon,dotprod")]
9317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
9318#[cfg_attr(
9319 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9320 assert_instr(sdot)
9321)]
9322#[cfg_attr(
9323 not(target_arch = "arm"),
9324 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9325)]
9326#[cfg_attr(
9327 target_arch = "arm",
9328 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9329)]
9330pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
9331 unsafe extern "unadjusted" {
9332 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v2i32.v8i8")]
9333 #[cfg_attr(
9334 any(target_arch = "aarch64", target_arch = "arm64ec"),
9335 link_name = "llvm.aarch64.neon.sdot.v2i32.v8i8"
9336 )]
9337 fn _vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t;
9338 }
9339 unsafe { _vdot_s32(a, b, c) }
9340}
9341#[doc = "Dot product arithmetic (vector)"]
9342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"]
9343#[inline]
9344#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9345#[target_feature(enable = "neon,dotprod")]
9346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
9347#[cfg_attr(
9348 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9349 assert_instr(sdot)
9350)]
9351#[cfg_attr(
9352 not(target_arch = "arm"),
9353 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9354)]
9355#[cfg_attr(
9356 target_arch = "arm",
9357 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9358)]
9359pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
9360 unsafe extern "unadjusted" {
9361 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v4i32.v16i8")]
9362 #[cfg_attr(
9363 any(target_arch = "aarch64", target_arch = "arm64ec"),
9364 link_name = "llvm.aarch64.neon.sdot.v4i32.v16i8"
9365 )]
9366 fn _vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t;
9367 }
9368 unsafe { _vdotq_s32(a, b, c) }
9369}
9370#[doc = "Dot product arithmetic (vector)"]
9371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"]
9372#[inline]
9373#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9374#[target_feature(enable = "neon,dotprod")]
9375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
9376#[cfg_attr(
9377 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9378 assert_instr(udot)
9379)]
9380#[cfg_attr(
9381 not(target_arch = "arm"),
9382 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9383)]
9384#[cfg_attr(
9385 target_arch = "arm",
9386 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9387)]
9388pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
9389 unsafe extern "unadjusted" {
9390 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v2i32.v8i8")]
9391 #[cfg_attr(
9392 any(target_arch = "aarch64", target_arch = "arm64ec"),
9393 link_name = "llvm.aarch64.neon.udot.v2i32.v8i8"
9394 )]
9395 fn _vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t;
9396 }
9397 unsafe { _vdot_u32(a, b, c) }
9398}
9399#[doc = "Dot product arithmetic (vector)"]
9400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"]
9401#[inline]
9402#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9403#[target_feature(enable = "neon,dotprod")]
9404#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
9405#[cfg_attr(
9406 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9407 assert_instr(udot)
9408)]
9409#[cfg_attr(
9410 not(target_arch = "arm"),
9411 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9412)]
9413#[cfg_attr(
9414 target_arch = "arm",
9415 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9416)]
9417pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
9418 unsafe extern "unadjusted" {
9419 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v4i32.v16i8")]
9420 #[cfg_attr(
9421 any(target_arch = "aarch64", target_arch = "arm64ec"),
9422 link_name = "llvm.aarch64.neon.udot.v4i32.v16i8"
9423 )]
9424 fn _vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t;
9425 }
9426 unsafe { _vdotq_u32(a, b, c) }
9427}
9428#[doc = "Set all vector lanes to the same value"]
9429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"]
9430#[inline]
9431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9432#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9433#[cfg_attr(
9434 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9435 assert_instr(dup, N = 2)
9436)]
9437#[rustc_legacy_const_generics(1)]
9438#[target_feature(enable = "neon,fp16")]
9439#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9440pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
9441 static_assert_uimm_bits!(N, 2);
9442 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9443}
9444#[doc = "Set all vector lanes to the same value"]
9445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"]
9446#[inline]
9447#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9448#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9449#[cfg_attr(
9450 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9451 assert_instr(dup, N = 2)
9452)]
9453#[rustc_legacy_const_generics(1)]
9454#[target_feature(enable = "neon,fp16")]
9455#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9456pub fn vdupq_lane_f16<const N: i32>(a: float16x4_t) -> float16x8_t {
9457 static_assert_uimm_bits!(N, 2);
9458 unsafe {
9459 simd_shuffle!(
9460 a,
9461 a,
9462 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9463 )
9464 }
9465}
9466#[doc = "Set all vector lanes to the same value"]
9467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"]
9468#[inline]
9469#[target_feature(enable = "neon")]
9470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9471#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9472#[cfg_attr(
9473 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9474 assert_instr(dup, N = 1)
9475)]
9476#[rustc_legacy_const_generics(1)]
9477#[cfg_attr(
9478 not(target_arch = "arm"),
9479 stable(feature = "neon_intrinsics", since = "1.59.0")
9480)]
9481#[cfg_attr(
9482 target_arch = "arm",
9483 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9484)]
9485pub fn vdup_lane_f32<const N: i32>(a: float32x2_t) -> float32x2_t {
9486 static_assert_uimm_bits!(N, 1);
9487 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9488}
9489#[doc = "Set all vector lanes to the same value"]
9490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"]
9491#[inline]
9492#[target_feature(enable = "neon")]
9493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9494#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9495#[cfg_attr(
9496 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9497 assert_instr(dup, N = 1)
9498)]
9499#[rustc_legacy_const_generics(1)]
9500#[cfg_attr(
9501 not(target_arch = "arm"),
9502 stable(feature = "neon_intrinsics", since = "1.59.0")
9503)]
9504#[cfg_attr(
9505 target_arch = "arm",
9506 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9507)]
9508pub fn vdup_lane_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
9509 static_assert_uimm_bits!(N, 1);
9510 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9511}
9512#[doc = "Set all vector lanes to the same value"]
9513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"]
9514#[inline]
9515#[target_feature(enable = "neon")]
9516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9517#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9518#[cfg_attr(
9519 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9520 assert_instr(dup, N = 1)
9521)]
9522#[rustc_legacy_const_generics(1)]
9523#[cfg_attr(
9524 not(target_arch = "arm"),
9525 stable(feature = "neon_intrinsics", since = "1.59.0")
9526)]
9527#[cfg_attr(
9528 target_arch = "arm",
9529 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9530)]
9531pub fn vdup_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
9532 static_assert_uimm_bits!(N, 1);
9533 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9534}
9535#[doc = "Set all vector lanes to the same value"]
9536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"]
9537#[inline]
9538#[target_feature(enable = "neon")]
9539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9540#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9541#[cfg_attr(
9542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9543 assert_instr(dup, N = 1)
9544)]
9545#[rustc_legacy_const_generics(1)]
9546#[cfg_attr(
9547 not(target_arch = "arm"),
9548 stable(feature = "neon_intrinsics", since = "1.59.0")
9549)]
9550#[cfg_attr(
9551 target_arch = "arm",
9552 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9553)]
9554pub fn vdupq_lane_f32<const N: i32>(a: float32x2_t) -> float32x4_t {
9555 static_assert_uimm_bits!(N, 1);
9556 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9557}
9558#[doc = "Set all vector lanes to the same value"]
9559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"]
9560#[inline]
9561#[target_feature(enable = "neon")]
9562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9563#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9564#[cfg_attr(
9565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9566 assert_instr(dup, N = 1)
9567)]
9568#[rustc_legacy_const_generics(1)]
9569#[cfg_attr(
9570 not(target_arch = "arm"),
9571 stable(feature = "neon_intrinsics", since = "1.59.0")
9572)]
9573#[cfg_attr(
9574 target_arch = "arm",
9575 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9576)]
9577pub fn vdupq_lane_s32<const N: i32>(a: int32x2_t) -> int32x4_t {
9578 static_assert_uimm_bits!(N, 1);
9579 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9580}
9581#[doc = "Set all vector lanes to the same value"]
9582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"]
9583#[inline]
9584#[target_feature(enable = "neon")]
9585#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9586#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9587#[cfg_attr(
9588 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9589 assert_instr(dup, N = 1)
9590)]
9591#[rustc_legacy_const_generics(1)]
9592#[cfg_attr(
9593 not(target_arch = "arm"),
9594 stable(feature = "neon_intrinsics", since = "1.59.0")
9595)]
9596#[cfg_attr(
9597 target_arch = "arm",
9598 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9599)]
9600pub fn vdupq_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x4_t {
9601 static_assert_uimm_bits!(N, 1);
9602 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9603}
9604#[doc = "Set all vector lanes to the same value"]
9605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"]
9606#[inline]
9607#[target_feature(enable = "neon")]
9608#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9609#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9610#[cfg_attr(
9611 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9612 assert_instr(dup, N = 2)
9613)]
9614#[rustc_legacy_const_generics(1)]
9615#[cfg_attr(
9616 not(target_arch = "arm"),
9617 stable(feature = "neon_intrinsics", since = "1.59.0")
9618)]
9619#[cfg_attr(
9620 target_arch = "arm",
9621 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9622)]
9623pub fn vdup_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x4_t {
9624 static_assert_uimm_bits!(N, 2);
9625 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9626}
9627#[doc = "Set all vector lanes to the same value"]
9628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"]
9629#[inline]
9630#[target_feature(enable = "neon")]
9631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9632#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9633#[cfg_attr(
9634 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9635 assert_instr(dup, N = 2)
9636)]
9637#[rustc_legacy_const_generics(1)]
9638#[cfg_attr(
9639 not(target_arch = "arm"),
9640 stable(feature = "neon_intrinsics", since = "1.59.0")
9641)]
9642#[cfg_attr(
9643 target_arch = "arm",
9644 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9645)]
9646pub fn vdup_lane_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
9647 static_assert_uimm_bits!(N, 2);
9648 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9649}
9650#[doc = "Set all vector lanes to the same value"]
9651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"]
9652#[inline]
9653#[target_feature(enable = "neon")]
9654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9655#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9656#[cfg_attr(
9657 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9658 assert_instr(dup, N = 2)
9659)]
9660#[rustc_legacy_const_generics(1)]
9661#[cfg_attr(
9662 not(target_arch = "arm"),
9663 stable(feature = "neon_intrinsics", since = "1.59.0")
9664)]
9665#[cfg_attr(
9666 target_arch = "arm",
9667 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9668)]
9669pub fn vdup_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
9670 static_assert_uimm_bits!(N, 2);
9671 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9672}
9673#[doc = "Set all vector lanes to the same value"]
9674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"]
9675#[inline]
9676#[target_feature(enable = "neon")]
9677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9678#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9679#[cfg_attr(
9680 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9681 assert_instr(dup, N = 2)
9682)]
9683#[rustc_legacy_const_generics(1)]
9684#[cfg_attr(
9685 not(target_arch = "arm"),
9686 stable(feature = "neon_intrinsics", since = "1.59.0")
9687)]
9688#[cfg_attr(
9689 target_arch = "arm",
9690 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9691)]
9692pub fn vdupq_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x8_t {
9693 static_assert_uimm_bits!(N, 2);
9694 unsafe {
9695 simd_shuffle!(
9696 a,
9697 a,
9698 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9699 )
9700 }
9701}
9702#[doc = "Set all vector lanes to the same value"]
9703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"]
9704#[inline]
9705#[target_feature(enable = "neon")]
9706#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9707#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9708#[cfg_attr(
9709 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9710 assert_instr(dup, N = 2)
9711)]
9712#[rustc_legacy_const_generics(1)]
9713#[cfg_attr(
9714 not(target_arch = "arm"),
9715 stable(feature = "neon_intrinsics", since = "1.59.0")
9716)]
9717#[cfg_attr(
9718 target_arch = "arm",
9719 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9720)]
9721pub fn vdupq_lane_s16<const N: i32>(a: int16x4_t) -> int16x8_t {
9722 static_assert_uimm_bits!(N, 2);
9723 unsafe {
9724 simd_shuffle!(
9725 a,
9726 a,
9727 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9728 )
9729 }
9730}
9731#[doc = "Set all vector lanes to the same value"]
9732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"]
9733#[inline]
9734#[target_feature(enable = "neon")]
9735#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9736#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9737#[cfg_attr(
9738 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9739 assert_instr(dup, N = 2)
9740)]
9741#[rustc_legacy_const_generics(1)]
9742#[cfg_attr(
9743 not(target_arch = "arm"),
9744 stable(feature = "neon_intrinsics", since = "1.59.0")
9745)]
9746#[cfg_attr(
9747 target_arch = "arm",
9748 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9749)]
9750pub fn vdupq_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x8_t {
9751 static_assert_uimm_bits!(N, 2);
9752 unsafe {
9753 simd_shuffle!(
9754 a,
9755 a,
9756 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9757 )
9758 }
9759}
9760#[doc = "Set all vector lanes to the same value"]
9761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"]
9762#[inline]
9763#[target_feature(enable = "neon")]
9764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9765#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9766#[cfg_attr(
9767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9768 assert_instr(dup, N = 4)
9769)]
9770#[rustc_legacy_const_generics(1)]
9771#[cfg_attr(
9772 not(target_arch = "arm"),
9773 stable(feature = "neon_intrinsics", since = "1.59.0")
9774)]
9775#[cfg_attr(
9776 target_arch = "arm",
9777 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9778)]
9779pub fn vdup_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x8_t {
9780 static_assert_uimm_bits!(N, 3);
9781 unsafe {
9782 simd_shuffle!(
9783 a,
9784 a,
9785 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9786 )
9787 }
9788}
9789#[doc = "Set all vector lanes to the same value"]
9790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"]
9791#[inline]
9792#[target_feature(enable = "neon")]
9793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9794#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9795#[cfg_attr(
9796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9797 assert_instr(dup, N = 4)
9798)]
9799#[rustc_legacy_const_generics(1)]
9800#[cfg_attr(
9801 not(target_arch = "arm"),
9802 stable(feature = "neon_intrinsics", since = "1.59.0")
9803)]
9804#[cfg_attr(
9805 target_arch = "arm",
9806 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9807)]
9808pub fn vdup_lane_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
9809 static_assert_uimm_bits!(N, 3);
9810 unsafe {
9811 simd_shuffle!(
9812 a,
9813 a,
9814 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9815 )
9816 }
9817}
9818#[doc = "Set all vector lanes to the same value"]
9819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"]
9820#[inline]
9821#[target_feature(enable = "neon")]
9822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9823#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9824#[cfg_attr(
9825 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9826 assert_instr(dup, N = 4)
9827)]
9828#[rustc_legacy_const_generics(1)]
9829#[cfg_attr(
9830 not(target_arch = "arm"),
9831 stable(feature = "neon_intrinsics", since = "1.59.0")
9832)]
9833#[cfg_attr(
9834 target_arch = "arm",
9835 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9836)]
9837pub fn vdup_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
9838 static_assert_uimm_bits!(N, 3);
9839 unsafe {
9840 simd_shuffle!(
9841 a,
9842 a,
9843 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9844 )
9845 }
9846}
9847#[doc = "Set all vector lanes to the same value"]
9848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"]
9849#[inline]
9850#[target_feature(enable = "neon")]
9851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9852#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9853#[cfg_attr(
9854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9855 assert_instr(dup, N = 4)
9856)]
9857#[rustc_legacy_const_generics(1)]
9858#[cfg_attr(
9859 not(target_arch = "arm"),
9860 stable(feature = "neon_intrinsics", since = "1.59.0")
9861)]
9862#[cfg_attr(
9863 target_arch = "arm",
9864 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9865)]
9866pub fn vdupq_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x16_t {
9867 static_assert_uimm_bits!(N, 3);
9868 unsafe {
9869 simd_shuffle!(
9870 a,
9871 a,
9872 [
9873 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9874 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9875 ]
9876 )
9877 }
9878}
9879#[doc = "Set all vector lanes to the same value"]
9880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"]
9881#[inline]
9882#[target_feature(enable = "neon")]
9883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9884#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9885#[cfg_attr(
9886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9887 assert_instr(dup, N = 4)
9888)]
9889#[rustc_legacy_const_generics(1)]
9890#[cfg_attr(
9891 not(target_arch = "arm"),
9892 stable(feature = "neon_intrinsics", since = "1.59.0")
9893)]
9894#[cfg_attr(
9895 target_arch = "arm",
9896 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9897)]
9898pub fn vdupq_lane_s8<const N: i32>(a: int8x8_t) -> int8x16_t {
9899 static_assert_uimm_bits!(N, 3);
9900 unsafe {
9901 simd_shuffle!(
9902 a,
9903 a,
9904 [
9905 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9906 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9907 ]
9908 )
9909 }
9910}
9911#[doc = "Set all vector lanes to the same value"]
9912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"]
9913#[inline]
9914#[target_feature(enable = "neon")]
9915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9916#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9917#[cfg_attr(
9918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9919 assert_instr(dup, N = 4)
9920)]
9921#[rustc_legacy_const_generics(1)]
9922#[cfg_attr(
9923 not(target_arch = "arm"),
9924 stable(feature = "neon_intrinsics", since = "1.59.0")
9925)]
9926#[cfg_attr(
9927 target_arch = "arm",
9928 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9929)]
9930pub fn vdupq_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x16_t {
9931 static_assert_uimm_bits!(N, 3);
9932 unsafe {
9933 simd_shuffle!(
9934 a,
9935 a,
9936 [
9937 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9938 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9939 ]
9940 )
9941 }
9942}
9943#[doc = "Set all vector lanes to the same value"]
9944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"]
9945#[inline]
9946#[target_feature(enable = "neon")]
9947#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9948#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
9949#[cfg_attr(
9950 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9951 assert_instr(nop, N = 0)
9952)]
9953#[rustc_legacy_const_generics(1)]
9954#[cfg_attr(
9955 not(target_arch = "arm"),
9956 stable(feature = "neon_intrinsics", since = "1.59.0")
9957)]
9958#[cfg_attr(
9959 target_arch = "arm",
9960 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9961)]
9962pub fn vdup_lane_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
9963 static_assert!(N == 0);
9964 a
9965}
9966#[doc = "Set all vector lanes to the same value"]
9967#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"]
9968#[inline]
9969#[target_feature(enable = "neon")]
9970#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9971#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
9972#[cfg_attr(
9973 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9974 assert_instr(nop, N = 0)
9975)]
9976#[rustc_legacy_const_generics(1)]
9977#[cfg_attr(
9978 not(target_arch = "arm"),
9979 stable(feature = "neon_intrinsics", since = "1.59.0")
9980)]
9981#[cfg_attr(
9982 target_arch = "arm",
9983 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9984)]
9985pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
9986 static_assert!(N == 0);
9987 a
9988}
9989#[doc = "Set all vector lanes to the same value"]
9990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"]
9991#[inline]
9992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9993#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
9994#[cfg_attr(
9995 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9996 assert_instr(dup, N = 4)
9997)]
9998#[rustc_legacy_const_generics(1)]
9999#[target_feature(enable = "neon,fp16")]
10000#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10001pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
10002 static_assert_uimm_bits!(N, 3);
10003 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10004}
10005#[doc = "Set all vector lanes to the same value"]
10006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"]
10007#[inline]
10008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10009#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10010#[cfg_attr(
10011 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10012 assert_instr(dup, N = 4)
10013)]
10014#[rustc_legacy_const_generics(1)]
10015#[target_feature(enable = "neon,fp16")]
10016#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10017pub fn vdupq_laneq_f16<const N: i32>(a: float16x8_t) -> float16x8_t {
10018 static_assert_uimm_bits!(N, 3);
10019 unsafe {
10020 simd_shuffle!(
10021 a,
10022 a,
10023 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10024 )
10025 }
10026}
10027#[doc = "Set all vector lanes to the same value"]
10028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"]
10029#[inline]
10030#[target_feature(enable = "neon")]
10031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10032#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10033#[cfg_attr(
10034 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10035 assert_instr(dup, N = 2)
10036)]
10037#[rustc_legacy_const_generics(1)]
10038#[cfg_attr(
10039 not(target_arch = "arm"),
10040 stable(feature = "neon_intrinsics", since = "1.59.0")
10041)]
10042#[cfg_attr(
10043 target_arch = "arm",
10044 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10045)]
10046pub fn vdup_laneq_f32<const N: i32>(a: float32x4_t) -> float32x2_t {
10047 static_assert_uimm_bits!(N, 2);
10048 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
10049}
10050#[doc = "Set all vector lanes to the same value"]
10051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"]
10052#[inline]
10053#[target_feature(enable = "neon")]
10054#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10055#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10056#[cfg_attr(
10057 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10058 assert_instr(dup, N = 2)
10059)]
10060#[rustc_legacy_const_generics(1)]
10061#[cfg_attr(
10062 not(target_arch = "arm"),
10063 stable(feature = "neon_intrinsics", since = "1.59.0")
10064)]
10065#[cfg_attr(
10066 target_arch = "arm",
10067 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10068)]
10069pub fn vdup_laneq_s32<const N: i32>(a: int32x4_t) -> int32x2_t {
10070 static_assert_uimm_bits!(N, 2);
10071 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
10072}
10073#[doc = "Set all vector lanes to the same value"]
10074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"]
10075#[inline]
10076#[target_feature(enable = "neon")]
10077#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10078#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10079#[cfg_attr(
10080 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10081 assert_instr(dup, N = 2)
10082)]
10083#[rustc_legacy_const_generics(1)]
10084#[cfg_attr(
10085 not(target_arch = "arm"),
10086 stable(feature = "neon_intrinsics", since = "1.59.0")
10087)]
10088#[cfg_attr(
10089 target_arch = "arm",
10090 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10091)]
10092pub fn vdup_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x2_t {
10093 static_assert_uimm_bits!(N, 2);
10094 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
10095}
10096#[doc = "Set all vector lanes to the same value"]
10097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"]
10098#[inline]
10099#[target_feature(enable = "neon")]
10100#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10101#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10102#[cfg_attr(
10103 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10104 assert_instr(dup, N = 2)
10105)]
10106#[rustc_legacy_const_generics(1)]
10107#[cfg_attr(
10108 not(target_arch = "arm"),
10109 stable(feature = "neon_intrinsics", since = "1.59.0")
10110)]
10111#[cfg_attr(
10112 target_arch = "arm",
10113 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10114)]
10115pub fn vdupq_laneq_f32<const N: i32>(a: float32x4_t) -> float32x4_t {
10116 static_assert_uimm_bits!(N, 2);
10117 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10118}
10119#[doc = "Set all vector lanes to the same value"]
10120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"]
10121#[inline]
10122#[target_feature(enable = "neon")]
10123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10124#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10125#[cfg_attr(
10126 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10127 assert_instr(dup, N = 2)
10128)]
10129#[rustc_legacy_const_generics(1)]
10130#[cfg_attr(
10131 not(target_arch = "arm"),
10132 stable(feature = "neon_intrinsics", since = "1.59.0")
10133)]
10134#[cfg_attr(
10135 target_arch = "arm",
10136 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10137)]
10138pub fn vdupq_laneq_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
10139 static_assert_uimm_bits!(N, 2);
10140 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10141}
10142#[doc = "Set all vector lanes to the same value"]
10143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"]
10144#[inline]
10145#[target_feature(enable = "neon")]
10146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10147#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10148#[cfg_attr(
10149 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10150 assert_instr(dup, N = 2)
10151)]
10152#[rustc_legacy_const_generics(1)]
10153#[cfg_attr(
10154 not(target_arch = "arm"),
10155 stable(feature = "neon_intrinsics", since = "1.59.0")
10156)]
10157#[cfg_attr(
10158 target_arch = "arm",
10159 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10160)]
10161pub fn vdupq_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
10162 static_assert_uimm_bits!(N, 2);
10163 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10164}
10165#[doc = "Set all vector lanes to the same value"]
10166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"]
10167#[inline]
10168#[target_feature(enable = "neon")]
10169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10170#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10171#[cfg_attr(
10172 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10173 assert_instr(dup, N = 4)
10174)]
10175#[rustc_legacy_const_generics(1)]
10176#[cfg_attr(
10177 not(target_arch = "arm"),
10178 stable(feature = "neon_intrinsics", since = "1.59.0")
10179)]
10180#[cfg_attr(
10181 target_arch = "arm",
10182 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10183)]
10184pub fn vdup_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x4_t {
10185 static_assert_uimm_bits!(N, 3);
10186 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10187}
10188#[doc = "Set all vector lanes to the same value"]
10189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"]
10190#[inline]
10191#[target_feature(enable = "neon")]
10192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10193#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10194#[cfg_attr(
10195 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10196 assert_instr(dup, N = 4)
10197)]
10198#[rustc_legacy_const_generics(1)]
10199#[cfg_attr(
10200 not(target_arch = "arm"),
10201 stable(feature = "neon_intrinsics", since = "1.59.0")
10202)]
10203#[cfg_attr(
10204 target_arch = "arm",
10205 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10206)]
10207pub fn vdup_laneq_s16<const N: i32>(a: int16x8_t) -> int16x4_t {
10208 static_assert_uimm_bits!(N, 3);
10209 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10210}
10211#[doc = "Set all vector lanes to the same value"]
10212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"]
10213#[inline]
10214#[target_feature(enable = "neon")]
10215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10216#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10217#[cfg_attr(
10218 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10219 assert_instr(dup, N = 4)
10220)]
10221#[rustc_legacy_const_generics(1)]
10222#[cfg_attr(
10223 not(target_arch = "arm"),
10224 stable(feature = "neon_intrinsics", since = "1.59.0")
10225)]
10226#[cfg_attr(
10227 target_arch = "arm",
10228 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10229)]
10230pub fn vdup_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x4_t {
10231 static_assert_uimm_bits!(N, 3);
10232 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10233}
10234#[doc = "Set all vector lanes to the same value"]
10235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"]
10236#[inline]
10237#[target_feature(enable = "neon")]
10238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10239#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10240#[cfg_attr(
10241 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10242 assert_instr(dup, N = 4)
10243)]
10244#[rustc_legacy_const_generics(1)]
10245#[cfg_attr(
10246 not(target_arch = "arm"),
10247 stable(feature = "neon_intrinsics", since = "1.59.0")
10248)]
10249#[cfg_attr(
10250 target_arch = "arm",
10251 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10252)]
10253pub fn vdupq_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x8_t {
10254 static_assert_uimm_bits!(N, 3);
10255 unsafe {
10256 simd_shuffle!(
10257 a,
10258 a,
10259 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10260 )
10261 }
10262}
10263#[doc = "Set all vector lanes to the same value"]
10264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"]
10265#[inline]
10266#[target_feature(enable = "neon")]
10267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10268#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10269#[cfg_attr(
10270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10271 assert_instr(dup, N = 4)
10272)]
10273#[rustc_legacy_const_generics(1)]
10274#[cfg_attr(
10275 not(target_arch = "arm"),
10276 stable(feature = "neon_intrinsics", since = "1.59.0")
10277)]
10278#[cfg_attr(
10279 target_arch = "arm",
10280 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10281)]
10282pub fn vdupq_laneq_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
10283 static_assert_uimm_bits!(N, 3);
10284 unsafe {
10285 simd_shuffle!(
10286 a,
10287 a,
10288 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10289 )
10290 }
10291}
10292#[doc = "Set all vector lanes to the same value"]
10293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"]
10294#[inline]
10295#[target_feature(enable = "neon")]
10296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10297#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10298#[cfg_attr(
10299 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10300 assert_instr(dup, N = 4)
10301)]
10302#[rustc_legacy_const_generics(1)]
10303#[cfg_attr(
10304 not(target_arch = "arm"),
10305 stable(feature = "neon_intrinsics", since = "1.59.0")
10306)]
10307#[cfg_attr(
10308 target_arch = "arm",
10309 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10310)]
10311pub fn vdupq_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
10312 static_assert_uimm_bits!(N, 3);
10313 unsafe {
10314 simd_shuffle!(
10315 a,
10316 a,
10317 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10318 )
10319 }
10320}
10321#[doc = "Set all vector lanes to the same value"]
10322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"]
10323#[inline]
10324#[target_feature(enable = "neon")]
10325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10326#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10327#[cfg_attr(
10328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10329 assert_instr(dup, N = 8)
10330)]
10331#[rustc_legacy_const_generics(1)]
10332#[cfg_attr(
10333 not(target_arch = "arm"),
10334 stable(feature = "neon_intrinsics", since = "1.59.0")
10335)]
10336#[cfg_attr(
10337 target_arch = "arm",
10338 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10339)]
10340pub fn vdup_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x8_t {
10341 static_assert_uimm_bits!(N, 4);
10342 unsafe {
10343 simd_shuffle!(
10344 a,
10345 a,
10346 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10347 )
10348 }
10349}
10350#[doc = "Set all vector lanes to the same value"]
10351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"]
10352#[inline]
10353#[target_feature(enable = "neon")]
10354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10355#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10356#[cfg_attr(
10357 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10358 assert_instr(dup, N = 8)
10359)]
10360#[rustc_legacy_const_generics(1)]
10361#[cfg_attr(
10362 not(target_arch = "arm"),
10363 stable(feature = "neon_intrinsics", since = "1.59.0")
10364)]
10365#[cfg_attr(
10366 target_arch = "arm",
10367 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10368)]
10369pub fn vdup_laneq_s8<const N: i32>(a: int8x16_t) -> int8x8_t {
10370 static_assert_uimm_bits!(N, 4);
10371 unsafe {
10372 simd_shuffle!(
10373 a,
10374 a,
10375 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10376 )
10377 }
10378}
10379#[doc = "Set all vector lanes to the same value"]
10380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"]
10381#[inline]
10382#[target_feature(enable = "neon")]
10383#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10384#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10385#[cfg_attr(
10386 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10387 assert_instr(dup, N = 8)
10388)]
10389#[rustc_legacy_const_generics(1)]
10390#[cfg_attr(
10391 not(target_arch = "arm"),
10392 stable(feature = "neon_intrinsics", since = "1.59.0")
10393)]
10394#[cfg_attr(
10395 target_arch = "arm",
10396 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10397)]
10398pub fn vdup_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x8_t {
10399 static_assert_uimm_bits!(N, 4);
10400 unsafe {
10401 simd_shuffle!(
10402 a,
10403 a,
10404 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10405 )
10406 }
10407}
10408#[doc = "Set all vector lanes to the same value"]
10409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"]
10410#[inline]
10411#[target_feature(enable = "neon")]
10412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10413#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10414#[cfg_attr(
10415 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10416 assert_instr(dup, N = 8)
10417)]
10418#[rustc_legacy_const_generics(1)]
10419#[cfg_attr(
10420 not(target_arch = "arm"),
10421 stable(feature = "neon_intrinsics", since = "1.59.0")
10422)]
10423#[cfg_attr(
10424 target_arch = "arm",
10425 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10426)]
10427pub fn vdupq_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x16_t {
10428 static_assert_uimm_bits!(N, 4);
10429 unsafe {
10430 simd_shuffle!(
10431 a,
10432 a,
10433 [
10434 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10435 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10436 ]
10437 )
10438 }
10439}
10440#[doc = "Set all vector lanes to the same value"]
10441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"]
10442#[inline]
10443#[target_feature(enable = "neon")]
10444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10445#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10446#[cfg_attr(
10447 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10448 assert_instr(dup, N = 8)
10449)]
10450#[rustc_legacy_const_generics(1)]
10451#[cfg_attr(
10452 not(target_arch = "arm"),
10453 stable(feature = "neon_intrinsics", since = "1.59.0")
10454)]
10455#[cfg_attr(
10456 target_arch = "arm",
10457 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10458)]
10459pub fn vdupq_laneq_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
10460 static_assert_uimm_bits!(N, 4);
10461 unsafe {
10462 simd_shuffle!(
10463 a,
10464 a,
10465 [
10466 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10467 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10468 ]
10469 )
10470 }
10471}
10472#[doc = "Set all vector lanes to the same value"]
10473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"]
10474#[inline]
10475#[target_feature(enable = "neon")]
10476#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10477#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10478#[cfg_attr(
10479 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10480 assert_instr(dup, N = 8)
10481)]
10482#[rustc_legacy_const_generics(1)]
10483#[cfg_attr(
10484 not(target_arch = "arm"),
10485 stable(feature = "neon_intrinsics", since = "1.59.0")
10486)]
10487#[cfg_attr(
10488 target_arch = "arm",
10489 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10490)]
10491pub fn vdupq_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
10492 static_assert_uimm_bits!(N, 4);
10493 unsafe {
10494 simd_shuffle!(
10495 a,
10496 a,
10497 [
10498 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10499 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10500 ]
10501 )
10502 }
10503}
10504#[doc = "Set all vector lanes to the same value"]
10505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"]
10506#[inline]
10507#[target_feature(enable = "neon")]
10508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10509#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
10510#[cfg_attr(
10511 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10512 assert_instr(nop, N = 1)
10513)]
10514#[rustc_legacy_const_generics(1)]
10515#[cfg_attr(
10516 not(target_arch = "arm"),
10517 stable(feature = "neon_intrinsics", since = "1.59.0")
10518)]
10519#[cfg_attr(
10520 target_arch = "arm",
10521 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10522)]
10523pub fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
10524 static_assert_uimm_bits!(N, 1);
10525 unsafe { transmute::<i64, _>(simd_extract!(a, N as u32)) }
10526}
10527#[doc = "Set all vector lanes to the same value"]
10528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"]
10529#[inline]
10530#[target_feature(enable = "neon")]
10531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
10533#[cfg_attr(
10534 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10535 assert_instr(nop, N = 1)
10536)]
10537#[rustc_legacy_const_generics(1)]
10538#[cfg_attr(
10539 not(target_arch = "arm"),
10540 stable(feature = "neon_intrinsics", since = "1.59.0")
10541)]
10542#[cfg_attr(
10543 target_arch = "arm",
10544 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10545)]
10546pub fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
10547 static_assert_uimm_bits!(N, 1);
10548 unsafe { transmute::<u64, _>(simd_extract!(a, N as u32)) }
10549}
10550#[doc = "Create a new vector with all lanes set to a value"]
10551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"]
10552#[inline]
10553#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10554#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10555#[cfg_attr(
10556 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10557 assert_instr(dup)
10558)]
10559#[target_feature(enable = "neon,fp16")]
10560#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10561pub fn vdup_n_f16(a: f16) -> float16x4_t {
10562 float16x4_t::splat(a)
10563}
10564#[doc = "Create a new vector with all lanes set to a value"]
10565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"]
10566#[inline]
10567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10568#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10569#[cfg_attr(
10570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10571 assert_instr(dup)
10572)]
10573#[target_feature(enable = "neon,fp16")]
10574#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10575pub fn vdupq_n_f16(a: f16) -> float16x8_t {
10576 float16x8_t::splat(a)
10577}
10578#[doc = "Duplicate vector element to vector or scalar"]
10579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)"]
10580#[inline]
10581#[target_feature(enable = "neon")]
10582#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10583#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10584#[cfg_attr(
10585 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10586 assert_instr(dup)
10587)]
10588#[cfg_attr(
10589 not(target_arch = "arm"),
10590 stable(feature = "neon_intrinsics", since = "1.59.0")
10591)]
10592#[cfg_attr(
10593 target_arch = "arm",
10594 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10595)]
10596pub fn vdup_n_f32(value: f32) -> float32x2_t {
10597 float32x2_t::splat(value)
10598}
10599#[doc = "Duplicate vector element to vector or scalar"]
10600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16)"]
10601#[inline]
10602#[target_feature(enable = "neon")]
10603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10604#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10605#[cfg_attr(
10606 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10607 assert_instr(dup)
10608)]
10609#[cfg_attr(
10610 not(target_arch = "arm"),
10611 stable(feature = "neon_intrinsics", since = "1.59.0")
10612)]
10613#[cfg_attr(
10614 target_arch = "arm",
10615 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10616)]
10617pub fn vdup_n_p16(value: p16) -> poly16x4_t {
10618 poly16x4_t::splat(value)
10619}
10620#[doc = "Duplicate vector element to vector or scalar"]
10621#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8)"]
10622#[inline]
10623#[target_feature(enable = "neon")]
10624#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10625#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10626#[cfg_attr(
10627 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10628 assert_instr(dup)
10629)]
10630#[cfg_attr(
10631 not(target_arch = "arm"),
10632 stable(feature = "neon_intrinsics", since = "1.59.0")
10633)]
10634#[cfg_attr(
10635 target_arch = "arm",
10636 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10637)]
10638pub fn vdup_n_p8(value: p8) -> poly8x8_t {
10639 poly8x8_t::splat(value)
10640}
10641#[doc = "Duplicate vector element to vector or scalar"]
10642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)"]
10643#[inline]
10644#[target_feature(enable = "neon")]
10645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10646#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10647#[cfg_attr(
10648 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10649 assert_instr(dup)
10650)]
10651#[cfg_attr(
10652 not(target_arch = "arm"),
10653 stable(feature = "neon_intrinsics", since = "1.59.0")
10654)]
10655#[cfg_attr(
10656 target_arch = "arm",
10657 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10658)]
10659pub fn vdup_n_s16(value: i16) -> int16x4_t {
10660 int16x4_t::splat(value)
10661}
10662#[doc = "Duplicate vector element to vector or scalar"]
10663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)"]
10664#[inline]
10665#[target_feature(enable = "neon")]
10666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10667#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10668#[cfg_attr(
10669 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10670 assert_instr(dup)
10671)]
10672#[cfg_attr(
10673 not(target_arch = "arm"),
10674 stable(feature = "neon_intrinsics", since = "1.59.0")
10675)]
10676#[cfg_attr(
10677 target_arch = "arm",
10678 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10679)]
10680pub fn vdup_n_s32(value: i32) -> int32x2_t {
10681 int32x2_t::splat(value)
10682}
10683#[doc = "Duplicate vector element to vector or scalar"]
10684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64)"]
10685#[inline]
10686#[target_feature(enable = "neon")]
10687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10688#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10689#[cfg_attr(
10690 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10691 assert_instr(fmov)
10692)]
10693#[cfg_attr(
10694 not(target_arch = "arm"),
10695 stable(feature = "neon_intrinsics", since = "1.59.0")
10696)]
10697#[cfg_attr(
10698 target_arch = "arm",
10699 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10700)]
10701pub fn vdup_n_s64(value: i64) -> int64x1_t {
10702 int64x1_t::splat(value)
10703}
10704#[doc = "Duplicate vector element to vector or scalar"]
10705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)"]
10706#[inline]
10707#[target_feature(enable = "neon")]
10708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10709#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10710#[cfg_attr(
10711 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10712 assert_instr(dup)
10713)]
10714#[cfg_attr(
10715 not(target_arch = "arm"),
10716 stable(feature = "neon_intrinsics", since = "1.59.0")
10717)]
10718#[cfg_attr(
10719 target_arch = "arm",
10720 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10721)]
10722pub fn vdup_n_s8(value: i8) -> int8x8_t {
10723 int8x8_t::splat(value)
10724}
10725#[doc = "Duplicate vector element to vector or scalar"]
10726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)"]
10727#[inline]
10728#[target_feature(enable = "neon")]
10729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10730#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10731#[cfg_attr(
10732 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10733 assert_instr(dup)
10734)]
10735#[cfg_attr(
10736 not(target_arch = "arm"),
10737 stable(feature = "neon_intrinsics", since = "1.59.0")
10738)]
10739#[cfg_attr(
10740 target_arch = "arm",
10741 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10742)]
10743pub fn vdup_n_u16(value: u16) -> uint16x4_t {
10744 uint16x4_t::splat(value)
10745}
10746#[doc = "Duplicate vector element to vector or scalar"]
10747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)"]
10748#[inline]
10749#[target_feature(enable = "neon")]
10750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10751#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10752#[cfg_attr(
10753 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10754 assert_instr(dup)
10755)]
10756#[cfg_attr(
10757 not(target_arch = "arm"),
10758 stable(feature = "neon_intrinsics", since = "1.59.0")
10759)]
10760#[cfg_attr(
10761 target_arch = "arm",
10762 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10763)]
10764pub fn vdup_n_u32(value: u32) -> uint32x2_t {
10765 uint32x2_t::splat(value)
10766}
10767#[doc = "Duplicate vector element to vector or scalar"]
10768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64)"]
10769#[inline]
10770#[target_feature(enable = "neon")]
10771#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10772#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10773#[cfg_attr(
10774 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10775 assert_instr(fmov)
10776)]
10777#[cfg_attr(
10778 not(target_arch = "arm"),
10779 stable(feature = "neon_intrinsics", since = "1.59.0")
10780)]
10781#[cfg_attr(
10782 target_arch = "arm",
10783 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10784)]
10785pub fn vdup_n_u64(value: u64) -> uint64x1_t {
10786 uint64x1_t::splat(value)
10787}
10788#[doc = "Duplicate vector element to vector or scalar"]
10789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)"]
10790#[inline]
10791#[target_feature(enable = "neon")]
10792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10793#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10794#[cfg_attr(
10795 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10796 assert_instr(dup)
10797)]
10798#[cfg_attr(
10799 not(target_arch = "arm"),
10800 stable(feature = "neon_intrinsics", since = "1.59.0")
10801)]
10802#[cfg_attr(
10803 target_arch = "arm",
10804 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10805)]
10806pub fn vdup_n_u8(value: u8) -> uint8x8_t {
10807 uint8x8_t::splat(value)
10808}
10809#[doc = "Duplicate vector element to vector or scalar"]
10810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)"]
10811#[inline]
10812#[target_feature(enable = "neon")]
10813#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10814#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10815#[cfg_attr(
10816 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10817 assert_instr(dup)
10818)]
10819#[cfg_attr(
10820 not(target_arch = "arm"),
10821 stable(feature = "neon_intrinsics", since = "1.59.0")
10822)]
10823#[cfg_attr(
10824 target_arch = "arm",
10825 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10826)]
10827pub fn vdupq_n_f32(value: f32) -> float32x4_t {
10828 float32x4_t::splat(value)
10829}
10830#[doc = "Duplicate vector element to vector or scalar"]
10831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16)"]
10832#[inline]
10833#[target_feature(enable = "neon")]
10834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10835#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10836#[cfg_attr(
10837 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10838 assert_instr(dup)
10839)]
10840#[cfg_attr(
10841 not(target_arch = "arm"),
10842 stable(feature = "neon_intrinsics", since = "1.59.0")
10843)]
10844#[cfg_attr(
10845 target_arch = "arm",
10846 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10847)]
10848pub fn vdupq_n_p16(value: p16) -> poly16x8_t {
10849 poly16x8_t::splat(value)
10850}
10851#[doc = "Duplicate vector element to vector or scalar"]
10852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8)"]
10853#[inline]
10854#[target_feature(enable = "neon")]
10855#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10856#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10857#[cfg_attr(
10858 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10859 assert_instr(dup)
10860)]
10861#[cfg_attr(
10862 not(target_arch = "arm"),
10863 stable(feature = "neon_intrinsics", since = "1.59.0")
10864)]
10865#[cfg_attr(
10866 target_arch = "arm",
10867 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10868)]
10869pub fn vdupq_n_p8(value: p8) -> poly8x16_t {
10870 poly8x16_t::splat(value)
10871}
10872#[doc = "Duplicate vector element to vector or scalar"]
10873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)"]
10874#[inline]
10875#[target_feature(enable = "neon")]
10876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10877#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10878#[cfg_attr(
10879 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10880 assert_instr(dup)
10881)]
10882#[cfg_attr(
10883 not(target_arch = "arm"),
10884 stable(feature = "neon_intrinsics", since = "1.59.0")
10885)]
10886#[cfg_attr(
10887 target_arch = "arm",
10888 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10889)]
10890pub fn vdupq_n_s16(value: i16) -> int16x8_t {
10891 int16x8_t::splat(value)
10892}
10893#[doc = "Duplicate vector element to vector or scalar"]
10894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)"]
10895#[inline]
10896#[target_feature(enable = "neon")]
10897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10898#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10899#[cfg_attr(
10900 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10901 assert_instr(dup)
10902)]
10903#[cfg_attr(
10904 not(target_arch = "arm"),
10905 stable(feature = "neon_intrinsics", since = "1.59.0")
10906)]
10907#[cfg_attr(
10908 target_arch = "arm",
10909 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10910)]
10911pub fn vdupq_n_s32(value: i32) -> int32x4_t {
10912 int32x4_t::splat(value)
10913}
10914#[doc = "Duplicate vector element to vector or scalar"]
10915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)"]
10916#[inline]
10917#[target_feature(enable = "neon")]
10918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10919#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10920#[cfg_attr(
10921 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10922 assert_instr(dup)
10923)]
10924#[cfg_attr(
10925 not(target_arch = "arm"),
10926 stable(feature = "neon_intrinsics", since = "1.59.0")
10927)]
10928#[cfg_attr(
10929 target_arch = "arm",
10930 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10931)]
10932pub fn vdupq_n_s64(value: i64) -> int64x2_t {
10933 int64x2_t::splat(value)
10934}
10935#[doc = "Duplicate vector element to vector or scalar"]
10936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)"]
10937#[inline]
10938#[target_feature(enable = "neon")]
10939#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10940#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10941#[cfg_attr(
10942 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10943 assert_instr(dup)
10944)]
10945#[cfg_attr(
10946 not(target_arch = "arm"),
10947 stable(feature = "neon_intrinsics", since = "1.59.0")
10948)]
10949#[cfg_attr(
10950 target_arch = "arm",
10951 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10952)]
10953pub fn vdupq_n_s8(value: i8) -> int8x16_t {
10954 int8x16_t::splat(value)
10955}
10956#[doc = "Duplicate vector element to vector or scalar"]
10957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)"]
10958#[inline]
10959#[target_feature(enable = "neon")]
10960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10961#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10962#[cfg_attr(
10963 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10964 assert_instr(dup)
10965)]
10966#[cfg_attr(
10967 not(target_arch = "arm"),
10968 stable(feature = "neon_intrinsics", since = "1.59.0")
10969)]
10970#[cfg_attr(
10971 target_arch = "arm",
10972 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10973)]
10974pub fn vdupq_n_u16(value: u16) -> uint16x8_t {
10975 uint16x8_t::splat(value)
10976}
10977#[doc = "Duplicate vector element to vector or scalar"]
10978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)"]
10979#[inline]
10980#[target_feature(enable = "neon")]
10981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10982#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10983#[cfg_attr(
10984 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10985 assert_instr(dup)
10986)]
10987#[cfg_attr(
10988 not(target_arch = "arm"),
10989 stable(feature = "neon_intrinsics", since = "1.59.0")
10990)]
10991#[cfg_attr(
10992 target_arch = "arm",
10993 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10994)]
10995pub fn vdupq_n_u32(value: u32) -> uint32x4_t {
10996 uint32x4_t::splat(value)
10997}
10998#[doc = "Duplicate vector element to vector or scalar"]
10999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64)"]
11000#[inline]
11001#[target_feature(enable = "neon")]
11002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11003#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
11004#[cfg_attr(
11005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11006 assert_instr(dup)
11007)]
11008#[cfg_attr(
11009 not(target_arch = "arm"),
11010 stable(feature = "neon_intrinsics", since = "1.59.0")
11011)]
11012#[cfg_attr(
11013 target_arch = "arm",
11014 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11015)]
11016pub fn vdupq_n_u64(value: u64) -> uint64x2_t {
11017 uint64x2_t::splat(value)
11018}
11019#[doc = "Duplicate vector element to vector or scalar"]
11020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)"]
11021#[inline]
11022#[target_feature(enable = "neon")]
11023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11024#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
11025#[cfg_attr(
11026 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11027 assert_instr(dup)
11028)]
11029#[cfg_attr(
11030 not(target_arch = "arm"),
11031 stable(feature = "neon_intrinsics", since = "1.59.0")
11032)]
11033#[cfg_attr(
11034 target_arch = "arm",
11035 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11036)]
11037pub fn vdupq_n_u8(value: u8) -> uint8x16_t {
11038 uint8x16_t::splat(value)
11039}
11040#[doc = "Duplicate vector element to vector or scalar"]
11041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32_vfp4)"]
11042#[inline]
11043#[target_feature(enable = "neon")]
11044#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
11045#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
11046#[cfg_attr(
11047 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11048 assert_instr(dup)
11049)]
11050#[cfg_attr(
11051 not(target_arch = "arm"),
11052 stable(feature = "neon_intrinsics", since = "1.59.0")
11053)]
11054#[cfg_attr(
11055 target_arch = "arm",
11056 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11057)]
11058fn vdup_n_f32_vfp4(value: f32) -> float32x2_t {
11059 float32x2_t::splat(value)
11060}
11061#[doc = "Duplicate vector element to vector or scalar"]
11062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32_vfp4)"]
11063#[inline]
11064#[target_feature(enable = "neon")]
11065#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
11066#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
11067#[cfg_attr(
11068 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11069 assert_instr(dup)
11070)]
11071#[cfg_attr(
11072 not(target_arch = "arm"),
11073 stable(feature = "neon_intrinsics", since = "1.59.0")
11074)]
11075#[cfg_attr(
11076 target_arch = "arm",
11077 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11078)]
11079fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t {
11080 float32x4_t::splat(value)
11081}
11082#[doc = "Set all vector lanes to the same value"]
11083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"]
11084#[inline]
11085#[target_feature(enable = "neon")]
11086#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11087#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
11088#[cfg_attr(
11089 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11090 assert_instr(dup, N = 0)
11091)]
11092#[rustc_legacy_const_generics(1)]
11093#[cfg_attr(
11094 not(target_arch = "arm"),
11095 stable(feature = "neon_intrinsics", since = "1.59.0")
11096)]
11097#[cfg_attr(
11098 target_arch = "arm",
11099 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11100)]
11101pub fn vdupq_lane_s64<const N: i32>(a: int64x1_t) -> int64x2_t {
11102 static_assert!(N == 0);
11103 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11104}
11105#[doc = "Set all vector lanes to the same value"]
11106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"]
11107#[inline]
11108#[target_feature(enable = "neon")]
11109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11110#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
11111#[cfg_attr(
11112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11113 assert_instr(dup, N = 0)
11114)]
11115#[rustc_legacy_const_generics(1)]
11116#[cfg_attr(
11117 not(target_arch = "arm"),
11118 stable(feature = "neon_intrinsics", since = "1.59.0")
11119)]
11120#[cfg_attr(
11121 target_arch = "arm",
11122 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11123)]
11124pub fn vdupq_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x2_t {
11125 static_assert!(N == 0);
11126 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11127}
11128#[doc = "Set all vector lanes to the same value"]
11129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"]
11130#[inline]
11131#[target_feature(enable = "neon")]
11132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11133#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
11134#[cfg_attr(
11135 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11136 assert_instr(dup, N = 1)
11137)]
11138#[rustc_legacy_const_generics(1)]
11139#[cfg_attr(
11140 not(target_arch = "arm"),
11141 stable(feature = "neon_intrinsics", since = "1.59.0")
11142)]
11143#[cfg_attr(
11144 target_arch = "arm",
11145 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11146)]
11147pub fn vdupq_laneq_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
11148 static_assert_uimm_bits!(N, 1);
11149 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11150}
11151#[doc = "Set all vector lanes to the same value"]
11152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"]
11153#[inline]
11154#[target_feature(enable = "neon")]
11155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11156#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
11157#[cfg_attr(
11158 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11159 assert_instr(dup, N = 1)
11160)]
11161#[rustc_legacy_const_generics(1)]
11162#[cfg_attr(
11163 not(target_arch = "arm"),
11164 stable(feature = "neon_intrinsics", since = "1.59.0")
11165)]
11166#[cfg_attr(
11167 target_arch = "arm",
11168 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11169)]
11170pub fn vdupq_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
11171 static_assert_uimm_bits!(N, 1);
11172 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11173}
11174#[doc = "Vector bitwise exclusive or (vector)"]
11175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"]
11176#[inline]
11177#[target_feature(enable = "neon")]
11178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11180#[cfg_attr(
11181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11182 assert_instr(eor)
11183)]
11184#[cfg_attr(
11185 not(target_arch = "arm"),
11186 stable(feature = "neon_intrinsics", since = "1.59.0")
11187)]
11188#[cfg_attr(
11189 target_arch = "arm",
11190 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11191)]
11192pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
11193 unsafe { simd_xor(a, b) }
11194}
11195#[doc = "Vector bitwise exclusive or (vector)"]
11196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"]
11197#[inline]
11198#[target_feature(enable = "neon")]
11199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11201#[cfg_attr(
11202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11203 assert_instr(eor)
11204)]
11205#[cfg_attr(
11206 not(target_arch = "arm"),
11207 stable(feature = "neon_intrinsics", since = "1.59.0")
11208)]
11209#[cfg_attr(
11210 target_arch = "arm",
11211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11212)]
11213pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
11214 unsafe { simd_xor(a, b) }
11215}
11216#[doc = "Vector bitwise exclusive or (vector)"]
11217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"]
11218#[inline]
11219#[target_feature(enable = "neon")]
11220#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11221#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11222#[cfg_attr(
11223 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11224 assert_instr(eor)
11225)]
11226#[cfg_attr(
11227 not(target_arch = "arm"),
11228 stable(feature = "neon_intrinsics", since = "1.59.0")
11229)]
11230#[cfg_attr(
11231 target_arch = "arm",
11232 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11233)]
11234pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
11235 unsafe { simd_xor(a, b) }
11236}
11237#[doc = "Vector bitwise exclusive or (vector)"]
11238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"]
11239#[inline]
11240#[target_feature(enable = "neon")]
11241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11243#[cfg_attr(
11244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11245 assert_instr(eor)
11246)]
11247#[cfg_attr(
11248 not(target_arch = "arm"),
11249 stable(feature = "neon_intrinsics", since = "1.59.0")
11250)]
11251#[cfg_attr(
11252 target_arch = "arm",
11253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11254)]
11255pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
11256 unsafe { simd_xor(a, b) }
11257}
11258#[doc = "Vector bitwise exclusive or (vector)"]
11259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"]
11260#[inline]
11261#[target_feature(enable = "neon")]
11262#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11263#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11264#[cfg_attr(
11265 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11266 assert_instr(eor)
11267)]
11268#[cfg_attr(
11269 not(target_arch = "arm"),
11270 stable(feature = "neon_intrinsics", since = "1.59.0")
11271)]
11272#[cfg_attr(
11273 target_arch = "arm",
11274 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11275)]
11276pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
11277 unsafe { simd_xor(a, b) }
11278}
11279#[doc = "Vector bitwise exclusive or (vector)"]
11280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"]
11281#[inline]
11282#[target_feature(enable = "neon")]
11283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11285#[cfg_attr(
11286 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11287 assert_instr(eor)
11288)]
11289#[cfg_attr(
11290 not(target_arch = "arm"),
11291 stable(feature = "neon_intrinsics", since = "1.59.0")
11292)]
11293#[cfg_attr(
11294 target_arch = "arm",
11295 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11296)]
11297pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
11298 unsafe { simd_xor(a, b) }
11299}
11300#[doc = "Vector bitwise exclusive or (vector)"]
11301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"]
11302#[inline]
11303#[target_feature(enable = "neon")]
11304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11305#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11306#[cfg_attr(
11307 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11308 assert_instr(eor)
11309)]
11310#[cfg_attr(
11311 not(target_arch = "arm"),
11312 stable(feature = "neon_intrinsics", since = "1.59.0")
11313)]
11314#[cfg_attr(
11315 target_arch = "arm",
11316 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11317)]
11318pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
11319 unsafe { simd_xor(a, b) }
11320}
11321#[doc = "Vector bitwise exclusive or (vector)"]
11322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"]
11323#[inline]
11324#[target_feature(enable = "neon")]
11325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11327#[cfg_attr(
11328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11329 assert_instr(eor)
11330)]
11331#[cfg_attr(
11332 not(target_arch = "arm"),
11333 stable(feature = "neon_intrinsics", since = "1.59.0")
11334)]
11335#[cfg_attr(
11336 target_arch = "arm",
11337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11338)]
11339pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
11340 unsafe { simd_xor(a, b) }
11341}
11342#[doc = "Vector bitwise exclusive or (vector)"]
11343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"]
11344#[inline]
11345#[target_feature(enable = "neon")]
11346#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11347#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11348#[cfg_attr(
11349 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11350 assert_instr(eor)
11351)]
11352#[cfg_attr(
11353 not(target_arch = "arm"),
11354 stable(feature = "neon_intrinsics", since = "1.59.0")
11355)]
11356#[cfg_attr(
11357 target_arch = "arm",
11358 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11359)]
11360pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
11361 unsafe { simd_xor(a, b) }
11362}
11363#[doc = "Vector bitwise exclusive or (vector)"]
11364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"]
11365#[inline]
11366#[target_feature(enable = "neon")]
11367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11369#[cfg_attr(
11370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11371 assert_instr(eor)
11372)]
11373#[cfg_attr(
11374 not(target_arch = "arm"),
11375 stable(feature = "neon_intrinsics", since = "1.59.0")
11376)]
11377#[cfg_attr(
11378 target_arch = "arm",
11379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11380)]
11381pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
11382 unsafe { simd_xor(a, b) }
11383}
11384#[doc = "Vector bitwise exclusive or (vector)"]
11385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"]
11386#[inline]
11387#[target_feature(enable = "neon")]
11388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11390#[cfg_attr(
11391 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11392 assert_instr(eor)
11393)]
11394#[cfg_attr(
11395 not(target_arch = "arm"),
11396 stable(feature = "neon_intrinsics", since = "1.59.0")
11397)]
11398#[cfg_attr(
11399 target_arch = "arm",
11400 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11401)]
11402pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
11403 unsafe { simd_xor(a, b) }
11404}
11405#[doc = "Vector bitwise exclusive or (vector)"]
11406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"]
11407#[inline]
11408#[target_feature(enable = "neon")]
11409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11410#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11411#[cfg_attr(
11412 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11413 assert_instr(eor)
11414)]
11415#[cfg_attr(
11416 not(target_arch = "arm"),
11417 stable(feature = "neon_intrinsics", since = "1.59.0")
11418)]
11419#[cfg_attr(
11420 target_arch = "arm",
11421 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11422)]
11423pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
11424 unsafe { simd_xor(a, b) }
11425}
11426#[doc = "Vector bitwise exclusive or (vector)"]
11427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"]
11428#[inline]
11429#[target_feature(enable = "neon")]
11430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11431#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11432#[cfg_attr(
11433 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11434 assert_instr(eor)
11435)]
11436#[cfg_attr(
11437 not(target_arch = "arm"),
11438 stable(feature = "neon_intrinsics", since = "1.59.0")
11439)]
11440#[cfg_attr(
11441 target_arch = "arm",
11442 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11443)]
11444pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
11445 unsafe { simd_xor(a, b) }
11446}
11447#[doc = "Vector bitwise exclusive or (vector)"]
11448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"]
11449#[inline]
11450#[target_feature(enable = "neon")]
11451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11453#[cfg_attr(
11454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11455 assert_instr(eor)
11456)]
11457#[cfg_attr(
11458 not(target_arch = "arm"),
11459 stable(feature = "neon_intrinsics", since = "1.59.0")
11460)]
11461#[cfg_attr(
11462 target_arch = "arm",
11463 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11464)]
11465pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
11466 unsafe { simd_xor(a, b) }
11467}
11468#[doc = "Vector bitwise exclusive or (vector)"]
11469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"]
11470#[inline]
11471#[target_feature(enable = "neon")]
11472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11474#[cfg_attr(
11475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11476 assert_instr(eor)
11477)]
11478#[cfg_attr(
11479 not(target_arch = "arm"),
11480 stable(feature = "neon_intrinsics", since = "1.59.0")
11481)]
11482#[cfg_attr(
11483 target_arch = "arm",
11484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11485)]
11486pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
11487 unsafe { simd_xor(a, b) }
11488}
11489#[doc = "Vector bitwise exclusive or (vector)"]
11490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"]
11491#[inline]
11492#[target_feature(enable = "neon")]
11493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11494#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11495#[cfg_attr(
11496 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11497 assert_instr(eor)
11498)]
11499#[cfg_attr(
11500 not(target_arch = "arm"),
11501 stable(feature = "neon_intrinsics", since = "1.59.0")
11502)]
11503#[cfg_attr(
11504 target_arch = "arm",
11505 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11506)]
11507pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
11508 unsafe { simd_xor(a, b) }
11509}
11510#[doc = "Extract vector from pair of vectors"]
11511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"]
11512#[inline]
11513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11514#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11515#[cfg_attr(
11516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11517 assert_instr(ext, N = 3)
11518)]
11519#[rustc_legacy_const_generics(2)]
11520#[target_feature(enable = "neon,fp16")]
11521#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
11522pub fn vext_f16<const N: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
11523 static_assert_uimm_bits!(N, 2);
11524 unsafe {
11525 match N & 0b11 {
11526 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11527 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11528 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11529 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11530 _ => unreachable_unchecked(),
11531 }
11532 }
11533}
11534#[doc = "Extract vector from pair of vectors"]
11535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"]
11536#[inline]
11537#[target_feature(enable = "neon")]
11538#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11539#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11540#[cfg_attr(
11541 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11542 assert_instr(ext, N = 1)
11543)]
11544#[rustc_legacy_const_generics(2)]
11545#[cfg_attr(
11546 not(target_arch = "arm"),
11547 stable(feature = "neon_intrinsics", since = "1.59.0")
11548)]
11549#[cfg_attr(
11550 target_arch = "arm",
11551 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11552)]
11553pub fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
11554 static_assert_uimm_bits!(N, 1);
11555 unsafe {
11556 match N & 0b1 {
11557 0 => simd_shuffle!(a, b, [0, 1]),
11558 1 => simd_shuffle!(a, b, [1, 2]),
11559 _ => unreachable_unchecked(),
11560 }
11561 }
11562}
11563#[doc = "Extract vector from pair of vectors"]
11564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"]
11565#[inline]
11566#[target_feature(enable = "neon")]
11567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11568#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11569#[cfg_attr(
11570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11571 assert_instr(ext, N = 1)
11572)]
11573#[rustc_legacy_const_generics(2)]
11574#[cfg_attr(
11575 not(target_arch = "arm"),
11576 stable(feature = "neon_intrinsics", since = "1.59.0")
11577)]
11578#[cfg_attr(
11579 target_arch = "arm",
11580 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11581)]
11582pub fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
11583 static_assert_uimm_bits!(N, 1);
11584 unsafe {
11585 match N & 0b1 {
11586 0 => simd_shuffle!(a, b, [0, 1]),
11587 1 => simd_shuffle!(a, b, [1, 2]),
11588 _ => unreachable_unchecked(),
11589 }
11590 }
11591}
11592#[doc = "Extract vector from pair of vectors"]
11593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"]
11594#[inline]
11595#[target_feature(enable = "neon")]
11596#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11597#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11598#[cfg_attr(
11599 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11600 assert_instr(ext, N = 1)
11601)]
11602#[rustc_legacy_const_generics(2)]
11603#[cfg_attr(
11604 not(target_arch = "arm"),
11605 stable(feature = "neon_intrinsics", since = "1.59.0")
11606)]
11607#[cfg_attr(
11608 target_arch = "arm",
11609 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11610)]
11611pub fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
11612 static_assert_uimm_bits!(N, 1);
11613 unsafe {
11614 match N & 0b1 {
11615 0 => simd_shuffle!(a, b, [0, 1]),
11616 1 => simd_shuffle!(a, b, [1, 2]),
11617 _ => unreachable_unchecked(),
11618 }
11619 }
11620}
11621#[doc = "Extract vector from pair of vectors"]
11622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"]
11623#[doc = "## Safety"]
11624#[doc = " * Neon instrinsic unsafe"]
11625#[inline]
11626#[target_feature(enable = "neon")]
11627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11628#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
11629#[cfg_attr(
11630 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11631 assert_instr(nop, N = 0)
11632)]
11633#[rustc_legacy_const_generics(2)]
11634#[cfg_attr(
11635 not(target_arch = "arm"),
11636 stable(feature = "neon_intrinsics", since = "1.59.0")
11637)]
11638#[cfg_attr(
11639 target_arch = "arm",
11640 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11641)]
11642pub unsafe fn vext_s64<const N: i32>(a: int64x1_t, _b: int64x1_t) -> int64x1_t {
11643 static_assert!(N == 0);
11644 a
11645}
11646#[doc = "Extract vector from pair of vectors"]
11647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"]
11648#[doc = "## Safety"]
11649#[doc = " * Neon instrinsic unsafe"]
11650#[inline]
11651#[target_feature(enable = "neon")]
11652#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11653#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
11654#[cfg_attr(
11655 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11656 assert_instr(nop, N = 0)
11657)]
11658#[rustc_legacy_const_generics(2)]
11659#[cfg_attr(
11660 not(target_arch = "arm"),
11661 stable(feature = "neon_intrinsics", since = "1.59.0")
11662)]
11663#[cfg_attr(
11664 target_arch = "arm",
11665 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11666)]
11667pub unsafe fn vext_u64<const N: i32>(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_t {
11668 static_assert!(N == 0);
11669 a
11670}
11671#[doc = "Extract vector from pair of vectors"]
11672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"]
11673#[inline]
11674#[target_feature(enable = "neon")]
11675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11676#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11677#[cfg_attr(
11678 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11679 assert_instr(ext, N = 7)
11680)]
11681#[rustc_legacy_const_generics(2)]
11682#[cfg_attr(
11683 not(target_arch = "arm"),
11684 stable(feature = "neon_intrinsics", since = "1.59.0")
11685)]
11686#[cfg_attr(
11687 target_arch = "arm",
11688 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11689)]
11690pub fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
11691 static_assert_uimm_bits!(N, 3);
11692 unsafe {
11693 match N & 0b111 {
11694 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11695 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11696 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11697 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11698 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11699 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11700 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11701 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11702 _ => unreachable_unchecked(),
11703 }
11704 }
11705}
11706#[doc = "Extract vector from pair of vectors"]
11707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"]
11708#[inline]
11709#[target_feature(enable = "neon")]
11710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11711#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11712#[cfg_attr(
11713 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11714 assert_instr(ext, N = 7)
11715)]
11716#[rustc_legacy_const_generics(2)]
11717#[cfg_attr(
11718 not(target_arch = "arm"),
11719 stable(feature = "neon_intrinsics", since = "1.59.0")
11720)]
11721#[cfg_attr(
11722 target_arch = "arm",
11723 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11724)]
11725pub fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
11726 static_assert_uimm_bits!(N, 3);
11727 unsafe {
11728 match N & 0b111 {
11729 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11730 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11731 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11732 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11733 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11734 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11735 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11736 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11737 _ => unreachable_unchecked(),
11738 }
11739 }
11740}
11741#[doc = "Extract vector from pair of vectors"]
11742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"]
11743#[inline]
11744#[target_feature(enable = "neon")]
11745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11746#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11747#[cfg_attr(
11748 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11749 assert_instr(ext, N = 7)
11750)]
11751#[rustc_legacy_const_generics(2)]
11752#[cfg_attr(
11753 not(target_arch = "arm"),
11754 stable(feature = "neon_intrinsics", since = "1.59.0")
11755)]
11756#[cfg_attr(
11757 target_arch = "arm",
11758 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11759)]
11760pub fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
11761 static_assert_uimm_bits!(N, 3);
11762 unsafe {
11763 match N & 0b111 {
11764 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11765 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11766 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11767 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11768 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11769 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11770 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11771 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11772 _ => unreachable_unchecked(),
11773 }
11774 }
11775}
11776#[doc = "Extract vector from pair of vectors"]
11777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"]
11778#[inline]
11779#[target_feature(enable = "neon")]
11780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11781#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11782#[cfg_attr(
11783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11784 assert_instr(ext, N = 7)
11785)]
11786#[rustc_legacy_const_generics(2)]
11787#[cfg_attr(
11788 not(target_arch = "arm"),
11789 stable(feature = "neon_intrinsics", since = "1.59.0")
11790)]
11791#[cfg_attr(
11792 target_arch = "arm",
11793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11794)]
11795pub fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
11796 static_assert_uimm_bits!(N, 3);
11797 unsafe {
11798 match N & 0b111 {
11799 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11800 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11801 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11802 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11803 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11804 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11805 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11806 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11807 _ => unreachable_unchecked(),
11808 }
11809 }
11810}
11811#[doc = "Extract vector from pair of vectors"]
11812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"]
11813#[inline]
11814#[target_feature(enable = "neon")]
11815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11816#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11817#[cfg_attr(
11818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11819 assert_instr(ext, N = 7)
11820)]
11821#[rustc_legacy_const_generics(2)]
11822#[cfg_attr(
11823 not(target_arch = "arm"),
11824 stable(feature = "neon_intrinsics", since = "1.59.0")
11825)]
11826#[cfg_attr(
11827 target_arch = "arm",
11828 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11829)]
11830pub fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
11831 static_assert_uimm_bits!(N, 3);
11832 unsafe {
11833 match N & 0b111 {
11834 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11835 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11836 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11837 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11838 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11839 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11840 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11841 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11842 _ => unreachable_unchecked(),
11843 }
11844 }
11845}
11846#[doc = "Extract vector from pair of vectors"]
11847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"]
11848#[inline]
11849#[target_feature(enable = "neon")]
11850#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11851#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11852#[cfg_attr(
11853 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11854 assert_instr(ext, N = 7)
11855)]
11856#[rustc_legacy_const_generics(2)]
11857#[cfg_attr(
11858 not(target_arch = "arm"),
11859 stable(feature = "neon_intrinsics", since = "1.59.0")
11860)]
11861#[cfg_attr(
11862 target_arch = "arm",
11863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11864)]
11865pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
11866 static_assert_uimm_bits!(N, 3);
11867 unsafe {
11868 match N & 0b111 {
11869 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11870 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11871 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11872 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11873 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11874 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11875 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11876 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11877 _ => unreachable_unchecked(),
11878 }
11879 }
11880}
11881#[doc = "Extract vector from pair of vectors"]
11882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"]
11883#[inline]
11884#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11885#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11886#[cfg_attr(
11887 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11888 assert_instr(ext, N = 7)
11889)]
11890#[rustc_legacy_const_generics(2)]
11891#[target_feature(enable = "neon,fp16")]
11892#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
11893pub fn vextq_f16<const N: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
11894 static_assert_uimm_bits!(N, 3);
11895 unsafe {
11896 match N & 0b111 {
11897 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11898 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11899 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11900 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11901 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11902 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11903 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11904 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11905 _ => unreachable_unchecked(),
11906 }
11907 }
11908}
11909#[doc = "Extract vector from pair of vectors"]
11910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"]
11911#[inline]
11912#[target_feature(enable = "neon")]
11913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11914#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11915#[cfg_attr(
11916 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11917 assert_instr(ext, N = 3)
11918)]
11919#[rustc_legacy_const_generics(2)]
11920#[cfg_attr(
11921 not(target_arch = "arm"),
11922 stable(feature = "neon_intrinsics", since = "1.59.0")
11923)]
11924#[cfg_attr(
11925 target_arch = "arm",
11926 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11927)]
11928pub fn vextq_f32<const N: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
11929 static_assert_uimm_bits!(N, 2);
11930 unsafe {
11931 match N & 0b11 {
11932 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11933 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11934 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11935 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11936 _ => unreachable_unchecked(),
11937 }
11938 }
11939}
11940#[doc = "Extract vector from pair of vectors"]
11941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"]
11942#[inline]
11943#[target_feature(enable = "neon")]
11944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11945#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11946#[cfg_attr(
11947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11948 assert_instr(ext, N = 3)
11949)]
11950#[rustc_legacy_const_generics(2)]
11951#[cfg_attr(
11952 not(target_arch = "arm"),
11953 stable(feature = "neon_intrinsics", since = "1.59.0")
11954)]
11955#[cfg_attr(
11956 target_arch = "arm",
11957 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11958)]
11959pub fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
11960 static_assert_uimm_bits!(N, 2);
11961 unsafe {
11962 match N & 0b11 {
11963 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11964 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11965 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11966 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11967 _ => unreachable_unchecked(),
11968 }
11969 }
11970}
11971#[doc = "Extract vector from pair of vectors"]
11972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"]
11973#[inline]
11974#[target_feature(enable = "neon")]
11975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11976#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11977#[cfg_attr(
11978 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11979 assert_instr(ext, N = 3)
11980)]
11981#[rustc_legacy_const_generics(2)]
11982#[cfg_attr(
11983 not(target_arch = "arm"),
11984 stable(feature = "neon_intrinsics", since = "1.59.0")
11985)]
11986#[cfg_attr(
11987 target_arch = "arm",
11988 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11989)]
11990pub fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
11991 static_assert_uimm_bits!(N, 2);
11992 unsafe {
11993 match N & 0b11 {
11994 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11995 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11996 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11997 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11998 _ => unreachable_unchecked(),
11999 }
12000 }
12001}
12002#[doc = "Extract vector from pair of vectors"]
12003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"]
12004#[inline]
12005#[target_feature(enable = "neon")]
12006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12007#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
12008#[cfg_attr(
12009 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12010 assert_instr(ext, N = 3)
12011)]
12012#[rustc_legacy_const_generics(2)]
12013#[cfg_attr(
12014 not(target_arch = "arm"),
12015 stable(feature = "neon_intrinsics", since = "1.59.0")
12016)]
12017#[cfg_attr(
12018 target_arch = "arm",
12019 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12020)]
12021pub fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
12022 static_assert_uimm_bits!(N, 2);
12023 unsafe {
12024 match N & 0b11 {
12025 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
12026 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
12027 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
12028 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
12029 _ => unreachable_unchecked(),
12030 }
12031 }
12032}
12033#[doc = "Extract vector from pair of vectors"]
12034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"]
12035#[inline]
12036#[target_feature(enable = "neon")]
12037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12038#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
12039#[cfg_attr(
12040 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12041 assert_instr(ext, N = 3)
12042)]
12043#[rustc_legacy_const_generics(2)]
12044#[cfg_attr(
12045 not(target_arch = "arm"),
12046 stable(feature = "neon_intrinsics", since = "1.59.0")
12047)]
12048#[cfg_attr(
12049 target_arch = "arm",
12050 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12051)]
12052pub fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
12053 static_assert_uimm_bits!(N, 2);
12054 unsafe {
12055 match N & 0b11 {
12056 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
12057 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
12058 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
12059 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
12060 _ => unreachable_unchecked(),
12061 }
12062 }
12063}
12064#[doc = "Extract vector from pair of vectors"]
12065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"]
12066#[inline]
12067#[target_feature(enable = "neon")]
12068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12069#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
12070#[cfg_attr(
12071 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12072 assert_instr(ext, N = 3)
12073)]
12074#[rustc_legacy_const_generics(2)]
12075#[cfg_attr(
12076 not(target_arch = "arm"),
12077 stable(feature = "neon_intrinsics", since = "1.59.0")
12078)]
12079#[cfg_attr(
12080 target_arch = "arm",
12081 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12082)]
12083pub fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
12084 static_assert_uimm_bits!(N, 2);
12085 unsafe {
12086 match N & 0b11 {
12087 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
12088 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
12089 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
12090 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
12091 _ => unreachable_unchecked(),
12092 }
12093 }
12094}
12095#[doc = "Extract vector from pair of vectors"]
12096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"]
12097#[inline]
12098#[target_feature(enable = "neon")]
12099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12100#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
12101#[cfg_attr(
12102 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12103 assert_instr(ext, N = 1)
12104)]
12105#[rustc_legacy_const_generics(2)]
12106#[cfg_attr(
12107 not(target_arch = "arm"),
12108 stable(feature = "neon_intrinsics", since = "1.59.0")
12109)]
12110#[cfg_attr(
12111 target_arch = "arm",
12112 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12113)]
12114pub fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
12115 static_assert_uimm_bits!(N, 1);
12116 unsafe {
12117 match N & 0b1 {
12118 0 => simd_shuffle!(a, b, [0, 1]),
12119 1 => simd_shuffle!(a, b, [1, 2]),
12120 _ => unreachable_unchecked(),
12121 }
12122 }
12123}
12124#[doc = "Extract vector from pair of vectors"]
12125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"]
12126#[inline]
12127#[target_feature(enable = "neon")]
12128#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12129#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
12130#[cfg_attr(
12131 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12132 assert_instr(ext, N = 1)
12133)]
12134#[rustc_legacy_const_generics(2)]
12135#[cfg_attr(
12136 not(target_arch = "arm"),
12137 stable(feature = "neon_intrinsics", since = "1.59.0")
12138)]
12139#[cfg_attr(
12140 target_arch = "arm",
12141 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12142)]
12143pub fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
12144 static_assert_uimm_bits!(N, 1);
12145 unsafe {
12146 match N & 0b1 {
12147 0 => simd_shuffle!(a, b, [0, 1]),
12148 1 => simd_shuffle!(a, b, [1, 2]),
12149 _ => unreachable_unchecked(),
12150 }
12151 }
12152}
12153#[doc = "Extract vector from pair of vectors"]
12154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"]
12155#[inline]
12156#[target_feature(enable = "neon")]
12157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12158#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12159#[cfg_attr(
12160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12161 assert_instr(ext, N = 15)
12162)]
12163#[rustc_legacy_const_generics(2)]
12164#[cfg_attr(
12165 not(target_arch = "arm"),
12166 stable(feature = "neon_intrinsics", since = "1.59.0")
12167)]
12168#[cfg_attr(
12169 target_arch = "arm",
12170 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12171)]
12172pub fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
12173 static_assert_uimm_bits!(N, 4);
12174 unsafe {
12175 match N & 0b1111 {
12176 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12177 1 => simd_shuffle!(
12178 a,
12179 b,
12180 [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12181 ),
12182 2 => simd_shuffle!(
12183 a,
12184 b,
12185 [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12186 ),
12187 3 => simd_shuffle!(
12188 a,
12189 b,
12190 [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12191 ),
12192 4 => simd_shuffle!(
12193 a,
12194 b,
12195 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12196 ),
12197 5 => simd_shuffle!(
12198 a,
12199 b,
12200 [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12201 ),
12202 6 => simd_shuffle!(
12203 a,
12204 b,
12205 [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12206 ),
12207 7 => simd_shuffle!(
12208 a,
12209 b,
12210 [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12211 ),
12212 8 => simd_shuffle!(
12213 a,
12214 b,
12215 [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12216 ),
12217 9 => simd_shuffle!(
12218 a,
12219 b,
12220 [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12221 ),
12222 10 => simd_shuffle!(
12223 a,
12224 b,
12225 [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12226 ),
12227 11 => simd_shuffle!(
12228 a,
12229 b,
12230 [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12231 ),
12232 12 => simd_shuffle!(
12233 a,
12234 b,
12235 [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12236 ),
12237 13 => simd_shuffle!(
12238 a,
12239 b,
12240 [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12241 ),
12242 14 => simd_shuffle!(
12243 a,
12244 b,
12245 [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12246 ),
12247 15 => simd_shuffle!(
12248 a,
12249 b,
12250 [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12251 ),
12252 _ => unreachable_unchecked(),
12253 }
12254 }
12255}
12256#[doc = "Extract vector from pair of vectors"]
12257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"]
12258#[inline]
12259#[target_feature(enable = "neon")]
12260#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12261#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12262#[cfg_attr(
12263 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12264 assert_instr(ext, N = 15)
12265)]
12266#[rustc_legacy_const_generics(2)]
12267#[cfg_attr(
12268 not(target_arch = "arm"),
12269 stable(feature = "neon_intrinsics", since = "1.59.0")
12270)]
12271#[cfg_attr(
12272 target_arch = "arm",
12273 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12274)]
12275pub fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
12276 static_assert_uimm_bits!(N, 4);
12277 unsafe {
12278 match N & 0b1111 {
12279 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12280 1 => simd_shuffle!(
12281 a,
12282 b,
12283 [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12284 ),
12285 2 => simd_shuffle!(
12286 a,
12287 b,
12288 [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12289 ),
12290 3 => simd_shuffle!(
12291 a,
12292 b,
12293 [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12294 ),
12295 4 => simd_shuffle!(
12296 a,
12297 b,
12298 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12299 ),
12300 5 => simd_shuffle!(
12301 a,
12302 b,
12303 [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12304 ),
12305 6 => simd_shuffle!(
12306 a,
12307 b,
12308 [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12309 ),
12310 7 => simd_shuffle!(
12311 a,
12312 b,
12313 [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12314 ),
12315 8 => simd_shuffle!(
12316 a,
12317 b,
12318 [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12319 ),
12320 9 => simd_shuffle!(
12321 a,
12322 b,
12323 [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12324 ),
12325 10 => simd_shuffle!(
12326 a,
12327 b,
12328 [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12329 ),
12330 11 => simd_shuffle!(
12331 a,
12332 b,
12333 [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12334 ),
12335 12 => simd_shuffle!(
12336 a,
12337 b,
12338 [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12339 ),
12340 13 => simd_shuffle!(
12341 a,
12342 b,
12343 [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12344 ),
12345 14 => simd_shuffle!(
12346 a,
12347 b,
12348 [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12349 ),
12350 15 => simd_shuffle!(
12351 a,
12352 b,
12353 [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12354 ),
12355 _ => unreachable_unchecked(),
12356 }
12357 }
12358}
12359#[doc = "Extract vector from pair of vectors"]
12360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"]
12361#[inline]
12362#[target_feature(enable = "neon")]
12363#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12364#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12365#[cfg_attr(
12366 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12367 assert_instr(ext, N = 15)
12368)]
12369#[rustc_legacy_const_generics(2)]
12370#[cfg_attr(
12371 not(target_arch = "arm"),
12372 stable(feature = "neon_intrinsics", since = "1.59.0")
12373)]
12374#[cfg_attr(
12375 target_arch = "arm",
12376 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12377)]
12378pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
12379 static_assert_uimm_bits!(N, 4);
12380 unsafe {
12381 match N & 0b1111 {
12382 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12383 1 => simd_shuffle!(
12384 a,
12385 b,
12386 [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12387 ),
12388 2 => simd_shuffle!(
12389 a,
12390 b,
12391 [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12392 ),
12393 3 => simd_shuffle!(
12394 a,
12395 b,
12396 [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12397 ),
12398 4 => simd_shuffle!(
12399 a,
12400 b,
12401 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12402 ),
12403 5 => simd_shuffle!(
12404 a,
12405 b,
12406 [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12407 ),
12408 6 => simd_shuffle!(
12409 a,
12410 b,
12411 [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12412 ),
12413 7 => simd_shuffle!(
12414 a,
12415 b,
12416 [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12417 ),
12418 8 => simd_shuffle!(
12419 a,
12420 b,
12421 [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12422 ),
12423 9 => simd_shuffle!(
12424 a,
12425 b,
12426 [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12427 ),
12428 10 => simd_shuffle!(
12429 a,
12430 b,
12431 [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12432 ),
12433 11 => simd_shuffle!(
12434 a,
12435 b,
12436 [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12437 ),
12438 12 => simd_shuffle!(
12439 a,
12440 b,
12441 [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12442 ),
12443 13 => simd_shuffle!(
12444 a,
12445 b,
12446 [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12447 ),
12448 14 => simd_shuffle!(
12449 a,
12450 b,
12451 [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12452 ),
12453 15 => simd_shuffle!(
12454 a,
12455 b,
12456 [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12457 ),
12458 _ => unreachable_unchecked(),
12459 }
12460 }
12461}
12462#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
12463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"]
12464#[inline]
12465#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12467#[cfg_attr(
12468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12469 assert_instr(fmla)
12470)]
12471#[target_feature(enable = "neon,fp16")]
12472#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12473pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
12474 unsafe extern "unadjusted" {
12475 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v4f16")]
12476 #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v4f16")]
12477 fn _vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t;
12478 }
12479 unsafe { _vfma_f16(b, c, a) }
12480}
12481#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
12482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"]
12483#[inline]
12484#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12486#[cfg_attr(
12487 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12488 assert_instr(fmla)
12489)]
12490#[target_feature(enable = "neon,fp16")]
12491#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12492pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
12493 unsafe extern "unadjusted" {
12494 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v8f16")]
12495 #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v8f16")]
12496 fn _vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t;
12497 }
12498 unsafe { _vfmaq_f16(b, c, a) }
12499}
12500#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"]
12502#[inline]
12503#[target_feature(enable = "neon")]
12504#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12505#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12506#[cfg_attr(
12507 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12508 assert_instr(fmla)
12509)]
12510#[cfg_attr(
12511 not(target_arch = "arm"),
12512 stable(feature = "neon_intrinsics", since = "1.59.0")
12513)]
12514#[cfg_attr(
12515 target_arch = "arm",
12516 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12517)]
12518pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
12519 unsafe extern "unadjusted" {
12520 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v2f32")]
12521 #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v2f32")]
12522 fn _vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t;
12523 }
12524 unsafe { _vfma_f32(b, c, a) }
12525}
12526#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"]
12528#[inline]
12529#[target_feature(enable = "neon")]
12530#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12531#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12532#[cfg_attr(
12533 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12534 assert_instr(fmla)
12535)]
12536#[cfg_attr(
12537 not(target_arch = "arm"),
12538 stable(feature = "neon_intrinsics", since = "1.59.0")
12539)]
12540#[cfg_attr(
12541 target_arch = "arm",
12542 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12543)]
12544pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
12545 unsafe extern "unadjusted" {
12546 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v4f32")]
12547 #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v4f32")]
12548 fn _vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t;
12549 }
12550 unsafe { _vfmaq_f32(b, c, a) }
12551}
12552#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"]
12554#[inline]
12555#[target_feature(enable = "neon")]
12556#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12558#[cfg_attr(
12559 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12560 assert_instr(fmla)
12561)]
12562#[cfg_attr(
12563 not(target_arch = "arm"),
12564 stable(feature = "neon_intrinsics", since = "1.59.0")
12565)]
12566#[cfg_attr(
12567 target_arch = "arm",
12568 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12569)]
12570pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
12571 vfma_f32(a, b, vdup_n_f32_vfp4(c))
12572}
12573#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"]
12575#[inline]
12576#[target_feature(enable = "neon")]
12577#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12579#[cfg_attr(
12580 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12581 assert_instr(fmla)
12582)]
12583#[cfg_attr(
12584 not(target_arch = "arm"),
12585 stable(feature = "neon_intrinsics", since = "1.59.0")
12586)]
12587#[cfg_attr(
12588 target_arch = "arm",
12589 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12590)]
12591pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
12592 vfmaq_f32(a, b, vdupq_n_f32_vfp4(c))
12593}
12594#[doc = "Floating-point fused multiply-subtract from accumulator"]
12595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"]
12596#[inline]
12597#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
12598#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12599#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
12600#[cfg_attr(
12601 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12602 assert_instr(fmls)
12603)]
12604#[target_feature(enable = "neon,fp16")]
12605#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12606pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
12607 unsafe {
12608 let b: float16x4_t = simd_neg(b);
12609 vfma_f16(a, b, c)
12610 }
12611}
12612#[doc = "Floating-point fused multiply-subtract from accumulator"]
12613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"]
12614#[inline]
12615#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
12616#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
12618#[cfg_attr(
12619 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12620 assert_instr(fmls)
12621)]
12622#[target_feature(enable = "neon,fp16")]
12623#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12624pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
12625 unsafe {
12626 let b: float16x8_t = simd_neg(b);
12627 vfmaq_f16(a, b, c)
12628 }
12629}
12630#[doc = "Floating-point fused multiply-subtract from accumulator"]
12631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"]
12632#[inline]
12633#[target_feature(enable = "neon")]
12634#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12636#[cfg_attr(
12637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12638 assert_instr(fmls)
12639)]
12640#[cfg_attr(
12641 not(target_arch = "arm"),
12642 stable(feature = "neon_intrinsics", since = "1.59.0")
12643)]
12644#[cfg_attr(
12645 target_arch = "arm",
12646 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12647)]
12648pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
12649 unsafe {
12650 let b: float32x2_t = simd_neg(b);
12651 vfma_f32(a, b, c)
12652 }
12653}
12654#[doc = "Floating-point fused multiply-subtract from accumulator"]
12655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"]
12656#[inline]
12657#[target_feature(enable = "neon")]
12658#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12659#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12660#[cfg_attr(
12661 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12662 assert_instr(fmls)
12663)]
12664#[cfg_attr(
12665 not(target_arch = "arm"),
12666 stable(feature = "neon_intrinsics", since = "1.59.0")
12667)]
12668#[cfg_attr(
12669 target_arch = "arm",
12670 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12671)]
12672pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
12673 unsafe {
12674 let b: float32x4_t = simd_neg(b);
12675 vfmaq_f32(a, b, c)
12676 }
12677}
12678#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
12679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"]
12680#[inline]
12681#[target_feature(enable = "neon")]
12682#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12683#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12684#[cfg_attr(
12685 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12686 assert_instr(fmls)
12687)]
12688#[cfg_attr(
12689 not(target_arch = "arm"),
12690 stable(feature = "neon_intrinsics", since = "1.59.0")
12691)]
12692#[cfg_attr(
12693 target_arch = "arm",
12694 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12695)]
12696pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
12697 vfms_f32(a, b, vdup_n_f32_vfp4(c))
12698}
12699#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
12700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"]
12701#[inline]
12702#[target_feature(enable = "neon")]
12703#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12704#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12705#[cfg_attr(
12706 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12707 assert_instr(fmls)
12708)]
12709#[cfg_attr(
12710 not(target_arch = "arm"),
12711 stable(feature = "neon_intrinsics", since = "1.59.0")
12712)]
12713#[cfg_attr(
12714 target_arch = "arm",
12715 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12716)]
12717pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
12718 vfmsq_f32(a, b, vdupq_n_f32_vfp4(c))
12719}
12720#[doc = "Duplicate vector element to vector"]
12721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"]
12722#[inline]
12723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12724#[target_feature(enable = "neon,fp16")]
12725#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12726#[cfg_attr(test, assert_instr(nop))]
12727pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
12728 unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12729}
12730#[doc = "Duplicate vector element to vector"]
12731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"]
12732#[inline]
12733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12734#[target_feature(enable = "neon,fp16")]
12735#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12736#[cfg_attr(test, assert_instr(nop))]
12737pub fn vget_low_f16(a: float16x8_t) -> float16x4_t {
12738 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
12739}
12740#[doc = "Duplicate vector element to vector or scalar"]
12741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"]
12742#[inline]
12743#[target_feature(enable = "neon")]
12744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12745#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12746#[cfg_attr(
12747 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12748 assert_instr(ext)
12749)]
12750#[cfg_attr(
12751 not(target_arch = "arm"),
12752 stable(feature = "neon_intrinsics", since = "1.59.0")
12753)]
12754#[cfg_attr(
12755 target_arch = "arm",
12756 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12757)]
12758pub fn vget_high_f32(a: float32x4_t) -> float32x2_t {
12759 unsafe { simd_shuffle!(a, a, [2, 3]) }
12760}
12761#[doc = "Duplicate vector element to vector or scalar"]
12762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"]
12763#[inline]
12764#[target_feature(enable = "neon")]
12765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12766#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12767#[cfg_attr(
12768 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12769 assert_instr(ext)
12770)]
12771#[cfg_attr(
12772 not(target_arch = "arm"),
12773 stable(feature = "neon_intrinsics", since = "1.59.0")
12774)]
12775#[cfg_attr(
12776 target_arch = "arm",
12777 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12778)]
12779pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t {
12780 unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12781}
12782#[doc = "Duplicate vector element to vector or scalar"]
12783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"]
12784#[inline]
12785#[target_feature(enable = "neon")]
12786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12787#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12788#[cfg_attr(
12789 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12790 assert_instr(ext)
12791)]
12792#[cfg_attr(
12793 not(target_arch = "arm"),
12794 stable(feature = "neon_intrinsics", since = "1.59.0")
12795)]
12796#[cfg_attr(
12797 target_arch = "arm",
12798 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12799)]
12800pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t {
12801 unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12802}
12803#[doc = "Duplicate vector element to vector or scalar"]
12804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"]
12805#[inline]
12806#[target_feature(enable = "neon")]
12807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12808#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12809#[cfg_attr(
12810 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12811 assert_instr(ext)
12812)]
12813#[cfg_attr(
12814 not(target_arch = "arm"),
12815 stable(feature = "neon_intrinsics", since = "1.59.0")
12816)]
12817#[cfg_attr(
12818 target_arch = "arm",
12819 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12820)]
12821pub fn vget_high_s16(a: int16x8_t) -> int16x4_t {
12822 unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12823}
12824#[doc = "Duplicate vector element to vector or scalar"]
12825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"]
12826#[inline]
12827#[target_feature(enable = "neon")]
12828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12829#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12830#[cfg_attr(
12831 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12832 assert_instr(ext)
12833)]
12834#[cfg_attr(
12835 not(target_arch = "arm"),
12836 stable(feature = "neon_intrinsics", since = "1.59.0")
12837)]
12838#[cfg_attr(
12839 target_arch = "arm",
12840 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12841)]
12842pub fn vget_high_s32(a: int32x4_t) -> int32x2_t {
12843 unsafe { simd_shuffle!(a, a, [2, 3]) }
12844}
12845#[doc = "Duplicate vector element to vector or scalar"]
12846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"]
12847#[inline]
12848#[target_feature(enable = "neon")]
12849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12850#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12851#[cfg_attr(
12852 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12853 assert_instr(ext)
12854)]
12855#[cfg_attr(
12856 not(target_arch = "arm"),
12857 stable(feature = "neon_intrinsics", since = "1.59.0")
12858)]
12859#[cfg_attr(
12860 target_arch = "arm",
12861 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12862)]
12863pub fn vget_high_s8(a: int8x16_t) -> int8x8_t {
12864 unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12865}
12866#[doc = "Duplicate vector element to vector or scalar"]
12867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"]
12868#[inline]
12869#[target_feature(enable = "neon")]
12870#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12871#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12872#[cfg_attr(
12873 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12874 assert_instr(ext)
12875)]
12876#[cfg_attr(
12877 not(target_arch = "arm"),
12878 stable(feature = "neon_intrinsics", since = "1.59.0")
12879)]
12880#[cfg_attr(
12881 target_arch = "arm",
12882 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12883)]
12884pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t {
12885 unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12886}
12887#[doc = "Duplicate vector element to vector or scalar"]
12888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"]
12889#[inline]
12890#[target_feature(enable = "neon")]
12891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12892#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12893#[cfg_attr(
12894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12895 assert_instr(ext)
12896)]
12897#[cfg_attr(
12898 not(target_arch = "arm"),
12899 stable(feature = "neon_intrinsics", since = "1.59.0")
12900)]
12901#[cfg_attr(
12902 target_arch = "arm",
12903 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12904)]
12905pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t {
12906 unsafe { simd_shuffle!(a, a, [2, 3]) }
12907}
12908#[doc = "Duplicate vector element to vector or scalar"]
12909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"]
12910#[inline]
12911#[target_feature(enable = "neon")]
12912#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12913#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12914#[cfg_attr(
12915 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12916 assert_instr(ext)
12917)]
12918#[cfg_attr(
12919 not(target_arch = "arm"),
12920 stable(feature = "neon_intrinsics", since = "1.59.0")
12921)]
12922#[cfg_attr(
12923 target_arch = "arm",
12924 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12925)]
12926pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t {
12927 unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12928}
12929#[doc = "Duplicate vector element to vector or scalar"]
12930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"]
12931#[inline]
12932#[target_feature(enable = "neon")]
12933#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12934#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12935#[cfg_attr(
12936 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12937 assert_instr(ext)
12938)]
12939#[cfg_attr(
12940 not(target_arch = "arm"),
12941 stable(feature = "neon_intrinsics", since = "1.59.0")
12942)]
12943#[cfg_attr(
12944 target_arch = "arm",
12945 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12946)]
12947pub fn vget_high_s64(a: int64x2_t) -> int64x1_t {
12948 unsafe { int64x1_t([simd_extract!(a, 1)]) }
12949}
12950#[doc = "Duplicate vector element to vector or scalar"]
12951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"]
12952#[inline]
12953#[target_feature(enable = "neon")]
12954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12955#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12956#[cfg_attr(
12957 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12958 assert_instr(ext)
12959)]
12960#[cfg_attr(
12961 not(target_arch = "arm"),
12962 stable(feature = "neon_intrinsics", since = "1.59.0")
12963)]
12964#[cfg_attr(
12965 target_arch = "arm",
12966 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12967)]
12968pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t {
12969 unsafe { uint64x1_t([simd_extract!(a, 1)]) }
12970}
12971#[doc = "Duplicate vector element to scalar"]
12972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"]
12973#[inline]
12974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12975#[target_feature(enable = "neon,fp16")]
12976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
12977#[cfg_attr(
12978 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12979 assert_instr(nop, LANE = 0)
12980)]
12981#[rustc_legacy_const_generics(1)]
12982#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12983pub fn vget_lane_f16<const LANE: i32>(a: float16x4_t) -> f16 {
12984 static_assert_uimm_bits!(LANE, 2);
12985 unsafe { simd_extract!(a, LANE as u32) }
12986}
12987#[doc = "Duplicate vector element to scalar"]
12988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"]
12989#[inline]
12990#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12991#[target_feature(enable = "neon,fp16")]
12992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
12993#[cfg_attr(
12994 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12995 assert_instr(nop, LANE = 0)
12996)]
12997#[rustc_legacy_const_generics(1)]
12998#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12999pub fn vgetq_lane_f16<const LANE: i32>(a: float16x8_t) -> f16 {
13000 static_assert_uimm_bits!(LANE, 3);
13001 unsafe { simd_extract!(a, LANE as u32) }
13002}
13003#[doc = "Move vector element to general-purpose register"]
13004#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"]
13005#[inline]
13006#[target_feature(enable = "neon")]
13007#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13008#[rustc_legacy_const_generics(1)]
13009#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13010#[cfg_attr(
13011 not(target_arch = "arm"),
13012 stable(feature = "neon_intrinsics", since = "1.59.0")
13013)]
13014#[cfg_attr(
13015 target_arch = "arm",
13016 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13017)]
13018pub fn vget_lane_f32<const IMM5: i32>(v: float32x2_t) -> f32 {
13019 static_assert_uimm_bits!(IMM5, 1);
13020 unsafe { simd_extract!(v, IMM5 as u32) }
13021}
13022#[doc = "Move vector element to general-purpose register"]
13023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"]
13024#[inline]
13025#[target_feature(enable = "neon")]
13026#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13027#[rustc_legacy_const_generics(1)]
13028#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13029#[cfg_attr(
13030 not(target_arch = "arm"),
13031 stable(feature = "neon_intrinsics", since = "1.59.0")
13032)]
13033#[cfg_attr(
13034 target_arch = "arm",
13035 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13036)]
13037pub fn vget_lane_p16<const IMM5: i32>(v: poly16x4_t) -> p16 {
13038 static_assert_uimm_bits!(IMM5, 2);
13039 unsafe { simd_extract!(v, IMM5 as u32) }
13040}
13041#[doc = "Move vector element to general-purpose register"]
13042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"]
13043#[inline]
13044#[target_feature(enable = "neon")]
13045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13046#[rustc_legacy_const_generics(1)]
13047#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13048#[cfg_attr(
13049 not(target_arch = "arm"),
13050 stable(feature = "neon_intrinsics", since = "1.59.0")
13051)]
13052#[cfg_attr(
13053 target_arch = "arm",
13054 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13055)]
13056pub fn vget_lane_p8<const IMM5: i32>(v: poly8x8_t) -> p8 {
13057 static_assert_uimm_bits!(IMM5, 3);
13058 unsafe { simd_extract!(v, IMM5 as u32) }
13059}
13060#[doc = "Move vector element to general-purpose register"]
13061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"]
13062#[inline]
13063#[target_feature(enable = "neon")]
13064#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13065#[rustc_legacy_const_generics(1)]
13066#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13067#[cfg_attr(
13068 not(target_arch = "arm"),
13069 stable(feature = "neon_intrinsics", since = "1.59.0")
13070)]
13071#[cfg_attr(
13072 target_arch = "arm",
13073 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13074)]
13075pub fn vget_lane_s16<const IMM5: i32>(v: int16x4_t) -> i16 {
13076 static_assert_uimm_bits!(IMM5, 2);
13077 unsafe { simd_extract!(v, IMM5 as u32) }
13078}
13079#[doc = "Move vector element to general-purpose register"]
13080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"]
13081#[inline]
13082#[target_feature(enable = "neon")]
13083#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13084#[rustc_legacy_const_generics(1)]
13085#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13086#[cfg_attr(
13087 not(target_arch = "arm"),
13088 stable(feature = "neon_intrinsics", since = "1.59.0")
13089)]
13090#[cfg_attr(
13091 target_arch = "arm",
13092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13093)]
13094pub fn vget_lane_s32<const IMM5: i32>(v: int32x2_t) -> i32 {
13095 static_assert_uimm_bits!(IMM5, 1);
13096 unsafe { simd_extract!(v, IMM5 as u32) }
13097}
13098#[doc = "Move vector element to general-purpose register"]
13099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"]
13100#[inline]
13101#[target_feature(enable = "neon")]
13102#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13103#[rustc_legacy_const_generics(1)]
13104#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13105#[cfg_attr(
13106 not(target_arch = "arm"),
13107 stable(feature = "neon_intrinsics", since = "1.59.0")
13108)]
13109#[cfg_attr(
13110 target_arch = "arm",
13111 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13112)]
13113pub fn vget_lane_s8<const IMM5: i32>(v: int8x8_t) -> i8 {
13114 static_assert_uimm_bits!(IMM5, 3);
13115 unsafe { simd_extract!(v, IMM5 as u32) }
13116}
13117#[doc = "Move vector element to general-purpose register"]
13118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"]
13119#[inline]
13120#[target_feature(enable = "neon")]
13121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13122#[rustc_legacy_const_generics(1)]
13123#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13124#[cfg_attr(
13125 not(target_arch = "arm"),
13126 stable(feature = "neon_intrinsics", since = "1.59.0")
13127)]
13128#[cfg_attr(
13129 target_arch = "arm",
13130 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13131)]
13132pub fn vget_lane_u16<const IMM5: i32>(v: uint16x4_t) -> u16 {
13133 static_assert_uimm_bits!(IMM5, 2);
13134 unsafe { simd_extract!(v, IMM5 as u32) }
13135}
13136#[doc = "Move vector element to general-purpose register"]
13137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"]
13138#[inline]
13139#[target_feature(enable = "neon")]
13140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13141#[rustc_legacy_const_generics(1)]
13142#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13143#[cfg_attr(
13144 not(target_arch = "arm"),
13145 stable(feature = "neon_intrinsics", since = "1.59.0")
13146)]
13147#[cfg_attr(
13148 target_arch = "arm",
13149 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13150)]
13151pub fn vget_lane_u32<const IMM5: i32>(v: uint32x2_t) -> u32 {
13152 static_assert_uimm_bits!(IMM5, 1);
13153 unsafe { simd_extract!(v, IMM5 as u32) }
13154}
13155#[doc = "Move vector element to general-purpose register"]
13156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"]
13157#[inline]
13158#[target_feature(enable = "neon")]
13159#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13160#[rustc_legacy_const_generics(1)]
13161#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13162#[cfg_attr(
13163 not(target_arch = "arm"),
13164 stable(feature = "neon_intrinsics", since = "1.59.0")
13165)]
13166#[cfg_attr(
13167 target_arch = "arm",
13168 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13169)]
13170pub fn vget_lane_u8<const IMM5: i32>(v: uint8x8_t) -> u8 {
13171 static_assert_uimm_bits!(IMM5, 3);
13172 unsafe { simd_extract!(v, IMM5 as u32) }
13173}
13174#[doc = "Move vector element to general-purpose register"]
13175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"]
13176#[inline]
13177#[target_feature(enable = "neon")]
13178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13179#[rustc_legacy_const_generics(1)]
13180#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13181#[cfg_attr(
13182 not(target_arch = "arm"),
13183 stable(feature = "neon_intrinsics", since = "1.59.0")
13184)]
13185#[cfg_attr(
13186 target_arch = "arm",
13187 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13188)]
13189pub fn vgetq_lane_f32<const IMM5: i32>(v: float32x4_t) -> f32 {
13190 static_assert_uimm_bits!(IMM5, 2);
13191 unsafe { simd_extract!(v, IMM5 as u32) }
13192}
13193#[doc = "Move vector element to general-purpose register"]
13194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"]
13195#[inline]
13196#[target_feature(enable = "neon")]
13197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13198#[rustc_legacy_const_generics(1)]
13199#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13200#[cfg_attr(
13201 not(target_arch = "arm"),
13202 stable(feature = "neon_intrinsics", since = "1.59.0")
13203)]
13204#[cfg_attr(
13205 target_arch = "arm",
13206 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13207)]
13208pub fn vgetq_lane_p16<const IMM5: i32>(v: poly16x8_t) -> p16 {
13209 static_assert_uimm_bits!(IMM5, 3);
13210 unsafe { simd_extract!(v, IMM5 as u32) }
13211}
13212#[doc = "Move vector element to general-purpose register"]
13213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"]
13214#[inline]
13215#[target_feature(enable = "neon")]
13216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13217#[rustc_legacy_const_generics(1)]
13218#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13219#[cfg_attr(
13220 not(target_arch = "arm"),
13221 stable(feature = "neon_intrinsics", since = "1.59.0")
13222)]
13223#[cfg_attr(
13224 target_arch = "arm",
13225 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13226)]
13227pub fn vgetq_lane_p64<const IMM5: i32>(v: poly64x2_t) -> p64 {
13228 static_assert_uimm_bits!(IMM5, 1);
13229 unsafe { simd_extract!(v, IMM5 as u32) }
13230}
13231#[doc = "Move vector element to general-purpose register"]
13232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"]
13233#[inline]
13234#[target_feature(enable = "neon")]
13235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13236#[rustc_legacy_const_generics(1)]
13237#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13238#[cfg_attr(
13239 not(target_arch = "arm"),
13240 stable(feature = "neon_intrinsics", since = "1.59.0")
13241)]
13242#[cfg_attr(
13243 target_arch = "arm",
13244 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13245)]
13246pub fn vgetq_lane_p8<const IMM5: i32>(v: poly8x16_t) -> p8 {
13247 static_assert_uimm_bits!(IMM5, 4);
13248 unsafe { simd_extract!(v, IMM5 as u32) }
13249}
13250#[doc = "Move vector element to general-purpose register"]
13251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"]
13252#[inline]
13253#[target_feature(enable = "neon")]
13254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13255#[rustc_legacy_const_generics(1)]
13256#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13257#[cfg_attr(
13258 not(target_arch = "arm"),
13259 stable(feature = "neon_intrinsics", since = "1.59.0")
13260)]
13261#[cfg_attr(
13262 target_arch = "arm",
13263 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13264)]
13265pub fn vgetq_lane_s16<const IMM5: i32>(v: int16x8_t) -> i16 {
13266 static_assert_uimm_bits!(IMM5, 3);
13267 unsafe { simd_extract!(v, IMM5 as u32) }
13268}
13269#[doc = "Move vector element to general-purpose register"]
13270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"]
13271#[inline]
13272#[target_feature(enable = "neon")]
13273#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13274#[rustc_legacy_const_generics(1)]
13275#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13276#[cfg_attr(
13277 not(target_arch = "arm"),
13278 stable(feature = "neon_intrinsics", since = "1.59.0")
13279)]
13280#[cfg_attr(
13281 target_arch = "arm",
13282 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13283)]
13284pub fn vgetq_lane_s32<const IMM5: i32>(v: int32x4_t) -> i32 {
13285 static_assert_uimm_bits!(IMM5, 2);
13286 unsafe { simd_extract!(v, IMM5 as u32) }
13287}
13288#[doc = "Move vector element to general-purpose register"]
13289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"]
13290#[inline]
13291#[target_feature(enable = "neon")]
13292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13293#[rustc_legacy_const_generics(1)]
13294#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13295#[cfg_attr(
13296 not(target_arch = "arm"),
13297 stable(feature = "neon_intrinsics", since = "1.59.0")
13298)]
13299#[cfg_attr(
13300 target_arch = "arm",
13301 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13302)]
13303pub fn vgetq_lane_s64<const IMM5: i32>(v: int64x2_t) -> i64 {
13304 static_assert_uimm_bits!(IMM5, 1);
13305 unsafe { simd_extract!(v, IMM5 as u32) }
13306}
13307#[doc = "Move vector element to general-purpose register"]
13308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"]
13309#[inline]
13310#[target_feature(enable = "neon")]
13311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13312#[rustc_legacy_const_generics(1)]
13313#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13314#[cfg_attr(
13315 not(target_arch = "arm"),
13316 stable(feature = "neon_intrinsics", since = "1.59.0")
13317)]
13318#[cfg_attr(
13319 target_arch = "arm",
13320 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13321)]
13322pub fn vgetq_lane_s8<const IMM5: i32>(v: int8x16_t) -> i8 {
13323 static_assert_uimm_bits!(IMM5, 4);
13324 unsafe { simd_extract!(v, IMM5 as u32) }
13325}
13326#[doc = "Move vector element to general-purpose register"]
13327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"]
13328#[inline]
13329#[target_feature(enable = "neon")]
13330#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13331#[rustc_legacy_const_generics(1)]
13332#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13333#[cfg_attr(
13334 not(target_arch = "arm"),
13335 stable(feature = "neon_intrinsics", since = "1.59.0")
13336)]
13337#[cfg_attr(
13338 target_arch = "arm",
13339 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13340)]
13341pub fn vgetq_lane_u16<const IMM5: i32>(v: uint16x8_t) -> u16 {
13342 static_assert_uimm_bits!(IMM5, 3);
13343 unsafe { simd_extract!(v, IMM5 as u32) }
13344}
13345#[doc = "Move vector element to general-purpose register"]
13346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"]
13347#[inline]
13348#[target_feature(enable = "neon")]
13349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13350#[rustc_legacy_const_generics(1)]
13351#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13352#[cfg_attr(
13353 not(target_arch = "arm"),
13354 stable(feature = "neon_intrinsics", since = "1.59.0")
13355)]
13356#[cfg_attr(
13357 target_arch = "arm",
13358 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13359)]
13360pub fn vgetq_lane_u32<const IMM5: i32>(v: uint32x4_t) -> u32 {
13361 static_assert_uimm_bits!(IMM5, 2);
13362 unsafe { simd_extract!(v, IMM5 as u32) }
13363}
13364#[doc = "Move vector element to general-purpose register"]
13365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"]
13366#[inline]
13367#[target_feature(enable = "neon")]
13368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13369#[rustc_legacy_const_generics(1)]
13370#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13371#[cfg_attr(
13372 not(target_arch = "arm"),
13373 stable(feature = "neon_intrinsics", since = "1.59.0")
13374)]
13375#[cfg_attr(
13376 target_arch = "arm",
13377 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13378)]
13379pub fn vgetq_lane_u64<const IMM5: i32>(v: uint64x2_t) -> u64 {
13380 static_assert_uimm_bits!(IMM5, 2);
13381 unsafe { simd_extract!(v, IMM5 as u32) }
13382}
13383#[doc = "Move vector element to general-purpose register"]
13384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"]
13385#[inline]
13386#[target_feature(enable = "neon")]
13387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13388#[rustc_legacy_const_generics(1)]
13389#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13390#[cfg_attr(
13391 not(target_arch = "arm"),
13392 stable(feature = "neon_intrinsics", since = "1.59.0")
13393)]
13394#[cfg_attr(
13395 target_arch = "arm",
13396 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13397)]
13398pub fn vgetq_lane_u8<const IMM5: i32>(v: uint8x16_t) -> u8 {
13399 static_assert_uimm_bits!(IMM5, 4);
13400 unsafe { simd_extract!(v, IMM5 as u32) }
13401}
13402#[doc = "Move vector element to general-purpose register"]
13403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)"]
13404#[inline]
13405#[target_feature(enable = "neon")]
13406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13407#[rustc_legacy_const_generics(1)]
13408#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13409#[cfg_attr(
13410 not(target_arch = "arm"),
13411 stable(feature = "neon_intrinsics", since = "1.59.0")
13412)]
13413#[cfg_attr(
13414 target_arch = "arm",
13415 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13416)]
13417pub fn vget_lane_p64<const IMM5: i32>(v: poly64x1_t) -> p64 {
13418 static_assert!(IMM5 == 0);
13419 unsafe { simd_extract!(v, IMM5 as u32) }
13420}
13421#[doc = "Move vector element to general-purpose register"]
13422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64)"]
13423#[inline]
13424#[target_feature(enable = "neon")]
13425#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13426#[rustc_legacy_const_generics(1)]
13427#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13428#[cfg_attr(
13429 not(target_arch = "arm"),
13430 stable(feature = "neon_intrinsics", since = "1.59.0")
13431)]
13432#[cfg_attr(
13433 target_arch = "arm",
13434 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13435)]
13436pub fn vget_lane_s64<const IMM5: i32>(v: int64x1_t) -> i64 {
13437 static_assert!(IMM5 == 0);
13438 unsafe { simd_extract!(v, IMM5 as u32) }
13439}
13440#[doc = "Move vector element to general-purpose register"]
13441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u64)"]
13442#[inline]
13443#[target_feature(enable = "neon")]
13444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13445#[rustc_legacy_const_generics(1)]
13446#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13447#[cfg_attr(
13448 not(target_arch = "arm"),
13449 stable(feature = "neon_intrinsics", since = "1.59.0")
13450)]
13451#[cfg_attr(
13452 target_arch = "arm",
13453 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13454)]
13455pub fn vget_lane_u64<const IMM5: i32>(v: uint64x1_t) -> u64 {
13456 static_assert!(IMM5 == 0);
13457 unsafe { simd_extract!(v, 0) }
13458}
13459#[doc = "Duplicate vector element to vector or scalar"]
13460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"]
13461#[inline]
13462#[target_feature(enable = "neon")]
13463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13464#[cfg_attr(test, assert_instr(nop))]
13465#[cfg_attr(
13466 not(target_arch = "arm"),
13467 stable(feature = "neon_intrinsics", since = "1.59.0")
13468)]
13469#[cfg_attr(
13470 target_arch = "arm",
13471 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13472)]
13473pub fn vget_low_f32(a: float32x4_t) -> float32x2_t {
13474 unsafe { simd_shuffle!(a, a, [0, 1]) }
13475}
13476#[doc = "Duplicate vector element to vector or scalar"]
13477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"]
13478#[inline]
13479#[target_feature(enable = "neon")]
13480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13481#[cfg_attr(test, assert_instr(nop))]
13482#[cfg_attr(
13483 not(target_arch = "arm"),
13484 stable(feature = "neon_intrinsics", since = "1.59.0")
13485)]
13486#[cfg_attr(
13487 target_arch = "arm",
13488 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13489)]
13490pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t {
13491 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13492}
13493#[doc = "Duplicate vector element to vector or scalar"]
13494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"]
13495#[inline]
13496#[target_feature(enable = "neon")]
13497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13498#[cfg_attr(test, assert_instr(nop))]
13499#[cfg_attr(
13500 not(target_arch = "arm"),
13501 stable(feature = "neon_intrinsics", since = "1.59.0")
13502)]
13503#[cfg_attr(
13504 target_arch = "arm",
13505 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13506)]
13507pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t {
13508 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13509}
13510#[doc = "Duplicate vector element to vector or scalar"]
13511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"]
13512#[inline]
13513#[target_feature(enable = "neon")]
13514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13515#[cfg_attr(test, assert_instr(nop))]
13516#[cfg_attr(
13517 not(target_arch = "arm"),
13518 stable(feature = "neon_intrinsics", since = "1.59.0")
13519)]
13520#[cfg_attr(
13521 target_arch = "arm",
13522 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13523)]
13524pub fn vget_low_s16(a: int16x8_t) -> int16x4_t {
13525 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13526}
13527#[doc = "Duplicate vector element to vector or scalar"]
13528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"]
13529#[inline]
13530#[target_feature(enable = "neon")]
13531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13532#[cfg_attr(test, assert_instr(nop))]
13533#[cfg_attr(
13534 not(target_arch = "arm"),
13535 stable(feature = "neon_intrinsics", since = "1.59.0")
13536)]
13537#[cfg_attr(
13538 target_arch = "arm",
13539 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13540)]
13541pub fn vget_low_s32(a: int32x4_t) -> int32x2_t {
13542 unsafe { simd_shuffle!(a, a, [0, 1]) }
13543}
13544#[doc = "Duplicate vector element to vector or scalar"]
13545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"]
13546#[inline]
13547#[target_feature(enable = "neon")]
13548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13549#[cfg_attr(test, assert_instr(nop))]
13550#[cfg_attr(
13551 not(target_arch = "arm"),
13552 stable(feature = "neon_intrinsics", since = "1.59.0")
13553)]
13554#[cfg_attr(
13555 target_arch = "arm",
13556 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13557)]
13558pub fn vget_low_s8(a: int8x16_t) -> int8x8_t {
13559 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13560}
13561#[doc = "Duplicate vector element to vector or scalar"]
13562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"]
13563#[inline]
13564#[target_feature(enable = "neon")]
13565#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13566#[cfg_attr(test, assert_instr(nop))]
13567#[cfg_attr(
13568 not(target_arch = "arm"),
13569 stable(feature = "neon_intrinsics", since = "1.59.0")
13570)]
13571#[cfg_attr(
13572 target_arch = "arm",
13573 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13574)]
13575pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t {
13576 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13577}
13578#[doc = "Duplicate vector element to vector or scalar"]
13579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"]
13580#[inline]
13581#[target_feature(enable = "neon")]
13582#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13583#[cfg_attr(test, assert_instr(nop))]
13584#[cfg_attr(
13585 not(target_arch = "arm"),
13586 stable(feature = "neon_intrinsics", since = "1.59.0")
13587)]
13588#[cfg_attr(
13589 target_arch = "arm",
13590 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13591)]
13592pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t {
13593 unsafe { simd_shuffle!(a, a, [0, 1]) }
13594}
13595#[doc = "Duplicate vector element to vector or scalar"]
13596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"]
13597#[inline]
13598#[target_feature(enable = "neon")]
13599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13600#[cfg_attr(test, assert_instr(nop))]
13601#[cfg_attr(
13602 not(target_arch = "arm"),
13603 stable(feature = "neon_intrinsics", since = "1.59.0")
13604)]
13605#[cfg_attr(
13606 target_arch = "arm",
13607 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13608)]
13609pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t {
13610 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13611}
13612#[doc = "Duplicate vector element to vector or scalar"]
13613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"]
13614#[inline]
13615#[target_feature(enable = "neon")]
13616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13617#[cfg_attr(test, assert_instr(nop))]
13618#[cfg_attr(
13619 not(target_arch = "arm"),
13620 stable(feature = "neon_intrinsics", since = "1.59.0")
13621)]
13622#[cfg_attr(
13623 target_arch = "arm",
13624 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13625)]
13626pub fn vget_low_s64(a: int64x2_t) -> int64x1_t {
13627 unsafe { int64x1_t([simd_extract!(a, 0)]) }
13628}
13629#[doc = "Duplicate vector element to vector or scalar"]
13630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"]
13631#[inline]
13632#[target_feature(enable = "neon")]
13633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13634#[cfg_attr(test, assert_instr(nop))]
13635#[cfg_attr(
13636 not(target_arch = "arm"),
13637 stable(feature = "neon_intrinsics", since = "1.59.0")
13638)]
13639#[cfg_attr(
13640 target_arch = "arm",
13641 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13642)]
13643pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t {
13644 unsafe { uint64x1_t([simd_extract!(a, 0)]) }
13645}
13646#[doc = "Halving add"]
13647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"]
13648#[inline]
13649#[target_feature(enable = "neon")]
13650#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13651#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
13652#[cfg_attr(
13653 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13654 assert_instr(shadd)
13655)]
13656#[cfg_attr(
13657 not(target_arch = "arm"),
13658 stable(feature = "neon_intrinsics", since = "1.59.0")
13659)]
13660#[cfg_attr(
13661 target_arch = "arm",
13662 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13663)]
13664pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
13665 unsafe extern "unadjusted" {
13666 #[cfg_attr(
13667 any(target_arch = "aarch64", target_arch = "arm64ec"),
13668 link_name = "llvm.aarch64.neon.shadd.v8i8"
13669 )]
13670 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")]
13671 fn _vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
13672 }
13673 unsafe { _vhadd_s8(a, b) }
13674}
13675#[doc = "Halving add"]
13676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"]
13677#[inline]
13678#[target_feature(enable = "neon")]
13679#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13680#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
13681#[cfg_attr(
13682 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13683 assert_instr(shadd)
13684)]
13685#[cfg_attr(
13686 not(target_arch = "arm"),
13687 stable(feature = "neon_intrinsics", since = "1.59.0")
13688)]
13689#[cfg_attr(
13690 target_arch = "arm",
13691 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13692)]
13693pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
13694 unsafe extern "unadjusted" {
13695 #[cfg_attr(
13696 any(target_arch = "aarch64", target_arch = "arm64ec"),
13697 link_name = "llvm.aarch64.neon.shadd.v16i8"
13698 )]
13699 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")]
13700 fn _vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
13701 }
13702 unsafe { _vhaddq_s8(a, b) }
13703}
13704#[doc = "Halving add"]
13705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"]
13706#[inline]
13707#[target_feature(enable = "neon")]
13708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13709#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
13710#[cfg_attr(
13711 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13712 assert_instr(shadd)
13713)]
13714#[cfg_attr(
13715 not(target_arch = "arm"),
13716 stable(feature = "neon_intrinsics", since = "1.59.0")
13717)]
13718#[cfg_attr(
13719 target_arch = "arm",
13720 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13721)]
13722pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
13723 unsafe extern "unadjusted" {
13724 #[cfg_attr(
13725 any(target_arch = "aarch64", target_arch = "arm64ec"),
13726 link_name = "llvm.aarch64.neon.shadd.v4i16"
13727 )]
13728 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")]
13729 fn _vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
13730 }
13731 unsafe { _vhadd_s16(a, b) }
13732}
13733#[doc = "Halving add"]
13734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"]
13735#[inline]
13736#[target_feature(enable = "neon")]
13737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13738#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
13739#[cfg_attr(
13740 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13741 assert_instr(shadd)
13742)]
13743#[cfg_attr(
13744 not(target_arch = "arm"),
13745 stable(feature = "neon_intrinsics", since = "1.59.0")
13746)]
13747#[cfg_attr(
13748 target_arch = "arm",
13749 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13750)]
13751pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
13752 unsafe extern "unadjusted" {
13753 #[cfg_attr(
13754 any(target_arch = "aarch64", target_arch = "arm64ec"),
13755 link_name = "llvm.aarch64.neon.shadd.v8i16"
13756 )]
13757 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")]
13758 fn _vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
13759 }
13760 unsafe { _vhaddq_s16(a, b) }
13761}
13762#[doc = "Halving add"]
13763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"]
13764#[inline]
13765#[target_feature(enable = "neon")]
13766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13767#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
13768#[cfg_attr(
13769 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13770 assert_instr(shadd)
13771)]
13772#[cfg_attr(
13773 not(target_arch = "arm"),
13774 stable(feature = "neon_intrinsics", since = "1.59.0")
13775)]
13776#[cfg_attr(
13777 target_arch = "arm",
13778 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13779)]
13780pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
13781 unsafe extern "unadjusted" {
13782 #[cfg_attr(
13783 any(target_arch = "aarch64", target_arch = "arm64ec"),
13784 link_name = "llvm.aarch64.neon.shadd.v2i32"
13785 )]
13786 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")]
13787 fn _vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
13788 }
13789 unsafe { _vhadd_s32(a, b) }
13790}
13791#[doc = "Halving add"]
13792#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"]
13793#[inline]
13794#[target_feature(enable = "neon")]
13795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13796#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
13797#[cfg_attr(
13798 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13799 assert_instr(shadd)
13800)]
13801#[cfg_attr(
13802 not(target_arch = "arm"),
13803 stable(feature = "neon_intrinsics", since = "1.59.0")
13804)]
13805#[cfg_attr(
13806 target_arch = "arm",
13807 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13808)]
13809pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
13810 unsafe extern "unadjusted" {
13811 #[cfg_attr(
13812 any(target_arch = "aarch64", target_arch = "arm64ec"),
13813 link_name = "llvm.aarch64.neon.shadd.v4i32"
13814 )]
13815 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")]
13816 fn _vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
13817 }
13818 unsafe { _vhaddq_s32(a, b) }
13819}
13820#[doc = "Halving add"]
13821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"]
13822#[inline]
13823#[target_feature(enable = "neon")]
13824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13825#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
13826#[cfg_attr(
13827 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13828 assert_instr(uhadd)
13829)]
13830#[cfg_attr(
13831 not(target_arch = "arm"),
13832 stable(feature = "neon_intrinsics", since = "1.59.0")
13833)]
13834#[cfg_attr(
13835 target_arch = "arm",
13836 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13837)]
13838pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
13839 unsafe extern "unadjusted" {
13840 #[cfg_attr(
13841 any(target_arch = "aarch64", target_arch = "arm64ec"),
13842 link_name = "llvm.aarch64.neon.uhadd.v8i8"
13843 )]
13844 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")]
13845 fn _vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
13846 }
13847 unsafe { _vhadd_u8(a, b) }
13848}
13849#[doc = "Halving add"]
13850#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"]
13851#[inline]
13852#[target_feature(enable = "neon")]
13853#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13854#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
13855#[cfg_attr(
13856 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13857 assert_instr(uhadd)
13858)]
13859#[cfg_attr(
13860 not(target_arch = "arm"),
13861 stable(feature = "neon_intrinsics", since = "1.59.0")
13862)]
13863#[cfg_attr(
13864 target_arch = "arm",
13865 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13866)]
13867pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
13868 unsafe extern "unadjusted" {
13869 #[cfg_attr(
13870 any(target_arch = "aarch64", target_arch = "arm64ec"),
13871 link_name = "llvm.aarch64.neon.uhadd.v16i8"
13872 )]
13873 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")]
13874 fn _vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
13875 }
13876 unsafe { _vhaddq_u8(a, b) }
13877}
13878#[doc = "Halving add"]
13879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"]
13880#[inline]
13881#[target_feature(enable = "neon")]
13882#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13883#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
13884#[cfg_attr(
13885 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13886 assert_instr(uhadd)
13887)]
13888#[cfg_attr(
13889 not(target_arch = "arm"),
13890 stable(feature = "neon_intrinsics", since = "1.59.0")
13891)]
13892#[cfg_attr(
13893 target_arch = "arm",
13894 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13895)]
13896pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
13897 unsafe extern "unadjusted" {
13898 #[cfg_attr(
13899 any(target_arch = "aarch64", target_arch = "arm64ec"),
13900 link_name = "llvm.aarch64.neon.uhadd.v4i16"
13901 )]
13902 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")]
13903 fn _vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
13904 }
13905 unsafe { _vhadd_u16(a, b) }
13906}
13907#[doc = "Halving add"]
13908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"]
13909#[inline]
13910#[target_feature(enable = "neon")]
13911#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13912#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
13913#[cfg_attr(
13914 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13915 assert_instr(uhadd)
13916)]
13917#[cfg_attr(
13918 not(target_arch = "arm"),
13919 stable(feature = "neon_intrinsics", since = "1.59.0")
13920)]
13921#[cfg_attr(
13922 target_arch = "arm",
13923 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13924)]
13925pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
13926 unsafe extern "unadjusted" {
13927 #[cfg_attr(
13928 any(target_arch = "aarch64", target_arch = "arm64ec"),
13929 link_name = "llvm.aarch64.neon.uhadd.v8i16"
13930 )]
13931 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")]
13932 fn _vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
13933 }
13934 unsafe { _vhaddq_u16(a, b) }
13935}
13936#[doc = "Halving add"]
13937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"]
13938#[inline]
13939#[target_feature(enable = "neon")]
13940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13941#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
13942#[cfg_attr(
13943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13944 assert_instr(uhadd)
13945)]
13946#[cfg_attr(
13947 not(target_arch = "arm"),
13948 stable(feature = "neon_intrinsics", since = "1.59.0")
13949)]
13950#[cfg_attr(
13951 target_arch = "arm",
13952 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13953)]
13954pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
13955 unsafe extern "unadjusted" {
13956 #[cfg_attr(
13957 any(target_arch = "aarch64", target_arch = "arm64ec"),
13958 link_name = "llvm.aarch64.neon.uhadd.v2i32"
13959 )]
13960 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")]
13961 fn _vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
13962 }
13963 unsafe { _vhadd_u32(a, b) }
13964}
13965#[doc = "Halving add"]
13966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"]
13967#[inline]
13968#[target_feature(enable = "neon")]
13969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13970#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
13971#[cfg_attr(
13972 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13973 assert_instr(uhadd)
13974)]
13975#[cfg_attr(
13976 not(target_arch = "arm"),
13977 stable(feature = "neon_intrinsics", since = "1.59.0")
13978)]
13979#[cfg_attr(
13980 target_arch = "arm",
13981 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13982)]
13983pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
13984 unsafe extern "unadjusted" {
13985 #[cfg_attr(
13986 any(target_arch = "aarch64", target_arch = "arm64ec"),
13987 link_name = "llvm.aarch64.neon.uhadd.v4i32"
13988 )]
13989 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")]
13990 fn _vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
13991 }
13992 unsafe { _vhaddq_u32(a, b) }
13993}
13994#[doc = "Signed halving subtract"]
13995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"]
13996#[inline]
13997#[target_feature(enable = "neon")]
13998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13999#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
14000#[cfg_attr(
14001 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14002 assert_instr(shsub)
14003)]
14004#[cfg_attr(
14005 not(target_arch = "arm"),
14006 stable(feature = "neon_intrinsics", since = "1.59.0")
14007)]
14008#[cfg_attr(
14009 target_arch = "arm",
14010 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14011)]
14012pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
14013 unsafe extern "unadjusted" {
14014 #[cfg_attr(
14015 any(target_arch = "aarch64", target_arch = "arm64ec"),
14016 link_name = "llvm.aarch64.neon.shsub.v4i16"
14017 )]
14018 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")]
14019 fn _vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
14020 }
14021 unsafe { _vhsub_s16(a, b) }
14022}
14023#[doc = "Signed halving subtract"]
14024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"]
14025#[inline]
14026#[target_feature(enable = "neon")]
14027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14028#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
14029#[cfg_attr(
14030 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14031 assert_instr(shsub)
14032)]
14033#[cfg_attr(
14034 not(target_arch = "arm"),
14035 stable(feature = "neon_intrinsics", since = "1.59.0")
14036)]
14037#[cfg_attr(
14038 target_arch = "arm",
14039 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14040)]
14041pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
14042 unsafe extern "unadjusted" {
14043 #[cfg_attr(
14044 any(target_arch = "aarch64", target_arch = "arm64ec"),
14045 link_name = "llvm.aarch64.neon.shsub.v8i16"
14046 )]
14047 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")]
14048 fn _vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
14049 }
14050 unsafe { _vhsubq_s16(a, b) }
14051}
14052#[doc = "Signed halving subtract"]
14053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"]
14054#[inline]
14055#[target_feature(enable = "neon")]
14056#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14057#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
14058#[cfg_attr(
14059 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14060 assert_instr(shsub)
14061)]
14062#[cfg_attr(
14063 not(target_arch = "arm"),
14064 stable(feature = "neon_intrinsics", since = "1.59.0")
14065)]
14066#[cfg_attr(
14067 target_arch = "arm",
14068 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14069)]
14070pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
14071 unsafe extern "unadjusted" {
14072 #[cfg_attr(
14073 any(target_arch = "aarch64", target_arch = "arm64ec"),
14074 link_name = "llvm.aarch64.neon.shsub.v2i32"
14075 )]
14076 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")]
14077 fn _vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
14078 }
14079 unsafe { _vhsub_s32(a, b) }
14080}
14081#[doc = "Signed halving subtract"]
14082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"]
14083#[inline]
14084#[target_feature(enable = "neon")]
14085#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14086#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
14087#[cfg_attr(
14088 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14089 assert_instr(shsub)
14090)]
14091#[cfg_attr(
14092 not(target_arch = "arm"),
14093 stable(feature = "neon_intrinsics", since = "1.59.0")
14094)]
14095#[cfg_attr(
14096 target_arch = "arm",
14097 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14098)]
14099pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
14100 unsafe extern "unadjusted" {
14101 #[cfg_attr(
14102 any(target_arch = "aarch64", target_arch = "arm64ec"),
14103 link_name = "llvm.aarch64.neon.shsub.v4i32"
14104 )]
14105 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")]
14106 fn _vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
14107 }
14108 unsafe { _vhsubq_s32(a, b) }
14109}
14110#[doc = "Signed halving subtract"]
14111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"]
14112#[inline]
14113#[target_feature(enable = "neon")]
14114#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14115#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
14116#[cfg_attr(
14117 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14118 assert_instr(shsub)
14119)]
14120#[cfg_attr(
14121 not(target_arch = "arm"),
14122 stable(feature = "neon_intrinsics", since = "1.59.0")
14123)]
14124#[cfg_attr(
14125 target_arch = "arm",
14126 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14127)]
14128pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
14129 unsafe extern "unadjusted" {
14130 #[cfg_attr(
14131 any(target_arch = "aarch64", target_arch = "arm64ec"),
14132 link_name = "llvm.aarch64.neon.shsub.v8i8"
14133 )]
14134 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")]
14135 fn _vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
14136 }
14137 unsafe { _vhsub_s8(a, b) }
14138}
14139#[doc = "Signed halving subtract"]
14140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"]
14141#[inline]
14142#[target_feature(enable = "neon")]
14143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14144#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
14145#[cfg_attr(
14146 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14147 assert_instr(shsub)
14148)]
14149#[cfg_attr(
14150 not(target_arch = "arm"),
14151 stable(feature = "neon_intrinsics", since = "1.59.0")
14152)]
14153#[cfg_attr(
14154 target_arch = "arm",
14155 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14156)]
14157pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
14158 unsafe extern "unadjusted" {
14159 #[cfg_attr(
14160 any(target_arch = "aarch64", target_arch = "arm64ec"),
14161 link_name = "llvm.aarch64.neon.shsub.v16i8"
14162 )]
14163 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")]
14164 fn _vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
14165 }
14166 unsafe { _vhsubq_s8(a, b) }
14167}
14168#[doc = "Signed halving subtract"]
14169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"]
14170#[inline]
14171#[target_feature(enable = "neon")]
14172#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14173#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
14174#[cfg_attr(
14175 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14176 assert_instr(uhsub)
14177)]
14178#[cfg_attr(
14179 not(target_arch = "arm"),
14180 stable(feature = "neon_intrinsics", since = "1.59.0")
14181)]
14182#[cfg_attr(
14183 target_arch = "arm",
14184 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14185)]
14186pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
14187 unsafe extern "unadjusted" {
14188 #[cfg_attr(
14189 any(target_arch = "aarch64", target_arch = "arm64ec"),
14190 link_name = "llvm.aarch64.neon.uhsub.v8i8"
14191 )]
14192 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")]
14193 fn _vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
14194 }
14195 unsafe { _vhsub_u8(a, b) }
14196}
14197#[doc = "Signed halving subtract"]
14198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"]
14199#[inline]
14200#[target_feature(enable = "neon")]
14201#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14202#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
14203#[cfg_attr(
14204 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14205 assert_instr(uhsub)
14206)]
14207#[cfg_attr(
14208 not(target_arch = "arm"),
14209 stable(feature = "neon_intrinsics", since = "1.59.0")
14210)]
14211#[cfg_attr(
14212 target_arch = "arm",
14213 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14214)]
14215pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
14216 unsafe extern "unadjusted" {
14217 #[cfg_attr(
14218 any(target_arch = "aarch64", target_arch = "arm64ec"),
14219 link_name = "llvm.aarch64.neon.uhsub.v16i8"
14220 )]
14221 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")]
14222 fn _vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
14223 }
14224 unsafe { _vhsubq_u8(a, b) }
14225}
14226#[doc = "Signed halving subtract"]
14227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"]
14228#[inline]
14229#[target_feature(enable = "neon")]
14230#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14231#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
14232#[cfg_attr(
14233 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14234 assert_instr(uhsub)
14235)]
14236#[cfg_attr(
14237 not(target_arch = "arm"),
14238 stable(feature = "neon_intrinsics", since = "1.59.0")
14239)]
14240#[cfg_attr(
14241 target_arch = "arm",
14242 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14243)]
14244pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
14245 unsafe extern "unadjusted" {
14246 #[cfg_attr(
14247 any(target_arch = "aarch64", target_arch = "arm64ec"),
14248 link_name = "llvm.aarch64.neon.uhsub.v4i16"
14249 )]
14250 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")]
14251 fn _vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
14252 }
14253 unsafe { _vhsub_u16(a, b) }
14254}
14255#[doc = "Signed halving subtract"]
14256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"]
14257#[inline]
14258#[target_feature(enable = "neon")]
14259#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14260#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
14261#[cfg_attr(
14262 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14263 assert_instr(uhsub)
14264)]
14265#[cfg_attr(
14266 not(target_arch = "arm"),
14267 stable(feature = "neon_intrinsics", since = "1.59.0")
14268)]
14269#[cfg_attr(
14270 target_arch = "arm",
14271 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14272)]
14273pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
14274 unsafe extern "unadjusted" {
14275 #[cfg_attr(
14276 any(target_arch = "aarch64", target_arch = "arm64ec"),
14277 link_name = "llvm.aarch64.neon.uhsub.v8i16"
14278 )]
14279 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")]
14280 fn _vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
14281 }
14282 unsafe { _vhsubq_u16(a, b) }
14283}
14284#[doc = "Signed halving subtract"]
14285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"]
14286#[inline]
14287#[target_feature(enable = "neon")]
14288#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14289#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
14290#[cfg_attr(
14291 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14292 assert_instr(uhsub)
14293)]
14294#[cfg_attr(
14295 not(target_arch = "arm"),
14296 stable(feature = "neon_intrinsics", since = "1.59.0")
14297)]
14298#[cfg_attr(
14299 target_arch = "arm",
14300 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14301)]
14302pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
14303 unsafe extern "unadjusted" {
14304 #[cfg_attr(
14305 any(target_arch = "aarch64", target_arch = "arm64ec"),
14306 link_name = "llvm.aarch64.neon.uhsub.v2i32"
14307 )]
14308 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")]
14309 fn _vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
14310 }
14311 unsafe { _vhsub_u32(a, b) }
14312}
14313#[doc = "Signed halving subtract"]
14314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"]
14315#[inline]
14316#[target_feature(enable = "neon")]
14317#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14318#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
14319#[cfg_attr(
14320 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14321 assert_instr(uhsub)
14322)]
14323#[cfg_attr(
14324 not(target_arch = "arm"),
14325 stable(feature = "neon_intrinsics", since = "1.59.0")
14326)]
14327#[cfg_attr(
14328 target_arch = "arm",
14329 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14330)]
14331pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
14332 unsafe extern "unadjusted" {
14333 #[cfg_attr(
14334 any(target_arch = "aarch64", target_arch = "arm64ec"),
14335 link_name = "llvm.aarch64.neon.uhsub.v4i32"
14336 )]
14337 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")]
14338 fn _vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
14339 }
14340 unsafe { _vhsubq_u32(a, b) }
14341}
14342#[doc = "Load one single-element structure and replicate to all lanes of one register"]
14343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"]
14344#[doc = "## Safety"]
14345#[doc = " * Neon instrinsic unsafe"]
14346#[inline]
14347#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14348#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14349#[cfg_attr(
14350 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14351 assert_instr(ld1r)
14352)]
14353#[target_feature(enable = "neon,fp16")]
14354#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14355pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
14356 let x: float16x4_t = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0)));
14357 simd_shuffle!(x, x, [0, 0, 0, 0])
14358}
14359#[doc = "Load one single-element structure and replicate to all lanes of one register"]
14360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
14361#[doc = "## Safety"]
14362#[doc = " * Neon instrinsic unsafe"]
14363#[inline]
14364#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14365#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14366#[cfg_attr(
14367 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14368 assert_instr(ld1r)
14369)]
14370#[target_feature(enable = "neon,fp16")]
14371#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14372pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
14373 let x: float16x8_t = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0)));
14374 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14375}
14376#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"]
14378#[doc = "## Safety"]
14379#[doc = " * Neon instrinsic unsafe"]
14380#[inline]
14381#[target_feature(enable = "neon")]
14382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14383#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14384#[cfg_attr(
14385 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14386 assert_instr(ld1r)
14387)]
14388#[cfg_attr(
14389 not(target_arch = "arm"),
14390 stable(feature = "neon_intrinsics", since = "1.59.0")
14391)]
14392#[cfg_attr(
14393 target_arch = "arm",
14394 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14395)]
14396pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t {
14397 let x = vld1_lane_f32::<0>(ptr, transmute(f32x2::splat(0.0)));
14398 simd_shuffle!(x, x, [0, 0])
14399}
14400#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"]
14402#[doc = "## Safety"]
14403#[doc = " * Neon instrinsic unsafe"]
14404#[inline]
14405#[target_feature(enable = "neon")]
14406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14407#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14408#[cfg_attr(
14409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14410 assert_instr(ld1r)
14411)]
14412#[cfg_attr(
14413 not(target_arch = "arm"),
14414 stable(feature = "neon_intrinsics", since = "1.59.0")
14415)]
14416#[cfg_attr(
14417 target_arch = "arm",
14418 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14419)]
14420pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t {
14421 let x = vld1_lane_p16::<0>(ptr, transmute(u16x4::splat(0)));
14422 simd_shuffle!(x, x, [0, 0, 0, 0])
14423}
14424#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"]
14426#[doc = "## Safety"]
14427#[doc = " * Neon instrinsic unsafe"]
14428#[inline]
14429#[target_feature(enable = "neon")]
14430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14431#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14432#[cfg_attr(
14433 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14434 assert_instr(ld1r)
14435)]
14436#[cfg_attr(
14437 not(target_arch = "arm"),
14438 stable(feature = "neon_intrinsics", since = "1.59.0")
14439)]
14440#[cfg_attr(
14441 target_arch = "arm",
14442 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14443)]
14444pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t {
14445 let x = vld1_lane_p8::<0>(ptr, transmute(u8x8::splat(0)));
14446 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14447}
14448#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"]
14450#[doc = "## Safety"]
14451#[doc = " * Neon instrinsic unsafe"]
14452#[inline]
14453#[target_feature(enable = "neon")]
14454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14455#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14456#[cfg_attr(
14457 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14458 assert_instr(ld1r)
14459)]
14460#[cfg_attr(
14461 not(target_arch = "arm"),
14462 stable(feature = "neon_intrinsics", since = "1.59.0")
14463)]
14464#[cfg_attr(
14465 target_arch = "arm",
14466 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14467)]
14468pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t {
14469 let x = vld1_lane_s16::<0>(ptr, transmute(i16x4::splat(0)));
14470 simd_shuffle!(x, x, [0, 0, 0, 0])
14471}
14472#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"]
14474#[doc = "## Safety"]
14475#[doc = " * Neon instrinsic unsafe"]
14476#[inline]
14477#[target_feature(enable = "neon")]
14478#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14479#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14480#[cfg_attr(
14481 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14482 assert_instr(ld1r)
14483)]
14484#[cfg_attr(
14485 not(target_arch = "arm"),
14486 stable(feature = "neon_intrinsics", since = "1.59.0")
14487)]
14488#[cfg_attr(
14489 target_arch = "arm",
14490 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14491)]
14492pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t {
14493 let x = vld1_lane_s32::<0>(ptr, transmute(i32x2::splat(0)));
14494 simd_shuffle!(x, x, [0, 0])
14495}
14496#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"]
14498#[doc = "## Safety"]
14499#[doc = " * Neon instrinsic unsafe"]
14500#[inline]
14501#[target_feature(enable = "neon")]
14502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14503#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14504#[cfg_attr(
14505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14506 assert_instr(ld1r)
14507)]
14508#[cfg_attr(
14509 not(target_arch = "arm"),
14510 stable(feature = "neon_intrinsics", since = "1.59.0")
14511)]
14512#[cfg_attr(
14513 target_arch = "arm",
14514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14515)]
14516pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t {
14517 let x = vld1_lane_s8::<0>(ptr, transmute(i8x8::splat(0)));
14518 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14519}
14520#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"]
14522#[doc = "## Safety"]
14523#[doc = " * Neon instrinsic unsafe"]
14524#[inline]
14525#[target_feature(enable = "neon")]
14526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14527#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14528#[cfg_attr(
14529 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14530 assert_instr(ld1r)
14531)]
14532#[cfg_attr(
14533 not(target_arch = "arm"),
14534 stable(feature = "neon_intrinsics", since = "1.59.0")
14535)]
14536#[cfg_attr(
14537 target_arch = "arm",
14538 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14539)]
14540pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t {
14541 let x = vld1_lane_u16::<0>(ptr, transmute(u16x4::splat(0)));
14542 simd_shuffle!(x, x, [0, 0, 0, 0])
14543}
14544#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"]
14546#[doc = "## Safety"]
14547#[doc = " * Neon instrinsic unsafe"]
14548#[inline]
14549#[target_feature(enable = "neon")]
14550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14551#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14552#[cfg_attr(
14553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14554 assert_instr(ld1r)
14555)]
14556#[cfg_attr(
14557 not(target_arch = "arm"),
14558 stable(feature = "neon_intrinsics", since = "1.59.0")
14559)]
14560#[cfg_attr(
14561 target_arch = "arm",
14562 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14563)]
14564pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t {
14565 let x = vld1_lane_u32::<0>(ptr, transmute(u32x2::splat(0)));
14566 simd_shuffle!(x, x, [0, 0])
14567}
14568#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"]
14570#[doc = "## Safety"]
14571#[doc = " * Neon instrinsic unsafe"]
14572#[inline]
14573#[target_feature(enable = "neon")]
14574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14575#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14576#[cfg_attr(
14577 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14578 assert_instr(ld1r)
14579)]
14580#[cfg_attr(
14581 not(target_arch = "arm"),
14582 stable(feature = "neon_intrinsics", since = "1.59.0")
14583)]
14584#[cfg_attr(
14585 target_arch = "arm",
14586 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14587)]
14588pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t {
14589 let x = vld1_lane_u8::<0>(ptr, transmute(u8x8::splat(0)));
14590 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14591}
14592#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"]
14594#[doc = "## Safety"]
14595#[doc = " * Neon instrinsic unsafe"]
14596#[inline]
14597#[target_feature(enable = "neon")]
14598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14599#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14600#[cfg_attr(
14601 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14602 assert_instr(ld1r)
14603)]
14604#[cfg_attr(
14605 not(target_arch = "arm"),
14606 stable(feature = "neon_intrinsics", since = "1.59.0")
14607)]
14608#[cfg_attr(
14609 target_arch = "arm",
14610 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14611)]
14612pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t {
14613 let x = vld1q_lane_f32::<0>(ptr, transmute(f32x4::splat(0.0)));
14614 simd_shuffle!(x, x, [0, 0, 0, 0])
14615}
14616#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"]
14618#[doc = "## Safety"]
14619#[doc = " * Neon instrinsic unsafe"]
14620#[inline]
14621#[target_feature(enable = "neon")]
14622#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14623#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14624#[cfg_attr(
14625 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14626 assert_instr(ld1r)
14627)]
14628#[cfg_attr(
14629 not(target_arch = "arm"),
14630 stable(feature = "neon_intrinsics", since = "1.59.0")
14631)]
14632#[cfg_attr(
14633 target_arch = "arm",
14634 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14635)]
14636pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t {
14637 let x = vld1q_lane_p16::<0>(ptr, transmute(u16x8::splat(0)));
14638 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14639}
14640#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"]
14642#[doc = "## Safety"]
14643#[doc = " * Neon instrinsic unsafe"]
14644#[inline]
14645#[target_feature(enable = "neon")]
14646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14647#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14648#[cfg_attr(
14649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14650 assert_instr(ld1r)
14651)]
14652#[cfg_attr(
14653 not(target_arch = "arm"),
14654 stable(feature = "neon_intrinsics", since = "1.59.0")
14655)]
14656#[cfg_attr(
14657 target_arch = "arm",
14658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14659)]
14660pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t {
14661 let x = vld1q_lane_p8::<0>(ptr, transmute(u8x16::splat(0)));
14662 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
14663}
14664#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"]
14666#[doc = "## Safety"]
14667#[doc = " * Neon instrinsic unsafe"]
14668#[inline]
14669#[target_feature(enable = "neon")]
14670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14671#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14672#[cfg_attr(
14673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14674 assert_instr(ld1r)
14675)]
14676#[cfg_attr(
14677 not(target_arch = "arm"),
14678 stable(feature = "neon_intrinsics", since = "1.59.0")
14679)]
14680#[cfg_attr(
14681 target_arch = "arm",
14682 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14683)]
14684pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t {
14685 let x = vld1q_lane_s16::<0>(ptr, transmute(i16x8::splat(0)));
14686 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14687}
14688#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"]
14690#[doc = "## Safety"]
14691#[doc = " * Neon instrinsic unsafe"]
14692#[inline]
14693#[target_feature(enable = "neon")]
14694#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14695#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14696#[cfg_attr(
14697 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14698 assert_instr(ld1r)
14699)]
14700#[cfg_attr(
14701 not(target_arch = "arm"),
14702 stable(feature = "neon_intrinsics", since = "1.59.0")
14703)]
14704#[cfg_attr(
14705 target_arch = "arm",
14706 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14707)]
14708pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
14709 let x = vld1q_lane_s32::<0>(ptr, transmute(i32x4::splat(0)));
14710 simd_shuffle!(x, x, [0, 0, 0, 0])
14711}
14712#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"]
14714#[doc = "## Safety"]
14715#[doc = " * Neon instrinsic unsafe"]
14716#[inline]
14717#[target_feature(enable = "neon")]
14718#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14719#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
14720#[cfg_attr(
14721 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14722 assert_instr(ld1)
14723)]
14724#[cfg_attr(
14725 not(target_arch = "arm"),
14726 stable(feature = "neon_intrinsics", since = "1.59.0")
14727)]
14728#[cfg_attr(
14729 target_arch = "arm",
14730 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14731)]
14732pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t {
14733 let x = vld1q_lane_s64::<0>(ptr, transmute(i64x2::splat(0)));
14734 simd_shuffle!(x, x, [0, 0])
14735}
14736#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"]
14738#[doc = "## Safety"]
14739#[doc = " * Neon instrinsic unsafe"]
14740#[inline]
14741#[target_feature(enable = "neon")]
14742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14743#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14744#[cfg_attr(
14745 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14746 assert_instr(ld1r)
14747)]
14748#[cfg_attr(
14749 not(target_arch = "arm"),
14750 stable(feature = "neon_intrinsics", since = "1.59.0")
14751)]
14752#[cfg_attr(
14753 target_arch = "arm",
14754 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14755)]
14756pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t {
14757 let x = vld1q_lane_s8::<0>(ptr, transmute(i8x16::splat(0)));
14758 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
14759}
14760#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"]
14762#[doc = "## Safety"]
14763#[doc = " * Neon instrinsic unsafe"]
14764#[inline]
14765#[target_feature(enable = "neon")]
14766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14767#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14768#[cfg_attr(
14769 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14770 assert_instr(ld1r)
14771)]
14772#[cfg_attr(
14773 not(target_arch = "arm"),
14774 stable(feature = "neon_intrinsics", since = "1.59.0")
14775)]
14776#[cfg_attr(
14777 target_arch = "arm",
14778 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14779)]
14780pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t {
14781 let x = vld1q_lane_u16::<0>(ptr, transmute(u16x8::splat(0)));
14782 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14783}
14784#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"]
14786#[doc = "## Safety"]
14787#[doc = " * Neon instrinsic unsafe"]
14788#[inline]
14789#[target_feature(enable = "neon")]
14790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14791#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14792#[cfg_attr(
14793 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14794 assert_instr(ld1r)
14795)]
14796#[cfg_attr(
14797 not(target_arch = "arm"),
14798 stable(feature = "neon_intrinsics", since = "1.59.0")
14799)]
14800#[cfg_attr(
14801 target_arch = "arm",
14802 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14803)]
14804pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
14805 let x = vld1q_lane_u32::<0>(ptr, transmute(u32x4::splat(0)));
14806 simd_shuffle!(x, x, [0, 0, 0, 0])
14807}
14808#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"]
14810#[doc = "## Safety"]
14811#[doc = " * Neon instrinsic unsafe"]
14812#[inline]
14813#[target_feature(enable = "neon")]
14814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14815#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
14816#[cfg_attr(
14817 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14818 assert_instr(ld1)
14819)]
14820#[cfg_attr(
14821 not(target_arch = "arm"),
14822 stable(feature = "neon_intrinsics", since = "1.59.0")
14823)]
14824#[cfg_attr(
14825 target_arch = "arm",
14826 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14827)]
14828pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t {
14829 let x = vld1q_lane_u64::<0>(ptr, transmute(u64x2::splat(0)));
14830 simd_shuffle!(x, x, [0, 0])
14831}
14832#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"]
14834#[doc = "## Safety"]
14835#[doc = " * Neon instrinsic unsafe"]
14836#[inline]
14837#[target_feature(enable = "neon")]
14838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14839#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14840#[cfg_attr(
14841 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14842 assert_instr(ld1r)
14843)]
14844#[cfg_attr(
14845 not(target_arch = "arm"),
14846 stable(feature = "neon_intrinsics", since = "1.59.0")
14847)]
14848#[cfg_attr(
14849 target_arch = "arm",
14850 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14851)]
14852pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t {
14853 let x = vld1q_lane_u8::<0>(ptr, transmute(u8x16::splat(0)));
14854 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
14855}
14856#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"]
14858#[doc = "## Safety"]
14859#[doc = " * Neon instrinsic unsafe"]
14860#[inline]
14861#[target_feature(enable = "neon,aes")]
14862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14863#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14864#[cfg_attr(
14865 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14866 assert_instr(ldr)
14867)]
14868#[cfg_attr(
14869 not(target_arch = "arm"),
14870 stable(feature = "neon_intrinsics", since = "1.59.0")
14871)]
14872#[cfg_attr(
14873 target_arch = "arm",
14874 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14875)]
14876pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t {
14877 let x: poly64x1_t;
14878 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14879 {
14880 x = crate::core_arch::aarch64::vld1_p64(ptr);
14881 }
14882 #[cfg(target_arch = "arm")]
14883 {
14884 x = crate::core_arch::arm::vld1_p64(ptr);
14885 };
14886 x
14887}
14888#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"]
14890#[doc = "## Safety"]
14891#[doc = " * Neon instrinsic unsafe"]
14892#[inline]
14893#[target_feature(enable = "neon")]
14894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14896#[cfg_attr(
14897 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14898 assert_instr(ldr)
14899)]
14900#[cfg_attr(
14901 not(target_arch = "arm"),
14902 stable(feature = "neon_intrinsics", since = "1.59.0")
14903)]
14904#[cfg_attr(
14905 target_arch = "arm",
14906 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14907)]
14908pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t {
14909 let x: int64x1_t;
14910 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14911 {
14912 x = crate::core_arch::aarch64::vld1_s64(ptr);
14913 }
14914 #[cfg(target_arch = "arm")]
14915 {
14916 x = crate::core_arch::arm::vld1_s64(ptr);
14917 };
14918 x
14919}
14920#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"]
14922#[doc = "## Safety"]
14923#[doc = " * Neon instrinsic unsafe"]
14924#[inline]
14925#[target_feature(enable = "neon")]
14926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14927#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14928#[cfg_attr(
14929 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14930 assert_instr(ldr)
14931)]
14932#[cfg_attr(
14933 not(target_arch = "arm"),
14934 stable(feature = "neon_intrinsics", since = "1.59.0")
14935)]
14936#[cfg_attr(
14937 target_arch = "arm",
14938 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14939)]
14940pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t {
14941 let x: uint64x1_t;
14942 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14943 {
14944 x = crate::core_arch::aarch64::vld1_u64(ptr);
14945 }
14946 #[cfg(target_arch = "arm")]
14947 {
14948 x = crate::core_arch::arm::vld1_u64(ptr);
14949 };
14950 x
14951}
14952#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
14954#[doc = "## Safety"]
14955#[doc = " * Neon instrinsic unsafe"]
14956#[inline]
14957#[cfg(target_endian = "little")]
14958#[cfg(target_arch = "arm")]
14959#[target_feature(enable = "neon,v7")]
14960#[target_feature(enable = "neon,fp16")]
14961#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14962#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14963pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
14964 transmute(vld1_v4f16(
14965 ptr as *const i8,
14966 crate::mem::align_of::<f16>() as i32,
14967 ))
14968}
14969#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
14971#[doc = "## Safety"]
14972#[doc = " * Neon instrinsic unsafe"]
14973#[inline]
14974#[cfg(target_endian = "big")]
14975#[cfg(target_arch = "arm")]
14976#[target_feature(enable = "neon,v7")]
14977#[target_feature(enable = "neon,fp16")]
14978#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14979#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14980pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
14981 let ret_val: float16x4_t = transmute(vld1_v4f16(
14982 ptr as *const i8,
14983 crate::mem::align_of::<f16>() as i32,
14984 ));
14985 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
14986}
14987#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
14989#[doc = "## Safety"]
14990#[doc = " * Neon instrinsic unsafe"]
14991#[inline]
14992#[cfg(target_endian = "little")]
14993#[cfg(target_arch = "arm")]
14994#[target_feature(enable = "neon,v7")]
14995#[target_feature(enable = "neon,fp16")]
14996#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14997#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14998pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
14999 transmute(vld1q_v8f16(
15000 ptr as *const i8,
15001 crate::mem::align_of::<f16>() as i32,
15002 ))
15003}
15004#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
15006#[doc = "## Safety"]
15007#[doc = " * Neon instrinsic unsafe"]
15008#[inline]
15009#[cfg(target_endian = "big")]
15010#[cfg(target_arch = "arm")]
15011#[target_feature(enable = "neon,v7")]
15012#[target_feature(enable = "neon,fp16")]
15013#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15014#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15015pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
15016 let ret_val: float16x8_t = transmute(vld1q_v8f16(
15017 ptr as *const i8,
15018 crate::mem::align_of::<f16>() as i32,
15019 ));
15020 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15021}
15022#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"]
15024#[doc = "## Safety"]
15025#[doc = " * Neon instrinsic unsafe"]
15026#[inline]
15027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15029#[cfg_attr(
15030 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15031 assert_instr(ld1)
15032)]
15033#[target_feature(enable = "neon,fp16")]
15034#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15035pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
15036 unsafe extern "unadjusted" {
15037 #[cfg_attr(
15038 any(target_arch = "aarch64", target_arch = "arm64ec"),
15039 link_name = "llvm.aarch64.neon.ld1x2.v4f16.p0f16"
15040 )]
15041 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f16.p0f16")]
15042 fn _vld1_f16_x2(a: *const f16) -> float16x4x2_t;
15043 }
15044 _vld1_f16_x2(a)
15045}
15046#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"]
15048#[doc = "## Safety"]
15049#[doc = " * Neon instrinsic unsafe"]
15050#[inline]
15051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15053#[cfg_attr(
15054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15055 assert_instr(ld1)
15056)]
15057#[target_feature(enable = "neon,fp16")]
15058#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15059pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
15060 unsafe extern "unadjusted" {
15061 #[cfg_attr(
15062 any(target_arch = "aarch64", target_arch = "arm64ec"),
15063 link_name = "llvm.aarch64.neon.ld1x3.v4f16.p0f16"
15064 )]
15065 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f16.p0f16")]
15066 fn _vld1_f16_x3(a: *const f16) -> float16x4x3_t;
15067 }
15068 _vld1_f16_x3(a)
15069}
15070#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"]
15072#[doc = "## Safety"]
15073#[doc = " * Neon instrinsic unsafe"]
15074#[inline]
15075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15077#[cfg_attr(
15078 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15079 assert_instr(ld1)
15080)]
15081#[target_feature(enable = "neon,fp16")]
15082#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15083pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
15084 unsafe extern "unadjusted" {
15085 #[cfg_attr(
15086 any(target_arch = "aarch64", target_arch = "arm64ec"),
15087 link_name = "llvm.aarch64.neon.ld1x4.v4f16.p0f16"
15088 )]
15089 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f16.p0f16")]
15090 fn _vld1_f16_x4(a: *const f16) -> float16x4x4_t;
15091 }
15092 _vld1_f16_x4(a)
15093}
15094#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"]
15096#[doc = "## Safety"]
15097#[doc = " * Neon instrinsic unsafe"]
15098#[inline]
15099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15100#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15101#[cfg_attr(
15102 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15103 assert_instr(ld1)
15104)]
15105#[target_feature(enable = "neon,fp16")]
15106#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15107pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
15108 unsafe extern "unadjusted" {
15109 #[cfg_attr(
15110 any(target_arch = "aarch64", target_arch = "arm64ec"),
15111 link_name = "llvm.aarch64.neon.ld1x2.v8f16.p0f16"
15112 )]
15113 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8f16.p0f16")]
15114 fn _vld1q_f16_x2(a: *const f16) -> float16x8x2_t;
15115 }
15116 _vld1q_f16_x2(a)
15117}
15118#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"]
15120#[doc = "## Safety"]
15121#[doc = " * Neon instrinsic unsafe"]
15122#[inline]
15123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15125#[cfg_attr(
15126 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15127 assert_instr(ld1)
15128)]
15129#[target_feature(enable = "neon,fp16")]
15130#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15131pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
15132 unsafe extern "unadjusted" {
15133 #[cfg_attr(
15134 any(target_arch = "aarch64", target_arch = "arm64ec"),
15135 link_name = "llvm.aarch64.neon.ld1x3.v8f16.p0f16"
15136 )]
15137 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8f16.p0f16")]
15138 fn _vld1q_f16_x3(a: *const f16) -> float16x8x3_t;
15139 }
15140 _vld1q_f16_x3(a)
15141}
15142#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"]
15144#[doc = "## Safety"]
15145#[doc = " * Neon instrinsic unsafe"]
15146#[inline]
15147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15149#[cfg_attr(
15150 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15151 assert_instr(ld1)
15152)]
15153#[target_feature(enable = "neon,fp16")]
15154#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15155pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
15156 unsafe extern "unadjusted" {
15157 #[cfg_attr(
15158 any(target_arch = "aarch64", target_arch = "arm64ec"),
15159 link_name = "llvm.aarch64.neon.ld1x4.v8f16.p0f16"
15160 )]
15161 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8f16.p0f16")]
15162 fn _vld1q_f16_x4(a: *const f16) -> float16x8x4_t;
15163 }
15164 _vld1q_f16_x4(a)
15165}
15166#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
15168#[doc = "## Safety"]
15169#[doc = " * Neon instrinsic unsafe"]
15170#[inline]
15171#[cfg(target_endian = "little")]
15172#[cfg(target_arch = "arm")]
15173#[target_feature(enable = "neon,v7")]
15174#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15175#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15176pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
15177 transmute(vld1_v2f32(
15178 ptr as *const i8,
15179 crate::mem::align_of::<f32>() as i32,
15180 ))
15181}
15182#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
15184#[doc = "## Safety"]
15185#[doc = " * Neon instrinsic unsafe"]
15186#[inline]
15187#[cfg(target_endian = "big")]
15188#[cfg(target_arch = "arm")]
15189#[target_feature(enable = "neon,v7")]
15190#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15191#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15192pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
15193 let ret_val: float32x2_t = transmute(vld1_v2f32(
15194 ptr as *const i8,
15195 crate::mem::align_of::<f32>() as i32,
15196 ));
15197 simd_shuffle!(ret_val, ret_val, [1, 0])
15198}
15199#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
15201#[doc = "## Safety"]
15202#[doc = " * Neon instrinsic unsafe"]
15203#[inline]
15204#[cfg(target_endian = "little")]
15205#[cfg(target_arch = "arm")]
15206#[target_feature(enable = "neon,v7")]
15207#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15208#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15209pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
15210 transmute(vld1q_v4f32(
15211 ptr as *const i8,
15212 crate::mem::align_of::<f32>() as i32,
15213 ))
15214}
15215#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
15217#[doc = "## Safety"]
15218#[doc = " * Neon instrinsic unsafe"]
15219#[inline]
15220#[cfg(target_endian = "big")]
15221#[cfg(target_arch = "arm")]
15222#[target_feature(enable = "neon,v7")]
15223#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15224#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15225pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
15226 let ret_val: float32x4_t = transmute(vld1q_v4f32(
15227 ptr as *const i8,
15228 crate::mem::align_of::<f32>() as i32,
15229 ));
15230 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15231}
15232#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
15234#[doc = "## Safety"]
15235#[doc = " * Neon instrinsic unsafe"]
15236#[inline]
15237#[cfg(target_endian = "little")]
15238#[cfg(target_arch = "arm")]
15239#[target_feature(enable = "neon,v7")]
15240#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15241#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15242pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
15243 transmute(vld1_v8i8(
15244 ptr as *const i8,
15245 crate::mem::align_of::<u8>() as i32,
15246 ))
15247}
15248#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
15250#[doc = "## Safety"]
15251#[doc = " * Neon instrinsic unsafe"]
15252#[inline]
15253#[cfg(target_endian = "big")]
15254#[cfg(target_arch = "arm")]
15255#[target_feature(enable = "neon,v7")]
15256#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15257#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15258pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
15259 let ret_val: uint8x8_t = transmute(vld1_v8i8(
15260 ptr as *const i8,
15261 crate::mem::align_of::<u8>() as i32,
15262 ));
15263 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15264}
15265#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
15267#[doc = "## Safety"]
15268#[doc = " * Neon instrinsic unsafe"]
15269#[inline]
15270#[cfg(target_endian = "little")]
15271#[cfg(target_arch = "arm")]
15272#[target_feature(enable = "neon,v7")]
15273#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15274#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15275pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
15276 transmute(vld1q_v16i8(
15277 ptr as *const i8,
15278 crate::mem::align_of::<u8>() as i32,
15279 ))
15280}
15281#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
15283#[doc = "## Safety"]
15284#[doc = " * Neon instrinsic unsafe"]
15285#[inline]
15286#[cfg(target_endian = "big")]
15287#[cfg(target_arch = "arm")]
15288#[target_feature(enable = "neon,v7")]
15289#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15290#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15291pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
15292 let ret_val: uint8x16_t = transmute(vld1q_v16i8(
15293 ptr as *const i8,
15294 crate::mem::align_of::<u8>() as i32,
15295 ));
15296 simd_shuffle!(
15297 ret_val,
15298 ret_val,
15299 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15300 )
15301}
15302#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
15304#[doc = "## Safety"]
15305#[doc = " * Neon instrinsic unsafe"]
15306#[inline]
15307#[cfg(target_endian = "little")]
15308#[cfg(target_arch = "arm")]
15309#[target_feature(enable = "neon,v7")]
15310#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15311#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15312pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
15313 transmute(vld1_v4i16(
15314 ptr as *const i8,
15315 crate::mem::align_of::<u16>() as i32,
15316 ))
15317}
15318#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
15320#[doc = "## Safety"]
15321#[doc = " * Neon instrinsic unsafe"]
15322#[inline]
15323#[cfg(target_endian = "big")]
15324#[cfg(target_arch = "arm")]
15325#[target_feature(enable = "neon,v7")]
15326#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15327#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15328pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
15329 let ret_val: uint16x4_t = transmute(vld1_v4i16(
15330 ptr as *const i8,
15331 crate::mem::align_of::<u16>() as i32,
15332 ));
15333 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15334}
15335#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
15337#[doc = "## Safety"]
15338#[doc = " * Neon instrinsic unsafe"]
15339#[inline]
15340#[cfg(target_endian = "little")]
15341#[cfg(target_arch = "arm")]
15342#[target_feature(enable = "neon,v7")]
15343#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15344#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15345pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
15346 transmute(vld1q_v8i16(
15347 ptr as *const i8,
15348 crate::mem::align_of::<u16>() as i32,
15349 ))
15350}
15351#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
15353#[doc = "## Safety"]
15354#[doc = " * Neon instrinsic unsafe"]
15355#[inline]
15356#[cfg(target_endian = "big")]
15357#[cfg(target_arch = "arm")]
15358#[target_feature(enable = "neon,v7")]
15359#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15360#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15361pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
15362 let ret_val: uint16x8_t = transmute(vld1q_v8i16(
15363 ptr as *const i8,
15364 crate::mem::align_of::<u16>() as i32,
15365 ));
15366 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15367}
15368#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
15370#[doc = "## Safety"]
15371#[doc = " * Neon instrinsic unsafe"]
15372#[inline]
15373#[cfg(target_endian = "little")]
15374#[cfg(target_arch = "arm")]
15375#[target_feature(enable = "neon,v7")]
15376#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15377#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15378pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
15379 transmute(vld1_v2i32(
15380 ptr as *const i8,
15381 crate::mem::align_of::<u32>() as i32,
15382 ))
15383}
15384#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
15386#[doc = "## Safety"]
15387#[doc = " * Neon instrinsic unsafe"]
15388#[inline]
15389#[cfg(target_endian = "big")]
15390#[cfg(target_arch = "arm")]
15391#[target_feature(enable = "neon,v7")]
15392#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15393#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15394pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
15395 let ret_val: uint32x2_t = transmute(vld1_v2i32(
15396 ptr as *const i8,
15397 crate::mem::align_of::<u32>() as i32,
15398 ));
15399 simd_shuffle!(ret_val, ret_val, [1, 0])
15400}
15401#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
15403#[doc = "## Safety"]
15404#[doc = " * Neon instrinsic unsafe"]
15405#[inline]
15406#[cfg(target_endian = "little")]
15407#[cfg(target_arch = "arm")]
15408#[target_feature(enable = "neon,v7")]
15409#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15410#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15411pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
15412 transmute(vld1q_v4i32(
15413 ptr as *const i8,
15414 crate::mem::align_of::<u32>() as i32,
15415 ))
15416}
15417#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
15419#[doc = "## Safety"]
15420#[doc = " * Neon instrinsic unsafe"]
15421#[inline]
15422#[cfg(target_endian = "big")]
15423#[cfg(target_arch = "arm")]
15424#[target_feature(enable = "neon,v7")]
15425#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15426#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15427pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
15428 let ret_val: uint32x4_t = transmute(vld1q_v4i32(
15429 ptr as *const i8,
15430 crate::mem::align_of::<u32>() as i32,
15431 ));
15432 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15433}
15434#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
15436#[doc = "## Safety"]
15437#[doc = " * Neon instrinsic unsafe"]
15438#[inline]
15439#[cfg(target_arch = "arm")]
15440#[target_feature(enable = "neon,v7")]
15441#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15443pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
15444 transmute(vld1_v1i64(
15445 ptr as *const i8,
15446 crate::mem::align_of::<u64>() as i32,
15447 ))
15448}
15449#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
15451#[doc = "## Safety"]
15452#[doc = " * Neon instrinsic unsafe"]
15453#[inline]
15454#[cfg(target_endian = "little")]
15455#[cfg(target_arch = "arm")]
15456#[target_feature(enable = "neon,v7")]
15457#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15458#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15459pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
15460 transmute(vld1q_v2i64(
15461 ptr as *const i8,
15462 crate::mem::align_of::<u64>() as i32,
15463 ))
15464}
15465#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
15467#[doc = "## Safety"]
15468#[doc = " * Neon instrinsic unsafe"]
15469#[inline]
15470#[cfg(target_endian = "big")]
15471#[cfg(target_arch = "arm")]
15472#[target_feature(enable = "neon,v7")]
15473#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15474#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15475pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
15476 let ret_val: uint64x2_t = transmute(vld1q_v2i64(
15477 ptr as *const i8,
15478 crate::mem::align_of::<u64>() as i32,
15479 ));
15480 simd_shuffle!(ret_val, ret_val, [1, 0])
15481}
15482#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
15484#[doc = "## Safety"]
15485#[doc = " * Neon instrinsic unsafe"]
15486#[inline]
15487#[cfg(target_endian = "little")]
15488#[cfg(target_arch = "arm")]
15489#[target_feature(enable = "neon,v7")]
15490#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15491#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15492pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
15493 transmute(vld1_v8i8(
15494 ptr as *const i8,
15495 crate::mem::align_of::<p8>() as i32,
15496 ))
15497}
15498#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
15500#[doc = "## Safety"]
15501#[doc = " * Neon instrinsic unsafe"]
15502#[inline]
15503#[cfg(target_endian = "big")]
15504#[cfg(target_arch = "arm")]
15505#[target_feature(enable = "neon,v7")]
15506#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15507#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15508pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
15509 let ret_val: poly8x8_t = transmute(vld1_v8i8(
15510 ptr as *const i8,
15511 crate::mem::align_of::<p8>() as i32,
15512 ));
15513 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15514}
15515#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
15517#[doc = "## Safety"]
15518#[doc = " * Neon instrinsic unsafe"]
15519#[inline]
15520#[cfg(target_endian = "little")]
15521#[cfg(target_arch = "arm")]
15522#[target_feature(enable = "neon,v7")]
15523#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15524#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15525pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
15526 transmute(vld1q_v16i8(
15527 ptr as *const i8,
15528 crate::mem::align_of::<p8>() as i32,
15529 ))
15530}
15531#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
15533#[doc = "## Safety"]
15534#[doc = " * Neon instrinsic unsafe"]
15535#[inline]
15536#[cfg(target_endian = "big")]
15537#[cfg(target_arch = "arm")]
15538#[target_feature(enable = "neon,v7")]
15539#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15540#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15541pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
15542 let ret_val: poly8x16_t = transmute(vld1q_v16i8(
15543 ptr as *const i8,
15544 crate::mem::align_of::<p8>() as i32,
15545 ));
15546 simd_shuffle!(
15547 ret_val,
15548 ret_val,
15549 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15550 )
15551}
15552#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
15554#[doc = "## Safety"]
15555#[doc = " * Neon instrinsic unsafe"]
15556#[inline]
15557#[cfg(target_endian = "little")]
15558#[cfg(target_arch = "arm")]
15559#[target_feature(enable = "neon,v7")]
15560#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15561#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15562pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
15563 transmute(vld1_v4i16(
15564 ptr as *const i8,
15565 crate::mem::align_of::<p16>() as i32,
15566 ))
15567}
15568#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
15570#[doc = "## Safety"]
15571#[doc = " * Neon instrinsic unsafe"]
15572#[inline]
15573#[cfg(target_endian = "big")]
15574#[cfg(target_arch = "arm")]
15575#[target_feature(enable = "neon,v7")]
15576#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15577#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15578pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
15579 let ret_val: poly16x4_t = transmute(vld1_v4i16(
15580 ptr as *const i8,
15581 crate::mem::align_of::<p16>() as i32,
15582 ));
15583 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15584}
15585#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
15587#[doc = "## Safety"]
15588#[doc = " * Neon instrinsic unsafe"]
15589#[inline]
15590#[cfg(target_endian = "little")]
15591#[cfg(target_arch = "arm")]
15592#[target_feature(enable = "neon,v7")]
15593#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15594#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15595pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
15596 transmute(vld1q_v8i16(
15597 ptr as *const i8,
15598 crate::mem::align_of::<p16>() as i32,
15599 ))
15600}
15601#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
15603#[doc = "## Safety"]
15604#[doc = " * Neon instrinsic unsafe"]
15605#[inline]
15606#[cfg(target_endian = "big")]
15607#[cfg(target_arch = "arm")]
15608#[target_feature(enable = "neon,v7")]
15609#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15610#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15611pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
15612 let ret_val: poly16x8_t = transmute(vld1q_v8i16(
15613 ptr as *const i8,
15614 crate::mem::align_of::<p16>() as i32,
15615 ));
15616 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15617}
15618#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
15620#[doc = "## Safety"]
15621#[doc = " * Neon instrinsic unsafe"]
15622#[inline]
15623#[cfg(target_endian = "little")]
15624#[cfg(target_arch = "arm")]
15625#[target_feature(enable = "neon,aes")]
15626#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15627#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15628pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
15629 transmute(vld1q_v2i64(
15630 ptr as *const i8,
15631 crate::mem::align_of::<p64>() as i32,
15632 ))
15633}
15634#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
15636#[doc = "## Safety"]
15637#[doc = " * Neon instrinsic unsafe"]
15638#[inline]
15639#[cfg(target_endian = "big")]
15640#[cfg(target_arch = "arm")]
15641#[target_feature(enable = "neon,aes")]
15642#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15643#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15644pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
15645 let ret_val: poly64x2_t = transmute(vld1q_v2i64(
15646 ptr as *const i8,
15647 crate::mem::align_of::<p64>() as i32,
15648 ));
15649 simd_shuffle!(ret_val, ret_val, [1, 0])
15650}
15651#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"]
15653#[doc = "## Safety"]
15654#[doc = " * Neon instrinsic unsafe"]
15655#[inline]
15656#[target_feature(enable = "neon")]
15657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15659#[cfg_attr(
15660 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15661 assert_instr(ld1)
15662)]
15663#[cfg_attr(
15664 not(target_arch = "arm"),
15665 stable(feature = "neon_intrinsics", since = "1.59.0")
15666)]
15667#[cfg_attr(
15668 target_arch = "arm",
15669 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15670)]
15671pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
15672 unsafe extern "unadjusted" {
15673 #[cfg_attr(
15674 any(target_arch = "aarch64", target_arch = "arm64ec"),
15675 link_name = "llvm.aarch64.neon.ld1x2.v2f32.p0"
15676 )]
15677 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2f32.p0")]
15678 fn _vld1_f32_x2(a: *const f32) -> float32x2x2_t;
15679 }
15680 _vld1_f32_x2(a)
15681}
15682#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"]
15684#[doc = "## Safety"]
15685#[doc = " * Neon instrinsic unsafe"]
15686#[inline]
15687#[target_feature(enable = "neon")]
15688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15689#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15690#[cfg_attr(
15691 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15692 assert_instr(ld1)
15693)]
15694#[cfg_attr(
15695 not(target_arch = "arm"),
15696 stable(feature = "neon_intrinsics", since = "1.59.0")
15697)]
15698#[cfg_attr(
15699 target_arch = "arm",
15700 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15701)]
15702pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
15703 unsafe extern "unadjusted" {
15704 #[cfg_attr(
15705 any(target_arch = "aarch64", target_arch = "arm64ec"),
15706 link_name = "llvm.aarch64.neon.ld1x3.v2f32.p0"
15707 )]
15708 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2f32.p0")]
15709 fn _vld1_f32_x3(a: *const f32) -> float32x2x3_t;
15710 }
15711 _vld1_f32_x3(a)
15712}
15713#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"]
15715#[doc = "## Safety"]
15716#[doc = " * Neon instrinsic unsafe"]
15717#[inline]
15718#[target_feature(enable = "neon")]
15719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15720#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15721#[cfg_attr(
15722 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15723 assert_instr(ld1)
15724)]
15725#[cfg_attr(
15726 not(target_arch = "arm"),
15727 stable(feature = "neon_intrinsics", since = "1.59.0")
15728)]
15729#[cfg_attr(
15730 target_arch = "arm",
15731 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15732)]
15733pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
15734 unsafe extern "unadjusted" {
15735 #[cfg_attr(
15736 any(target_arch = "aarch64", target_arch = "arm64ec"),
15737 link_name = "llvm.aarch64.neon.ld1x4.v2f32.p0"
15738 )]
15739 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2f32.p0")]
15740 fn _vld1_f32_x4(a: *const f32) -> float32x2x4_t;
15741 }
15742 _vld1_f32_x4(a)
15743}
15744#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"]
15746#[doc = "## Safety"]
15747#[doc = " * Neon instrinsic unsafe"]
15748#[inline]
15749#[target_feature(enable = "neon")]
15750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15751#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15752#[cfg_attr(
15753 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15754 assert_instr(ld1)
15755)]
15756#[cfg_attr(
15757 not(target_arch = "arm"),
15758 stable(feature = "neon_intrinsics", since = "1.59.0")
15759)]
15760#[cfg_attr(
15761 target_arch = "arm",
15762 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15763)]
15764pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
15765 unsafe extern "unadjusted" {
15766 #[cfg_attr(
15767 any(target_arch = "aarch64", target_arch = "arm64ec"),
15768 link_name = "llvm.aarch64.neon.ld1x2.v4f32.p0"
15769 )]
15770 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f32.p0")]
15771 fn _vld1q_f32_x2(a: *const f32) -> float32x4x2_t;
15772 }
15773 _vld1q_f32_x2(a)
15774}
15775#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"]
15777#[doc = "## Safety"]
15778#[doc = " * Neon instrinsic unsafe"]
15779#[inline]
15780#[target_feature(enable = "neon")]
15781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15783#[cfg_attr(
15784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15785 assert_instr(ld1)
15786)]
15787#[cfg_attr(
15788 not(target_arch = "arm"),
15789 stable(feature = "neon_intrinsics", since = "1.59.0")
15790)]
15791#[cfg_attr(
15792 target_arch = "arm",
15793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15794)]
15795pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
15796 unsafe extern "unadjusted" {
15797 #[cfg_attr(
15798 any(target_arch = "aarch64", target_arch = "arm64ec"),
15799 link_name = "llvm.aarch64.neon.ld1x3.v4f32.p0"
15800 )]
15801 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f32.p0")]
15802 fn _vld1q_f32_x3(a: *const f32) -> float32x4x3_t;
15803 }
15804 _vld1q_f32_x3(a)
15805}
15806#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"]
15808#[doc = "## Safety"]
15809#[doc = " * Neon instrinsic unsafe"]
15810#[inline]
15811#[target_feature(enable = "neon")]
15812#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15813#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15814#[cfg_attr(
15815 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15816 assert_instr(ld1)
15817)]
15818#[cfg_attr(
15819 not(target_arch = "arm"),
15820 stable(feature = "neon_intrinsics", since = "1.59.0")
15821)]
15822#[cfg_attr(
15823 target_arch = "arm",
15824 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15825)]
15826pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
15827 unsafe extern "unadjusted" {
15828 #[cfg_attr(
15829 any(target_arch = "aarch64", target_arch = "arm64ec"),
15830 link_name = "llvm.aarch64.neon.ld1x4.v4f32.p0"
15831 )]
15832 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f32.p0")]
15833 fn _vld1q_f32_x4(a: *const f32) -> float32x4x4_t;
15834 }
15835 _vld1q_f32_x4(a)
15836}
15837#[doc = "Load one single-element structure to one lane of one register"]
15838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"]
15839#[doc = "## Safety"]
15840#[doc = " * Neon instrinsic unsafe"]
15841#[inline]
15842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
15844#[cfg_attr(
15845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15846 assert_instr(ld1, LANE = 0)
15847)]
15848#[rustc_legacy_const_generics(2)]
15849#[target_feature(enable = "neon,fp16")]
15850#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15851pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t) -> float16x4_t {
15852 static_assert_uimm_bits!(LANE, 2);
15853 simd_insert!(src, LANE as u32, *ptr)
15854}
15855#[doc = "Load one single-element structure to one lane of one register"]
15856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"]
15857#[doc = "## Safety"]
15858#[doc = " * Neon instrinsic unsafe"]
15859#[inline]
15860#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15861#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
15862#[cfg_attr(
15863 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15864 assert_instr(ld1, LANE = 0)
15865)]
15866#[rustc_legacy_const_generics(2)]
15867#[target_feature(enable = "neon,fp16")]
15868#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15869pub unsafe fn vld1q_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x8_t) -> float16x8_t {
15870 static_assert_uimm_bits!(LANE, 3);
15871 simd_insert!(src, LANE as u32, *ptr)
15872}
15873#[doc = "Load one single-element structure to one lane of one register."]
15874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"]
15875#[doc = "## Safety"]
15876#[doc = " * Neon instrinsic unsafe"]
15877#[inline]
15878#[target_feature(enable = "neon")]
15879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15880#[rustc_legacy_const_generics(2)]
15881#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
15882#[cfg_attr(
15883 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15884 assert_instr(ld1, LANE = 1)
15885)]
15886#[cfg_attr(
15887 not(target_arch = "arm"),
15888 stable(feature = "neon_intrinsics", since = "1.59.0")
15889)]
15890#[cfg_attr(
15891 target_arch = "arm",
15892 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15893)]
15894pub unsafe fn vld1_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x2_t) -> float32x2_t {
15895 static_assert_uimm_bits!(LANE, 1);
15896 simd_insert!(src, LANE as u32, *ptr)
15897}
15898#[doc = "Load one single-element structure to one lane of one register."]
15899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"]
15900#[doc = "## Safety"]
15901#[doc = " * Neon instrinsic unsafe"]
15902#[inline]
15903#[target_feature(enable = "neon")]
15904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15905#[rustc_legacy_const_generics(2)]
15906#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
15907#[cfg_attr(
15908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15909 assert_instr(ld1, LANE = 3)
15910)]
15911#[cfg_attr(
15912 not(target_arch = "arm"),
15913 stable(feature = "neon_intrinsics", since = "1.59.0")
15914)]
15915#[cfg_attr(
15916 target_arch = "arm",
15917 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15918)]
15919pub unsafe fn vld1_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x4_t) -> poly16x4_t {
15920 static_assert_uimm_bits!(LANE, 2);
15921 simd_insert!(src, LANE as u32, *ptr)
15922}
15923#[doc = "Load one single-element structure to one lane of one register."]
15924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"]
15925#[doc = "## Safety"]
15926#[doc = " * Neon instrinsic unsafe"]
15927#[inline]
15928#[target_feature(enable = "neon")]
15929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15930#[rustc_legacy_const_generics(2)]
15931#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
15932#[cfg_attr(
15933 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15934 assert_instr(ld1, LANE = 7)
15935)]
15936#[cfg_attr(
15937 not(target_arch = "arm"),
15938 stable(feature = "neon_intrinsics", since = "1.59.0")
15939)]
15940#[cfg_attr(
15941 target_arch = "arm",
15942 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15943)]
15944pub unsafe fn vld1_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x8_t) -> poly8x8_t {
15945 static_assert_uimm_bits!(LANE, 3);
15946 simd_insert!(src, LANE as u32, *ptr)
15947}
15948#[doc = "Load one single-element structure to one lane of one register."]
15949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"]
15950#[doc = "## Safety"]
15951#[doc = " * Neon instrinsic unsafe"]
15952#[inline]
15953#[target_feature(enable = "neon")]
15954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15955#[rustc_legacy_const_generics(2)]
15956#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
15957#[cfg_attr(
15958 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15959 assert_instr(ld1, LANE = 3)
15960)]
15961#[cfg_attr(
15962 not(target_arch = "arm"),
15963 stable(feature = "neon_intrinsics", since = "1.59.0")
15964)]
15965#[cfg_attr(
15966 target_arch = "arm",
15967 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15968)]
15969pub unsafe fn vld1_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x4_t) -> int16x4_t {
15970 static_assert_uimm_bits!(LANE, 2);
15971 simd_insert!(src, LANE as u32, *ptr)
15972}
15973#[doc = "Load one single-element structure to one lane of one register."]
15974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"]
15975#[doc = "## Safety"]
15976#[doc = " * Neon instrinsic unsafe"]
15977#[inline]
15978#[target_feature(enable = "neon")]
15979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15980#[rustc_legacy_const_generics(2)]
15981#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
15982#[cfg_attr(
15983 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15984 assert_instr(ld1, LANE = 1)
15985)]
15986#[cfg_attr(
15987 not(target_arch = "arm"),
15988 stable(feature = "neon_intrinsics", since = "1.59.0")
15989)]
15990#[cfg_attr(
15991 target_arch = "arm",
15992 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15993)]
15994pub unsafe fn vld1_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x2_t) -> int32x2_t {
15995 static_assert_uimm_bits!(LANE, 1);
15996 simd_insert!(src, LANE as u32, *ptr)
15997}
15998#[doc = "Load one single-element structure to one lane of one register."]
15999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"]
16000#[doc = "## Safety"]
16001#[doc = " * Neon instrinsic unsafe"]
16002#[inline]
16003#[target_feature(enable = "neon")]
16004#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16005#[rustc_legacy_const_generics(2)]
16006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
16007#[cfg_attr(
16008 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16009 assert_instr(ldr, LANE = 0)
16010)]
16011#[cfg_attr(
16012 not(target_arch = "arm"),
16013 stable(feature = "neon_intrinsics", since = "1.59.0")
16014)]
16015#[cfg_attr(
16016 target_arch = "arm",
16017 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16018)]
16019pub unsafe fn vld1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) -> int64x1_t {
16020 static_assert!(LANE == 0);
16021 simd_insert!(src, LANE as u32, *ptr)
16022}
16023#[doc = "Load one single-element structure to one lane of one register."]
16024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"]
16025#[doc = "## Safety"]
16026#[doc = " * Neon instrinsic unsafe"]
16027#[inline]
16028#[target_feature(enable = "neon")]
16029#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16030#[rustc_legacy_const_generics(2)]
16031#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
16032#[cfg_attr(
16033 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16034 assert_instr(ld1, LANE = 7)
16035)]
16036#[cfg_attr(
16037 not(target_arch = "arm"),
16038 stable(feature = "neon_intrinsics", since = "1.59.0")
16039)]
16040#[cfg_attr(
16041 target_arch = "arm",
16042 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16043)]
16044pub unsafe fn vld1_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x8_t) -> int8x8_t {
16045 static_assert_uimm_bits!(LANE, 3);
16046 simd_insert!(src, LANE as u32, *ptr)
16047}
16048#[doc = "Load one single-element structure to one lane of one register."]
16049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"]
16050#[doc = "## Safety"]
16051#[doc = " * Neon instrinsic unsafe"]
16052#[inline]
16053#[target_feature(enable = "neon")]
16054#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16055#[rustc_legacy_const_generics(2)]
16056#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
16057#[cfg_attr(
16058 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16059 assert_instr(ld1, LANE = 3)
16060)]
16061#[cfg_attr(
16062 not(target_arch = "arm"),
16063 stable(feature = "neon_intrinsics", since = "1.59.0")
16064)]
16065#[cfg_attr(
16066 target_arch = "arm",
16067 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16068)]
16069pub unsafe fn vld1_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x4_t) -> uint16x4_t {
16070 static_assert_uimm_bits!(LANE, 2);
16071 simd_insert!(src, LANE as u32, *ptr)
16072}
16073#[doc = "Load one single-element structure to one lane of one register."]
16074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"]
16075#[doc = "## Safety"]
16076#[doc = " * Neon instrinsic unsafe"]
16077#[inline]
16078#[target_feature(enable = "neon")]
16079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16080#[rustc_legacy_const_generics(2)]
16081#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
16082#[cfg_attr(
16083 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16084 assert_instr(ld1, LANE = 1)
16085)]
16086#[cfg_attr(
16087 not(target_arch = "arm"),
16088 stable(feature = "neon_intrinsics", since = "1.59.0")
16089)]
16090#[cfg_attr(
16091 target_arch = "arm",
16092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16093)]
16094pub unsafe fn vld1_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x2_t) -> uint32x2_t {
16095 static_assert_uimm_bits!(LANE, 1);
16096 simd_insert!(src, LANE as u32, *ptr)
16097}
16098#[doc = "Load one single-element structure to one lane of one register."]
16099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"]
16100#[doc = "## Safety"]
16101#[doc = " * Neon instrinsic unsafe"]
16102#[inline]
16103#[target_feature(enable = "neon")]
16104#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16105#[rustc_legacy_const_generics(2)]
16106#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
16107#[cfg_attr(
16108 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16109 assert_instr(ldr, LANE = 0)
16110)]
16111#[cfg_attr(
16112 not(target_arch = "arm"),
16113 stable(feature = "neon_intrinsics", since = "1.59.0")
16114)]
16115#[cfg_attr(
16116 target_arch = "arm",
16117 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16118)]
16119pub unsafe fn vld1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -> uint64x1_t {
16120 static_assert!(LANE == 0);
16121 simd_insert!(src, LANE as u32, *ptr)
16122}
16123#[doc = "Load one single-element structure to one lane of one register."]
16124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"]
16125#[doc = "## Safety"]
16126#[doc = " * Neon instrinsic unsafe"]
16127#[inline]
16128#[target_feature(enable = "neon")]
16129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16130#[rustc_legacy_const_generics(2)]
16131#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
16132#[cfg_attr(
16133 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16134 assert_instr(ld1, LANE = 7)
16135)]
16136#[cfg_attr(
16137 not(target_arch = "arm"),
16138 stable(feature = "neon_intrinsics", since = "1.59.0")
16139)]
16140#[cfg_attr(
16141 target_arch = "arm",
16142 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16143)]
16144pub unsafe fn vld1_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x8_t) -> uint8x8_t {
16145 static_assert_uimm_bits!(LANE, 3);
16146 simd_insert!(src, LANE as u32, *ptr)
16147}
16148#[doc = "Load one single-element structure to one lane of one register."]
16149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"]
16150#[doc = "## Safety"]
16151#[doc = " * Neon instrinsic unsafe"]
16152#[inline]
16153#[target_feature(enable = "neon")]
16154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16155#[rustc_legacy_const_generics(2)]
16156#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16157#[cfg_attr(
16158 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16159 assert_instr(ld1, LANE = 3)
16160)]
16161#[cfg_attr(
16162 not(target_arch = "arm"),
16163 stable(feature = "neon_intrinsics", since = "1.59.0")
16164)]
16165#[cfg_attr(
16166 target_arch = "arm",
16167 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16168)]
16169pub unsafe fn vld1q_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x4_t) -> float32x4_t {
16170 static_assert_uimm_bits!(LANE, 2);
16171 simd_insert!(src, LANE as u32, *ptr)
16172}
16173#[doc = "Load one single-element structure to one lane of one register."]
16174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"]
16175#[doc = "## Safety"]
16176#[doc = " * Neon instrinsic unsafe"]
16177#[inline]
16178#[target_feature(enable = "neon")]
16179#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16180#[rustc_legacy_const_generics(2)]
16181#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16182#[cfg_attr(
16183 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16184 assert_instr(ld1, LANE = 7)
16185)]
16186#[cfg_attr(
16187 not(target_arch = "arm"),
16188 stable(feature = "neon_intrinsics", since = "1.59.0")
16189)]
16190#[cfg_attr(
16191 target_arch = "arm",
16192 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16193)]
16194pub unsafe fn vld1q_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x8_t) -> poly16x8_t {
16195 static_assert_uimm_bits!(LANE, 3);
16196 simd_insert!(src, LANE as u32, *ptr)
16197}
16198#[doc = "Load one single-element structure to one lane of one register."]
16199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"]
16200#[doc = "## Safety"]
16201#[doc = " * Neon instrinsic unsafe"]
16202#[inline]
16203#[target_feature(enable = "neon")]
16204#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16205#[rustc_legacy_const_generics(2)]
16206#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16207#[cfg_attr(
16208 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16209 assert_instr(ld1, LANE = 15)
16210)]
16211#[cfg_attr(
16212 not(target_arch = "arm"),
16213 stable(feature = "neon_intrinsics", since = "1.59.0")
16214)]
16215#[cfg_attr(
16216 target_arch = "arm",
16217 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16218)]
16219pub unsafe fn vld1q_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x16_t) -> poly8x16_t {
16220 static_assert_uimm_bits!(LANE, 4);
16221 simd_insert!(src, LANE as u32, *ptr)
16222}
16223#[doc = "Load one single-element structure to one lane of one register."]
16224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"]
16225#[doc = "## Safety"]
16226#[doc = " * Neon instrinsic unsafe"]
16227#[inline]
16228#[target_feature(enable = "neon")]
16229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16230#[rustc_legacy_const_generics(2)]
16231#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16232#[cfg_attr(
16233 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16234 assert_instr(ld1, LANE = 7)
16235)]
16236#[cfg_attr(
16237 not(target_arch = "arm"),
16238 stable(feature = "neon_intrinsics", since = "1.59.0")
16239)]
16240#[cfg_attr(
16241 target_arch = "arm",
16242 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16243)]
16244pub unsafe fn vld1q_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x8_t) -> int16x8_t {
16245 static_assert_uimm_bits!(LANE, 3);
16246 simd_insert!(src, LANE as u32, *ptr)
16247}
16248#[doc = "Load one single-element structure to one lane of one register."]
16249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"]
16250#[doc = "## Safety"]
16251#[doc = " * Neon instrinsic unsafe"]
16252#[inline]
16253#[target_feature(enable = "neon")]
16254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16255#[rustc_legacy_const_generics(2)]
16256#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16257#[cfg_attr(
16258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16259 assert_instr(ld1, LANE = 3)
16260)]
16261#[cfg_attr(
16262 not(target_arch = "arm"),
16263 stable(feature = "neon_intrinsics", since = "1.59.0")
16264)]
16265#[cfg_attr(
16266 target_arch = "arm",
16267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16268)]
16269pub unsafe fn vld1q_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x4_t) -> int32x4_t {
16270 static_assert_uimm_bits!(LANE, 2);
16271 simd_insert!(src, LANE as u32, *ptr)
16272}
16273#[doc = "Load one single-element structure to one lane of one register."]
16274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"]
16275#[doc = "## Safety"]
16276#[doc = " * Neon instrinsic unsafe"]
16277#[inline]
16278#[target_feature(enable = "neon")]
16279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16280#[rustc_legacy_const_generics(2)]
16281#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16282#[cfg_attr(
16283 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16284 assert_instr(ld1, LANE = 1)
16285)]
16286#[cfg_attr(
16287 not(target_arch = "arm"),
16288 stable(feature = "neon_intrinsics", since = "1.59.0")
16289)]
16290#[cfg_attr(
16291 target_arch = "arm",
16292 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16293)]
16294pub unsafe fn vld1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -> int64x2_t {
16295 static_assert_uimm_bits!(LANE, 1);
16296 simd_insert!(src, LANE as u32, *ptr)
16297}
16298#[doc = "Load one single-element structure to one lane of one register."]
16299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"]
16300#[doc = "## Safety"]
16301#[doc = " * Neon instrinsic unsafe"]
16302#[inline]
16303#[target_feature(enable = "neon")]
16304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16305#[rustc_legacy_const_generics(2)]
16306#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16307#[cfg_attr(
16308 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16309 assert_instr(ld1, LANE = 15)
16310)]
16311#[cfg_attr(
16312 not(target_arch = "arm"),
16313 stable(feature = "neon_intrinsics", since = "1.59.0")
16314)]
16315#[cfg_attr(
16316 target_arch = "arm",
16317 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16318)]
16319pub unsafe fn vld1q_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x16_t) -> int8x16_t {
16320 static_assert_uimm_bits!(LANE, 4);
16321 simd_insert!(src, LANE as u32, *ptr)
16322}
16323#[doc = "Load one single-element structure to one lane of one register."]
16324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"]
16325#[doc = "## Safety"]
16326#[doc = " * Neon instrinsic unsafe"]
16327#[inline]
16328#[target_feature(enable = "neon")]
16329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16330#[rustc_legacy_const_generics(2)]
16331#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16332#[cfg_attr(
16333 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16334 assert_instr(ld1, LANE = 7)
16335)]
16336#[cfg_attr(
16337 not(target_arch = "arm"),
16338 stable(feature = "neon_intrinsics", since = "1.59.0")
16339)]
16340#[cfg_attr(
16341 target_arch = "arm",
16342 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16343)]
16344pub unsafe fn vld1q_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x8_t) -> uint16x8_t {
16345 static_assert_uimm_bits!(LANE, 3);
16346 simd_insert!(src, LANE as u32, *ptr)
16347}
16348#[doc = "Load one single-element structure to one lane of one register."]
16349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"]
16350#[doc = "## Safety"]
16351#[doc = " * Neon instrinsic unsafe"]
16352#[inline]
16353#[target_feature(enable = "neon")]
16354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16355#[rustc_legacy_const_generics(2)]
16356#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16357#[cfg_attr(
16358 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16359 assert_instr(ld1, LANE = 3)
16360)]
16361#[cfg_attr(
16362 not(target_arch = "arm"),
16363 stable(feature = "neon_intrinsics", since = "1.59.0")
16364)]
16365#[cfg_attr(
16366 target_arch = "arm",
16367 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16368)]
16369pub unsafe fn vld1q_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x4_t) -> uint32x4_t {
16370 static_assert_uimm_bits!(LANE, 2);
16371 simd_insert!(src, LANE as u32, *ptr)
16372}
16373#[doc = "Load one single-element structure to one lane of one register."]
16374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"]
16375#[doc = "## Safety"]
16376#[doc = " * Neon instrinsic unsafe"]
16377#[inline]
16378#[target_feature(enable = "neon")]
16379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16380#[rustc_legacy_const_generics(2)]
16381#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16382#[cfg_attr(
16383 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16384 assert_instr(ld1, LANE = 1)
16385)]
16386#[cfg_attr(
16387 not(target_arch = "arm"),
16388 stable(feature = "neon_intrinsics", since = "1.59.0")
16389)]
16390#[cfg_attr(
16391 target_arch = "arm",
16392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16393)]
16394pub unsafe fn vld1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t) -> uint64x2_t {
16395 static_assert_uimm_bits!(LANE, 1);
16396 simd_insert!(src, LANE as u32, *ptr)
16397}
16398#[doc = "Load one single-element structure to one lane of one register."]
16399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"]
16400#[doc = "## Safety"]
16401#[doc = " * Neon instrinsic unsafe"]
16402#[inline]
16403#[target_feature(enable = "neon")]
16404#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16405#[rustc_legacy_const_generics(2)]
16406#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16407#[cfg_attr(
16408 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16409 assert_instr(ld1, LANE = 15)
16410)]
16411#[cfg_attr(
16412 not(target_arch = "arm"),
16413 stable(feature = "neon_intrinsics", since = "1.59.0")
16414)]
16415#[cfg_attr(
16416 target_arch = "arm",
16417 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16418)]
16419pub unsafe fn vld1q_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x16_t) -> uint8x16_t {
16420 static_assert_uimm_bits!(LANE, 4);
16421 simd_insert!(src, LANE as u32, *ptr)
16422}
16423#[doc = "Load one single-element structure to one lane of one register."]
16424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"]
16425#[doc = "## Safety"]
16426#[doc = " * Neon instrinsic unsafe"]
16427#[inline]
16428#[target_feature(enable = "neon,aes")]
16429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16430#[rustc_legacy_const_generics(2)]
16431#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
16432#[cfg_attr(
16433 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16434 assert_instr(ldr, LANE = 0)
16435)]
16436#[cfg_attr(
16437 not(target_arch = "arm"),
16438 stable(feature = "neon_intrinsics", since = "1.59.0")
16439)]
16440#[cfg_attr(
16441 target_arch = "arm",
16442 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16443)]
16444pub unsafe fn vld1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -> poly64x1_t {
16445 static_assert!(LANE == 0);
16446 simd_insert!(src, LANE as u32, *ptr)
16447}
16448#[doc = "Load one single-element structure to one lane of one register."]
16449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"]
16450#[doc = "## Safety"]
16451#[doc = " * Neon instrinsic unsafe"]
16452#[inline]
16453#[target_feature(enable = "neon,aes")]
16454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16455#[rustc_legacy_const_generics(2)]
16456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16457#[cfg_attr(
16458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16459 assert_instr(ld1, LANE = 1)
16460)]
16461#[cfg_attr(
16462 not(target_arch = "arm"),
16463 stable(feature = "neon_intrinsics", since = "1.59.0")
16464)]
16465#[cfg_attr(
16466 target_arch = "arm",
16467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16468)]
16469pub unsafe fn vld1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t) -> poly64x2_t {
16470 static_assert_uimm_bits!(LANE, 1);
16471 simd_insert!(src, LANE as u32, *ptr)
16472}
16473#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
16475#[doc = "## Safety"]
16476#[doc = " * Neon instrinsic unsafe"]
16477#[inline]
16478#[cfg(target_arch = "arm")]
16479#[target_feature(enable = "neon,aes")]
16480#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16482pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
16483 let a: *const i8 = ptr as *const i8;
16484 let b: i32 = crate::mem::align_of::<p64>() as i32;
16485 unsafe extern "unadjusted" {
16486 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")]
16487 fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t;
16488 }
16489 transmute(_vld1_v1i64(a, b))
16490}
16491#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"]
16493#[doc = "## Safety"]
16494#[doc = " * Neon instrinsic unsafe"]
16495#[inline]
16496#[target_feature(enable = "neon,aes")]
16497#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16498#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16499#[cfg_attr(
16500 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16501 assert_instr(ld1)
16502)]
16503#[cfg_attr(
16504 not(target_arch = "arm"),
16505 stable(feature = "neon_intrinsics", since = "1.59.0")
16506)]
16507#[cfg_attr(
16508 target_arch = "arm",
16509 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16510)]
16511pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
16512 transmute(vld1_s64_x2(transmute(a)))
16513}
16514#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"]
16516#[doc = "## Safety"]
16517#[doc = " * Neon instrinsic unsafe"]
16518#[inline]
16519#[target_feature(enable = "neon,aes")]
16520#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16521#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16522#[cfg_attr(
16523 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16524 assert_instr(ld1)
16525)]
16526#[cfg_attr(
16527 not(target_arch = "arm"),
16528 stable(feature = "neon_intrinsics", since = "1.59.0")
16529)]
16530#[cfg_attr(
16531 target_arch = "arm",
16532 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16533)]
16534pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
16535 transmute(vld1_s64_x3(transmute(a)))
16536}
16537#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"]
16539#[doc = "## Safety"]
16540#[doc = " * Neon instrinsic unsafe"]
16541#[inline]
16542#[target_feature(enable = "neon,aes")]
16543#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16544#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16545#[cfg_attr(
16546 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16547 assert_instr(ld1)
16548)]
16549#[cfg_attr(
16550 not(target_arch = "arm"),
16551 stable(feature = "neon_intrinsics", since = "1.59.0")
16552)]
16553#[cfg_attr(
16554 target_arch = "arm",
16555 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16556)]
16557pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
16558 transmute(vld1_s64_x4(transmute(a)))
16559}
16560#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16561#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
16562#[doc = "## Safety"]
16563#[doc = " * Neon instrinsic unsafe"]
16564#[inline]
16565#[cfg(target_endian = "little")]
16566#[target_feature(enable = "neon,aes")]
16567#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16568#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16569#[cfg_attr(
16570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16571 assert_instr(ld1)
16572)]
16573#[cfg_attr(
16574 not(target_arch = "arm"),
16575 stable(feature = "neon_intrinsics", since = "1.59.0")
16576)]
16577#[cfg_attr(
16578 target_arch = "arm",
16579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16580)]
16581pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
16582 transmute(vld1q_s64_x2(transmute(a)))
16583}
16584#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
16586#[doc = "## Safety"]
16587#[doc = " * Neon instrinsic unsafe"]
16588#[inline]
16589#[cfg(target_endian = "big")]
16590#[target_feature(enable = "neon,aes")]
16591#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16592#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16593#[cfg_attr(
16594 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16595 assert_instr(ld1)
16596)]
16597#[cfg_attr(
16598 not(target_arch = "arm"),
16599 stable(feature = "neon_intrinsics", since = "1.59.0")
16600)]
16601#[cfg_attr(
16602 target_arch = "arm",
16603 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16604)]
16605pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
16606 let mut ret_val: poly64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
16607 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16608 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16609 ret_val
16610}
16611#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
16613#[doc = "## Safety"]
16614#[doc = " * Neon instrinsic unsafe"]
16615#[inline]
16616#[cfg(target_endian = "little")]
16617#[target_feature(enable = "neon,aes")]
16618#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16619#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16620#[cfg_attr(
16621 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16622 assert_instr(ld1)
16623)]
16624#[cfg_attr(
16625 not(target_arch = "arm"),
16626 stable(feature = "neon_intrinsics", since = "1.59.0")
16627)]
16628#[cfg_attr(
16629 target_arch = "arm",
16630 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16631)]
16632pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
16633 transmute(vld1q_s64_x3(transmute(a)))
16634}
16635#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
16637#[doc = "## Safety"]
16638#[doc = " * Neon instrinsic unsafe"]
16639#[inline]
16640#[cfg(target_endian = "big")]
16641#[target_feature(enable = "neon,aes")]
16642#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16643#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16644#[cfg_attr(
16645 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16646 assert_instr(ld1)
16647)]
16648#[cfg_attr(
16649 not(target_arch = "arm"),
16650 stable(feature = "neon_intrinsics", since = "1.59.0")
16651)]
16652#[cfg_attr(
16653 target_arch = "arm",
16654 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16655)]
16656pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
16657 let mut ret_val: poly64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
16658 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16659 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16660 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
16661 ret_val
16662}
16663#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
16665#[doc = "## Safety"]
16666#[doc = " * Neon instrinsic unsafe"]
16667#[inline]
16668#[cfg(target_endian = "little")]
16669#[target_feature(enable = "neon,aes")]
16670#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16671#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16672#[cfg_attr(
16673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16674 assert_instr(ld1)
16675)]
16676#[cfg_attr(
16677 not(target_arch = "arm"),
16678 stable(feature = "neon_intrinsics", since = "1.59.0")
16679)]
16680#[cfg_attr(
16681 target_arch = "arm",
16682 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16683)]
16684pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
16685 transmute(vld1q_s64_x4(transmute(a)))
16686}
16687#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
16689#[doc = "## Safety"]
16690#[doc = " * Neon instrinsic unsafe"]
16691#[inline]
16692#[cfg(target_endian = "big")]
16693#[target_feature(enable = "neon,aes")]
16694#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16695#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16696#[cfg_attr(
16697 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16698 assert_instr(ld1)
16699)]
16700#[cfg_attr(
16701 not(target_arch = "arm"),
16702 stable(feature = "neon_intrinsics", since = "1.59.0")
16703)]
16704#[cfg_attr(
16705 target_arch = "arm",
16706 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16707)]
16708pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
16709 let mut ret_val: poly64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
16710 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16711 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16712 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
16713 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
16714 ret_val
16715}
16716#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
16718#[doc = "## Safety"]
16719#[doc = " * Neon instrinsic unsafe"]
16720#[inline]
16721#[cfg(target_arch = "arm")]
16722#[target_feature(enable = "neon,v7")]
16723#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16724#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
16725pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
16726 vld1_v8i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
16727}
16728#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
16730#[doc = "## Safety"]
16731#[doc = " * Neon instrinsic unsafe"]
16732#[inline]
16733#[cfg(target_arch = "arm")]
16734#[target_feature(enable = "neon,v7")]
16735#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16736#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
16737pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
16738 vld1q_v16i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
16739}
16740#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
16742#[doc = "## Safety"]
16743#[doc = " * Neon instrinsic unsafe"]
16744#[inline]
16745#[cfg(target_arch = "arm")]
16746#[target_feature(enable = "neon,v7")]
16747#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16748#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
16749pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
16750 vld1_v4i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
16751}
16752#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
16754#[doc = "## Safety"]
16755#[doc = " * Neon instrinsic unsafe"]
16756#[inline]
16757#[cfg(target_arch = "arm")]
16758#[target_feature(enable = "neon,v7")]
16759#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16760#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
16761pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
16762 vld1q_v8i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
16763}
16764#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
16766#[doc = "## Safety"]
16767#[doc = " * Neon instrinsic unsafe"]
16768#[inline]
16769#[cfg(target_arch = "arm")]
16770#[target_feature(enable = "neon,v7")]
16771#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16772#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16773pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
16774 vld1_v2i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
16775}
16776#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
16778#[doc = "## Safety"]
16779#[doc = " * Neon instrinsic unsafe"]
16780#[inline]
16781#[cfg(target_arch = "arm")]
16782#[target_feature(enable = "neon,v7")]
16783#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16784#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
16785pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
16786 vld1q_v4i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
16787}
16788#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
16790#[doc = "## Safety"]
16791#[doc = " * Neon instrinsic unsafe"]
16792#[inline]
16793#[cfg(target_arch = "arm")]
16794#[target_feature(enable = "neon,v7")]
16795#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16796#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16797pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
16798 vld1_v1i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
16799}
16800#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
16802#[doc = "## Safety"]
16803#[doc = " * Neon instrinsic unsafe"]
16804#[inline]
16805#[cfg(target_arch = "arm")]
16806#[target_feature(enable = "neon,v7")]
16807#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16808#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
16809pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
16810 vld1q_v2i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
16811}
16812#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"]
16814#[doc = "## Safety"]
16815#[doc = " * Neon instrinsic unsafe"]
16816#[inline]
16817#[target_feature(enable = "neon")]
16818#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16819#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16820#[cfg_attr(
16821 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16822 assert_instr(ld1)
16823)]
16824#[cfg_attr(
16825 not(target_arch = "arm"),
16826 stable(feature = "neon_intrinsics", since = "1.59.0")
16827)]
16828#[cfg_attr(
16829 target_arch = "arm",
16830 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16831)]
16832pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
16833 unsafe extern "unadjusted" {
16834 #[cfg_attr(
16835 any(target_arch = "aarch64", target_arch = "arm64ec"),
16836 link_name = "llvm.aarch64.neon.ld1x2.v8i8.p0"
16837 )]
16838 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i8.p0")]
16839 fn _vld1_s8_x2(a: *const i8) -> int8x8x2_t;
16840 }
16841 _vld1_s8_x2(a)
16842}
16843#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"]
16845#[doc = "## Safety"]
16846#[doc = " * Neon instrinsic unsafe"]
16847#[inline]
16848#[target_feature(enable = "neon")]
16849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16850#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16851#[cfg_attr(
16852 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16853 assert_instr(ld1)
16854)]
16855#[cfg_attr(
16856 not(target_arch = "arm"),
16857 stable(feature = "neon_intrinsics", since = "1.59.0")
16858)]
16859#[cfg_attr(
16860 target_arch = "arm",
16861 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16862)]
16863pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
16864 unsafe extern "unadjusted" {
16865 #[cfg_attr(
16866 any(target_arch = "aarch64", target_arch = "arm64ec"),
16867 link_name = "llvm.aarch64.neon.ld1x3.v8i8.p0"
16868 )]
16869 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i8.p0")]
16870 fn _vld1_s8_x3(a: *const i8) -> int8x8x3_t;
16871 }
16872 _vld1_s8_x3(a)
16873}
16874#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"]
16876#[doc = "## Safety"]
16877#[doc = " * Neon instrinsic unsafe"]
16878#[inline]
16879#[target_feature(enable = "neon")]
16880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16882#[cfg_attr(
16883 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16884 assert_instr(ld1)
16885)]
16886#[cfg_attr(
16887 not(target_arch = "arm"),
16888 stable(feature = "neon_intrinsics", since = "1.59.0")
16889)]
16890#[cfg_attr(
16891 target_arch = "arm",
16892 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16893)]
16894pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
16895 unsafe extern "unadjusted" {
16896 #[cfg_attr(
16897 any(target_arch = "aarch64", target_arch = "arm64ec"),
16898 link_name = "llvm.aarch64.neon.ld1x4.v8i8.p0"
16899 )]
16900 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i8.p0")]
16901 fn _vld1_s8_x4(a: *const i8) -> int8x8x4_t;
16902 }
16903 _vld1_s8_x4(a)
16904}
16905#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"]
16907#[doc = "## Safety"]
16908#[doc = " * Neon instrinsic unsafe"]
16909#[inline]
16910#[target_feature(enable = "neon")]
16911#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16912#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16913#[cfg_attr(
16914 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16915 assert_instr(ld1)
16916)]
16917#[cfg_attr(
16918 not(target_arch = "arm"),
16919 stable(feature = "neon_intrinsics", since = "1.59.0")
16920)]
16921#[cfg_attr(
16922 target_arch = "arm",
16923 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16924)]
16925pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
16926 unsafe extern "unadjusted" {
16927 #[cfg_attr(
16928 any(target_arch = "aarch64", target_arch = "arm64ec"),
16929 link_name = "llvm.aarch64.neon.ld1x2.v16i8.p0"
16930 )]
16931 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v16i8.p0")]
16932 fn _vld1q_s8_x2(a: *const i8) -> int8x16x2_t;
16933 }
16934 _vld1q_s8_x2(a)
16935}
16936#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"]
16938#[doc = "## Safety"]
16939#[doc = " * Neon instrinsic unsafe"]
16940#[inline]
16941#[target_feature(enable = "neon")]
16942#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16943#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16944#[cfg_attr(
16945 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16946 assert_instr(ld1)
16947)]
16948#[cfg_attr(
16949 not(target_arch = "arm"),
16950 stable(feature = "neon_intrinsics", since = "1.59.0")
16951)]
16952#[cfg_attr(
16953 target_arch = "arm",
16954 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16955)]
16956pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
16957 unsafe extern "unadjusted" {
16958 #[cfg_attr(
16959 any(target_arch = "aarch64", target_arch = "arm64ec"),
16960 link_name = "llvm.aarch64.neon.ld1x3.v16i8.p0"
16961 )]
16962 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v16i8.p0")]
16963 fn _vld1q_s8_x3(a: *const i8) -> int8x16x3_t;
16964 }
16965 _vld1q_s8_x3(a)
16966}
16967#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"]
16969#[doc = "## Safety"]
16970#[doc = " * Neon instrinsic unsafe"]
16971#[inline]
16972#[target_feature(enable = "neon")]
16973#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16974#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16975#[cfg_attr(
16976 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16977 assert_instr(ld1)
16978)]
16979#[cfg_attr(
16980 not(target_arch = "arm"),
16981 stable(feature = "neon_intrinsics", since = "1.59.0")
16982)]
16983#[cfg_attr(
16984 target_arch = "arm",
16985 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16986)]
16987pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
16988 unsafe extern "unadjusted" {
16989 #[cfg_attr(
16990 any(target_arch = "aarch64", target_arch = "arm64ec"),
16991 link_name = "llvm.aarch64.neon.ld1x4.v16i8.p0"
16992 )]
16993 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v16i8.p0")]
16994 fn _vld1q_s8_x4(a: *const i8) -> int8x16x4_t;
16995 }
16996 _vld1q_s8_x4(a)
16997}
16998#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"]
17000#[doc = "## Safety"]
17001#[doc = " * Neon instrinsic unsafe"]
17002#[inline]
17003#[target_feature(enable = "neon")]
17004#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17005#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17006#[cfg_attr(
17007 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17008 assert_instr(ld1)
17009)]
17010#[cfg_attr(
17011 not(target_arch = "arm"),
17012 stable(feature = "neon_intrinsics", since = "1.59.0")
17013)]
17014#[cfg_attr(
17015 target_arch = "arm",
17016 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17017)]
17018pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
17019 unsafe extern "unadjusted" {
17020 #[cfg_attr(
17021 any(target_arch = "aarch64", target_arch = "arm64ec"),
17022 link_name = "llvm.aarch64.neon.ld1x2.v4i16.p0"
17023 )]
17024 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i16.p0")]
17025 fn _vld1_s16_x2(a: *const i16) -> int16x4x2_t;
17026 }
17027 _vld1_s16_x2(a)
17028}
17029#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"]
17031#[doc = "## Safety"]
17032#[doc = " * Neon instrinsic unsafe"]
17033#[inline]
17034#[target_feature(enable = "neon")]
17035#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17036#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17037#[cfg_attr(
17038 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17039 assert_instr(ld1)
17040)]
17041#[cfg_attr(
17042 not(target_arch = "arm"),
17043 stable(feature = "neon_intrinsics", since = "1.59.0")
17044)]
17045#[cfg_attr(
17046 target_arch = "arm",
17047 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17048)]
17049pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
17050 unsafe extern "unadjusted" {
17051 #[cfg_attr(
17052 any(target_arch = "aarch64", target_arch = "arm64ec"),
17053 link_name = "llvm.aarch64.neon.ld1x3.v4i16.p0"
17054 )]
17055 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i16.p0")]
17056 fn _vld1_s16_x3(a: *const i16) -> int16x4x3_t;
17057 }
17058 _vld1_s16_x3(a)
17059}
17060#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"]
17062#[doc = "## Safety"]
17063#[doc = " * Neon instrinsic unsafe"]
17064#[inline]
17065#[target_feature(enable = "neon")]
17066#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17067#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17068#[cfg_attr(
17069 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17070 assert_instr(ld1)
17071)]
17072#[cfg_attr(
17073 not(target_arch = "arm"),
17074 stable(feature = "neon_intrinsics", since = "1.59.0")
17075)]
17076#[cfg_attr(
17077 target_arch = "arm",
17078 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17079)]
17080pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
17081 unsafe extern "unadjusted" {
17082 #[cfg_attr(
17083 any(target_arch = "aarch64", target_arch = "arm64ec"),
17084 link_name = "llvm.aarch64.neon.ld1x4.v4i16.p0"
17085 )]
17086 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i16.p0")]
17087 fn _vld1_s16_x4(a: *const i16) -> int16x4x4_t;
17088 }
17089 _vld1_s16_x4(a)
17090}
17091#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"]
17093#[doc = "## Safety"]
17094#[doc = " * Neon instrinsic unsafe"]
17095#[inline]
17096#[target_feature(enable = "neon")]
17097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17099#[cfg_attr(
17100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17101 assert_instr(ld1)
17102)]
17103#[cfg_attr(
17104 not(target_arch = "arm"),
17105 stable(feature = "neon_intrinsics", since = "1.59.0")
17106)]
17107#[cfg_attr(
17108 target_arch = "arm",
17109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17110)]
17111pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
17112 unsafe extern "unadjusted" {
17113 #[cfg_attr(
17114 any(target_arch = "aarch64", target_arch = "arm64ec"),
17115 link_name = "llvm.aarch64.neon.ld1x2.v8i16.p0"
17116 )]
17117 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i16.p0")]
17118 fn _vld1q_s16_x2(a: *const i16) -> int16x8x2_t;
17119 }
17120 _vld1q_s16_x2(a)
17121}
17122#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"]
17124#[doc = "## Safety"]
17125#[doc = " * Neon instrinsic unsafe"]
17126#[inline]
17127#[target_feature(enable = "neon")]
17128#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17129#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17130#[cfg_attr(
17131 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17132 assert_instr(ld1)
17133)]
17134#[cfg_attr(
17135 not(target_arch = "arm"),
17136 stable(feature = "neon_intrinsics", since = "1.59.0")
17137)]
17138#[cfg_attr(
17139 target_arch = "arm",
17140 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17141)]
17142pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
17143 unsafe extern "unadjusted" {
17144 #[cfg_attr(
17145 any(target_arch = "aarch64", target_arch = "arm64ec"),
17146 link_name = "llvm.aarch64.neon.ld1x3.v8i16.p0"
17147 )]
17148 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i16.p0")]
17149 fn _vld1q_s16_x3(a: *const i16) -> int16x8x3_t;
17150 }
17151 _vld1q_s16_x3(a)
17152}
17153#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"]
17155#[doc = "## Safety"]
17156#[doc = " * Neon instrinsic unsafe"]
17157#[inline]
17158#[target_feature(enable = "neon")]
17159#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17160#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17161#[cfg_attr(
17162 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17163 assert_instr(ld1)
17164)]
17165#[cfg_attr(
17166 not(target_arch = "arm"),
17167 stable(feature = "neon_intrinsics", since = "1.59.0")
17168)]
17169#[cfg_attr(
17170 target_arch = "arm",
17171 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17172)]
17173pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
17174 unsafe extern "unadjusted" {
17175 #[cfg_attr(
17176 any(target_arch = "aarch64", target_arch = "arm64ec"),
17177 link_name = "llvm.aarch64.neon.ld1x4.v8i16.p0"
17178 )]
17179 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i16.p0")]
17180 fn _vld1q_s16_x4(a: *const i16) -> int16x8x4_t;
17181 }
17182 _vld1q_s16_x4(a)
17183}
17184#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"]
17186#[doc = "## Safety"]
17187#[doc = " * Neon instrinsic unsafe"]
17188#[inline]
17189#[target_feature(enable = "neon")]
17190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17191#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17192#[cfg_attr(
17193 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17194 assert_instr(ld1)
17195)]
17196#[cfg_attr(
17197 not(target_arch = "arm"),
17198 stable(feature = "neon_intrinsics", since = "1.59.0")
17199)]
17200#[cfg_attr(
17201 target_arch = "arm",
17202 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17203)]
17204pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
17205 unsafe extern "unadjusted" {
17206 #[cfg_attr(
17207 any(target_arch = "aarch64", target_arch = "arm64ec"),
17208 link_name = "llvm.aarch64.neon.ld1x2.v2i32.p0"
17209 )]
17210 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i32.p0")]
17211 fn _vld1_s32_x2(a: *const i32) -> int32x2x2_t;
17212 }
17213 _vld1_s32_x2(a)
17214}
17215#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"]
17217#[doc = "## Safety"]
17218#[doc = " * Neon instrinsic unsafe"]
17219#[inline]
17220#[target_feature(enable = "neon")]
17221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17223#[cfg_attr(
17224 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17225 assert_instr(ld1)
17226)]
17227#[cfg_attr(
17228 not(target_arch = "arm"),
17229 stable(feature = "neon_intrinsics", since = "1.59.0")
17230)]
17231#[cfg_attr(
17232 target_arch = "arm",
17233 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17234)]
17235pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
17236 unsafe extern "unadjusted" {
17237 #[cfg_attr(
17238 any(target_arch = "aarch64", target_arch = "arm64ec"),
17239 link_name = "llvm.aarch64.neon.ld1x3.v2i32.p0"
17240 )]
17241 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i32.p0")]
17242 fn _vld1_s32_x3(a: *const i32) -> int32x2x3_t;
17243 }
17244 _vld1_s32_x3(a)
17245}
17246#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"]
17248#[doc = "## Safety"]
17249#[doc = " * Neon instrinsic unsafe"]
17250#[inline]
17251#[target_feature(enable = "neon")]
17252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17254#[cfg_attr(
17255 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17256 assert_instr(ld1)
17257)]
17258#[cfg_attr(
17259 not(target_arch = "arm"),
17260 stable(feature = "neon_intrinsics", since = "1.59.0")
17261)]
17262#[cfg_attr(
17263 target_arch = "arm",
17264 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17265)]
17266pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
17267 unsafe extern "unadjusted" {
17268 #[cfg_attr(
17269 any(target_arch = "aarch64", target_arch = "arm64ec"),
17270 link_name = "llvm.aarch64.neon.ld1x4.v2i32.p0"
17271 )]
17272 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i32.p0")]
17273 fn _vld1_s32_x4(a: *const i32) -> int32x2x4_t;
17274 }
17275 _vld1_s32_x4(a)
17276}
17277#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"]
17279#[doc = "## Safety"]
17280#[doc = " * Neon instrinsic unsafe"]
17281#[inline]
17282#[target_feature(enable = "neon")]
17283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17285#[cfg_attr(
17286 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17287 assert_instr(ld1)
17288)]
17289#[cfg_attr(
17290 not(target_arch = "arm"),
17291 stable(feature = "neon_intrinsics", since = "1.59.0")
17292)]
17293#[cfg_attr(
17294 target_arch = "arm",
17295 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17296)]
17297pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
17298 unsafe extern "unadjusted" {
17299 #[cfg_attr(
17300 any(target_arch = "aarch64", target_arch = "arm64ec"),
17301 link_name = "llvm.aarch64.neon.ld1x2.v4i32.p0"
17302 )]
17303 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i32.p0")]
17304 fn _vld1q_s32_x2(a: *const i32) -> int32x4x2_t;
17305 }
17306 _vld1q_s32_x2(a)
17307}
17308#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"]
17310#[doc = "## Safety"]
17311#[doc = " * Neon instrinsic unsafe"]
17312#[inline]
17313#[target_feature(enable = "neon")]
17314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17315#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17316#[cfg_attr(
17317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17318 assert_instr(ld1)
17319)]
17320#[cfg_attr(
17321 not(target_arch = "arm"),
17322 stable(feature = "neon_intrinsics", since = "1.59.0")
17323)]
17324#[cfg_attr(
17325 target_arch = "arm",
17326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17327)]
17328pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
17329 unsafe extern "unadjusted" {
17330 #[cfg_attr(
17331 any(target_arch = "aarch64", target_arch = "arm64ec"),
17332 link_name = "llvm.aarch64.neon.ld1x3.v4i32.p0"
17333 )]
17334 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i32.p0")]
17335 fn _vld1q_s32_x3(a: *const i32) -> int32x4x3_t;
17336 }
17337 _vld1q_s32_x3(a)
17338}
17339#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"]
17341#[doc = "## Safety"]
17342#[doc = " * Neon instrinsic unsafe"]
17343#[inline]
17344#[target_feature(enable = "neon")]
17345#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17347#[cfg_attr(
17348 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17349 assert_instr(ld1)
17350)]
17351#[cfg_attr(
17352 not(target_arch = "arm"),
17353 stable(feature = "neon_intrinsics", since = "1.59.0")
17354)]
17355#[cfg_attr(
17356 target_arch = "arm",
17357 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17358)]
17359pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
17360 unsafe extern "unadjusted" {
17361 #[cfg_attr(
17362 any(target_arch = "aarch64", target_arch = "arm64ec"),
17363 link_name = "llvm.aarch64.neon.ld1x4.v4i32.p0"
17364 )]
17365 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i32.p0")]
17366 fn _vld1q_s32_x4(a: *const i32) -> int32x4x4_t;
17367 }
17368 _vld1q_s32_x4(a)
17369}
17370#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"]
17372#[doc = "## Safety"]
17373#[doc = " * Neon instrinsic unsafe"]
17374#[inline]
17375#[target_feature(enable = "neon")]
17376#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17377#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17378#[cfg_attr(
17379 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17380 assert_instr(ld1)
17381)]
17382#[cfg_attr(
17383 not(target_arch = "arm"),
17384 stable(feature = "neon_intrinsics", since = "1.59.0")
17385)]
17386#[cfg_attr(
17387 target_arch = "arm",
17388 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17389)]
17390pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
17391 unsafe extern "unadjusted" {
17392 #[cfg_attr(
17393 any(target_arch = "aarch64", target_arch = "arm64ec"),
17394 link_name = "llvm.aarch64.neon.ld1x2.v1i64.p0"
17395 )]
17396 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v1i64.p0")]
17397 fn _vld1_s64_x2(a: *const i64) -> int64x1x2_t;
17398 }
17399 _vld1_s64_x2(a)
17400}
17401#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"]
17403#[doc = "## Safety"]
17404#[doc = " * Neon instrinsic unsafe"]
17405#[inline]
17406#[target_feature(enable = "neon")]
17407#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17408#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17409#[cfg_attr(
17410 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17411 assert_instr(ld1)
17412)]
17413#[cfg_attr(
17414 not(target_arch = "arm"),
17415 stable(feature = "neon_intrinsics", since = "1.59.0")
17416)]
17417#[cfg_attr(
17418 target_arch = "arm",
17419 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17420)]
17421pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
17422 unsafe extern "unadjusted" {
17423 #[cfg_attr(
17424 any(target_arch = "aarch64", target_arch = "arm64ec"),
17425 link_name = "llvm.aarch64.neon.ld1x3.v1i64.p0"
17426 )]
17427 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v1i64.p0")]
17428 fn _vld1_s64_x3(a: *const i64) -> int64x1x3_t;
17429 }
17430 _vld1_s64_x3(a)
17431}
17432#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"]
17434#[doc = "## Safety"]
17435#[doc = " * Neon instrinsic unsafe"]
17436#[inline]
17437#[target_feature(enable = "neon")]
17438#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17439#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17440#[cfg_attr(
17441 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17442 assert_instr(ld1)
17443)]
17444#[cfg_attr(
17445 not(target_arch = "arm"),
17446 stable(feature = "neon_intrinsics", since = "1.59.0")
17447)]
17448#[cfg_attr(
17449 target_arch = "arm",
17450 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17451)]
17452pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
17453 unsafe extern "unadjusted" {
17454 #[cfg_attr(
17455 any(target_arch = "aarch64", target_arch = "arm64ec"),
17456 link_name = "llvm.aarch64.neon.ld1x4.v1i64.p0"
17457 )]
17458 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v1i64.p0")]
17459 fn _vld1_s64_x4(a: *const i64) -> int64x1x4_t;
17460 }
17461 _vld1_s64_x4(a)
17462}
17463#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"]
17465#[doc = "## Safety"]
17466#[doc = " * Neon instrinsic unsafe"]
17467#[inline]
17468#[target_feature(enable = "neon")]
17469#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17470#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17471#[cfg_attr(
17472 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17473 assert_instr(ld1)
17474)]
17475#[cfg_attr(
17476 not(target_arch = "arm"),
17477 stable(feature = "neon_intrinsics", since = "1.59.0")
17478)]
17479#[cfg_attr(
17480 target_arch = "arm",
17481 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17482)]
17483pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
17484 unsafe extern "unadjusted" {
17485 #[cfg_attr(
17486 any(target_arch = "aarch64", target_arch = "arm64ec"),
17487 link_name = "llvm.aarch64.neon.ld1x2.v2i64.p0"
17488 )]
17489 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i64.p0")]
17490 fn _vld1q_s64_x2(a: *const i64) -> int64x2x2_t;
17491 }
17492 _vld1q_s64_x2(a)
17493}
17494#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"]
17496#[doc = "## Safety"]
17497#[doc = " * Neon instrinsic unsafe"]
17498#[inline]
17499#[target_feature(enable = "neon")]
17500#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17501#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17502#[cfg_attr(
17503 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17504 assert_instr(ld1)
17505)]
17506#[cfg_attr(
17507 not(target_arch = "arm"),
17508 stable(feature = "neon_intrinsics", since = "1.59.0")
17509)]
17510#[cfg_attr(
17511 target_arch = "arm",
17512 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17513)]
17514pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
17515 unsafe extern "unadjusted" {
17516 #[cfg_attr(
17517 any(target_arch = "aarch64", target_arch = "arm64ec"),
17518 link_name = "llvm.aarch64.neon.ld1x3.v2i64.p0"
17519 )]
17520 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i64.p0")]
17521 fn _vld1q_s64_x3(a: *const i64) -> int64x2x3_t;
17522 }
17523 _vld1q_s64_x3(a)
17524}
17525#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"]
17527#[doc = "## Safety"]
17528#[doc = " * Neon instrinsic unsafe"]
17529#[inline]
17530#[target_feature(enable = "neon")]
17531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17533#[cfg_attr(
17534 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17535 assert_instr(ld1)
17536)]
17537#[cfg_attr(
17538 not(target_arch = "arm"),
17539 stable(feature = "neon_intrinsics", since = "1.59.0")
17540)]
17541#[cfg_attr(
17542 target_arch = "arm",
17543 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17544)]
17545pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
17546 unsafe extern "unadjusted" {
17547 #[cfg_attr(
17548 any(target_arch = "aarch64", target_arch = "arm64ec"),
17549 link_name = "llvm.aarch64.neon.ld1x4.v2i64.p0"
17550 )]
17551 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i64.p0")]
17552 fn _vld1q_s64_x4(a: *const i64) -> int64x2x4_t;
17553 }
17554 _vld1q_s64_x4(a)
17555}
17556#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
17558#[doc = "## Safety"]
17559#[doc = " * Neon instrinsic unsafe"]
17560#[inline]
17561#[cfg(target_endian = "little")]
17562#[target_feature(enable = "neon")]
17563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17564#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17565#[cfg_attr(
17566 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17567 assert_instr(ld1)
17568)]
17569#[cfg_attr(
17570 not(target_arch = "arm"),
17571 stable(feature = "neon_intrinsics", since = "1.59.0")
17572)]
17573#[cfg_attr(
17574 target_arch = "arm",
17575 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17576)]
17577pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
17578 transmute(vld1_s8_x2(transmute(a)))
17579}
17580#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
17582#[doc = "## Safety"]
17583#[doc = " * Neon instrinsic unsafe"]
17584#[inline]
17585#[cfg(target_endian = "big")]
17586#[target_feature(enable = "neon")]
17587#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17588#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17589#[cfg_attr(
17590 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17591 assert_instr(ld1)
17592)]
17593#[cfg_attr(
17594 not(target_arch = "arm"),
17595 stable(feature = "neon_intrinsics", since = "1.59.0")
17596)]
17597#[cfg_attr(
17598 target_arch = "arm",
17599 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17600)]
17601pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
17602 let mut ret_val: uint8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
17603 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17604 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17605 ret_val
17606}
17607#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
17609#[doc = "## Safety"]
17610#[doc = " * Neon instrinsic unsafe"]
17611#[inline]
17612#[cfg(target_endian = "little")]
17613#[target_feature(enable = "neon")]
17614#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17615#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17616#[cfg_attr(
17617 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17618 assert_instr(ld1)
17619)]
17620#[cfg_attr(
17621 not(target_arch = "arm"),
17622 stable(feature = "neon_intrinsics", since = "1.59.0")
17623)]
17624#[cfg_attr(
17625 target_arch = "arm",
17626 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17627)]
17628pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
17629 transmute(vld1_s8_x3(transmute(a)))
17630}
17631#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
17633#[doc = "## Safety"]
17634#[doc = " * Neon instrinsic unsafe"]
17635#[inline]
17636#[cfg(target_endian = "big")]
17637#[target_feature(enable = "neon")]
17638#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17639#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17640#[cfg_attr(
17641 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17642 assert_instr(ld1)
17643)]
17644#[cfg_attr(
17645 not(target_arch = "arm"),
17646 stable(feature = "neon_intrinsics", since = "1.59.0")
17647)]
17648#[cfg_attr(
17649 target_arch = "arm",
17650 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17651)]
17652pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
17653 let mut ret_val: uint8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
17654 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17655 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17656 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
17657 ret_val
17658}
17659#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
17661#[doc = "## Safety"]
17662#[doc = " * Neon instrinsic unsafe"]
17663#[inline]
17664#[cfg(target_endian = "little")]
17665#[target_feature(enable = "neon")]
17666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17667#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17668#[cfg_attr(
17669 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17670 assert_instr(ld1)
17671)]
17672#[cfg_attr(
17673 not(target_arch = "arm"),
17674 stable(feature = "neon_intrinsics", since = "1.59.0")
17675)]
17676#[cfg_attr(
17677 target_arch = "arm",
17678 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17679)]
17680pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
17681 transmute(vld1_s8_x4(transmute(a)))
17682}
17683#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
17685#[doc = "## Safety"]
17686#[doc = " * Neon instrinsic unsafe"]
17687#[inline]
17688#[cfg(target_endian = "big")]
17689#[target_feature(enable = "neon")]
17690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17691#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17692#[cfg_attr(
17693 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17694 assert_instr(ld1)
17695)]
17696#[cfg_attr(
17697 not(target_arch = "arm"),
17698 stable(feature = "neon_intrinsics", since = "1.59.0")
17699)]
17700#[cfg_attr(
17701 target_arch = "arm",
17702 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17703)]
17704pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
17705 let mut ret_val: uint8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
17706 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17707 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17708 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
17709 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
17710 ret_val
17711}
17712#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
17714#[doc = "## Safety"]
17715#[doc = " * Neon instrinsic unsafe"]
17716#[inline]
17717#[cfg(target_endian = "little")]
17718#[target_feature(enable = "neon")]
17719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17720#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17721#[cfg_attr(
17722 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17723 assert_instr(ld1)
17724)]
17725#[cfg_attr(
17726 not(target_arch = "arm"),
17727 stable(feature = "neon_intrinsics", since = "1.59.0")
17728)]
17729#[cfg_attr(
17730 target_arch = "arm",
17731 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17732)]
17733pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
17734 transmute(vld1q_s8_x2(transmute(a)))
17735}
17736#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
17738#[doc = "## Safety"]
17739#[doc = " * Neon instrinsic unsafe"]
17740#[inline]
17741#[cfg(target_endian = "big")]
17742#[target_feature(enable = "neon")]
17743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17744#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17745#[cfg_attr(
17746 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17747 assert_instr(ld1)
17748)]
17749#[cfg_attr(
17750 not(target_arch = "arm"),
17751 stable(feature = "neon_intrinsics", since = "1.59.0")
17752)]
17753#[cfg_attr(
17754 target_arch = "arm",
17755 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17756)]
17757pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
17758 let mut ret_val: uint8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
17759 ret_val.0 = unsafe {
17760 simd_shuffle!(
17761 ret_val.0,
17762 ret_val.0,
17763 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17764 )
17765 };
17766 ret_val.1 = unsafe {
17767 simd_shuffle!(
17768 ret_val.1,
17769 ret_val.1,
17770 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17771 )
17772 };
17773 ret_val
17774}
17775#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
17777#[doc = "## Safety"]
17778#[doc = " * Neon instrinsic unsafe"]
17779#[inline]
17780#[cfg(target_endian = "little")]
17781#[target_feature(enable = "neon")]
17782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17783#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17784#[cfg_attr(
17785 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17786 assert_instr(ld1)
17787)]
17788#[cfg_attr(
17789 not(target_arch = "arm"),
17790 stable(feature = "neon_intrinsics", since = "1.59.0")
17791)]
17792#[cfg_attr(
17793 target_arch = "arm",
17794 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17795)]
17796pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
17797 transmute(vld1q_s8_x3(transmute(a)))
17798}
17799#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
17801#[doc = "## Safety"]
17802#[doc = " * Neon instrinsic unsafe"]
17803#[inline]
17804#[cfg(target_endian = "big")]
17805#[target_feature(enable = "neon")]
17806#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17807#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17808#[cfg_attr(
17809 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17810 assert_instr(ld1)
17811)]
17812#[cfg_attr(
17813 not(target_arch = "arm"),
17814 stable(feature = "neon_intrinsics", since = "1.59.0")
17815)]
17816#[cfg_attr(
17817 target_arch = "arm",
17818 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17819)]
17820pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
17821 let mut ret_val: uint8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
17822 ret_val.0 = unsafe {
17823 simd_shuffle!(
17824 ret_val.0,
17825 ret_val.0,
17826 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17827 )
17828 };
17829 ret_val.1 = unsafe {
17830 simd_shuffle!(
17831 ret_val.1,
17832 ret_val.1,
17833 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17834 )
17835 };
17836 ret_val.2 = unsafe {
17837 simd_shuffle!(
17838 ret_val.2,
17839 ret_val.2,
17840 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17841 )
17842 };
17843 ret_val
17844}
17845#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
17847#[doc = "## Safety"]
17848#[doc = " * Neon instrinsic unsafe"]
17849#[inline]
17850#[cfg(target_endian = "little")]
17851#[target_feature(enable = "neon")]
17852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17853#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17854#[cfg_attr(
17855 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17856 assert_instr(ld1)
17857)]
17858#[cfg_attr(
17859 not(target_arch = "arm"),
17860 stable(feature = "neon_intrinsics", since = "1.59.0")
17861)]
17862#[cfg_attr(
17863 target_arch = "arm",
17864 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17865)]
17866pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
17867 transmute(vld1q_s8_x4(transmute(a)))
17868}
17869#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
17871#[doc = "## Safety"]
17872#[doc = " * Neon instrinsic unsafe"]
17873#[inline]
17874#[cfg(target_endian = "big")]
17875#[target_feature(enable = "neon")]
17876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17877#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17878#[cfg_attr(
17879 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17880 assert_instr(ld1)
17881)]
17882#[cfg_attr(
17883 not(target_arch = "arm"),
17884 stable(feature = "neon_intrinsics", since = "1.59.0")
17885)]
17886#[cfg_attr(
17887 target_arch = "arm",
17888 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17889)]
17890pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
17891 let mut ret_val: uint8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
17892 ret_val.0 = unsafe {
17893 simd_shuffle!(
17894 ret_val.0,
17895 ret_val.0,
17896 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17897 )
17898 };
17899 ret_val.1 = unsafe {
17900 simd_shuffle!(
17901 ret_val.1,
17902 ret_val.1,
17903 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17904 )
17905 };
17906 ret_val.2 = unsafe {
17907 simd_shuffle!(
17908 ret_val.2,
17909 ret_val.2,
17910 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17911 )
17912 };
17913 ret_val.3 = unsafe {
17914 simd_shuffle!(
17915 ret_val.3,
17916 ret_val.3,
17917 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17918 )
17919 };
17920 ret_val
17921}
17922#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
17924#[doc = "## Safety"]
17925#[doc = " * Neon instrinsic unsafe"]
17926#[inline]
17927#[cfg(target_endian = "little")]
17928#[target_feature(enable = "neon")]
17929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17930#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17931#[cfg_attr(
17932 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17933 assert_instr(ld1)
17934)]
17935#[cfg_attr(
17936 not(target_arch = "arm"),
17937 stable(feature = "neon_intrinsics", since = "1.59.0")
17938)]
17939#[cfg_attr(
17940 target_arch = "arm",
17941 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17942)]
17943pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
17944 transmute(vld1_s16_x2(transmute(a)))
17945}
17946#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
17948#[doc = "## Safety"]
17949#[doc = " * Neon instrinsic unsafe"]
17950#[inline]
17951#[cfg(target_endian = "big")]
17952#[target_feature(enable = "neon")]
17953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17955#[cfg_attr(
17956 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17957 assert_instr(ld1)
17958)]
17959#[cfg_attr(
17960 not(target_arch = "arm"),
17961 stable(feature = "neon_intrinsics", since = "1.59.0")
17962)]
17963#[cfg_attr(
17964 target_arch = "arm",
17965 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17966)]
17967pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
17968 let mut ret_val: uint16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
17969 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
17970 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
17971 ret_val
17972}
17973#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
17975#[doc = "## Safety"]
17976#[doc = " * Neon instrinsic unsafe"]
17977#[inline]
17978#[cfg(target_endian = "little")]
17979#[target_feature(enable = "neon")]
17980#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17981#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17982#[cfg_attr(
17983 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17984 assert_instr(ld1)
17985)]
17986#[cfg_attr(
17987 not(target_arch = "arm"),
17988 stable(feature = "neon_intrinsics", since = "1.59.0")
17989)]
17990#[cfg_attr(
17991 target_arch = "arm",
17992 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17993)]
17994pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
17995 transmute(vld1_s16_x3(transmute(a)))
17996}
17997#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17998#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
17999#[doc = "## Safety"]
18000#[doc = " * Neon instrinsic unsafe"]
18001#[inline]
18002#[cfg(target_endian = "big")]
18003#[target_feature(enable = "neon")]
18004#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18005#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18006#[cfg_attr(
18007 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18008 assert_instr(ld1)
18009)]
18010#[cfg_attr(
18011 not(target_arch = "arm"),
18012 stable(feature = "neon_intrinsics", since = "1.59.0")
18013)]
18014#[cfg_attr(
18015 target_arch = "arm",
18016 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18017)]
18018pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
18019 let mut ret_val: uint16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
18020 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18021 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18022 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18023 ret_val
18024}
18025#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
18027#[doc = "## Safety"]
18028#[doc = " * Neon instrinsic unsafe"]
18029#[inline]
18030#[cfg(target_endian = "little")]
18031#[target_feature(enable = "neon")]
18032#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18033#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18034#[cfg_attr(
18035 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18036 assert_instr(ld1)
18037)]
18038#[cfg_attr(
18039 not(target_arch = "arm"),
18040 stable(feature = "neon_intrinsics", since = "1.59.0")
18041)]
18042#[cfg_attr(
18043 target_arch = "arm",
18044 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18045)]
18046pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
18047 transmute(vld1_s16_x4(transmute(a)))
18048}
18049#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
18051#[doc = "## Safety"]
18052#[doc = " * Neon instrinsic unsafe"]
18053#[inline]
18054#[cfg(target_endian = "big")]
18055#[target_feature(enable = "neon")]
18056#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18057#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18058#[cfg_attr(
18059 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18060 assert_instr(ld1)
18061)]
18062#[cfg_attr(
18063 not(target_arch = "arm"),
18064 stable(feature = "neon_intrinsics", since = "1.59.0")
18065)]
18066#[cfg_attr(
18067 target_arch = "arm",
18068 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18069)]
18070pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
18071 let mut ret_val: uint16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
18072 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18073 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18074 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18075 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
18076 ret_val
18077}
18078#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
18080#[doc = "## Safety"]
18081#[doc = " * Neon instrinsic unsafe"]
18082#[inline]
18083#[cfg(target_endian = "little")]
18084#[target_feature(enable = "neon")]
18085#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18086#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18087#[cfg_attr(
18088 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18089 assert_instr(ld1)
18090)]
18091#[cfg_attr(
18092 not(target_arch = "arm"),
18093 stable(feature = "neon_intrinsics", since = "1.59.0")
18094)]
18095#[cfg_attr(
18096 target_arch = "arm",
18097 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18098)]
18099pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
18100 transmute(vld1q_s16_x2(transmute(a)))
18101}
18102#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
18104#[doc = "## Safety"]
18105#[doc = " * Neon instrinsic unsafe"]
18106#[inline]
18107#[cfg(target_endian = "big")]
18108#[target_feature(enable = "neon")]
18109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18110#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18111#[cfg_attr(
18112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18113 assert_instr(ld1)
18114)]
18115#[cfg_attr(
18116 not(target_arch = "arm"),
18117 stable(feature = "neon_intrinsics", since = "1.59.0")
18118)]
18119#[cfg_attr(
18120 target_arch = "arm",
18121 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18122)]
18123pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
18124 let mut ret_val: uint16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
18125 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18126 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18127 ret_val
18128}
18129#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
18131#[doc = "## Safety"]
18132#[doc = " * Neon instrinsic unsafe"]
18133#[inline]
18134#[cfg(target_endian = "little")]
18135#[target_feature(enable = "neon")]
18136#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18137#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18138#[cfg_attr(
18139 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18140 assert_instr(ld1)
18141)]
18142#[cfg_attr(
18143 not(target_arch = "arm"),
18144 stable(feature = "neon_intrinsics", since = "1.59.0")
18145)]
18146#[cfg_attr(
18147 target_arch = "arm",
18148 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18149)]
18150pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
18151 transmute(vld1q_s16_x3(transmute(a)))
18152}
18153#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
18155#[doc = "## Safety"]
18156#[doc = " * Neon instrinsic unsafe"]
18157#[inline]
18158#[cfg(target_endian = "big")]
18159#[target_feature(enable = "neon")]
18160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18162#[cfg_attr(
18163 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18164 assert_instr(ld1)
18165)]
18166#[cfg_attr(
18167 not(target_arch = "arm"),
18168 stable(feature = "neon_intrinsics", since = "1.59.0")
18169)]
18170#[cfg_attr(
18171 target_arch = "arm",
18172 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18173)]
18174pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
18175 let mut ret_val: uint16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
18176 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18177 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18178 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18179 ret_val
18180}
18181#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
18183#[doc = "## Safety"]
18184#[doc = " * Neon instrinsic unsafe"]
18185#[inline]
18186#[cfg(target_endian = "little")]
18187#[target_feature(enable = "neon")]
18188#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18189#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18190#[cfg_attr(
18191 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18192 assert_instr(ld1)
18193)]
18194#[cfg_attr(
18195 not(target_arch = "arm"),
18196 stable(feature = "neon_intrinsics", since = "1.59.0")
18197)]
18198#[cfg_attr(
18199 target_arch = "arm",
18200 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18201)]
18202pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
18203 transmute(vld1q_s16_x4(transmute(a)))
18204}
18205#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
18207#[doc = "## Safety"]
18208#[doc = " * Neon instrinsic unsafe"]
18209#[inline]
18210#[cfg(target_endian = "big")]
18211#[target_feature(enable = "neon")]
18212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18214#[cfg_attr(
18215 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18216 assert_instr(ld1)
18217)]
18218#[cfg_attr(
18219 not(target_arch = "arm"),
18220 stable(feature = "neon_intrinsics", since = "1.59.0")
18221)]
18222#[cfg_attr(
18223 target_arch = "arm",
18224 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18225)]
18226pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
18227 let mut ret_val: uint16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
18228 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18229 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18230 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18231 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
18232 ret_val
18233}
18234#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
18236#[doc = "## Safety"]
18237#[doc = " * Neon instrinsic unsafe"]
18238#[inline]
18239#[cfg(target_endian = "little")]
18240#[target_feature(enable = "neon")]
18241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18243#[cfg_attr(
18244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18245 assert_instr(ld1)
18246)]
18247#[cfg_attr(
18248 not(target_arch = "arm"),
18249 stable(feature = "neon_intrinsics", since = "1.59.0")
18250)]
18251#[cfg_attr(
18252 target_arch = "arm",
18253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18254)]
18255pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
18256 transmute(vld1_s32_x2(transmute(a)))
18257}
18258#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
18260#[doc = "## Safety"]
18261#[doc = " * Neon instrinsic unsafe"]
18262#[inline]
18263#[cfg(target_endian = "big")]
18264#[target_feature(enable = "neon")]
18265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18267#[cfg_attr(
18268 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18269 assert_instr(ld1)
18270)]
18271#[cfg_attr(
18272 not(target_arch = "arm"),
18273 stable(feature = "neon_intrinsics", since = "1.59.0")
18274)]
18275#[cfg_attr(
18276 target_arch = "arm",
18277 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18278)]
18279pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
18280 let mut ret_val: uint32x2x2_t = transmute(vld1_s32_x2(transmute(a)));
18281 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18282 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18283 ret_val
18284}
18285#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
18287#[doc = "## Safety"]
18288#[doc = " * Neon instrinsic unsafe"]
18289#[inline]
18290#[cfg(target_endian = "little")]
18291#[target_feature(enable = "neon")]
18292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18293#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18294#[cfg_attr(
18295 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18296 assert_instr(ld1)
18297)]
18298#[cfg_attr(
18299 not(target_arch = "arm"),
18300 stable(feature = "neon_intrinsics", since = "1.59.0")
18301)]
18302#[cfg_attr(
18303 target_arch = "arm",
18304 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18305)]
18306pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
18307 transmute(vld1_s32_x3(transmute(a)))
18308}
18309#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
18311#[doc = "## Safety"]
18312#[doc = " * Neon instrinsic unsafe"]
18313#[inline]
18314#[cfg(target_endian = "big")]
18315#[target_feature(enable = "neon")]
18316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18318#[cfg_attr(
18319 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18320 assert_instr(ld1)
18321)]
18322#[cfg_attr(
18323 not(target_arch = "arm"),
18324 stable(feature = "neon_intrinsics", since = "1.59.0")
18325)]
18326#[cfg_attr(
18327 target_arch = "arm",
18328 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18329)]
18330pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
18331 let mut ret_val: uint32x2x3_t = transmute(vld1_s32_x3(transmute(a)));
18332 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18333 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18334 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18335 ret_val
18336}
18337#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
18339#[doc = "## Safety"]
18340#[doc = " * Neon instrinsic unsafe"]
18341#[inline]
18342#[cfg(target_endian = "little")]
18343#[target_feature(enable = "neon")]
18344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18345#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18346#[cfg_attr(
18347 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18348 assert_instr(ld1)
18349)]
18350#[cfg_attr(
18351 not(target_arch = "arm"),
18352 stable(feature = "neon_intrinsics", since = "1.59.0")
18353)]
18354#[cfg_attr(
18355 target_arch = "arm",
18356 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18357)]
18358pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
18359 transmute(vld1_s32_x4(transmute(a)))
18360}
18361#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
18363#[doc = "## Safety"]
18364#[doc = " * Neon instrinsic unsafe"]
18365#[inline]
18366#[cfg(target_endian = "big")]
18367#[target_feature(enable = "neon")]
18368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18370#[cfg_attr(
18371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18372 assert_instr(ld1)
18373)]
18374#[cfg_attr(
18375 not(target_arch = "arm"),
18376 stable(feature = "neon_intrinsics", since = "1.59.0")
18377)]
18378#[cfg_attr(
18379 target_arch = "arm",
18380 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18381)]
18382pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
18383 let mut ret_val: uint32x2x4_t = transmute(vld1_s32_x4(transmute(a)));
18384 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18385 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18386 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18387 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
18388 ret_val
18389}
18390#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
18392#[doc = "## Safety"]
18393#[doc = " * Neon instrinsic unsafe"]
18394#[inline]
18395#[cfg(target_endian = "little")]
18396#[target_feature(enable = "neon")]
18397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18398#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18399#[cfg_attr(
18400 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18401 assert_instr(ld1)
18402)]
18403#[cfg_attr(
18404 not(target_arch = "arm"),
18405 stable(feature = "neon_intrinsics", since = "1.59.0")
18406)]
18407#[cfg_attr(
18408 target_arch = "arm",
18409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18410)]
18411pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
18412 transmute(vld1q_s32_x2(transmute(a)))
18413}
18414#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
18416#[doc = "## Safety"]
18417#[doc = " * Neon instrinsic unsafe"]
18418#[inline]
18419#[cfg(target_endian = "big")]
18420#[target_feature(enable = "neon")]
18421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18423#[cfg_attr(
18424 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18425 assert_instr(ld1)
18426)]
18427#[cfg_attr(
18428 not(target_arch = "arm"),
18429 stable(feature = "neon_intrinsics", since = "1.59.0")
18430)]
18431#[cfg_attr(
18432 target_arch = "arm",
18433 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18434)]
18435pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
18436 let mut ret_val: uint32x4x2_t = transmute(vld1q_s32_x2(transmute(a)));
18437 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18438 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18439 ret_val
18440}
18441#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
18443#[doc = "## Safety"]
18444#[doc = " * Neon instrinsic unsafe"]
18445#[inline]
18446#[cfg(target_endian = "little")]
18447#[target_feature(enable = "neon")]
18448#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18449#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18450#[cfg_attr(
18451 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18452 assert_instr(ld1)
18453)]
18454#[cfg_attr(
18455 not(target_arch = "arm"),
18456 stable(feature = "neon_intrinsics", since = "1.59.0")
18457)]
18458#[cfg_attr(
18459 target_arch = "arm",
18460 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18461)]
18462pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
18463 transmute(vld1q_s32_x3(transmute(a)))
18464}
18465#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
18467#[doc = "## Safety"]
18468#[doc = " * Neon instrinsic unsafe"]
18469#[inline]
18470#[cfg(target_endian = "big")]
18471#[target_feature(enable = "neon")]
18472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18474#[cfg_attr(
18475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18476 assert_instr(ld1)
18477)]
18478#[cfg_attr(
18479 not(target_arch = "arm"),
18480 stable(feature = "neon_intrinsics", since = "1.59.0")
18481)]
18482#[cfg_attr(
18483 target_arch = "arm",
18484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18485)]
18486pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
18487 let mut ret_val: uint32x4x3_t = transmute(vld1q_s32_x3(transmute(a)));
18488 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18489 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18490 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18491 ret_val
18492}
18493#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
18495#[doc = "## Safety"]
18496#[doc = " * Neon instrinsic unsafe"]
18497#[inline]
18498#[cfg(target_endian = "little")]
18499#[target_feature(enable = "neon")]
18500#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18501#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18502#[cfg_attr(
18503 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18504 assert_instr(ld1)
18505)]
18506#[cfg_attr(
18507 not(target_arch = "arm"),
18508 stable(feature = "neon_intrinsics", since = "1.59.0")
18509)]
18510#[cfg_attr(
18511 target_arch = "arm",
18512 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18513)]
18514pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
18515 transmute(vld1q_s32_x4(transmute(a)))
18516}
18517#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
18519#[doc = "## Safety"]
18520#[doc = " * Neon instrinsic unsafe"]
18521#[inline]
18522#[cfg(target_endian = "big")]
18523#[target_feature(enable = "neon")]
18524#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18525#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18526#[cfg_attr(
18527 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18528 assert_instr(ld1)
18529)]
18530#[cfg_attr(
18531 not(target_arch = "arm"),
18532 stable(feature = "neon_intrinsics", since = "1.59.0")
18533)]
18534#[cfg_attr(
18535 target_arch = "arm",
18536 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18537)]
18538pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
18539 let mut ret_val: uint32x4x4_t = transmute(vld1q_s32_x4(transmute(a)));
18540 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18541 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18542 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18543 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
18544 ret_val
18545}
18546#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
18548#[doc = "## Safety"]
18549#[doc = " * Neon instrinsic unsafe"]
18550#[inline]
18551#[target_feature(enable = "neon")]
18552#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18553#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18554#[cfg_attr(
18555 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18556 assert_instr(ld1)
18557)]
18558#[cfg_attr(
18559 not(target_arch = "arm"),
18560 stable(feature = "neon_intrinsics", since = "1.59.0")
18561)]
18562#[cfg_attr(
18563 target_arch = "arm",
18564 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18565)]
18566pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
18567 transmute(vld1_s64_x2(transmute(a)))
18568}
18569#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
18571#[doc = "## Safety"]
18572#[doc = " * Neon instrinsic unsafe"]
18573#[inline]
18574#[target_feature(enable = "neon")]
18575#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18576#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18577#[cfg_attr(
18578 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18579 assert_instr(ld1)
18580)]
18581#[cfg_attr(
18582 not(target_arch = "arm"),
18583 stable(feature = "neon_intrinsics", since = "1.59.0")
18584)]
18585#[cfg_attr(
18586 target_arch = "arm",
18587 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18588)]
18589pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
18590 transmute(vld1_s64_x3(transmute(a)))
18591}
18592#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
18594#[doc = "## Safety"]
18595#[doc = " * Neon instrinsic unsafe"]
18596#[inline]
18597#[target_feature(enable = "neon")]
18598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18599#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18600#[cfg_attr(
18601 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18602 assert_instr(ld1)
18603)]
18604#[cfg_attr(
18605 not(target_arch = "arm"),
18606 stable(feature = "neon_intrinsics", since = "1.59.0")
18607)]
18608#[cfg_attr(
18609 target_arch = "arm",
18610 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18611)]
18612pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
18613 transmute(vld1_s64_x4(transmute(a)))
18614}
18615#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
18617#[doc = "## Safety"]
18618#[doc = " * Neon instrinsic unsafe"]
18619#[inline]
18620#[cfg(target_endian = "little")]
18621#[target_feature(enable = "neon")]
18622#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18623#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18624#[cfg_attr(
18625 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18626 assert_instr(ld1)
18627)]
18628#[cfg_attr(
18629 not(target_arch = "arm"),
18630 stable(feature = "neon_intrinsics", since = "1.59.0")
18631)]
18632#[cfg_attr(
18633 target_arch = "arm",
18634 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18635)]
18636pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
18637 transmute(vld1q_s64_x2(transmute(a)))
18638}
18639#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
18641#[doc = "## Safety"]
18642#[doc = " * Neon instrinsic unsafe"]
18643#[inline]
18644#[cfg(target_endian = "big")]
18645#[target_feature(enable = "neon")]
18646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18647#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18648#[cfg_attr(
18649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18650 assert_instr(ld1)
18651)]
18652#[cfg_attr(
18653 not(target_arch = "arm"),
18654 stable(feature = "neon_intrinsics", since = "1.59.0")
18655)]
18656#[cfg_attr(
18657 target_arch = "arm",
18658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18659)]
18660pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
18661 let mut ret_val: uint64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
18662 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18663 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18664 ret_val
18665}
18666#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
18668#[doc = "## Safety"]
18669#[doc = " * Neon instrinsic unsafe"]
18670#[inline]
18671#[cfg(target_endian = "little")]
18672#[target_feature(enable = "neon")]
18673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18674#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18675#[cfg_attr(
18676 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18677 assert_instr(ld1)
18678)]
18679#[cfg_attr(
18680 not(target_arch = "arm"),
18681 stable(feature = "neon_intrinsics", since = "1.59.0")
18682)]
18683#[cfg_attr(
18684 target_arch = "arm",
18685 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18686)]
18687pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
18688 transmute(vld1q_s64_x3(transmute(a)))
18689}
18690#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
18692#[doc = "## Safety"]
18693#[doc = " * Neon instrinsic unsafe"]
18694#[inline]
18695#[cfg(target_endian = "big")]
18696#[target_feature(enable = "neon")]
18697#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18698#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18699#[cfg_attr(
18700 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18701 assert_instr(ld1)
18702)]
18703#[cfg_attr(
18704 not(target_arch = "arm"),
18705 stable(feature = "neon_intrinsics", since = "1.59.0")
18706)]
18707#[cfg_attr(
18708 target_arch = "arm",
18709 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18710)]
18711pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
18712 let mut ret_val: uint64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
18713 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18714 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18715 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18716 ret_val
18717}
18718#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
18720#[doc = "## Safety"]
18721#[doc = " * Neon instrinsic unsafe"]
18722#[inline]
18723#[cfg(target_endian = "little")]
18724#[target_feature(enable = "neon")]
18725#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18726#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18727#[cfg_attr(
18728 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18729 assert_instr(ld1)
18730)]
18731#[cfg_attr(
18732 not(target_arch = "arm"),
18733 stable(feature = "neon_intrinsics", since = "1.59.0")
18734)]
18735#[cfg_attr(
18736 target_arch = "arm",
18737 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18738)]
18739pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
18740 transmute(vld1q_s64_x4(transmute(a)))
18741}
18742#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
18744#[doc = "## Safety"]
18745#[doc = " * Neon instrinsic unsafe"]
18746#[inline]
18747#[cfg(target_endian = "big")]
18748#[target_feature(enable = "neon")]
18749#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18750#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18751#[cfg_attr(
18752 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18753 assert_instr(ld1)
18754)]
18755#[cfg_attr(
18756 not(target_arch = "arm"),
18757 stable(feature = "neon_intrinsics", since = "1.59.0")
18758)]
18759#[cfg_attr(
18760 target_arch = "arm",
18761 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18762)]
18763pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
18764 let mut ret_val: uint64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
18765 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18766 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18767 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18768 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
18769 ret_val
18770}
18771#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
18773#[doc = "## Safety"]
18774#[doc = " * Neon instrinsic unsafe"]
18775#[inline]
18776#[cfg(target_endian = "little")]
18777#[target_feature(enable = "neon")]
18778#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18779#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18780#[cfg_attr(
18781 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18782 assert_instr(ld1)
18783)]
18784#[cfg_attr(
18785 not(target_arch = "arm"),
18786 stable(feature = "neon_intrinsics", since = "1.59.0")
18787)]
18788#[cfg_attr(
18789 target_arch = "arm",
18790 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18791)]
18792pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
18793 transmute(vld1_s8_x2(transmute(a)))
18794}
18795#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
18797#[doc = "## Safety"]
18798#[doc = " * Neon instrinsic unsafe"]
18799#[inline]
18800#[cfg(target_endian = "big")]
18801#[target_feature(enable = "neon")]
18802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18803#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18804#[cfg_attr(
18805 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18806 assert_instr(ld1)
18807)]
18808#[cfg_attr(
18809 not(target_arch = "arm"),
18810 stable(feature = "neon_intrinsics", since = "1.59.0")
18811)]
18812#[cfg_attr(
18813 target_arch = "arm",
18814 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18815)]
18816pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
18817 let mut ret_val: poly8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
18818 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18819 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18820 ret_val
18821}
18822#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
18824#[doc = "## Safety"]
18825#[doc = " * Neon instrinsic unsafe"]
18826#[inline]
18827#[cfg(target_endian = "little")]
18828#[target_feature(enable = "neon")]
18829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18831#[cfg_attr(
18832 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18833 assert_instr(ld1)
18834)]
18835#[cfg_attr(
18836 not(target_arch = "arm"),
18837 stable(feature = "neon_intrinsics", since = "1.59.0")
18838)]
18839#[cfg_attr(
18840 target_arch = "arm",
18841 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18842)]
18843pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
18844 transmute(vld1_s8_x3(transmute(a)))
18845}
18846#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
18848#[doc = "## Safety"]
18849#[doc = " * Neon instrinsic unsafe"]
18850#[inline]
18851#[cfg(target_endian = "big")]
18852#[target_feature(enable = "neon")]
18853#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18854#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18855#[cfg_attr(
18856 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18857 assert_instr(ld1)
18858)]
18859#[cfg_attr(
18860 not(target_arch = "arm"),
18861 stable(feature = "neon_intrinsics", since = "1.59.0")
18862)]
18863#[cfg_attr(
18864 target_arch = "arm",
18865 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18866)]
18867pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
18868 let mut ret_val: poly8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
18869 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18870 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18871 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18872 ret_val
18873}
18874#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
18876#[doc = "## Safety"]
18877#[doc = " * Neon instrinsic unsafe"]
18878#[inline]
18879#[cfg(target_endian = "little")]
18880#[target_feature(enable = "neon")]
18881#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18882#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18883#[cfg_attr(
18884 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18885 assert_instr(ld1)
18886)]
18887#[cfg_attr(
18888 not(target_arch = "arm"),
18889 stable(feature = "neon_intrinsics", since = "1.59.0")
18890)]
18891#[cfg_attr(
18892 target_arch = "arm",
18893 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18894)]
18895pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
18896 transmute(vld1_s8_x4(transmute(a)))
18897}
18898#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
18900#[doc = "## Safety"]
18901#[doc = " * Neon instrinsic unsafe"]
18902#[inline]
18903#[cfg(target_endian = "big")]
18904#[target_feature(enable = "neon")]
18905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18907#[cfg_attr(
18908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18909 assert_instr(ld1)
18910)]
18911#[cfg_attr(
18912 not(target_arch = "arm"),
18913 stable(feature = "neon_intrinsics", since = "1.59.0")
18914)]
18915#[cfg_attr(
18916 target_arch = "arm",
18917 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18918)]
18919pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
18920 let mut ret_val: poly8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
18921 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18922 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18923 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18924 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
18925 ret_val
18926}
18927#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
18929#[doc = "## Safety"]
18930#[doc = " * Neon instrinsic unsafe"]
18931#[inline]
18932#[cfg(target_endian = "little")]
18933#[target_feature(enable = "neon")]
18934#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18935#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18936#[cfg_attr(
18937 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18938 assert_instr(ld1)
18939)]
18940#[cfg_attr(
18941 not(target_arch = "arm"),
18942 stable(feature = "neon_intrinsics", since = "1.59.0")
18943)]
18944#[cfg_attr(
18945 target_arch = "arm",
18946 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18947)]
18948pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
18949 transmute(vld1q_s8_x2(transmute(a)))
18950}
18951#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
18953#[doc = "## Safety"]
18954#[doc = " * Neon instrinsic unsafe"]
18955#[inline]
18956#[cfg(target_endian = "big")]
18957#[target_feature(enable = "neon")]
18958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18960#[cfg_attr(
18961 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18962 assert_instr(ld1)
18963)]
18964#[cfg_attr(
18965 not(target_arch = "arm"),
18966 stable(feature = "neon_intrinsics", since = "1.59.0")
18967)]
18968#[cfg_attr(
18969 target_arch = "arm",
18970 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18971)]
18972pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
18973 let mut ret_val: poly8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
18974 ret_val.0 = unsafe {
18975 simd_shuffle!(
18976 ret_val.0,
18977 ret_val.0,
18978 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18979 )
18980 };
18981 ret_val.1 = unsafe {
18982 simd_shuffle!(
18983 ret_val.1,
18984 ret_val.1,
18985 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18986 )
18987 };
18988 ret_val
18989}
18990#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18991#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
18992#[doc = "## Safety"]
18993#[doc = " * Neon instrinsic unsafe"]
18994#[inline]
18995#[cfg(target_endian = "little")]
18996#[target_feature(enable = "neon")]
18997#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18998#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18999#[cfg_attr(
19000 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19001 assert_instr(ld1)
19002)]
19003#[cfg_attr(
19004 not(target_arch = "arm"),
19005 stable(feature = "neon_intrinsics", since = "1.59.0")
19006)]
19007#[cfg_attr(
19008 target_arch = "arm",
19009 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19010)]
19011pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
19012 transmute(vld1q_s8_x3(transmute(a)))
19013}
19014#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
19016#[doc = "## Safety"]
19017#[doc = " * Neon instrinsic unsafe"]
19018#[inline]
19019#[cfg(target_endian = "big")]
19020#[target_feature(enable = "neon")]
19021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19022#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19023#[cfg_attr(
19024 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19025 assert_instr(ld1)
19026)]
19027#[cfg_attr(
19028 not(target_arch = "arm"),
19029 stable(feature = "neon_intrinsics", since = "1.59.0")
19030)]
19031#[cfg_attr(
19032 target_arch = "arm",
19033 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19034)]
19035pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
19036 let mut ret_val: poly8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
19037 ret_val.0 = unsafe {
19038 simd_shuffle!(
19039 ret_val.0,
19040 ret_val.0,
19041 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19042 )
19043 };
19044 ret_val.1 = unsafe {
19045 simd_shuffle!(
19046 ret_val.1,
19047 ret_val.1,
19048 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19049 )
19050 };
19051 ret_val.2 = unsafe {
19052 simd_shuffle!(
19053 ret_val.2,
19054 ret_val.2,
19055 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19056 )
19057 };
19058 ret_val
19059}
19060#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
19062#[doc = "## Safety"]
19063#[doc = " * Neon instrinsic unsafe"]
19064#[inline]
19065#[cfg(target_endian = "little")]
19066#[target_feature(enable = "neon")]
19067#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19068#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19069#[cfg_attr(
19070 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19071 assert_instr(ld1)
19072)]
19073#[cfg_attr(
19074 not(target_arch = "arm"),
19075 stable(feature = "neon_intrinsics", since = "1.59.0")
19076)]
19077#[cfg_attr(
19078 target_arch = "arm",
19079 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19080)]
19081pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
19082 transmute(vld1q_s8_x4(transmute(a)))
19083}
19084#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
19086#[doc = "## Safety"]
19087#[doc = " * Neon instrinsic unsafe"]
19088#[inline]
19089#[cfg(target_endian = "big")]
19090#[target_feature(enable = "neon")]
19091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19093#[cfg_attr(
19094 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19095 assert_instr(ld1)
19096)]
19097#[cfg_attr(
19098 not(target_arch = "arm"),
19099 stable(feature = "neon_intrinsics", since = "1.59.0")
19100)]
19101#[cfg_attr(
19102 target_arch = "arm",
19103 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19104)]
19105pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
19106 let mut ret_val: poly8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
19107 ret_val.0 = unsafe {
19108 simd_shuffle!(
19109 ret_val.0,
19110 ret_val.0,
19111 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19112 )
19113 };
19114 ret_val.1 = unsafe {
19115 simd_shuffle!(
19116 ret_val.1,
19117 ret_val.1,
19118 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19119 )
19120 };
19121 ret_val.2 = unsafe {
19122 simd_shuffle!(
19123 ret_val.2,
19124 ret_val.2,
19125 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19126 )
19127 };
19128 ret_val.3 = unsafe {
19129 simd_shuffle!(
19130 ret_val.3,
19131 ret_val.3,
19132 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19133 )
19134 };
19135 ret_val
19136}
19137#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
19139#[doc = "## Safety"]
19140#[doc = " * Neon instrinsic unsafe"]
19141#[inline]
19142#[cfg(target_endian = "little")]
19143#[target_feature(enable = "neon")]
19144#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19145#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19146#[cfg_attr(
19147 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19148 assert_instr(ld1)
19149)]
19150#[cfg_attr(
19151 not(target_arch = "arm"),
19152 stable(feature = "neon_intrinsics", since = "1.59.0")
19153)]
19154#[cfg_attr(
19155 target_arch = "arm",
19156 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19157)]
19158pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
19159 transmute(vld1_s16_x2(transmute(a)))
19160}
19161#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
19163#[doc = "## Safety"]
19164#[doc = " * Neon instrinsic unsafe"]
19165#[inline]
19166#[cfg(target_endian = "big")]
19167#[target_feature(enable = "neon")]
19168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19169#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19170#[cfg_attr(
19171 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19172 assert_instr(ld1)
19173)]
19174#[cfg_attr(
19175 not(target_arch = "arm"),
19176 stable(feature = "neon_intrinsics", since = "1.59.0")
19177)]
19178#[cfg_attr(
19179 target_arch = "arm",
19180 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19181)]
19182pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
19183 let mut ret_val: poly16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
19184 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19185 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19186 ret_val
19187}
19188#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
19190#[doc = "## Safety"]
19191#[doc = " * Neon instrinsic unsafe"]
19192#[inline]
19193#[cfg(target_endian = "little")]
19194#[target_feature(enable = "neon")]
19195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19196#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19197#[cfg_attr(
19198 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19199 assert_instr(ld1)
19200)]
19201#[cfg_attr(
19202 not(target_arch = "arm"),
19203 stable(feature = "neon_intrinsics", since = "1.59.0")
19204)]
19205#[cfg_attr(
19206 target_arch = "arm",
19207 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19208)]
19209pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
19210 transmute(vld1_s16_x3(transmute(a)))
19211}
19212#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
19214#[doc = "## Safety"]
19215#[doc = " * Neon instrinsic unsafe"]
19216#[inline]
19217#[cfg(target_endian = "big")]
19218#[target_feature(enable = "neon")]
19219#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19220#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19221#[cfg_attr(
19222 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19223 assert_instr(ld1)
19224)]
19225#[cfg_attr(
19226 not(target_arch = "arm"),
19227 stable(feature = "neon_intrinsics", since = "1.59.0")
19228)]
19229#[cfg_attr(
19230 target_arch = "arm",
19231 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19232)]
19233pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
19234 let mut ret_val: poly16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
19235 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19236 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19237 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
19238 ret_val
19239}
19240#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
19242#[doc = "## Safety"]
19243#[doc = " * Neon instrinsic unsafe"]
19244#[inline]
19245#[cfg(target_endian = "little")]
19246#[target_feature(enable = "neon")]
19247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19249#[cfg_attr(
19250 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19251 assert_instr(ld1)
19252)]
19253#[cfg_attr(
19254 not(target_arch = "arm"),
19255 stable(feature = "neon_intrinsics", since = "1.59.0")
19256)]
19257#[cfg_attr(
19258 target_arch = "arm",
19259 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19260)]
19261pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
19262 transmute(vld1_s16_x4(transmute(a)))
19263}
19264#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
19266#[doc = "## Safety"]
19267#[doc = " * Neon instrinsic unsafe"]
19268#[inline]
19269#[cfg(target_endian = "big")]
19270#[target_feature(enable = "neon")]
19271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19272#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19273#[cfg_attr(
19274 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19275 assert_instr(ld1)
19276)]
19277#[cfg_attr(
19278 not(target_arch = "arm"),
19279 stable(feature = "neon_intrinsics", since = "1.59.0")
19280)]
19281#[cfg_attr(
19282 target_arch = "arm",
19283 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19284)]
19285pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
19286 let mut ret_val: poly16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
19287 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19288 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19289 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
19290 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
19291 ret_val
19292}
19293#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
19295#[doc = "## Safety"]
19296#[doc = " * Neon instrinsic unsafe"]
19297#[inline]
19298#[cfg(target_endian = "little")]
19299#[target_feature(enable = "neon")]
19300#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19301#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19302#[cfg_attr(
19303 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19304 assert_instr(ld1)
19305)]
19306#[cfg_attr(
19307 not(target_arch = "arm"),
19308 stable(feature = "neon_intrinsics", since = "1.59.0")
19309)]
19310#[cfg_attr(
19311 target_arch = "arm",
19312 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19313)]
19314pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
19315 transmute(vld1q_s16_x2(transmute(a)))
19316}
19317#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19318#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
19319#[doc = "## Safety"]
19320#[doc = " * Neon instrinsic unsafe"]
19321#[inline]
19322#[cfg(target_endian = "big")]
19323#[target_feature(enable = "neon")]
19324#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19325#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19326#[cfg_attr(
19327 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19328 assert_instr(ld1)
19329)]
19330#[cfg_attr(
19331 not(target_arch = "arm"),
19332 stable(feature = "neon_intrinsics", since = "1.59.0")
19333)]
19334#[cfg_attr(
19335 target_arch = "arm",
19336 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19337)]
19338pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
19339 let mut ret_val: poly16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
19340 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19341 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19342 ret_val
19343}
19344#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
19346#[doc = "## Safety"]
19347#[doc = " * Neon instrinsic unsafe"]
19348#[inline]
19349#[cfg(target_endian = "little")]
19350#[target_feature(enable = "neon")]
19351#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19352#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19353#[cfg_attr(
19354 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19355 assert_instr(ld1)
19356)]
19357#[cfg_attr(
19358 not(target_arch = "arm"),
19359 stable(feature = "neon_intrinsics", since = "1.59.0")
19360)]
19361#[cfg_attr(
19362 target_arch = "arm",
19363 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19364)]
19365pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
19366 transmute(vld1q_s16_x3(transmute(a)))
19367}
19368#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
19370#[doc = "## Safety"]
19371#[doc = " * Neon instrinsic unsafe"]
19372#[inline]
19373#[cfg(target_endian = "big")]
19374#[target_feature(enable = "neon")]
19375#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19376#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19377#[cfg_attr(
19378 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19379 assert_instr(ld1)
19380)]
19381#[cfg_attr(
19382 not(target_arch = "arm"),
19383 stable(feature = "neon_intrinsics", since = "1.59.0")
19384)]
19385#[cfg_attr(
19386 target_arch = "arm",
19387 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19388)]
19389pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
19390 let mut ret_val: poly16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
19391 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19392 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19393 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19394 ret_val
19395}
19396#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
19398#[doc = "## Safety"]
19399#[doc = " * Neon instrinsic unsafe"]
19400#[inline]
19401#[cfg(target_endian = "little")]
19402#[target_feature(enable = "neon")]
19403#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19404#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19405#[cfg_attr(
19406 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19407 assert_instr(ld1)
19408)]
19409#[cfg_attr(
19410 not(target_arch = "arm"),
19411 stable(feature = "neon_intrinsics", since = "1.59.0")
19412)]
19413#[cfg_attr(
19414 target_arch = "arm",
19415 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19416)]
19417pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
19418 transmute(vld1q_s16_x4(transmute(a)))
19419}
19420#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19421#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
19422#[doc = "## Safety"]
19423#[doc = " * Neon instrinsic unsafe"]
19424#[inline]
19425#[cfg(target_endian = "big")]
19426#[target_feature(enable = "neon")]
19427#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19428#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19429#[cfg_attr(
19430 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19431 assert_instr(ld1)
19432)]
19433#[cfg_attr(
19434 not(target_arch = "arm"),
19435 stable(feature = "neon_intrinsics", since = "1.59.0")
19436)]
19437#[cfg_attr(
19438 target_arch = "arm",
19439 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19440)]
19441pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
19442 let mut ret_val: poly16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
19443 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19444 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19445 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19446 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
19447 ret_val
19448}
19449#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v1i64)"]
19451#[doc = "## Safety"]
19452#[doc = " * Neon instrinsic unsafe"]
19453#[inline]
19454#[cfg(target_arch = "arm")]
19455#[target_feature(enable = "neon,v7")]
19456#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19457unsafe fn vld1_v1i64(a: *const i8, b: i32) -> int64x1_t {
19458 unsafe extern "unadjusted" {
19459 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")]
19460 fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t;
19461 }
19462 _vld1_v1i64(a, b)
19463}
19464#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19465#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2f32)"]
19466#[doc = "## Safety"]
19467#[doc = " * Neon instrinsic unsafe"]
19468#[inline]
19469#[cfg(target_arch = "arm")]
19470#[target_feature(enable = "neon,v7")]
19471#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19472unsafe fn vld1_v2f32(a: *const i8, b: i32) -> float32x2_t {
19473 unsafe extern "unadjusted" {
19474 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2f32")]
19475 fn _vld1_v2f32(a: *const i8, b: i32) -> float32x2_t;
19476 }
19477 _vld1_v2f32(a, b)
19478}
19479#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2i32)"]
19481#[doc = "## Safety"]
19482#[doc = " * Neon instrinsic unsafe"]
19483#[inline]
19484#[cfg(target_arch = "arm")]
19485#[target_feature(enable = "neon,v7")]
19486#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19487unsafe fn vld1_v2i32(a: *const i8, b: i32) -> int32x2_t {
19488 unsafe extern "unadjusted" {
19489 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i32")]
19490 fn _vld1_v2i32(a: *const i8, b: i32) -> int32x2_t;
19491 }
19492 _vld1_v2i32(a, b)
19493}
19494#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4i16)"]
19496#[doc = "## Safety"]
19497#[doc = " * Neon instrinsic unsafe"]
19498#[inline]
19499#[cfg(target_arch = "arm")]
19500#[target_feature(enable = "neon,v7")]
19501#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19502unsafe fn vld1_v4i16(a: *const i8, b: i32) -> int16x4_t {
19503 unsafe extern "unadjusted" {
19504 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i16")]
19505 fn _vld1_v4i16(a: *const i8, b: i32) -> int16x4_t;
19506 }
19507 _vld1_v4i16(a, b)
19508}
19509#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v8i8)"]
19511#[doc = "## Safety"]
19512#[doc = " * Neon instrinsic unsafe"]
19513#[inline]
19514#[cfg(target_arch = "arm")]
19515#[target_feature(enable = "neon,v7")]
19516#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19517unsafe fn vld1_v8i8(a: *const i8, b: i32) -> int8x8_t {
19518 unsafe extern "unadjusted" {
19519 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i8")]
19520 fn _vld1_v8i8(a: *const i8, b: i32) -> int8x8_t;
19521 }
19522 _vld1_v8i8(a, b)
19523}
19524#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v16i8)"]
19526#[doc = "## Safety"]
19527#[doc = " * Neon instrinsic unsafe"]
19528#[inline]
19529#[cfg(target_arch = "arm")]
19530#[target_feature(enable = "neon,v7")]
19531#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19532unsafe fn vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t {
19533 unsafe extern "unadjusted" {
19534 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v16i8")]
19535 fn _vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t;
19536 }
19537 _vld1q_v16i8(a, b)
19538}
19539#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v2i64)"]
19541#[doc = "## Safety"]
19542#[doc = " * Neon instrinsic unsafe"]
19543#[inline]
19544#[cfg(target_arch = "arm")]
19545#[target_feature(enable = "neon,v7")]
19546#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19547unsafe fn vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t {
19548 unsafe extern "unadjusted" {
19549 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i64")]
19550 fn _vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t;
19551 }
19552 _vld1q_v2i64(a, b)
19553}
19554#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4f32)"]
19556#[doc = "## Safety"]
19557#[doc = " * Neon instrinsic unsafe"]
19558#[inline]
19559#[cfg(target_arch = "arm")]
19560#[target_feature(enable = "neon,v7")]
19561#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19562unsafe fn vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t {
19563 unsafe extern "unadjusted" {
19564 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32")]
19565 fn _vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t;
19566 }
19567 _vld1q_v4f32(a, b)
19568}
19569#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4i32)"]
19571#[doc = "## Safety"]
19572#[doc = " * Neon instrinsic unsafe"]
19573#[inline]
19574#[cfg(target_arch = "arm")]
19575#[target_feature(enable = "neon,v7")]
19576#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19577unsafe fn vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t {
19578 unsafe extern "unadjusted" {
19579 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i32")]
19580 fn _vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t;
19581 }
19582 _vld1q_v4i32(a, b)
19583}
19584#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8i16)"]
19586#[doc = "## Safety"]
19587#[doc = " * Neon instrinsic unsafe"]
19588#[inline]
19589#[cfg(target_arch = "arm")]
19590#[target_feature(enable = "neon,v7")]
19591#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19592unsafe fn vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t {
19593 unsafe extern "unadjusted" {
19594 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i16")]
19595 fn _vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t;
19596 }
19597 _vld1q_v8i16(a, b)
19598}
19599#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4f16)"]
19601#[doc = "## Safety"]
19602#[doc = " * Neon instrinsic unsafe"]
19603#[inline]
19604#[cfg(target_arch = "arm")]
19605#[target_feature(enable = "neon,v7")]
19606#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19607#[target_feature(enable = "neon,fp16")]
19608#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19609unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t {
19610 unsafe extern "unadjusted" {
19611 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f16")]
19612 fn _vld1_v4f16(a: *const i8, b: i32) -> float16x4_t;
19613 }
19614 _vld1_v4f16(a, b)
19615}
19616#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8f16)"]
19618#[doc = "## Safety"]
19619#[doc = " * Neon instrinsic unsafe"]
19620#[inline]
19621#[cfg(target_arch = "arm")]
19622#[target_feature(enable = "neon,v7")]
19623#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19624#[target_feature(enable = "neon,fp16")]
19625#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19626unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t {
19627 unsafe extern "unadjusted" {
19628 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8f16")]
19629 fn _vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t;
19630 }
19631 _vld1q_v8f16(a, b)
19632}
19633#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
19634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"]
19635#[doc = "## Safety"]
19636#[doc = " * Neon instrinsic unsafe"]
19637#[inline]
19638#[target_feature(enable = "neon,aes")]
19639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19640#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
19641#[cfg_attr(
19642 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19643 assert_instr(ld1r)
19644)]
19645#[cfg_attr(
19646 not(target_arch = "arm"),
19647 stable(feature = "neon_intrinsics", since = "1.59.0")
19648)]
19649#[cfg_attr(
19650 target_arch = "arm",
19651 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19652)]
19653pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t {
19654 let x = vld1q_lane_p64::<0>(ptr, transmute(u64x2::splat(0)));
19655 simd_shuffle!(x, x, [0, 0])
19656}
19657#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
19659#[doc = "## Safety"]
19660#[doc = " * Neon instrinsic unsafe"]
19661#[inline]
19662#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19663#[cfg(target_arch = "arm")]
19664#[target_feature(enable = "neon,fp16")]
19665#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
19666#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19667pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
19668 unsafe extern "unadjusted" {
19669 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f16.p0f16")]
19670 fn _vld2_dup_f16(ptr: *const f16, size: i32) -> float16x4x2_t;
19671 }
19672 _vld2_dup_f16(a as _, 2)
19673}
19674#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
19676#[doc = "## Safety"]
19677#[doc = " * Neon instrinsic unsafe"]
19678#[inline]
19679#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19680#[cfg(target_arch = "arm")]
19681#[target_feature(enable = "neon,fp16")]
19682#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
19683#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19684pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
19685 unsafe extern "unadjusted" {
19686 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8f16.p0f16")]
19687 fn _vld2q_dup_f16(ptr: *const f16, size: i32) -> float16x8x2_t;
19688 }
19689 _vld2q_dup_f16(a as _, 2)
19690}
19691#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
19693#[doc = "## Safety"]
19694#[doc = " * Neon instrinsic unsafe"]
19695#[inline]
19696#[cfg(not(target_arch = "arm"))]
19697#[cfg_attr(
19698 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19699 assert_instr(ld2r)
19700)]
19701#[target_feature(enable = "neon,fp16")]
19702#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19703pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
19704 unsafe extern "unadjusted" {
19705 #[cfg_attr(
19706 any(target_arch = "aarch64", target_arch = "arm64ec"),
19707 link_name = "llvm.aarch64.neon.ld2r.v4f16.p0f16"
19708 )]
19709 fn _vld2_dup_f16(ptr: *const f16) -> float16x4x2_t;
19710 }
19711 _vld2_dup_f16(a as _)
19712}
19713#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
19715#[doc = "## Safety"]
19716#[doc = " * Neon instrinsic unsafe"]
19717#[inline]
19718#[cfg(not(target_arch = "arm"))]
19719#[cfg_attr(
19720 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19721 assert_instr(ld2r)
19722)]
19723#[target_feature(enable = "neon,fp16")]
19724#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19725pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
19726 unsafe extern "unadjusted" {
19727 #[cfg_attr(
19728 any(target_arch = "aarch64", target_arch = "arm64ec"),
19729 link_name = "llvm.aarch64.neon.ld2r.v8f16.p0f16"
19730 )]
19731 fn _vld2q_dup_f16(ptr: *const f16) -> float16x8x2_t;
19732 }
19733 _vld2q_dup_f16(a as _)
19734}
19735#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
19737#[doc = "## Safety"]
19738#[doc = " * Neon instrinsic unsafe"]
19739#[inline]
19740#[target_feature(enable = "neon,v7")]
19741#[cfg(target_arch = "arm")]
19742#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19743#[cfg_attr(test, assert_instr(vld2))]
19744pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
19745 unsafe extern "unadjusted" {
19746 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2f32.p0")]
19747 fn _vld2_dup_f32(ptr: *const i8, size: i32) -> float32x2x2_t;
19748 }
19749 _vld2_dup_f32(a as *const i8, 4)
19750}
19751#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
19753#[doc = "## Safety"]
19754#[doc = " * Neon instrinsic unsafe"]
19755#[inline]
19756#[target_feature(enable = "neon,v7")]
19757#[cfg(target_arch = "arm")]
19758#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19759#[cfg_attr(test, assert_instr(vld2))]
19760pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
19761 unsafe extern "unadjusted" {
19762 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f32.p0")]
19763 fn _vld2q_dup_f32(ptr: *const i8, size: i32) -> float32x4x2_t;
19764 }
19765 _vld2q_dup_f32(a as *const i8, 4)
19766}
19767#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
19769#[doc = "## Safety"]
19770#[doc = " * Neon instrinsic unsafe"]
19771#[inline]
19772#[target_feature(enable = "neon,v7")]
19773#[cfg(target_arch = "arm")]
19774#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19775#[cfg_attr(test, assert_instr(vld2))]
19776pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
19777 unsafe extern "unadjusted" {
19778 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i8.p0")]
19779 fn _vld2_dup_s8(ptr: *const i8, size: i32) -> int8x8x2_t;
19780 }
19781 _vld2_dup_s8(a as *const i8, 1)
19782}
19783#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
19785#[doc = "## Safety"]
19786#[doc = " * Neon instrinsic unsafe"]
19787#[inline]
19788#[target_feature(enable = "neon,v7")]
19789#[cfg(target_arch = "arm")]
19790#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19791#[cfg_attr(test, assert_instr(vld2))]
19792pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
19793 unsafe extern "unadjusted" {
19794 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v16i8.p0")]
19795 fn _vld2q_dup_s8(ptr: *const i8, size: i32) -> int8x16x2_t;
19796 }
19797 _vld2q_dup_s8(a as *const i8, 1)
19798}
19799#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
19801#[doc = "## Safety"]
19802#[doc = " * Neon instrinsic unsafe"]
19803#[inline]
19804#[target_feature(enable = "neon,v7")]
19805#[cfg(target_arch = "arm")]
19806#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19807#[cfg_attr(test, assert_instr(vld2))]
19808pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
19809 unsafe extern "unadjusted" {
19810 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i16.p0")]
19811 fn _vld2_dup_s16(ptr: *const i8, size: i32) -> int16x4x2_t;
19812 }
19813 _vld2_dup_s16(a as *const i8, 2)
19814}
19815#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
19817#[doc = "## Safety"]
19818#[doc = " * Neon instrinsic unsafe"]
19819#[inline]
19820#[target_feature(enable = "neon,v7")]
19821#[cfg(target_arch = "arm")]
19822#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19823#[cfg_attr(test, assert_instr(vld2))]
19824pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
19825 unsafe extern "unadjusted" {
19826 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i16.p0")]
19827 fn _vld2q_dup_s16(ptr: *const i8, size: i32) -> int16x8x2_t;
19828 }
19829 _vld2q_dup_s16(a as *const i8, 2)
19830}
19831#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
19833#[doc = "## Safety"]
19834#[doc = " * Neon instrinsic unsafe"]
19835#[inline]
19836#[target_feature(enable = "neon,v7")]
19837#[cfg(target_arch = "arm")]
19838#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19839#[cfg_attr(test, assert_instr(vld2))]
19840pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
19841 unsafe extern "unadjusted" {
19842 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2i32.p0")]
19843 fn _vld2_dup_s32(ptr: *const i8, size: i32) -> int32x2x2_t;
19844 }
19845 _vld2_dup_s32(a as *const i8, 4)
19846}
19847#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
19849#[doc = "## Safety"]
19850#[doc = " * Neon instrinsic unsafe"]
19851#[inline]
19852#[target_feature(enable = "neon,v7")]
19853#[cfg(target_arch = "arm")]
19854#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19855#[cfg_attr(test, assert_instr(vld2))]
19856pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
19857 unsafe extern "unadjusted" {
19858 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i32.p0")]
19859 fn _vld2q_dup_s32(ptr: *const i8, size: i32) -> int32x4x2_t;
19860 }
19861 _vld2q_dup_s32(a as *const i8, 4)
19862}
19863#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
19865#[doc = "## Safety"]
19866#[doc = " * Neon instrinsic unsafe"]
19867#[inline]
19868#[target_feature(enable = "neon")]
19869#[cfg(not(target_arch = "arm"))]
19870#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19871#[cfg_attr(test, assert_instr(ld2r))]
19872pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
19873 unsafe extern "unadjusted" {
19874 #[cfg_attr(
19875 any(target_arch = "aarch64", target_arch = "arm64ec"),
19876 link_name = "llvm.aarch64.neon.ld2r.v2f32.p0"
19877 )]
19878 fn _vld2_dup_f32(ptr: *const f32) -> float32x2x2_t;
19879 }
19880 _vld2_dup_f32(a as _)
19881}
19882#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
19884#[doc = "## Safety"]
19885#[doc = " * Neon instrinsic unsafe"]
19886#[inline]
19887#[target_feature(enable = "neon")]
19888#[cfg(not(target_arch = "arm"))]
19889#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19890#[cfg_attr(test, assert_instr(ld2r))]
19891pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
19892 unsafe extern "unadjusted" {
19893 #[cfg_attr(
19894 any(target_arch = "aarch64", target_arch = "arm64ec"),
19895 link_name = "llvm.aarch64.neon.ld2r.v4f32.p0"
19896 )]
19897 fn _vld2q_dup_f32(ptr: *const f32) -> float32x4x2_t;
19898 }
19899 _vld2q_dup_f32(a as _)
19900}
19901#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
19903#[doc = "## Safety"]
19904#[doc = " * Neon instrinsic unsafe"]
19905#[inline]
19906#[target_feature(enable = "neon")]
19907#[cfg(not(target_arch = "arm"))]
19908#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19909#[cfg_attr(test, assert_instr(ld2r))]
19910pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
19911 unsafe extern "unadjusted" {
19912 #[cfg_attr(
19913 any(target_arch = "aarch64", target_arch = "arm64ec"),
19914 link_name = "llvm.aarch64.neon.ld2r.v8i8.p0"
19915 )]
19916 fn _vld2_dup_s8(ptr: *const i8) -> int8x8x2_t;
19917 }
19918 _vld2_dup_s8(a as _)
19919}
19920#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
19922#[doc = "## Safety"]
19923#[doc = " * Neon instrinsic unsafe"]
19924#[inline]
19925#[target_feature(enable = "neon")]
19926#[cfg(not(target_arch = "arm"))]
19927#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19928#[cfg_attr(test, assert_instr(ld2r))]
19929pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
19930 unsafe extern "unadjusted" {
19931 #[cfg_attr(
19932 any(target_arch = "aarch64", target_arch = "arm64ec"),
19933 link_name = "llvm.aarch64.neon.ld2r.v16i8.p0"
19934 )]
19935 fn _vld2q_dup_s8(ptr: *const i8) -> int8x16x2_t;
19936 }
19937 _vld2q_dup_s8(a as _)
19938}
19939#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
19941#[doc = "## Safety"]
19942#[doc = " * Neon instrinsic unsafe"]
19943#[inline]
19944#[target_feature(enable = "neon")]
19945#[cfg(not(target_arch = "arm"))]
19946#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19947#[cfg_attr(test, assert_instr(ld2r))]
19948pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
19949 unsafe extern "unadjusted" {
19950 #[cfg_attr(
19951 any(target_arch = "aarch64", target_arch = "arm64ec"),
19952 link_name = "llvm.aarch64.neon.ld2r.v4i16.p0"
19953 )]
19954 fn _vld2_dup_s16(ptr: *const i16) -> int16x4x2_t;
19955 }
19956 _vld2_dup_s16(a as _)
19957}
19958#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
19960#[doc = "## Safety"]
19961#[doc = " * Neon instrinsic unsafe"]
19962#[inline]
19963#[target_feature(enable = "neon")]
19964#[cfg(not(target_arch = "arm"))]
19965#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19966#[cfg_attr(test, assert_instr(ld2r))]
19967pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
19968 unsafe extern "unadjusted" {
19969 #[cfg_attr(
19970 any(target_arch = "aarch64", target_arch = "arm64ec"),
19971 link_name = "llvm.aarch64.neon.ld2r.v8i16.p0"
19972 )]
19973 fn _vld2q_dup_s16(ptr: *const i16) -> int16x8x2_t;
19974 }
19975 _vld2q_dup_s16(a as _)
19976}
19977#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
19979#[doc = "## Safety"]
19980#[doc = " * Neon instrinsic unsafe"]
19981#[inline]
19982#[target_feature(enable = "neon")]
19983#[cfg(not(target_arch = "arm"))]
19984#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19985#[cfg_attr(test, assert_instr(ld2r))]
19986pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
19987 unsafe extern "unadjusted" {
19988 #[cfg_attr(
19989 any(target_arch = "aarch64", target_arch = "arm64ec"),
19990 link_name = "llvm.aarch64.neon.ld2r.v2i32.p0"
19991 )]
19992 fn _vld2_dup_s32(ptr: *const i32) -> int32x2x2_t;
19993 }
19994 _vld2_dup_s32(a as _)
19995}
19996#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
19998#[doc = "## Safety"]
19999#[doc = " * Neon instrinsic unsafe"]
20000#[inline]
20001#[target_feature(enable = "neon")]
20002#[cfg(not(target_arch = "arm"))]
20003#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20004#[cfg_attr(test, assert_instr(ld2r))]
20005pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
20006 unsafe extern "unadjusted" {
20007 #[cfg_attr(
20008 any(target_arch = "aarch64", target_arch = "arm64ec"),
20009 link_name = "llvm.aarch64.neon.ld2r.v4i32.p0"
20010 )]
20011 fn _vld2q_dup_s32(ptr: *const i32) -> int32x4x2_t;
20012 }
20013 _vld2q_dup_s32(a as _)
20014}
20015#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"]
20017#[doc = "## Safety"]
20018#[doc = " * Neon instrinsic unsafe"]
20019#[inline]
20020#[target_feature(enable = "neon,aes")]
20021#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
20022#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
20023#[cfg_attr(
20024 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20025 assert_instr(ld2r)
20026)]
20027#[cfg_attr(
20028 not(target_arch = "arm"),
20029 stable(feature = "neon_intrinsics", since = "1.59.0")
20030)]
20031#[cfg_attr(
20032 target_arch = "arm",
20033 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20034)]
20035pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t {
20036 transmute(vld2_dup_s64(transmute(a)))
20037}
20038#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20039#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
20040#[doc = "## Safety"]
20041#[doc = " * Neon instrinsic unsafe"]
20042#[inline]
20043#[target_feature(enable = "neon,v7")]
20044#[cfg(target_arch = "arm")]
20045#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20046#[cfg_attr(test, assert_instr(nop))]
20047pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
20048 unsafe extern "unadjusted" {
20049 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v1i64.p0")]
20050 fn _vld2_dup_s64(ptr: *const i8, size: i32) -> int64x1x2_t;
20051 }
20052 _vld2_dup_s64(a as *const i8, 8)
20053}
20054#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
20056#[doc = "## Safety"]
20057#[doc = " * Neon instrinsic unsafe"]
20058#[inline]
20059#[target_feature(enable = "neon")]
20060#[cfg(not(target_arch = "arm"))]
20061#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20062#[cfg_attr(test, assert_instr(ld2r))]
20063pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
20064 unsafe extern "unadjusted" {
20065 #[cfg_attr(
20066 any(target_arch = "aarch64", target_arch = "arm64ec"),
20067 link_name = "llvm.aarch64.neon.ld2r.v1i64.p0"
20068 )]
20069 fn _vld2_dup_s64(ptr: *const i64) -> int64x1x2_t;
20070 }
20071 _vld2_dup_s64(a as _)
20072}
20073#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"]
20075#[doc = "## Safety"]
20076#[doc = " * Neon instrinsic unsafe"]
20077#[inline]
20078#[target_feature(enable = "neon")]
20079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20080#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
20081#[cfg_attr(
20082 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20083 assert_instr(ld2r)
20084)]
20085#[cfg_attr(
20086 not(target_arch = "arm"),
20087 stable(feature = "neon_intrinsics", since = "1.59.0")
20088)]
20089#[cfg_attr(
20090 target_arch = "arm",
20091 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20092)]
20093pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t {
20094 transmute(vld2_dup_s64(transmute(a)))
20095}
20096#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
20098#[doc = "## Safety"]
20099#[doc = " * Neon instrinsic unsafe"]
20100#[inline]
20101#[cfg(target_endian = "little")]
20102#[target_feature(enable = "neon")]
20103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20105#[cfg_attr(
20106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20107 assert_instr(ld2r)
20108)]
20109#[cfg_attr(
20110 not(target_arch = "arm"),
20111 stable(feature = "neon_intrinsics", since = "1.59.0")
20112)]
20113#[cfg_attr(
20114 target_arch = "arm",
20115 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20116)]
20117pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
20118 transmute(vld2_dup_s8(transmute(a)))
20119}
20120#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
20122#[doc = "## Safety"]
20123#[doc = " * Neon instrinsic unsafe"]
20124#[inline]
20125#[cfg(target_endian = "big")]
20126#[target_feature(enable = "neon")]
20127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20128#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20129#[cfg_attr(
20130 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20131 assert_instr(ld2r)
20132)]
20133#[cfg_attr(
20134 not(target_arch = "arm"),
20135 stable(feature = "neon_intrinsics", since = "1.59.0")
20136)]
20137#[cfg_attr(
20138 target_arch = "arm",
20139 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20140)]
20141pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
20142 let mut ret_val: uint8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
20143 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20144 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20145 ret_val
20146}
20147#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
20149#[doc = "## Safety"]
20150#[doc = " * Neon instrinsic unsafe"]
20151#[inline]
20152#[cfg(target_endian = "little")]
20153#[target_feature(enable = "neon")]
20154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20155#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20156#[cfg_attr(
20157 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20158 assert_instr(ld2r)
20159)]
20160#[cfg_attr(
20161 not(target_arch = "arm"),
20162 stable(feature = "neon_intrinsics", since = "1.59.0")
20163)]
20164#[cfg_attr(
20165 target_arch = "arm",
20166 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20167)]
20168pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
20169 transmute(vld2q_dup_s8(transmute(a)))
20170}
20171#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
20173#[doc = "## Safety"]
20174#[doc = " * Neon instrinsic unsafe"]
20175#[inline]
20176#[cfg(target_endian = "big")]
20177#[target_feature(enable = "neon")]
20178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20180#[cfg_attr(
20181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20182 assert_instr(ld2r)
20183)]
20184#[cfg_attr(
20185 not(target_arch = "arm"),
20186 stable(feature = "neon_intrinsics", since = "1.59.0")
20187)]
20188#[cfg_attr(
20189 target_arch = "arm",
20190 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20191)]
20192pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
20193 let mut ret_val: uint8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
20194 ret_val.0 = unsafe {
20195 simd_shuffle!(
20196 ret_val.0,
20197 ret_val.0,
20198 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20199 )
20200 };
20201 ret_val.1 = unsafe {
20202 simd_shuffle!(
20203 ret_val.1,
20204 ret_val.1,
20205 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20206 )
20207 };
20208 ret_val
20209}
20210#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
20212#[doc = "## Safety"]
20213#[doc = " * Neon instrinsic unsafe"]
20214#[inline]
20215#[cfg(target_endian = "little")]
20216#[target_feature(enable = "neon")]
20217#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20218#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20219#[cfg_attr(
20220 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20221 assert_instr(ld2r)
20222)]
20223#[cfg_attr(
20224 not(target_arch = "arm"),
20225 stable(feature = "neon_intrinsics", since = "1.59.0")
20226)]
20227#[cfg_attr(
20228 target_arch = "arm",
20229 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20230)]
20231pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
20232 transmute(vld2_dup_s16(transmute(a)))
20233}
20234#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
20236#[doc = "## Safety"]
20237#[doc = " * Neon instrinsic unsafe"]
20238#[inline]
20239#[cfg(target_endian = "big")]
20240#[target_feature(enable = "neon")]
20241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20243#[cfg_attr(
20244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20245 assert_instr(ld2r)
20246)]
20247#[cfg_attr(
20248 not(target_arch = "arm"),
20249 stable(feature = "neon_intrinsics", since = "1.59.0")
20250)]
20251#[cfg_attr(
20252 target_arch = "arm",
20253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20254)]
20255pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
20256 let mut ret_val: uint16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
20257 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20258 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20259 ret_val
20260}
20261#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
20263#[doc = "## Safety"]
20264#[doc = " * Neon instrinsic unsafe"]
20265#[inline]
20266#[cfg(target_endian = "little")]
20267#[target_feature(enable = "neon")]
20268#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20269#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20270#[cfg_attr(
20271 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20272 assert_instr(ld2r)
20273)]
20274#[cfg_attr(
20275 not(target_arch = "arm"),
20276 stable(feature = "neon_intrinsics", since = "1.59.0")
20277)]
20278#[cfg_attr(
20279 target_arch = "arm",
20280 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20281)]
20282pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
20283 transmute(vld2q_dup_s16(transmute(a)))
20284}
20285#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
20287#[doc = "## Safety"]
20288#[doc = " * Neon instrinsic unsafe"]
20289#[inline]
20290#[cfg(target_endian = "big")]
20291#[target_feature(enable = "neon")]
20292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20293#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20294#[cfg_attr(
20295 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20296 assert_instr(ld2r)
20297)]
20298#[cfg_attr(
20299 not(target_arch = "arm"),
20300 stable(feature = "neon_intrinsics", since = "1.59.0")
20301)]
20302#[cfg_attr(
20303 target_arch = "arm",
20304 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20305)]
20306pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
20307 let mut ret_val: uint16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
20308 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20309 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20310 ret_val
20311}
20312#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
20314#[doc = "## Safety"]
20315#[doc = " * Neon instrinsic unsafe"]
20316#[inline]
20317#[cfg(target_endian = "little")]
20318#[target_feature(enable = "neon")]
20319#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20320#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20321#[cfg_attr(
20322 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20323 assert_instr(ld2r)
20324)]
20325#[cfg_attr(
20326 not(target_arch = "arm"),
20327 stable(feature = "neon_intrinsics", since = "1.59.0")
20328)]
20329#[cfg_attr(
20330 target_arch = "arm",
20331 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20332)]
20333pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
20334 transmute(vld2_dup_s32(transmute(a)))
20335}
20336#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
20338#[doc = "## Safety"]
20339#[doc = " * Neon instrinsic unsafe"]
20340#[inline]
20341#[cfg(target_endian = "big")]
20342#[target_feature(enable = "neon")]
20343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20344#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20345#[cfg_attr(
20346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20347 assert_instr(ld2r)
20348)]
20349#[cfg_attr(
20350 not(target_arch = "arm"),
20351 stable(feature = "neon_intrinsics", since = "1.59.0")
20352)]
20353#[cfg_attr(
20354 target_arch = "arm",
20355 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20356)]
20357pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
20358 let mut ret_val: uint32x2x2_t = transmute(vld2_dup_s32(transmute(a)));
20359 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
20360 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
20361 ret_val
20362}
20363#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
20365#[doc = "## Safety"]
20366#[doc = " * Neon instrinsic unsafe"]
20367#[inline]
20368#[cfg(target_endian = "little")]
20369#[target_feature(enable = "neon")]
20370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20371#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20372#[cfg_attr(
20373 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20374 assert_instr(ld2r)
20375)]
20376#[cfg_attr(
20377 not(target_arch = "arm"),
20378 stable(feature = "neon_intrinsics", since = "1.59.0")
20379)]
20380#[cfg_attr(
20381 target_arch = "arm",
20382 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20383)]
20384pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
20385 transmute(vld2q_dup_s32(transmute(a)))
20386}
20387#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
20389#[doc = "## Safety"]
20390#[doc = " * Neon instrinsic unsafe"]
20391#[inline]
20392#[cfg(target_endian = "big")]
20393#[target_feature(enable = "neon")]
20394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20396#[cfg_attr(
20397 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20398 assert_instr(ld2r)
20399)]
20400#[cfg_attr(
20401 not(target_arch = "arm"),
20402 stable(feature = "neon_intrinsics", since = "1.59.0")
20403)]
20404#[cfg_attr(
20405 target_arch = "arm",
20406 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20407)]
20408pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
20409 let mut ret_val: uint32x4x2_t = transmute(vld2q_dup_s32(transmute(a)));
20410 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20411 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20412 ret_val
20413}
20414#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
20416#[doc = "## Safety"]
20417#[doc = " * Neon instrinsic unsafe"]
20418#[inline]
20419#[cfg(target_endian = "little")]
20420#[target_feature(enable = "neon")]
20421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20423#[cfg_attr(
20424 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20425 assert_instr(ld2r)
20426)]
20427#[cfg_attr(
20428 not(target_arch = "arm"),
20429 stable(feature = "neon_intrinsics", since = "1.59.0")
20430)]
20431#[cfg_attr(
20432 target_arch = "arm",
20433 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20434)]
20435pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
20436 transmute(vld2_dup_s8(transmute(a)))
20437}
20438#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
20440#[doc = "## Safety"]
20441#[doc = " * Neon instrinsic unsafe"]
20442#[inline]
20443#[cfg(target_endian = "big")]
20444#[target_feature(enable = "neon")]
20445#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20446#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20447#[cfg_attr(
20448 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20449 assert_instr(ld2r)
20450)]
20451#[cfg_attr(
20452 not(target_arch = "arm"),
20453 stable(feature = "neon_intrinsics", since = "1.59.0")
20454)]
20455#[cfg_attr(
20456 target_arch = "arm",
20457 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20458)]
20459pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
20460 let mut ret_val: poly8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
20461 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20462 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20463 ret_val
20464}
20465#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
20467#[doc = "## Safety"]
20468#[doc = " * Neon instrinsic unsafe"]
20469#[inline]
20470#[cfg(target_endian = "little")]
20471#[target_feature(enable = "neon")]
20472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20474#[cfg_attr(
20475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20476 assert_instr(ld2r)
20477)]
20478#[cfg_attr(
20479 not(target_arch = "arm"),
20480 stable(feature = "neon_intrinsics", since = "1.59.0")
20481)]
20482#[cfg_attr(
20483 target_arch = "arm",
20484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20485)]
20486pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
20487 transmute(vld2q_dup_s8(transmute(a)))
20488}
20489#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
20491#[doc = "## Safety"]
20492#[doc = " * Neon instrinsic unsafe"]
20493#[inline]
20494#[cfg(target_endian = "big")]
20495#[target_feature(enable = "neon")]
20496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20497#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20498#[cfg_attr(
20499 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20500 assert_instr(ld2r)
20501)]
20502#[cfg_attr(
20503 not(target_arch = "arm"),
20504 stable(feature = "neon_intrinsics", since = "1.59.0")
20505)]
20506#[cfg_attr(
20507 target_arch = "arm",
20508 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20509)]
20510pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
20511 let mut ret_val: poly8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
20512 ret_val.0 = unsafe {
20513 simd_shuffle!(
20514 ret_val.0,
20515 ret_val.0,
20516 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20517 )
20518 };
20519 ret_val.1 = unsafe {
20520 simd_shuffle!(
20521 ret_val.1,
20522 ret_val.1,
20523 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20524 )
20525 };
20526 ret_val
20527}
20528#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
20530#[doc = "## Safety"]
20531#[doc = " * Neon instrinsic unsafe"]
20532#[inline]
20533#[cfg(target_endian = "little")]
20534#[target_feature(enable = "neon")]
20535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20536#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20537#[cfg_attr(
20538 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20539 assert_instr(ld2r)
20540)]
20541#[cfg_attr(
20542 not(target_arch = "arm"),
20543 stable(feature = "neon_intrinsics", since = "1.59.0")
20544)]
20545#[cfg_attr(
20546 target_arch = "arm",
20547 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20548)]
20549pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
20550 transmute(vld2_dup_s16(transmute(a)))
20551}
20552#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
20554#[doc = "## Safety"]
20555#[doc = " * Neon instrinsic unsafe"]
20556#[inline]
20557#[cfg(target_endian = "big")]
20558#[target_feature(enable = "neon")]
20559#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20560#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20561#[cfg_attr(
20562 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20563 assert_instr(ld2r)
20564)]
20565#[cfg_attr(
20566 not(target_arch = "arm"),
20567 stable(feature = "neon_intrinsics", since = "1.59.0")
20568)]
20569#[cfg_attr(
20570 target_arch = "arm",
20571 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20572)]
20573pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
20574 let mut ret_val: poly16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
20575 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20576 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20577 ret_val
20578}
20579#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
20581#[doc = "## Safety"]
20582#[doc = " * Neon instrinsic unsafe"]
20583#[inline]
20584#[cfg(target_endian = "little")]
20585#[target_feature(enable = "neon")]
20586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20588#[cfg_attr(
20589 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20590 assert_instr(ld2r)
20591)]
20592#[cfg_attr(
20593 not(target_arch = "arm"),
20594 stable(feature = "neon_intrinsics", since = "1.59.0")
20595)]
20596#[cfg_attr(
20597 target_arch = "arm",
20598 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20599)]
20600pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
20601 transmute(vld2q_dup_s16(transmute(a)))
20602}
20603#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
20605#[doc = "## Safety"]
20606#[doc = " * Neon instrinsic unsafe"]
20607#[inline]
20608#[cfg(target_endian = "big")]
20609#[target_feature(enable = "neon")]
20610#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20611#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20612#[cfg_attr(
20613 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20614 assert_instr(ld2r)
20615)]
20616#[cfg_attr(
20617 not(target_arch = "arm"),
20618 stable(feature = "neon_intrinsics", since = "1.59.0")
20619)]
20620#[cfg_attr(
20621 target_arch = "arm",
20622 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20623)]
20624pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
20625 let mut ret_val: poly16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
20626 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20627 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20628 ret_val
20629}
20630#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
20632#[doc = "## Safety"]
20633#[doc = " * Neon instrinsic unsafe"]
20634#[inline]
20635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20636#[cfg(target_arch = "arm")]
20637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20638#[target_feature(enable = "neon,fp16")]
20639#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20640pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
20641 unsafe extern "unadjusted" {
20642 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f16.p0f16")]
20643 fn _vld2_f16(ptr: *const f16, size: i32) -> float16x4x2_t;
20644 }
20645 _vld2_f16(a as _, 2)
20646}
20647#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
20649#[doc = "## Safety"]
20650#[doc = " * Neon instrinsic unsafe"]
20651#[inline]
20652#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20653#[cfg(target_arch = "arm")]
20654#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20655#[target_feature(enable = "neon,fp16")]
20656#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20657pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
20658 unsafe extern "unadjusted" {
20659 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8f16.p0f16")]
20660 fn _vld2q_f16(ptr: *const f16, size: i32) -> float16x8x2_t;
20661 }
20662 _vld2q_f16(a as _, 2)
20663}
20664#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
20666#[doc = "## Safety"]
20667#[doc = " * Neon instrinsic unsafe"]
20668#[inline]
20669#[cfg(not(target_arch = "arm"))]
20670#[cfg_attr(
20671 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20672 assert_instr(ld2)
20673)]
20674#[target_feature(enable = "neon,fp16")]
20675#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20676pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
20677 unsafe extern "unadjusted" {
20678 #[cfg_attr(
20679 any(target_arch = "aarch64", target_arch = "arm64ec"),
20680 link_name = "llvm.aarch64.neon.ld2.v4f16.p0f16"
20681 )]
20682 fn _vld2_f16(ptr: *const f16) -> float16x4x2_t;
20683 }
20684 _vld2_f16(a as _)
20685}
20686#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
20688#[doc = "## Safety"]
20689#[doc = " * Neon instrinsic unsafe"]
20690#[inline]
20691#[cfg(not(target_arch = "arm"))]
20692#[cfg_attr(
20693 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20694 assert_instr(ld2)
20695)]
20696#[target_feature(enable = "neon,fp16")]
20697#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20698pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
20699 unsafe extern "unadjusted" {
20700 #[cfg_attr(
20701 any(target_arch = "aarch64", target_arch = "arm64ec"),
20702 link_name = "llvm.aarch64.neon.ld2.v8f16.p0f16"
20703 )]
20704 fn _vld2q_f16(ptr: *const f16) -> float16x8x2_t;
20705 }
20706 _vld2q_f16(a as _)
20707}
20708#[doc = "Load multiple 2-element structures to two registers"]
20709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
20710#[doc = "## Safety"]
20711#[doc = " * Neon instrinsic unsafe"]
20712#[inline]
20713#[target_feature(enable = "neon,v7")]
20714#[cfg(target_arch = "arm")]
20715#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20716#[cfg_attr(test, assert_instr(vld2))]
20717pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
20718 unsafe extern "unadjusted" {
20719 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2f32")]
20720 fn _vld2_f32(ptr: *const i8, size: i32) -> float32x2x2_t;
20721 }
20722 _vld2_f32(a as *const i8, 4)
20723}
20724#[doc = "Load multiple 2-element structures to two registers"]
20725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
20726#[doc = "## Safety"]
20727#[doc = " * Neon instrinsic unsafe"]
20728#[inline]
20729#[target_feature(enable = "neon,v7")]
20730#[cfg(target_arch = "arm")]
20731#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20732#[cfg_attr(test, assert_instr(vld2))]
20733pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
20734 unsafe extern "unadjusted" {
20735 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f32")]
20736 fn _vld2q_f32(ptr: *const i8, size: i32) -> float32x4x2_t;
20737 }
20738 _vld2q_f32(a as *const i8, 4)
20739}
20740#[doc = "Load multiple 2-element structures to two registers"]
20741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
20742#[doc = "## Safety"]
20743#[doc = " * Neon instrinsic unsafe"]
20744#[inline]
20745#[target_feature(enable = "neon,v7")]
20746#[cfg(target_arch = "arm")]
20747#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20748#[cfg_attr(test, assert_instr(vld2))]
20749pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
20750 unsafe extern "unadjusted" {
20751 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i8")]
20752 fn _vld2_s8(ptr: *const i8, size: i32) -> int8x8x2_t;
20753 }
20754 _vld2_s8(a as *const i8, 1)
20755}
20756#[doc = "Load multiple 2-element structures to two registers"]
20757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
20758#[doc = "## Safety"]
20759#[doc = " * Neon instrinsic unsafe"]
20760#[inline]
20761#[target_feature(enable = "neon,v7")]
20762#[cfg(target_arch = "arm")]
20763#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20764#[cfg_attr(test, assert_instr(vld2))]
20765pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
20766 unsafe extern "unadjusted" {
20767 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v16i8")]
20768 fn _vld2q_s8(ptr: *const i8, size: i32) -> int8x16x2_t;
20769 }
20770 _vld2q_s8(a as *const i8, 1)
20771}
20772#[doc = "Load multiple 2-element structures to two registers"]
20773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
20774#[doc = "## Safety"]
20775#[doc = " * Neon instrinsic unsafe"]
20776#[inline]
20777#[target_feature(enable = "neon,v7")]
20778#[cfg(target_arch = "arm")]
20779#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20780#[cfg_attr(test, assert_instr(vld2))]
20781pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
20782 unsafe extern "unadjusted" {
20783 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i16")]
20784 fn _vld2_s16(ptr: *const i8, size: i32) -> int16x4x2_t;
20785 }
20786 _vld2_s16(a as *const i8, 2)
20787}
20788#[doc = "Load multiple 2-element structures to two registers"]
20789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
20790#[doc = "## Safety"]
20791#[doc = " * Neon instrinsic unsafe"]
20792#[inline]
20793#[target_feature(enable = "neon,v7")]
20794#[cfg(target_arch = "arm")]
20795#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20796#[cfg_attr(test, assert_instr(vld2))]
20797pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
20798 unsafe extern "unadjusted" {
20799 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i16")]
20800 fn _vld2q_s16(ptr: *const i8, size: i32) -> int16x8x2_t;
20801 }
20802 _vld2q_s16(a as *const i8, 2)
20803}
20804#[doc = "Load multiple 2-element structures to two registers"]
20805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
20806#[doc = "## Safety"]
20807#[doc = " * Neon instrinsic unsafe"]
20808#[inline]
20809#[target_feature(enable = "neon,v7")]
20810#[cfg(target_arch = "arm")]
20811#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20812#[cfg_attr(test, assert_instr(vld2))]
20813pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
20814 unsafe extern "unadjusted" {
20815 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2i32")]
20816 fn _vld2_s32(ptr: *const i8, size: i32) -> int32x2x2_t;
20817 }
20818 _vld2_s32(a as *const i8, 4)
20819}
20820#[doc = "Load multiple 2-element structures to two registers"]
20821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
20822#[doc = "## Safety"]
20823#[doc = " * Neon instrinsic unsafe"]
20824#[inline]
20825#[target_feature(enable = "neon,v7")]
20826#[cfg(target_arch = "arm")]
20827#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20828#[cfg_attr(test, assert_instr(vld2))]
20829pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
20830 unsafe extern "unadjusted" {
20831 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i32")]
20832 fn _vld2q_s32(ptr: *const i8, size: i32) -> int32x4x2_t;
20833 }
20834 _vld2q_s32(a as *const i8, 4)
20835}
20836#[doc = "Load multiple 2-element structures to two registers"]
20837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
20838#[doc = "## Safety"]
20839#[doc = " * Neon instrinsic unsafe"]
20840#[inline]
20841#[target_feature(enable = "neon")]
20842#[cfg(not(target_arch = "arm"))]
20843#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20844#[cfg_attr(test, assert_instr(ld2))]
20845pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
20846 unsafe extern "unadjusted" {
20847 #[cfg_attr(
20848 any(target_arch = "aarch64", target_arch = "arm64ec"),
20849 link_name = "llvm.aarch64.neon.ld2.v2f32.p0"
20850 )]
20851 fn _vld2_f32(ptr: *const float32x2_t) -> float32x2x2_t;
20852 }
20853 _vld2_f32(a as _)
20854}
20855#[doc = "Load multiple 2-element structures to two registers"]
20856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
20857#[doc = "## Safety"]
20858#[doc = " * Neon instrinsic unsafe"]
20859#[inline]
20860#[target_feature(enable = "neon")]
20861#[cfg(not(target_arch = "arm"))]
20862#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20863#[cfg_attr(test, assert_instr(ld2))]
20864pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
20865 unsafe extern "unadjusted" {
20866 #[cfg_attr(
20867 any(target_arch = "aarch64", target_arch = "arm64ec"),
20868 link_name = "llvm.aarch64.neon.ld2.v4f32.p0"
20869 )]
20870 fn _vld2q_f32(ptr: *const float32x4_t) -> float32x4x2_t;
20871 }
20872 _vld2q_f32(a as _)
20873}
20874#[doc = "Load multiple 2-element structures to two registers"]
20875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
20876#[doc = "## Safety"]
20877#[doc = " * Neon instrinsic unsafe"]
20878#[inline]
20879#[target_feature(enable = "neon")]
20880#[cfg(not(target_arch = "arm"))]
20881#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20882#[cfg_attr(test, assert_instr(ld2))]
20883pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
20884 unsafe extern "unadjusted" {
20885 #[cfg_attr(
20886 any(target_arch = "aarch64", target_arch = "arm64ec"),
20887 link_name = "llvm.aarch64.neon.ld2.v8i8.p0"
20888 )]
20889 fn _vld2_s8(ptr: *const int8x8_t) -> int8x8x2_t;
20890 }
20891 _vld2_s8(a as _)
20892}
20893#[doc = "Load multiple 2-element structures to two registers"]
20894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
20895#[doc = "## Safety"]
20896#[doc = " * Neon instrinsic unsafe"]
20897#[inline]
20898#[target_feature(enable = "neon")]
20899#[cfg(not(target_arch = "arm"))]
20900#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20901#[cfg_attr(test, assert_instr(ld2))]
20902pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
20903 unsafe extern "unadjusted" {
20904 #[cfg_attr(
20905 any(target_arch = "aarch64", target_arch = "arm64ec"),
20906 link_name = "llvm.aarch64.neon.ld2.v16i8.p0"
20907 )]
20908 fn _vld2q_s8(ptr: *const int8x16_t) -> int8x16x2_t;
20909 }
20910 _vld2q_s8(a as _)
20911}
20912#[doc = "Load multiple 2-element structures to two registers"]
20913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
20914#[doc = "## Safety"]
20915#[doc = " * Neon instrinsic unsafe"]
20916#[inline]
20917#[target_feature(enable = "neon")]
20918#[cfg(not(target_arch = "arm"))]
20919#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20920#[cfg_attr(test, assert_instr(ld2))]
20921pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
20922 unsafe extern "unadjusted" {
20923 #[cfg_attr(
20924 any(target_arch = "aarch64", target_arch = "arm64ec"),
20925 link_name = "llvm.aarch64.neon.ld2.v4i16.p0"
20926 )]
20927 fn _vld2_s16(ptr: *const int16x4_t) -> int16x4x2_t;
20928 }
20929 _vld2_s16(a as _)
20930}
20931#[doc = "Load multiple 2-element structures to two registers"]
20932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
20933#[doc = "## Safety"]
20934#[doc = " * Neon instrinsic unsafe"]
20935#[inline]
20936#[target_feature(enable = "neon")]
20937#[cfg(not(target_arch = "arm"))]
20938#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20939#[cfg_attr(test, assert_instr(ld2))]
20940pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
20941 unsafe extern "unadjusted" {
20942 #[cfg_attr(
20943 any(target_arch = "aarch64", target_arch = "arm64ec"),
20944 link_name = "llvm.aarch64.neon.ld2.v8i16.p0"
20945 )]
20946 fn _vld2q_s16(ptr: *const int16x8_t) -> int16x8x2_t;
20947 }
20948 _vld2q_s16(a as _)
20949}
20950#[doc = "Load multiple 2-element structures to two registers"]
20951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
20952#[doc = "## Safety"]
20953#[doc = " * Neon instrinsic unsafe"]
20954#[inline]
20955#[target_feature(enable = "neon")]
20956#[cfg(not(target_arch = "arm"))]
20957#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20958#[cfg_attr(test, assert_instr(ld2))]
20959pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
20960 unsafe extern "unadjusted" {
20961 #[cfg_attr(
20962 any(target_arch = "aarch64", target_arch = "arm64ec"),
20963 link_name = "llvm.aarch64.neon.ld2.v2i32.p0"
20964 )]
20965 fn _vld2_s32(ptr: *const int32x2_t) -> int32x2x2_t;
20966 }
20967 _vld2_s32(a as _)
20968}
20969#[doc = "Load multiple 2-element structures to two registers"]
20970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
20971#[doc = "## Safety"]
20972#[doc = " * Neon instrinsic unsafe"]
20973#[inline]
20974#[target_feature(enable = "neon")]
20975#[cfg(not(target_arch = "arm"))]
20976#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20977#[cfg_attr(test, assert_instr(ld2))]
20978pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
20979 unsafe extern "unadjusted" {
20980 #[cfg_attr(
20981 any(target_arch = "aarch64", target_arch = "arm64ec"),
20982 link_name = "llvm.aarch64.neon.ld2.v4i32.p0"
20983 )]
20984 fn _vld2q_s32(ptr: *const int32x4_t) -> int32x4x2_t;
20985 }
20986 _vld2q_s32(a as _)
20987}
20988#[doc = "Load multiple 2-element structures to two registers"]
20989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
20990#[doc = "## Safety"]
20991#[doc = " * Neon instrinsic unsafe"]
20992#[inline]
20993#[target_feature(enable = "neon,v7")]
20994#[cfg(target_arch = "arm")]
20995#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
20996#[rustc_legacy_const_generics(2)]
20997#[target_feature(enable = "neon,fp16")]
20998#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20999pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
21000 static_assert_uimm_bits!(LANE, 2);
21001 unsafe extern "unadjusted" {
21002 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f16.p0")]
21003 fn _vld2_lane_f16(
21004 ptr: *const f16,
21005 a: float16x4_t,
21006 b: float16x4_t,
21007 n: i32,
21008 size: i32,
21009 ) -> float16x4x2_t;
21010 }
21011 _vld2_lane_f16(a as _, b.0, b.1, LANE, 2)
21012}
21013#[doc = "Load multiple 2-element structures to two registers"]
21014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
21015#[doc = "## Safety"]
21016#[doc = " * Neon instrinsic unsafe"]
21017#[inline]
21018#[target_feature(enable = "neon,v7")]
21019#[cfg(target_arch = "arm")]
21020#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21021#[rustc_legacy_const_generics(2)]
21022#[target_feature(enable = "neon,fp16")]
21023#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21024pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
21025 static_assert_uimm_bits!(LANE, 3);
21026 unsafe extern "unadjusted" {
21027 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8f16.p0")]
21028 fn _vld2q_lane_f16(
21029 ptr: *const f16,
21030 a: float16x8_t,
21031 b: float16x8_t,
21032 n: i32,
21033 size: i32,
21034 ) -> float16x8x2_t;
21035 }
21036 _vld2q_lane_f16(a as _, b.0, b.1, LANE, 2)
21037}
21038#[doc = "Load multiple 2-element structures to two registers"]
21039#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
21040#[doc = "## Safety"]
21041#[doc = " * Neon instrinsic unsafe"]
21042#[inline]
21043#[cfg(not(target_arch = "arm"))]
21044#[cfg_attr(
21045 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21046 assert_instr(ld2, LANE = 0)
21047)]
21048#[rustc_legacy_const_generics(2)]
21049#[target_feature(enable = "neon,fp16")]
21050#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21051pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
21052 static_assert_uimm_bits!(LANE, 2);
21053 unsafe extern "unadjusted" {
21054 #[cfg_attr(
21055 any(target_arch = "aarch64", target_arch = "arm64ec"),
21056 link_name = "llvm.aarch64.neon.ld2lane.v4f16.p0"
21057 )]
21058 fn _vld2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *const f16)
21059 -> float16x4x2_t;
21060 }
21061 _vld2_lane_f16(b.0, b.1, LANE as i64, a as _)
21062}
21063#[doc = "Load multiple 2-element structures to two registers"]
21064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
21065#[doc = "## Safety"]
21066#[doc = " * Neon instrinsic unsafe"]
21067#[inline]
21068#[cfg(not(target_arch = "arm"))]
21069#[cfg_attr(
21070 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21071 assert_instr(ld2, LANE = 0)
21072)]
21073#[rustc_legacy_const_generics(2)]
21074#[target_feature(enable = "neon,fp16")]
21075#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
21076pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
21077 static_assert_uimm_bits!(LANE, 3);
21078 unsafe extern "unadjusted" {
21079 #[cfg_attr(
21080 any(target_arch = "aarch64", target_arch = "arm64ec"),
21081 link_name = "llvm.aarch64.neon.ld2lane.v8f16.p0"
21082 )]
21083 fn _vld2q_lane_f16(
21084 a: float16x8_t,
21085 b: float16x8_t,
21086 n: i64,
21087 ptr: *const f16,
21088 ) -> float16x8x2_t;
21089 }
21090 _vld2q_lane_f16(b.0, b.1, LANE as i64, a as _)
21091}
21092#[doc = "Load multiple 2-element structures to two registers"]
21093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
21094#[doc = "## Safety"]
21095#[doc = " * Neon instrinsic unsafe"]
21096#[inline]
21097#[target_feature(enable = "neon")]
21098#[cfg(not(target_arch = "arm"))]
21099#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21100#[rustc_legacy_const_generics(2)]
21101#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21102pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) -> float32x2x2_t {
21103 static_assert_uimm_bits!(LANE, 2);
21104 unsafe extern "unadjusted" {
21105 #[cfg_attr(
21106 any(target_arch = "aarch64", target_arch = "arm64ec"),
21107 link_name = "llvm.aarch64.neon.ld2lane.v2f32.p0"
21108 )]
21109 fn _vld2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *const i8) -> float32x2x2_t;
21110 }
21111 _vld2_lane_f32(b.0, b.1, LANE as i64, a as _)
21112}
21113#[doc = "Load multiple 2-element structures to two registers"]
21114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
21115#[doc = "## Safety"]
21116#[doc = " * Neon instrinsic unsafe"]
21117#[inline]
21118#[target_feature(enable = "neon")]
21119#[cfg(not(target_arch = "arm"))]
21120#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21121#[rustc_legacy_const_generics(2)]
21122#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21123pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -> float32x4x2_t {
21124 static_assert_uimm_bits!(LANE, 2);
21125 unsafe extern "unadjusted" {
21126 #[cfg_attr(
21127 any(target_arch = "aarch64", target_arch = "arm64ec"),
21128 link_name = "llvm.aarch64.neon.ld2lane.v4f32.p0"
21129 )]
21130 fn _vld2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *const i8)
21131 -> float32x4x2_t;
21132 }
21133 _vld2q_lane_f32(b.0, b.1, LANE as i64, a as _)
21134}
21135#[doc = "Load multiple 2-element structures to two registers"]
21136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
21137#[doc = "## Safety"]
21138#[doc = " * Neon instrinsic unsafe"]
21139#[inline]
21140#[target_feature(enable = "neon")]
21141#[cfg(not(target_arch = "arm"))]
21142#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21143#[rustc_legacy_const_generics(2)]
21144#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21145pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8x8x2_t {
21146 static_assert_uimm_bits!(LANE, 3);
21147 unsafe extern "unadjusted" {
21148 #[cfg_attr(
21149 any(target_arch = "aarch64", target_arch = "arm64ec"),
21150 link_name = "llvm.aarch64.neon.ld2lane.v8i8.p0"
21151 )]
21152 fn _vld2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *const i8) -> int8x8x2_t;
21153 }
21154 _vld2_lane_s8(b.0, b.1, LANE as i64, a as _)
21155}
21156#[doc = "Load multiple 2-element structures to two registers"]
21157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
21158#[doc = "## Safety"]
21159#[doc = " * Neon instrinsic unsafe"]
21160#[inline]
21161#[target_feature(enable = "neon")]
21162#[cfg(not(target_arch = "arm"))]
21163#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21164#[rustc_legacy_const_generics(2)]
21165#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21166pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> int16x4x2_t {
21167 static_assert_uimm_bits!(LANE, 2);
21168 unsafe extern "unadjusted" {
21169 #[cfg_attr(
21170 any(target_arch = "aarch64", target_arch = "arm64ec"),
21171 link_name = "llvm.aarch64.neon.ld2lane.v4i16.p0"
21172 )]
21173 fn _vld2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *const i8) -> int16x4x2_t;
21174 }
21175 _vld2_lane_s16(b.0, b.1, LANE as i64, a as _)
21176}
21177#[doc = "Load multiple 2-element structures to two registers"]
21178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
21179#[doc = "## Safety"]
21180#[doc = " * Neon instrinsic unsafe"]
21181#[inline]
21182#[target_feature(enable = "neon")]
21183#[cfg(not(target_arch = "arm"))]
21184#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21185#[rustc_legacy_const_generics(2)]
21186#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21187pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) -> int16x8x2_t {
21188 static_assert_uimm_bits!(LANE, 3);
21189 unsafe extern "unadjusted" {
21190 #[cfg_attr(
21191 any(target_arch = "aarch64", target_arch = "arm64ec"),
21192 link_name = "llvm.aarch64.neon.ld2lane.v8i16.p0"
21193 )]
21194 fn _vld2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *const i8) -> int16x8x2_t;
21195 }
21196 _vld2q_lane_s16(b.0, b.1, LANE as i64, a as _)
21197}
21198#[doc = "Load multiple 2-element structures to two registers"]
21199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
21200#[doc = "## Safety"]
21201#[doc = " * Neon instrinsic unsafe"]
21202#[inline]
21203#[target_feature(enable = "neon")]
21204#[cfg(not(target_arch = "arm"))]
21205#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21206#[rustc_legacy_const_generics(2)]
21207#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21208pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> int32x2x2_t {
21209 static_assert_uimm_bits!(LANE, 1);
21210 unsafe extern "unadjusted" {
21211 #[cfg_attr(
21212 any(target_arch = "aarch64", target_arch = "arm64ec"),
21213 link_name = "llvm.aarch64.neon.ld2lane.v2i32.p0"
21214 )]
21215 fn _vld2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *const i8) -> int32x2x2_t;
21216 }
21217 _vld2_lane_s32(b.0, b.1, LANE as i64, a as _)
21218}
21219#[doc = "Load multiple 2-element structures to two registers"]
21220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
21221#[doc = "## Safety"]
21222#[doc = " * Neon instrinsic unsafe"]
21223#[inline]
21224#[target_feature(enable = "neon")]
21225#[cfg(not(target_arch = "arm"))]
21226#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21227#[rustc_legacy_const_generics(2)]
21228#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21229pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) -> int32x4x2_t {
21230 static_assert_uimm_bits!(LANE, 2);
21231 unsafe extern "unadjusted" {
21232 #[cfg_attr(
21233 any(target_arch = "aarch64", target_arch = "arm64ec"),
21234 link_name = "llvm.aarch64.neon.ld2lane.v4i32.p0"
21235 )]
21236 fn _vld2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *const i8) -> int32x4x2_t;
21237 }
21238 _vld2q_lane_s32(b.0, b.1, LANE as i64, a as _)
21239}
21240#[doc = "Load multiple 2-element structures to two registers"]
21241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
21242#[doc = "## Safety"]
21243#[doc = " * Neon instrinsic unsafe"]
21244#[inline]
21245#[target_feature(enable = "neon,v7")]
21246#[cfg(target_arch = "arm")]
21247#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21248#[rustc_legacy_const_generics(2)]
21249#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21250pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) -> float32x2x2_t {
21251 static_assert_uimm_bits!(LANE, 1);
21252 unsafe extern "unadjusted" {
21253 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2f32.p0")]
21254 fn _vld2_lane_f32(
21255 ptr: *const i8,
21256 a: float32x2_t,
21257 b: float32x2_t,
21258 n: i32,
21259 size: i32,
21260 ) -> float32x2x2_t;
21261 }
21262 _vld2_lane_f32(a as _, b.0, b.1, LANE, 4)
21263}
21264#[doc = "Load multiple 2-element structures to two registers"]
21265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
21266#[doc = "## Safety"]
21267#[doc = " * Neon instrinsic unsafe"]
21268#[inline]
21269#[target_feature(enable = "neon,v7")]
21270#[cfg(target_arch = "arm")]
21271#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21272#[rustc_legacy_const_generics(2)]
21273#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21274pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -> float32x4x2_t {
21275 static_assert_uimm_bits!(LANE, 2);
21276 unsafe extern "unadjusted" {
21277 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f32.p0")]
21278 fn _vld2q_lane_f32(
21279 ptr: *const i8,
21280 a: float32x4_t,
21281 b: float32x4_t,
21282 n: i32,
21283 size: i32,
21284 ) -> float32x4x2_t;
21285 }
21286 _vld2q_lane_f32(a as _, b.0, b.1, LANE, 4)
21287}
21288#[doc = "Load multiple 2-element structures to two registers"]
21289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
21290#[doc = "## Safety"]
21291#[doc = " * Neon instrinsic unsafe"]
21292#[inline]
21293#[target_feature(enable = "neon,v7")]
21294#[cfg(target_arch = "arm")]
21295#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21296#[rustc_legacy_const_generics(2)]
21297#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21298pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) -> int16x8x2_t {
21299 static_assert_uimm_bits!(LANE, 3);
21300 unsafe extern "unadjusted" {
21301 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i16.p0")]
21302 fn _vld2q_lane_s16(
21303 ptr: *const i8,
21304 a: int16x8_t,
21305 b: int16x8_t,
21306 n: i32,
21307 size: i32,
21308 ) -> int16x8x2_t;
21309 }
21310 _vld2q_lane_s16(a as _, b.0, b.1, LANE, 2)
21311}
21312#[doc = "Load multiple 2-element structures to two registers"]
21313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
21314#[doc = "## Safety"]
21315#[doc = " * Neon instrinsic unsafe"]
21316#[inline]
21317#[target_feature(enable = "neon,v7")]
21318#[cfg(target_arch = "arm")]
21319#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21320#[rustc_legacy_const_generics(2)]
21321#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21322pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) -> int32x4x2_t {
21323 static_assert_uimm_bits!(LANE, 2);
21324 unsafe extern "unadjusted" {
21325 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i32.p0")]
21326 fn _vld2q_lane_s32(
21327 ptr: *const i8,
21328 a: int32x4_t,
21329 b: int32x4_t,
21330 n: i32,
21331 size: i32,
21332 ) -> int32x4x2_t;
21333 }
21334 _vld2q_lane_s32(a as _, b.0, b.1, LANE, 4)
21335}
21336#[doc = "Load multiple 2-element structures to two registers"]
21337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
21338#[doc = "## Safety"]
21339#[doc = " * Neon instrinsic unsafe"]
21340#[inline]
21341#[target_feature(enable = "neon,v7")]
21342#[cfg(target_arch = "arm")]
21343#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21344#[rustc_legacy_const_generics(2)]
21345#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21346pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8x8x2_t {
21347 static_assert_uimm_bits!(LANE, 3);
21348 unsafe extern "unadjusted" {
21349 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i8.p0")]
21350 fn _vld2_lane_s8(ptr: *const i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32)
21351 -> int8x8x2_t;
21352 }
21353 _vld2_lane_s8(a as _, b.0, b.1, LANE, 1)
21354}
21355#[doc = "Load multiple 2-element structures to two registers"]
21356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
21357#[doc = "## Safety"]
21358#[doc = " * Neon instrinsic unsafe"]
21359#[inline]
21360#[target_feature(enable = "neon,v7")]
21361#[cfg(target_arch = "arm")]
21362#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21363#[rustc_legacy_const_generics(2)]
21364#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21365pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> int16x4x2_t {
21366 static_assert_uimm_bits!(LANE, 2);
21367 unsafe extern "unadjusted" {
21368 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i16.p0")]
21369 fn _vld2_lane_s16(
21370 ptr: *const i8,
21371 a: int16x4_t,
21372 b: int16x4_t,
21373 n: i32,
21374 size: i32,
21375 ) -> int16x4x2_t;
21376 }
21377 _vld2_lane_s16(a as _, b.0, b.1, LANE, 2)
21378}
21379#[doc = "Load multiple 2-element structures to two registers"]
21380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
21381#[doc = "## Safety"]
21382#[doc = " * Neon instrinsic unsafe"]
21383#[inline]
21384#[target_feature(enable = "neon,v7")]
21385#[cfg(target_arch = "arm")]
21386#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21387#[rustc_legacy_const_generics(2)]
21388#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21389pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> int32x2x2_t {
21390 static_assert_uimm_bits!(LANE, 1);
21391 unsafe extern "unadjusted" {
21392 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2i32.p0")]
21393 fn _vld2_lane_s32(
21394 ptr: *const i8,
21395 a: int32x2_t,
21396 b: int32x2_t,
21397 n: i32,
21398 size: i32,
21399 ) -> int32x2x2_t;
21400 }
21401 _vld2_lane_s32(a as _, b.0, b.1, LANE, 4)
21402}
21403#[doc = "Load multiple 2-element structures to two registers"]
21404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"]
21405#[doc = "## Safety"]
21406#[doc = " * Neon instrinsic unsafe"]
21407#[inline]
21408#[target_feature(enable = "neon")]
21409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21410#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21411#[cfg_attr(
21412 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21413 assert_instr(ld2, LANE = 0)
21414)]
21415#[rustc_legacy_const_generics(2)]
21416#[cfg_attr(
21417 not(target_arch = "arm"),
21418 stable(feature = "neon_intrinsics", since = "1.59.0")
21419)]
21420#[cfg_attr(
21421 target_arch = "arm",
21422 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21423)]
21424pub unsafe fn vld2_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x2_t) -> uint8x8x2_t {
21425 static_assert_uimm_bits!(LANE, 3);
21426 transmute(vld2_lane_s8::<LANE>(transmute(a), transmute(b)))
21427}
21428#[doc = "Load multiple 2-element structures to two registers"]
21429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"]
21430#[doc = "## Safety"]
21431#[doc = " * Neon instrinsic unsafe"]
21432#[inline]
21433#[target_feature(enable = "neon")]
21434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21435#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21436#[cfg_attr(
21437 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21438 assert_instr(ld2, LANE = 0)
21439)]
21440#[rustc_legacy_const_generics(2)]
21441#[cfg_attr(
21442 not(target_arch = "arm"),
21443 stable(feature = "neon_intrinsics", since = "1.59.0")
21444)]
21445#[cfg_attr(
21446 target_arch = "arm",
21447 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21448)]
21449pub unsafe fn vld2_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x2_t) -> uint16x4x2_t {
21450 static_assert_uimm_bits!(LANE, 2);
21451 transmute(vld2_lane_s16::<LANE>(transmute(a), transmute(b)))
21452}
21453#[doc = "Load multiple 2-element structures to two registers"]
21454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"]
21455#[doc = "## Safety"]
21456#[doc = " * Neon instrinsic unsafe"]
21457#[inline]
21458#[target_feature(enable = "neon")]
21459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21461#[cfg_attr(
21462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21463 assert_instr(ld2, LANE = 0)
21464)]
21465#[rustc_legacy_const_generics(2)]
21466#[cfg_attr(
21467 not(target_arch = "arm"),
21468 stable(feature = "neon_intrinsics", since = "1.59.0")
21469)]
21470#[cfg_attr(
21471 target_arch = "arm",
21472 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21473)]
21474pub unsafe fn vld2q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x2_t) -> uint16x8x2_t {
21475 static_assert_uimm_bits!(LANE, 3);
21476 transmute(vld2q_lane_s16::<LANE>(transmute(a), transmute(b)))
21477}
21478#[doc = "Load multiple 2-element structures to two registers"]
21479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"]
21480#[doc = "## Safety"]
21481#[doc = " * Neon instrinsic unsafe"]
21482#[inline]
21483#[target_feature(enable = "neon")]
21484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21486#[cfg_attr(
21487 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21488 assert_instr(ld2, LANE = 0)
21489)]
21490#[rustc_legacy_const_generics(2)]
21491#[cfg_attr(
21492 not(target_arch = "arm"),
21493 stable(feature = "neon_intrinsics", since = "1.59.0")
21494)]
21495#[cfg_attr(
21496 target_arch = "arm",
21497 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21498)]
21499pub unsafe fn vld2_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x2_t) -> uint32x2x2_t {
21500 static_assert_uimm_bits!(LANE, 1);
21501 transmute(vld2_lane_s32::<LANE>(transmute(a), transmute(b)))
21502}
21503#[doc = "Load multiple 2-element structures to two registers"]
21504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"]
21505#[doc = "## Safety"]
21506#[doc = " * Neon instrinsic unsafe"]
21507#[inline]
21508#[target_feature(enable = "neon")]
21509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21511#[cfg_attr(
21512 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21513 assert_instr(ld2, LANE = 0)
21514)]
21515#[rustc_legacy_const_generics(2)]
21516#[cfg_attr(
21517 not(target_arch = "arm"),
21518 stable(feature = "neon_intrinsics", since = "1.59.0")
21519)]
21520#[cfg_attr(
21521 target_arch = "arm",
21522 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21523)]
21524pub unsafe fn vld2q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x2_t) -> uint32x4x2_t {
21525 static_assert_uimm_bits!(LANE, 2);
21526 transmute(vld2q_lane_s32::<LANE>(transmute(a), transmute(b)))
21527}
21528#[doc = "Load multiple 2-element structures to two registers"]
21529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"]
21530#[doc = "## Safety"]
21531#[doc = " * Neon instrinsic unsafe"]
21532#[inline]
21533#[target_feature(enable = "neon")]
21534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21536#[cfg_attr(
21537 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21538 assert_instr(ld2, LANE = 0)
21539)]
21540#[rustc_legacy_const_generics(2)]
21541#[cfg_attr(
21542 not(target_arch = "arm"),
21543 stable(feature = "neon_intrinsics", since = "1.59.0")
21544)]
21545#[cfg_attr(
21546 target_arch = "arm",
21547 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21548)]
21549pub unsafe fn vld2_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x2_t) -> poly8x8x2_t {
21550 static_assert_uimm_bits!(LANE, 3);
21551 transmute(vld2_lane_s8::<LANE>(transmute(a), transmute(b)))
21552}
21553#[doc = "Load multiple 2-element structures to two registers"]
21554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"]
21555#[doc = "## Safety"]
21556#[doc = " * Neon instrinsic unsafe"]
21557#[inline]
21558#[target_feature(enable = "neon")]
21559#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21560#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21561#[cfg_attr(
21562 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21563 assert_instr(ld2, LANE = 0)
21564)]
21565#[rustc_legacy_const_generics(2)]
21566#[cfg_attr(
21567 not(target_arch = "arm"),
21568 stable(feature = "neon_intrinsics", since = "1.59.0")
21569)]
21570#[cfg_attr(
21571 target_arch = "arm",
21572 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21573)]
21574pub unsafe fn vld2_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x2_t) -> poly16x4x2_t {
21575 static_assert_uimm_bits!(LANE, 2);
21576 transmute(vld2_lane_s16::<LANE>(transmute(a), transmute(b)))
21577}
21578#[doc = "Load multiple 2-element structures to two registers"]
21579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"]
21580#[doc = "## Safety"]
21581#[doc = " * Neon instrinsic unsafe"]
21582#[inline]
21583#[target_feature(enable = "neon")]
21584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21585#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21586#[cfg_attr(
21587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21588 assert_instr(ld2, LANE = 0)
21589)]
21590#[rustc_legacy_const_generics(2)]
21591#[cfg_attr(
21592 not(target_arch = "arm"),
21593 stable(feature = "neon_intrinsics", since = "1.59.0")
21594)]
21595#[cfg_attr(
21596 target_arch = "arm",
21597 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21598)]
21599pub unsafe fn vld2q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x2_t) -> poly16x8x2_t {
21600 static_assert_uimm_bits!(LANE, 3);
21601 transmute(vld2q_lane_s16::<LANE>(transmute(a), transmute(b)))
21602}
21603#[doc = "Load multiple 2-element structures to two registers"]
21604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"]
21605#[doc = "## Safety"]
21606#[doc = " * Neon instrinsic unsafe"]
21607#[inline]
21608#[target_feature(enable = "neon,aes")]
21609#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
21610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
21611#[cfg_attr(
21612 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21613 assert_instr(nop)
21614)]
21615#[cfg_attr(
21616 not(target_arch = "arm"),
21617 stable(feature = "neon_intrinsics", since = "1.59.0")
21618)]
21619#[cfg_attr(
21620 target_arch = "arm",
21621 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21622)]
21623pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t {
21624 transmute(vld2_s64(transmute(a)))
21625}
21626#[doc = "Load multiple 2-element structures to two registers"]
21627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
21628#[doc = "## Safety"]
21629#[doc = " * Neon instrinsic unsafe"]
21630#[inline]
21631#[target_feature(enable = "neon,v7")]
21632#[cfg(target_arch = "arm")]
21633#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21634#[cfg_attr(test, assert_instr(nop))]
21635pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
21636 unsafe extern "unadjusted" {
21637 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v1i64")]
21638 fn _vld2_s64(ptr: *const i8, size: i32) -> int64x1x2_t;
21639 }
21640 _vld2_s64(a as *const i8, 8)
21641}
21642#[doc = "Load multiple 2-element structures to two registers"]
21643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
21644#[doc = "## Safety"]
21645#[doc = " * Neon instrinsic unsafe"]
21646#[inline]
21647#[target_feature(enable = "neon")]
21648#[cfg(not(target_arch = "arm"))]
21649#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21650#[cfg_attr(test, assert_instr(nop))]
21651pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
21652 unsafe extern "unadjusted" {
21653 #[cfg_attr(
21654 any(target_arch = "aarch64", target_arch = "arm64ec"),
21655 link_name = "llvm.aarch64.neon.ld2.v1i64.p0"
21656 )]
21657 fn _vld2_s64(ptr: *const int64x1_t) -> int64x1x2_t;
21658 }
21659 _vld2_s64(a as _)
21660}
21661#[doc = "Load multiple 2-element structures to two registers"]
21662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"]
21663#[doc = "## Safety"]
21664#[doc = " * Neon instrinsic unsafe"]
21665#[inline]
21666#[target_feature(enable = "neon")]
21667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
21669#[cfg_attr(
21670 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21671 assert_instr(nop)
21672)]
21673#[cfg_attr(
21674 not(target_arch = "arm"),
21675 stable(feature = "neon_intrinsics", since = "1.59.0")
21676)]
21677#[cfg_attr(
21678 target_arch = "arm",
21679 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21680)]
21681pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t {
21682 transmute(vld2_s64(transmute(a)))
21683}
21684#[doc = "Load multiple 2-element structures to two registers"]
21685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
21686#[doc = "## Safety"]
21687#[doc = " * Neon instrinsic unsafe"]
21688#[inline]
21689#[cfg(target_endian = "little")]
21690#[target_feature(enable = "neon")]
21691#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21692#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21693#[cfg_attr(
21694 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21695 assert_instr(ld2)
21696)]
21697#[cfg_attr(
21698 not(target_arch = "arm"),
21699 stable(feature = "neon_intrinsics", since = "1.59.0")
21700)]
21701#[cfg_attr(
21702 target_arch = "arm",
21703 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21704)]
21705pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
21706 transmute(vld2_s8(transmute(a)))
21707}
21708#[doc = "Load multiple 2-element structures to two registers"]
21709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
21710#[doc = "## Safety"]
21711#[doc = " * Neon instrinsic unsafe"]
21712#[inline]
21713#[cfg(target_endian = "big")]
21714#[target_feature(enable = "neon")]
21715#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21716#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21717#[cfg_attr(
21718 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21719 assert_instr(ld2)
21720)]
21721#[cfg_attr(
21722 not(target_arch = "arm"),
21723 stable(feature = "neon_intrinsics", since = "1.59.0")
21724)]
21725#[cfg_attr(
21726 target_arch = "arm",
21727 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21728)]
21729pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
21730 let mut ret_val: uint8x8x2_t = transmute(vld2_s8(transmute(a)));
21731 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
21732 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
21733 ret_val
21734}
21735#[doc = "Load multiple 2-element structures to two registers"]
21736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
21737#[doc = "## Safety"]
21738#[doc = " * Neon instrinsic unsafe"]
21739#[inline]
21740#[cfg(target_endian = "little")]
21741#[target_feature(enable = "neon")]
21742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21743#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21744#[cfg_attr(
21745 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21746 assert_instr(ld2)
21747)]
21748#[cfg_attr(
21749 not(target_arch = "arm"),
21750 stable(feature = "neon_intrinsics", since = "1.59.0")
21751)]
21752#[cfg_attr(
21753 target_arch = "arm",
21754 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21755)]
21756pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
21757 transmute(vld2q_s8(transmute(a)))
21758}
21759#[doc = "Load multiple 2-element structures to two registers"]
21760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
21761#[doc = "## Safety"]
21762#[doc = " * Neon instrinsic unsafe"]
21763#[inline]
21764#[cfg(target_endian = "big")]
21765#[target_feature(enable = "neon")]
21766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21767#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21768#[cfg_attr(
21769 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21770 assert_instr(ld2)
21771)]
21772#[cfg_attr(
21773 not(target_arch = "arm"),
21774 stable(feature = "neon_intrinsics", since = "1.59.0")
21775)]
21776#[cfg_attr(
21777 target_arch = "arm",
21778 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21779)]
21780pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
21781 let mut ret_val: uint8x16x2_t = transmute(vld2q_s8(transmute(a)));
21782 ret_val.0 = unsafe {
21783 simd_shuffle!(
21784 ret_val.0,
21785 ret_val.0,
21786 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
21787 )
21788 };
21789 ret_val.1 = unsafe {
21790 simd_shuffle!(
21791 ret_val.1,
21792 ret_val.1,
21793 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
21794 )
21795 };
21796 ret_val
21797}
21798#[doc = "Load multiple 2-element structures to two registers"]
21799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
21800#[doc = "## Safety"]
21801#[doc = " * Neon instrinsic unsafe"]
21802#[inline]
21803#[cfg(target_endian = "little")]
21804#[target_feature(enable = "neon")]
21805#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21806#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21807#[cfg_attr(
21808 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21809 assert_instr(ld2)
21810)]
21811#[cfg_attr(
21812 not(target_arch = "arm"),
21813 stable(feature = "neon_intrinsics", since = "1.59.0")
21814)]
21815#[cfg_attr(
21816 target_arch = "arm",
21817 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21818)]
21819pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
21820 transmute(vld2_s16(transmute(a)))
21821}
21822#[doc = "Load multiple 2-element structures to two registers"]
21823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
21824#[doc = "## Safety"]
21825#[doc = " * Neon instrinsic unsafe"]
21826#[inline]
21827#[cfg(target_endian = "big")]
21828#[target_feature(enable = "neon")]
21829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21831#[cfg_attr(
21832 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21833 assert_instr(ld2)
21834)]
21835#[cfg_attr(
21836 not(target_arch = "arm"),
21837 stable(feature = "neon_intrinsics", since = "1.59.0")
21838)]
21839#[cfg_attr(
21840 target_arch = "arm",
21841 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21842)]
21843pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
21844 let mut ret_val: uint16x4x2_t = transmute(vld2_s16(transmute(a)));
21845 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
21846 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
21847 ret_val
21848}
21849#[doc = "Load multiple 2-element structures to two registers"]
21850#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
21851#[doc = "## Safety"]
21852#[doc = " * Neon instrinsic unsafe"]
21853#[inline]
21854#[cfg(target_endian = "little")]
21855#[target_feature(enable = "neon")]
21856#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21857#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21858#[cfg_attr(
21859 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21860 assert_instr(ld2)
21861)]
21862#[cfg_attr(
21863 not(target_arch = "arm"),
21864 stable(feature = "neon_intrinsics", since = "1.59.0")
21865)]
21866#[cfg_attr(
21867 target_arch = "arm",
21868 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21869)]
21870pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
21871 transmute(vld2q_s16(transmute(a)))
21872}
21873#[doc = "Load multiple 2-element structures to two registers"]
21874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
21875#[doc = "## Safety"]
21876#[doc = " * Neon instrinsic unsafe"]
21877#[inline]
21878#[cfg(target_endian = "big")]
21879#[target_feature(enable = "neon")]
21880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21882#[cfg_attr(
21883 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21884 assert_instr(ld2)
21885)]
21886#[cfg_attr(
21887 not(target_arch = "arm"),
21888 stable(feature = "neon_intrinsics", since = "1.59.0")
21889)]
21890#[cfg_attr(
21891 target_arch = "arm",
21892 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21893)]
21894pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
21895 let mut ret_val: uint16x8x2_t = transmute(vld2q_s16(transmute(a)));
21896 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
21897 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
21898 ret_val
21899}
21900#[doc = "Load multiple 2-element structures to two registers"]
21901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
21902#[doc = "## Safety"]
21903#[doc = " * Neon instrinsic unsafe"]
21904#[inline]
21905#[cfg(target_endian = "little")]
21906#[target_feature(enable = "neon")]
21907#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21908#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21909#[cfg_attr(
21910 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21911 assert_instr(ld2)
21912)]
21913#[cfg_attr(
21914 not(target_arch = "arm"),
21915 stable(feature = "neon_intrinsics", since = "1.59.0")
21916)]
21917#[cfg_attr(
21918 target_arch = "arm",
21919 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21920)]
21921pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
21922 transmute(vld2_s32(transmute(a)))
21923}
21924#[doc = "Load multiple 2-element structures to two registers"]
21925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
21926#[doc = "## Safety"]
21927#[doc = " * Neon instrinsic unsafe"]
21928#[inline]
21929#[cfg(target_endian = "big")]
21930#[target_feature(enable = "neon")]
21931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21933#[cfg_attr(
21934 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21935 assert_instr(ld2)
21936)]
21937#[cfg_attr(
21938 not(target_arch = "arm"),
21939 stable(feature = "neon_intrinsics", since = "1.59.0")
21940)]
21941#[cfg_attr(
21942 target_arch = "arm",
21943 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21944)]
21945pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
21946 let mut ret_val: uint32x2x2_t = transmute(vld2_s32(transmute(a)));
21947 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
21948 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
21949 ret_val
21950}
21951#[doc = "Load multiple 2-element structures to two registers"]
21952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
21953#[doc = "## Safety"]
21954#[doc = " * Neon instrinsic unsafe"]
21955#[inline]
21956#[cfg(target_endian = "little")]
21957#[target_feature(enable = "neon")]
21958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21960#[cfg_attr(
21961 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21962 assert_instr(ld2)
21963)]
21964#[cfg_attr(
21965 not(target_arch = "arm"),
21966 stable(feature = "neon_intrinsics", since = "1.59.0")
21967)]
21968#[cfg_attr(
21969 target_arch = "arm",
21970 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21971)]
21972pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
21973 transmute(vld2q_s32(transmute(a)))
21974}
21975#[doc = "Load multiple 2-element structures to two registers"]
21976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
21977#[doc = "## Safety"]
21978#[doc = " * Neon instrinsic unsafe"]
21979#[inline]
21980#[cfg(target_endian = "big")]
21981#[target_feature(enable = "neon")]
21982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21983#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21984#[cfg_attr(
21985 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21986 assert_instr(ld2)
21987)]
21988#[cfg_attr(
21989 not(target_arch = "arm"),
21990 stable(feature = "neon_intrinsics", since = "1.59.0")
21991)]
21992#[cfg_attr(
21993 target_arch = "arm",
21994 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21995)]
21996pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
21997 let mut ret_val: uint32x4x2_t = transmute(vld2q_s32(transmute(a)));
21998 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
21999 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22000 ret_val
22001}
22002#[doc = "Load multiple 2-element structures to two registers"]
22003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
22004#[doc = "## Safety"]
22005#[doc = " * Neon instrinsic unsafe"]
22006#[inline]
22007#[cfg(target_endian = "little")]
22008#[target_feature(enable = "neon")]
22009#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22010#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22011#[cfg_attr(
22012 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22013 assert_instr(ld2)
22014)]
22015#[cfg_attr(
22016 not(target_arch = "arm"),
22017 stable(feature = "neon_intrinsics", since = "1.59.0")
22018)]
22019#[cfg_attr(
22020 target_arch = "arm",
22021 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22022)]
22023pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
22024 transmute(vld2_s8(transmute(a)))
22025}
22026#[doc = "Load multiple 2-element structures to two registers"]
22027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
22028#[doc = "## Safety"]
22029#[doc = " * Neon instrinsic unsafe"]
22030#[inline]
22031#[cfg(target_endian = "big")]
22032#[target_feature(enable = "neon")]
22033#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22034#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22035#[cfg_attr(
22036 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22037 assert_instr(ld2)
22038)]
22039#[cfg_attr(
22040 not(target_arch = "arm"),
22041 stable(feature = "neon_intrinsics", since = "1.59.0")
22042)]
22043#[cfg_attr(
22044 target_arch = "arm",
22045 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22046)]
22047pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
22048 let mut ret_val: poly8x8x2_t = transmute(vld2_s8(transmute(a)));
22049 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22050 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22051 ret_val
22052}
22053#[doc = "Load multiple 2-element structures to two registers"]
22054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
22055#[doc = "## Safety"]
22056#[doc = " * Neon instrinsic unsafe"]
22057#[inline]
22058#[cfg(target_endian = "little")]
22059#[target_feature(enable = "neon")]
22060#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22061#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22062#[cfg_attr(
22063 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22064 assert_instr(ld2)
22065)]
22066#[cfg_attr(
22067 not(target_arch = "arm"),
22068 stable(feature = "neon_intrinsics", since = "1.59.0")
22069)]
22070#[cfg_attr(
22071 target_arch = "arm",
22072 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22073)]
22074pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
22075 transmute(vld2q_s8(transmute(a)))
22076}
22077#[doc = "Load multiple 2-element structures to two registers"]
22078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
22079#[doc = "## Safety"]
22080#[doc = " * Neon instrinsic unsafe"]
22081#[inline]
22082#[cfg(target_endian = "big")]
22083#[target_feature(enable = "neon")]
22084#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22085#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22086#[cfg_attr(
22087 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22088 assert_instr(ld2)
22089)]
22090#[cfg_attr(
22091 not(target_arch = "arm"),
22092 stable(feature = "neon_intrinsics", since = "1.59.0")
22093)]
22094#[cfg_attr(
22095 target_arch = "arm",
22096 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22097)]
22098pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
22099 let mut ret_val: poly8x16x2_t = transmute(vld2q_s8(transmute(a)));
22100 ret_val.0 = unsafe {
22101 simd_shuffle!(
22102 ret_val.0,
22103 ret_val.0,
22104 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22105 )
22106 };
22107 ret_val.1 = unsafe {
22108 simd_shuffle!(
22109 ret_val.1,
22110 ret_val.1,
22111 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22112 )
22113 };
22114 ret_val
22115}
22116#[doc = "Load multiple 2-element structures to two registers"]
22117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
22118#[doc = "## Safety"]
22119#[doc = " * Neon instrinsic unsafe"]
22120#[inline]
22121#[cfg(target_endian = "little")]
22122#[target_feature(enable = "neon")]
22123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22125#[cfg_attr(
22126 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22127 assert_instr(ld2)
22128)]
22129#[cfg_attr(
22130 not(target_arch = "arm"),
22131 stable(feature = "neon_intrinsics", since = "1.59.0")
22132)]
22133#[cfg_attr(
22134 target_arch = "arm",
22135 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22136)]
22137pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
22138 transmute(vld2_s16(transmute(a)))
22139}
22140#[doc = "Load multiple 2-element structures to two registers"]
22141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
22142#[doc = "## Safety"]
22143#[doc = " * Neon instrinsic unsafe"]
22144#[inline]
22145#[cfg(target_endian = "big")]
22146#[target_feature(enable = "neon")]
22147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22149#[cfg_attr(
22150 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22151 assert_instr(ld2)
22152)]
22153#[cfg_attr(
22154 not(target_arch = "arm"),
22155 stable(feature = "neon_intrinsics", since = "1.59.0")
22156)]
22157#[cfg_attr(
22158 target_arch = "arm",
22159 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22160)]
22161pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
22162 let mut ret_val: poly16x4x2_t = transmute(vld2_s16(transmute(a)));
22163 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22164 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22165 ret_val
22166}
22167#[doc = "Load multiple 2-element structures to two registers"]
22168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
22169#[doc = "## Safety"]
22170#[doc = " * Neon instrinsic unsafe"]
22171#[inline]
22172#[cfg(target_endian = "little")]
22173#[target_feature(enable = "neon")]
22174#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22175#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22176#[cfg_attr(
22177 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22178 assert_instr(ld2)
22179)]
22180#[cfg_attr(
22181 not(target_arch = "arm"),
22182 stable(feature = "neon_intrinsics", since = "1.59.0")
22183)]
22184#[cfg_attr(
22185 target_arch = "arm",
22186 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22187)]
22188pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
22189 transmute(vld2q_s16(transmute(a)))
22190}
22191#[doc = "Load multiple 2-element structures to two registers"]
22192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
22193#[doc = "## Safety"]
22194#[doc = " * Neon instrinsic unsafe"]
22195#[inline]
22196#[cfg(target_endian = "big")]
22197#[target_feature(enable = "neon")]
22198#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22199#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22200#[cfg_attr(
22201 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22202 assert_instr(ld2)
22203)]
22204#[cfg_attr(
22205 not(target_arch = "arm"),
22206 stable(feature = "neon_intrinsics", since = "1.59.0")
22207)]
22208#[cfg_attr(
22209 target_arch = "arm",
22210 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22211)]
22212pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
22213 let mut ret_val: poly16x8x2_t = transmute(vld2q_s16(transmute(a)));
22214 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22215 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22216 ret_val
22217}
22218#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
22220#[doc = "## Safety"]
22221#[doc = " * Neon instrinsic unsafe"]
22222#[inline]
22223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22224#[cfg(target_arch = "arm")]
22225#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22226#[target_feature(enable = "neon,fp16")]
22227#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22228pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
22229 unsafe extern "unadjusted" {
22230 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f16.p0f16")]
22231 fn _vld3_dup_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
22232 }
22233 _vld3_dup_f16(a as _, 2)
22234}
22235#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
22237#[doc = "## Safety"]
22238#[doc = " * Neon instrinsic unsafe"]
22239#[inline]
22240#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22241#[cfg(target_arch = "arm")]
22242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22243#[target_feature(enable = "neon,fp16")]
22244#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22245pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
22246 unsafe extern "unadjusted" {
22247 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8f16.p0f16")]
22248 fn _vld3q_dup_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
22249 }
22250 _vld3q_dup_f16(a as _, 2)
22251}
22252#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
22254#[doc = "## Safety"]
22255#[doc = " * Neon instrinsic unsafe"]
22256#[inline]
22257#[cfg(not(target_arch = "arm"))]
22258#[cfg_attr(
22259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22260 assert_instr(ld3r)
22261)]
22262#[target_feature(enable = "neon,fp16")]
22263#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22264pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
22265 unsafe extern "unadjusted" {
22266 #[cfg_attr(
22267 any(target_arch = "aarch64", target_arch = "arm64ec"),
22268 link_name = "llvm.aarch64.neon.ld3r.v4f16.p0f16"
22269 )]
22270 fn _vld3_dup_f16(ptr: *const f16) -> float16x4x3_t;
22271 }
22272 _vld3_dup_f16(a as _)
22273}
22274#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
22276#[doc = "## Safety"]
22277#[doc = " * Neon instrinsic unsafe"]
22278#[inline]
22279#[cfg(not(target_arch = "arm"))]
22280#[cfg_attr(
22281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22282 assert_instr(ld3r)
22283)]
22284#[target_feature(enable = "neon,fp16")]
22285#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22286pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
22287 unsafe extern "unadjusted" {
22288 #[cfg_attr(
22289 any(target_arch = "aarch64", target_arch = "arm64ec"),
22290 link_name = "llvm.aarch64.neon.ld3r.v8f16.p0f16"
22291 )]
22292 fn _vld3q_dup_f16(ptr: *const f16) -> float16x8x3_t;
22293 }
22294 _vld3q_dup_f16(a as _)
22295}
22296#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
22298#[doc = "## Safety"]
22299#[doc = " * Neon instrinsic unsafe"]
22300#[inline]
22301#[target_feature(enable = "neon")]
22302#[cfg(not(target_arch = "arm"))]
22303#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22304#[cfg_attr(test, assert_instr(ld3r))]
22305pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
22306 unsafe extern "unadjusted" {
22307 #[cfg_attr(
22308 any(target_arch = "aarch64", target_arch = "arm64ec"),
22309 link_name = "llvm.aarch64.neon.ld3r.v2f32.p0"
22310 )]
22311 fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t;
22312 }
22313 _vld3_dup_f32(a as _)
22314}
22315#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
22317#[doc = "## Safety"]
22318#[doc = " * Neon instrinsic unsafe"]
22319#[inline]
22320#[target_feature(enable = "neon")]
22321#[cfg(not(target_arch = "arm"))]
22322#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22323#[cfg_attr(test, assert_instr(ld3r))]
22324pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
22325 unsafe extern "unadjusted" {
22326 #[cfg_attr(
22327 any(target_arch = "aarch64", target_arch = "arm64ec"),
22328 link_name = "llvm.aarch64.neon.ld3r.v4f32.p0"
22329 )]
22330 fn _vld3q_dup_f32(ptr: *const f32) -> float32x4x3_t;
22331 }
22332 _vld3q_dup_f32(a as _)
22333}
22334#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
22336#[doc = "## Safety"]
22337#[doc = " * Neon instrinsic unsafe"]
22338#[inline]
22339#[target_feature(enable = "neon")]
22340#[cfg(not(target_arch = "arm"))]
22341#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22342#[cfg_attr(test, assert_instr(ld3r))]
22343pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
22344 unsafe extern "unadjusted" {
22345 #[cfg_attr(
22346 any(target_arch = "aarch64", target_arch = "arm64ec"),
22347 link_name = "llvm.aarch64.neon.ld3r.v8i8.p0"
22348 )]
22349 fn _vld3_dup_s8(ptr: *const i8) -> int8x8x3_t;
22350 }
22351 _vld3_dup_s8(a as _)
22352}
22353#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
22355#[doc = "## Safety"]
22356#[doc = " * Neon instrinsic unsafe"]
22357#[inline]
22358#[target_feature(enable = "neon")]
22359#[cfg(not(target_arch = "arm"))]
22360#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22361#[cfg_attr(test, assert_instr(ld3r))]
22362pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
22363 unsafe extern "unadjusted" {
22364 #[cfg_attr(
22365 any(target_arch = "aarch64", target_arch = "arm64ec"),
22366 link_name = "llvm.aarch64.neon.ld3r.v16i8.p0"
22367 )]
22368 fn _vld3q_dup_s8(ptr: *const i8) -> int8x16x3_t;
22369 }
22370 _vld3q_dup_s8(a as _)
22371}
22372#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
22374#[doc = "## Safety"]
22375#[doc = " * Neon instrinsic unsafe"]
22376#[inline]
22377#[target_feature(enable = "neon")]
22378#[cfg(not(target_arch = "arm"))]
22379#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22380#[cfg_attr(test, assert_instr(ld3r))]
22381pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
22382 unsafe extern "unadjusted" {
22383 #[cfg_attr(
22384 any(target_arch = "aarch64", target_arch = "arm64ec"),
22385 link_name = "llvm.aarch64.neon.ld3r.v4i16.p0"
22386 )]
22387 fn _vld3_dup_s16(ptr: *const i16) -> int16x4x3_t;
22388 }
22389 _vld3_dup_s16(a as _)
22390}
22391#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
22393#[doc = "## Safety"]
22394#[doc = " * Neon instrinsic unsafe"]
22395#[inline]
22396#[target_feature(enable = "neon")]
22397#[cfg(not(target_arch = "arm"))]
22398#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22399#[cfg_attr(test, assert_instr(ld3r))]
22400pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
22401 unsafe extern "unadjusted" {
22402 #[cfg_attr(
22403 any(target_arch = "aarch64", target_arch = "arm64ec"),
22404 link_name = "llvm.aarch64.neon.ld3r.v8i16.p0"
22405 )]
22406 fn _vld3q_dup_s16(ptr: *const i16) -> int16x8x3_t;
22407 }
22408 _vld3q_dup_s16(a as _)
22409}
22410#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
22412#[doc = "## Safety"]
22413#[doc = " * Neon instrinsic unsafe"]
22414#[inline]
22415#[target_feature(enable = "neon")]
22416#[cfg(not(target_arch = "arm"))]
22417#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22418#[cfg_attr(test, assert_instr(ld3r))]
22419pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
22420 unsafe extern "unadjusted" {
22421 #[cfg_attr(
22422 any(target_arch = "aarch64", target_arch = "arm64ec"),
22423 link_name = "llvm.aarch64.neon.ld3r.v2i32.p0"
22424 )]
22425 fn _vld3_dup_s32(ptr: *const i32) -> int32x2x3_t;
22426 }
22427 _vld3_dup_s32(a as _)
22428}
22429#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
22431#[doc = "## Safety"]
22432#[doc = " * Neon instrinsic unsafe"]
22433#[inline]
22434#[target_feature(enable = "neon")]
22435#[cfg(not(target_arch = "arm"))]
22436#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22437#[cfg_attr(test, assert_instr(ld3r))]
22438pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
22439 unsafe extern "unadjusted" {
22440 #[cfg_attr(
22441 any(target_arch = "aarch64", target_arch = "arm64ec"),
22442 link_name = "llvm.aarch64.neon.ld3r.v4i32.p0"
22443 )]
22444 fn _vld3q_dup_s32(ptr: *const i32) -> int32x4x3_t;
22445 }
22446 _vld3q_dup_s32(a as _)
22447}
22448#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
22450#[doc = "## Safety"]
22451#[doc = " * Neon instrinsic unsafe"]
22452#[inline]
22453#[target_feature(enable = "neon")]
22454#[cfg(not(target_arch = "arm"))]
22455#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22456#[cfg_attr(test, assert_instr(ld3r))]
22457pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
22458 unsafe extern "unadjusted" {
22459 #[cfg_attr(
22460 any(target_arch = "aarch64", target_arch = "arm64ec"),
22461 link_name = "llvm.aarch64.neon.ld3r.v1i64.p0"
22462 )]
22463 fn _vld3_dup_s64(ptr: *const i64) -> int64x1x3_t;
22464 }
22465 _vld3_dup_s64(a as _)
22466}
22467#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
22469#[doc = "## Safety"]
22470#[doc = " * Neon instrinsic unsafe"]
22471#[inline]
22472#[target_feature(enable = "neon,v7")]
22473#[cfg(target_arch = "arm")]
22474#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22475#[cfg_attr(test, assert_instr(vld3))]
22476pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
22477 unsafe extern "unadjusted" {
22478 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2f32.p0")]
22479 fn _vld3_dup_f32(ptr: *const i8, size: i32) -> float32x2x3_t;
22480 }
22481 _vld3_dup_f32(a as *const i8, 4)
22482}
22483#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
22485#[doc = "## Safety"]
22486#[doc = " * Neon instrinsic unsafe"]
22487#[inline]
22488#[target_feature(enable = "neon,v7")]
22489#[cfg(target_arch = "arm")]
22490#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22491#[cfg_attr(test, assert_instr(vld3))]
22492pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
22493 unsafe extern "unadjusted" {
22494 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f32.p0")]
22495 fn _vld3q_dup_f32(ptr: *const i8, size: i32) -> float32x4x3_t;
22496 }
22497 _vld3q_dup_f32(a as *const i8, 4)
22498}
22499#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
22501#[doc = "## Safety"]
22502#[doc = " * Neon instrinsic unsafe"]
22503#[inline]
22504#[target_feature(enable = "neon,v7")]
22505#[cfg(target_arch = "arm")]
22506#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22507#[cfg_attr(test, assert_instr(vld3))]
22508pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
22509 unsafe extern "unadjusted" {
22510 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i8.p0")]
22511 fn _vld3_dup_s8(ptr: *const i8, size: i32) -> int8x8x3_t;
22512 }
22513 _vld3_dup_s8(a as *const i8, 1)
22514}
22515#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
22517#[doc = "## Safety"]
22518#[doc = " * Neon instrinsic unsafe"]
22519#[inline]
22520#[target_feature(enable = "neon,v7")]
22521#[cfg(target_arch = "arm")]
22522#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22523#[cfg_attr(test, assert_instr(vld3))]
22524pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
22525 unsafe extern "unadjusted" {
22526 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v16i8.p0")]
22527 fn _vld3q_dup_s8(ptr: *const i8, size: i32) -> int8x16x3_t;
22528 }
22529 _vld3q_dup_s8(a as *const i8, 1)
22530}
22531#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
22533#[doc = "## Safety"]
22534#[doc = " * Neon instrinsic unsafe"]
22535#[inline]
22536#[target_feature(enable = "neon,v7")]
22537#[cfg(target_arch = "arm")]
22538#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22539#[cfg_attr(test, assert_instr(vld3))]
22540pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
22541 unsafe extern "unadjusted" {
22542 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i16.p0")]
22543 fn _vld3_dup_s16(ptr: *const i8, size: i32) -> int16x4x3_t;
22544 }
22545 _vld3_dup_s16(a as *const i8, 2)
22546}
22547#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
22549#[doc = "## Safety"]
22550#[doc = " * Neon instrinsic unsafe"]
22551#[inline]
22552#[target_feature(enable = "neon,v7")]
22553#[cfg(target_arch = "arm")]
22554#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22555#[cfg_attr(test, assert_instr(vld3))]
22556pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
22557 unsafe extern "unadjusted" {
22558 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i16.p0")]
22559 fn _vld3q_dup_s16(ptr: *const i8, size: i32) -> int16x8x3_t;
22560 }
22561 _vld3q_dup_s16(a as *const i8, 2)
22562}
22563#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
22565#[doc = "## Safety"]
22566#[doc = " * Neon instrinsic unsafe"]
22567#[inline]
22568#[target_feature(enable = "neon,v7")]
22569#[cfg(target_arch = "arm")]
22570#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22571#[cfg_attr(test, assert_instr(vld3))]
22572pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
22573 unsafe extern "unadjusted" {
22574 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2i32.p0")]
22575 fn _vld3_dup_s32(ptr: *const i8, size: i32) -> int32x2x3_t;
22576 }
22577 _vld3_dup_s32(a as *const i8, 4)
22578}
22579#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
22581#[doc = "## Safety"]
22582#[doc = " * Neon instrinsic unsafe"]
22583#[inline]
22584#[target_feature(enable = "neon,v7")]
22585#[cfg(target_arch = "arm")]
22586#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22587#[cfg_attr(test, assert_instr(vld3))]
22588pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
22589 unsafe extern "unadjusted" {
22590 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i32.p0")]
22591 fn _vld3q_dup_s32(ptr: *const i8, size: i32) -> int32x4x3_t;
22592 }
22593 _vld3q_dup_s32(a as *const i8, 4)
22594}
22595#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"]
22597#[doc = "## Safety"]
22598#[doc = " * Neon instrinsic unsafe"]
22599#[inline]
22600#[target_feature(enable = "neon,aes")]
22601#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
22602#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
22603#[cfg_attr(
22604 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22605 assert_instr(ld3r)
22606)]
22607#[cfg_attr(
22608 not(target_arch = "arm"),
22609 stable(feature = "neon_intrinsics", since = "1.59.0")
22610)]
22611#[cfg_attr(
22612 target_arch = "arm",
22613 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22614)]
22615pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t {
22616 transmute(vld3_dup_s64(transmute(a)))
22617}
22618#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
22620#[doc = "## Safety"]
22621#[doc = " * Neon instrinsic unsafe"]
22622#[inline]
22623#[cfg(target_arch = "arm")]
22624#[target_feature(enable = "neon,v7")]
22625#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22626#[cfg_attr(test, assert_instr(nop))]
22627pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
22628 unsafe extern "unadjusted" {
22629 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v1i64.p0")]
22630 fn _vld3_dup_s64(ptr: *const i8, size: i32) -> int64x1x3_t;
22631 }
22632 _vld3_dup_s64(a as *const i8, 8)
22633}
22634#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"]
22636#[doc = "## Safety"]
22637#[doc = " * Neon instrinsic unsafe"]
22638#[inline]
22639#[target_feature(enable = "neon")]
22640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
22642#[cfg_attr(
22643 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22644 assert_instr(ld3r)
22645)]
22646#[cfg_attr(
22647 not(target_arch = "arm"),
22648 stable(feature = "neon_intrinsics", since = "1.59.0")
22649)]
22650#[cfg_attr(
22651 target_arch = "arm",
22652 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22653)]
22654pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t {
22655 transmute(vld3_dup_s64(transmute(a)))
22656}
22657#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
22659#[doc = "## Safety"]
22660#[doc = " * Neon instrinsic unsafe"]
22661#[inline]
22662#[cfg(target_endian = "little")]
22663#[target_feature(enable = "neon")]
22664#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22665#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22666#[cfg_attr(
22667 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22668 assert_instr(ld3r)
22669)]
22670#[cfg_attr(
22671 not(target_arch = "arm"),
22672 stable(feature = "neon_intrinsics", since = "1.59.0")
22673)]
22674#[cfg_attr(
22675 target_arch = "arm",
22676 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22677)]
22678pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
22679 transmute(vld3_dup_s8(transmute(a)))
22680}
22681#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
22683#[doc = "## Safety"]
22684#[doc = " * Neon instrinsic unsafe"]
22685#[inline]
22686#[cfg(target_endian = "big")]
22687#[target_feature(enable = "neon")]
22688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22689#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22690#[cfg_attr(
22691 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22692 assert_instr(ld3r)
22693)]
22694#[cfg_attr(
22695 not(target_arch = "arm"),
22696 stable(feature = "neon_intrinsics", since = "1.59.0")
22697)]
22698#[cfg_attr(
22699 target_arch = "arm",
22700 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22701)]
22702pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
22703 let mut ret_val: uint8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
22704 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22705 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22706 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22707 ret_val
22708}
22709#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
22711#[doc = "## Safety"]
22712#[doc = " * Neon instrinsic unsafe"]
22713#[inline]
22714#[cfg(target_endian = "little")]
22715#[target_feature(enable = "neon")]
22716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22717#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22718#[cfg_attr(
22719 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22720 assert_instr(ld3r)
22721)]
22722#[cfg_attr(
22723 not(target_arch = "arm"),
22724 stable(feature = "neon_intrinsics", since = "1.59.0")
22725)]
22726#[cfg_attr(
22727 target_arch = "arm",
22728 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22729)]
22730pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
22731 transmute(vld3q_dup_s8(transmute(a)))
22732}
22733#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
22735#[doc = "## Safety"]
22736#[doc = " * Neon instrinsic unsafe"]
22737#[inline]
22738#[cfg(target_endian = "big")]
22739#[target_feature(enable = "neon")]
22740#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22741#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22742#[cfg_attr(
22743 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22744 assert_instr(ld3r)
22745)]
22746#[cfg_attr(
22747 not(target_arch = "arm"),
22748 stable(feature = "neon_intrinsics", since = "1.59.0")
22749)]
22750#[cfg_attr(
22751 target_arch = "arm",
22752 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22753)]
22754pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
22755 let mut ret_val: uint8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
22756 ret_val.0 = unsafe {
22757 simd_shuffle!(
22758 ret_val.0,
22759 ret_val.0,
22760 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22761 )
22762 };
22763 ret_val.1 = unsafe {
22764 simd_shuffle!(
22765 ret_val.1,
22766 ret_val.1,
22767 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22768 )
22769 };
22770 ret_val.2 = unsafe {
22771 simd_shuffle!(
22772 ret_val.2,
22773 ret_val.2,
22774 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22775 )
22776 };
22777 ret_val
22778}
22779#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
22781#[doc = "## Safety"]
22782#[doc = " * Neon instrinsic unsafe"]
22783#[inline]
22784#[cfg(target_endian = "little")]
22785#[target_feature(enable = "neon")]
22786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22787#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22788#[cfg_attr(
22789 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22790 assert_instr(ld3r)
22791)]
22792#[cfg_attr(
22793 not(target_arch = "arm"),
22794 stable(feature = "neon_intrinsics", since = "1.59.0")
22795)]
22796#[cfg_attr(
22797 target_arch = "arm",
22798 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22799)]
22800pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
22801 transmute(vld3_dup_s16(transmute(a)))
22802}
22803#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
22805#[doc = "## Safety"]
22806#[doc = " * Neon instrinsic unsafe"]
22807#[inline]
22808#[cfg(target_endian = "big")]
22809#[target_feature(enable = "neon")]
22810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22812#[cfg_attr(
22813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22814 assert_instr(ld3r)
22815)]
22816#[cfg_attr(
22817 not(target_arch = "arm"),
22818 stable(feature = "neon_intrinsics", since = "1.59.0")
22819)]
22820#[cfg_attr(
22821 target_arch = "arm",
22822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22823)]
22824pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
22825 let mut ret_val: uint16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
22826 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22827 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22828 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
22829 ret_val
22830}
22831#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
22833#[doc = "## Safety"]
22834#[doc = " * Neon instrinsic unsafe"]
22835#[inline]
22836#[cfg(target_endian = "little")]
22837#[target_feature(enable = "neon")]
22838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22839#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22840#[cfg_attr(
22841 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22842 assert_instr(ld3r)
22843)]
22844#[cfg_attr(
22845 not(target_arch = "arm"),
22846 stable(feature = "neon_intrinsics", since = "1.59.0")
22847)]
22848#[cfg_attr(
22849 target_arch = "arm",
22850 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22851)]
22852pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
22853 transmute(vld3q_dup_s16(transmute(a)))
22854}
22855#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
22857#[doc = "## Safety"]
22858#[doc = " * Neon instrinsic unsafe"]
22859#[inline]
22860#[cfg(target_endian = "big")]
22861#[target_feature(enable = "neon")]
22862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22863#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22864#[cfg_attr(
22865 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22866 assert_instr(ld3r)
22867)]
22868#[cfg_attr(
22869 not(target_arch = "arm"),
22870 stable(feature = "neon_intrinsics", since = "1.59.0")
22871)]
22872#[cfg_attr(
22873 target_arch = "arm",
22874 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22875)]
22876pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
22877 let mut ret_val: uint16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
22878 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22879 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22880 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22881 ret_val
22882}
22883#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
22885#[doc = "## Safety"]
22886#[doc = " * Neon instrinsic unsafe"]
22887#[inline]
22888#[cfg(target_endian = "little")]
22889#[target_feature(enable = "neon")]
22890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22892#[cfg_attr(
22893 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22894 assert_instr(ld3r)
22895)]
22896#[cfg_attr(
22897 not(target_arch = "arm"),
22898 stable(feature = "neon_intrinsics", since = "1.59.0")
22899)]
22900#[cfg_attr(
22901 target_arch = "arm",
22902 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22903)]
22904pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
22905 transmute(vld3_dup_s32(transmute(a)))
22906}
22907#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
22909#[doc = "## Safety"]
22910#[doc = " * Neon instrinsic unsafe"]
22911#[inline]
22912#[cfg(target_endian = "big")]
22913#[target_feature(enable = "neon")]
22914#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22915#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22916#[cfg_attr(
22917 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22918 assert_instr(ld3r)
22919)]
22920#[cfg_attr(
22921 not(target_arch = "arm"),
22922 stable(feature = "neon_intrinsics", since = "1.59.0")
22923)]
22924#[cfg_attr(
22925 target_arch = "arm",
22926 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22927)]
22928pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
22929 let mut ret_val: uint32x2x3_t = transmute(vld3_dup_s32(transmute(a)));
22930 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
22931 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
22932 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
22933 ret_val
22934}
22935#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
22937#[doc = "## Safety"]
22938#[doc = " * Neon instrinsic unsafe"]
22939#[inline]
22940#[cfg(target_endian = "little")]
22941#[target_feature(enable = "neon")]
22942#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22943#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22944#[cfg_attr(
22945 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22946 assert_instr(ld3r)
22947)]
22948#[cfg_attr(
22949 not(target_arch = "arm"),
22950 stable(feature = "neon_intrinsics", since = "1.59.0")
22951)]
22952#[cfg_attr(
22953 target_arch = "arm",
22954 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22955)]
22956pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
22957 transmute(vld3q_dup_s32(transmute(a)))
22958}
22959#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
22961#[doc = "## Safety"]
22962#[doc = " * Neon instrinsic unsafe"]
22963#[inline]
22964#[cfg(target_endian = "big")]
22965#[target_feature(enable = "neon")]
22966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22967#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22968#[cfg_attr(
22969 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22970 assert_instr(ld3r)
22971)]
22972#[cfg_attr(
22973 not(target_arch = "arm"),
22974 stable(feature = "neon_intrinsics", since = "1.59.0")
22975)]
22976#[cfg_attr(
22977 target_arch = "arm",
22978 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22979)]
22980pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
22981 let mut ret_val: uint32x4x3_t = transmute(vld3q_dup_s32(transmute(a)));
22982 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22983 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22984 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
22985 ret_val
22986}
22987#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
22989#[doc = "## Safety"]
22990#[doc = " * Neon instrinsic unsafe"]
22991#[inline]
22992#[cfg(target_endian = "little")]
22993#[target_feature(enable = "neon")]
22994#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22995#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22996#[cfg_attr(
22997 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22998 assert_instr(ld3r)
22999)]
23000#[cfg_attr(
23001 not(target_arch = "arm"),
23002 stable(feature = "neon_intrinsics", since = "1.59.0")
23003)]
23004#[cfg_attr(
23005 target_arch = "arm",
23006 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23007)]
23008pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
23009 transmute(vld3_dup_s8(transmute(a)))
23010}
23011#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
23013#[doc = "## Safety"]
23014#[doc = " * Neon instrinsic unsafe"]
23015#[inline]
23016#[cfg(target_endian = "big")]
23017#[target_feature(enable = "neon")]
23018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23019#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23020#[cfg_attr(
23021 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23022 assert_instr(ld3r)
23023)]
23024#[cfg_attr(
23025 not(target_arch = "arm"),
23026 stable(feature = "neon_intrinsics", since = "1.59.0")
23027)]
23028#[cfg_attr(
23029 target_arch = "arm",
23030 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23031)]
23032pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
23033 let mut ret_val: poly8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
23034 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
23035 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
23036 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
23037 ret_val
23038}
23039#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
23041#[doc = "## Safety"]
23042#[doc = " * Neon instrinsic unsafe"]
23043#[inline]
23044#[cfg(target_endian = "little")]
23045#[target_feature(enable = "neon")]
23046#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23047#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23048#[cfg_attr(
23049 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23050 assert_instr(ld3r)
23051)]
23052#[cfg_attr(
23053 not(target_arch = "arm"),
23054 stable(feature = "neon_intrinsics", since = "1.59.0")
23055)]
23056#[cfg_attr(
23057 target_arch = "arm",
23058 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23059)]
23060pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
23061 transmute(vld3q_dup_s8(transmute(a)))
23062}
23063#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
23065#[doc = "## Safety"]
23066#[doc = " * Neon instrinsic unsafe"]
23067#[inline]
23068#[cfg(target_endian = "big")]
23069#[target_feature(enable = "neon")]
23070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23071#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23072#[cfg_attr(
23073 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23074 assert_instr(ld3r)
23075)]
23076#[cfg_attr(
23077 not(target_arch = "arm"),
23078 stable(feature = "neon_intrinsics", since = "1.59.0")
23079)]
23080#[cfg_attr(
23081 target_arch = "arm",
23082 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23083)]
23084pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
23085 let mut ret_val: poly8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
23086 ret_val.0 = unsafe {
23087 simd_shuffle!(
23088 ret_val.0,
23089 ret_val.0,
23090 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
23091 )
23092 };
23093 ret_val.1 = unsafe {
23094 simd_shuffle!(
23095 ret_val.1,
23096 ret_val.1,
23097 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
23098 )
23099 };
23100 ret_val.2 = unsafe {
23101 simd_shuffle!(
23102 ret_val.2,
23103 ret_val.2,
23104 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
23105 )
23106 };
23107 ret_val
23108}
23109#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
23111#[doc = "## Safety"]
23112#[doc = " * Neon instrinsic unsafe"]
23113#[inline]
23114#[cfg(target_endian = "little")]
23115#[target_feature(enable = "neon")]
23116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23118#[cfg_attr(
23119 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23120 assert_instr(ld3r)
23121)]
23122#[cfg_attr(
23123 not(target_arch = "arm"),
23124 stable(feature = "neon_intrinsics", since = "1.59.0")
23125)]
23126#[cfg_attr(
23127 target_arch = "arm",
23128 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23129)]
23130pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
23131 transmute(vld3_dup_s16(transmute(a)))
23132}
23133#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
23135#[doc = "## Safety"]
23136#[doc = " * Neon instrinsic unsafe"]
23137#[inline]
23138#[cfg(target_endian = "big")]
23139#[target_feature(enable = "neon")]
23140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23142#[cfg_attr(
23143 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23144 assert_instr(ld3r)
23145)]
23146#[cfg_attr(
23147 not(target_arch = "arm"),
23148 stable(feature = "neon_intrinsics", since = "1.59.0")
23149)]
23150#[cfg_attr(
23151 target_arch = "arm",
23152 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23153)]
23154pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
23155 let mut ret_val: poly16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
23156 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
23157 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
23158 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
23159 ret_val
23160}
23161#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
23163#[doc = "## Safety"]
23164#[doc = " * Neon instrinsic unsafe"]
23165#[inline]
23166#[cfg(target_endian = "little")]
23167#[target_feature(enable = "neon")]
23168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23169#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23170#[cfg_attr(
23171 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23172 assert_instr(ld3r)
23173)]
23174#[cfg_attr(
23175 not(target_arch = "arm"),
23176 stable(feature = "neon_intrinsics", since = "1.59.0")
23177)]
23178#[cfg_attr(
23179 target_arch = "arm",
23180 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23181)]
23182pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
23183 transmute(vld3q_dup_s16(transmute(a)))
23184}
23185#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
23187#[doc = "## Safety"]
23188#[doc = " * Neon instrinsic unsafe"]
23189#[inline]
23190#[cfg(target_endian = "big")]
23191#[target_feature(enable = "neon")]
23192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23193#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23194#[cfg_attr(
23195 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23196 assert_instr(ld3r)
23197)]
23198#[cfg_attr(
23199 not(target_arch = "arm"),
23200 stable(feature = "neon_intrinsics", since = "1.59.0")
23201)]
23202#[cfg_attr(
23203 target_arch = "arm",
23204 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23205)]
23206pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
23207 let mut ret_val: poly16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
23208 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
23209 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
23210 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
23211 ret_val
23212}
23213#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
23215#[doc = "## Safety"]
23216#[doc = " * Neon instrinsic unsafe"]
23217#[inline]
23218#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23219#[cfg(target_arch = "arm")]
23220#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23221#[target_feature(enable = "neon,fp16")]
23222#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23223pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
23224 unsafe extern "unadjusted" {
23225 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f16.p0f16")]
23226 fn _vld3_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
23227 }
23228 _vld3_f16(a as _, 2)
23229}
23230#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
23232#[doc = "## Safety"]
23233#[doc = " * Neon instrinsic unsafe"]
23234#[inline]
23235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23236#[cfg(target_arch = "arm")]
23237#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23238#[target_feature(enable = "neon,fp16")]
23239#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23240pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
23241 unsafe extern "unadjusted" {
23242 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8f16.p0f16")]
23243 fn _vld3q_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
23244 }
23245 _vld3q_f16(a as _, 2)
23246}
23247#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
23249#[doc = "## Safety"]
23250#[doc = " * Neon instrinsic unsafe"]
23251#[inline]
23252#[cfg(not(target_arch = "arm"))]
23253#[cfg_attr(
23254 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23255 assert_instr(ld3)
23256)]
23257#[target_feature(enable = "neon,fp16")]
23258#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23259pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
23260 unsafe extern "unadjusted" {
23261 #[cfg_attr(
23262 any(target_arch = "aarch64", target_arch = "arm64ec"),
23263 link_name = "llvm.aarch64.neon.ld3.v4f16.p0f16"
23264 )]
23265 fn _vld3_f16(ptr: *const f16) -> float16x4x3_t;
23266 }
23267 _vld3_f16(a as _)
23268}
23269#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
23271#[doc = "## Safety"]
23272#[doc = " * Neon instrinsic unsafe"]
23273#[inline]
23274#[cfg(not(target_arch = "arm"))]
23275#[cfg_attr(
23276 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23277 assert_instr(ld3)
23278)]
23279#[target_feature(enable = "neon,fp16")]
23280#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23281pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
23282 unsafe extern "unadjusted" {
23283 #[cfg_attr(
23284 any(target_arch = "aarch64", target_arch = "arm64ec"),
23285 link_name = "llvm.aarch64.neon.ld3.v8f16.p0f16"
23286 )]
23287 fn _vld3q_f16(ptr: *const f16) -> float16x8x3_t;
23288 }
23289 _vld3q_f16(a as _)
23290}
23291#[doc = "Load multiple 3-element structures to three registers"]
23292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
23293#[doc = "## Safety"]
23294#[doc = " * Neon instrinsic unsafe"]
23295#[inline]
23296#[target_feature(enable = "neon")]
23297#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23298#[cfg(not(target_arch = "arm"))]
23299#[cfg_attr(test, assert_instr(ld3))]
23300pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
23301 unsafe extern "unadjusted" {
23302 #[cfg_attr(
23303 any(target_arch = "aarch64", target_arch = "arm64ec"),
23304 link_name = "llvm.aarch64.neon.ld3.v2f32.p0"
23305 )]
23306 fn _vld3_f32(ptr: *const float32x2_t) -> float32x2x3_t;
23307 }
23308 _vld3_f32(a as _)
23309}
23310#[doc = "Load multiple 3-element structures to three registers"]
23311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
23312#[doc = "## Safety"]
23313#[doc = " * Neon instrinsic unsafe"]
23314#[inline]
23315#[target_feature(enable = "neon")]
23316#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23317#[cfg(not(target_arch = "arm"))]
23318#[cfg_attr(test, assert_instr(ld3))]
23319pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
23320 unsafe extern "unadjusted" {
23321 #[cfg_attr(
23322 any(target_arch = "aarch64", target_arch = "arm64ec"),
23323 link_name = "llvm.aarch64.neon.ld3.v4f32.p0"
23324 )]
23325 fn _vld3q_f32(ptr: *const float32x4_t) -> float32x4x3_t;
23326 }
23327 _vld3q_f32(a as _)
23328}
23329#[doc = "Load multiple 3-element structures to three registers"]
23330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
23331#[doc = "## Safety"]
23332#[doc = " * Neon instrinsic unsafe"]
23333#[inline]
23334#[target_feature(enable = "neon")]
23335#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23336#[cfg(not(target_arch = "arm"))]
23337#[cfg_attr(test, assert_instr(ld3))]
23338pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
23339 unsafe extern "unadjusted" {
23340 #[cfg_attr(
23341 any(target_arch = "aarch64", target_arch = "arm64ec"),
23342 link_name = "llvm.aarch64.neon.ld3.v8i8.p0"
23343 )]
23344 fn _vld3_s8(ptr: *const int8x8_t) -> int8x8x3_t;
23345 }
23346 _vld3_s8(a as _)
23347}
23348#[doc = "Load multiple 3-element structures to three registers"]
23349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
23350#[doc = "## Safety"]
23351#[doc = " * Neon instrinsic unsafe"]
23352#[inline]
23353#[target_feature(enable = "neon")]
23354#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23355#[cfg(not(target_arch = "arm"))]
23356#[cfg_attr(test, assert_instr(ld3))]
23357pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
23358 unsafe extern "unadjusted" {
23359 #[cfg_attr(
23360 any(target_arch = "aarch64", target_arch = "arm64ec"),
23361 link_name = "llvm.aarch64.neon.ld3.v16i8.p0"
23362 )]
23363 fn _vld3q_s8(ptr: *const int8x16_t) -> int8x16x3_t;
23364 }
23365 _vld3q_s8(a as _)
23366}
23367#[doc = "Load multiple 3-element structures to three registers"]
23368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
23369#[doc = "## Safety"]
23370#[doc = " * Neon instrinsic unsafe"]
23371#[inline]
23372#[target_feature(enable = "neon")]
23373#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23374#[cfg(not(target_arch = "arm"))]
23375#[cfg_attr(test, assert_instr(ld3))]
23376pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
23377 unsafe extern "unadjusted" {
23378 #[cfg_attr(
23379 any(target_arch = "aarch64", target_arch = "arm64ec"),
23380 link_name = "llvm.aarch64.neon.ld3.v4i16.p0"
23381 )]
23382 fn _vld3_s16(ptr: *const int16x4_t) -> int16x4x3_t;
23383 }
23384 _vld3_s16(a as _)
23385}
23386#[doc = "Load multiple 3-element structures to three registers"]
23387#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
23388#[doc = "## Safety"]
23389#[doc = " * Neon instrinsic unsafe"]
23390#[inline]
23391#[target_feature(enable = "neon")]
23392#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23393#[cfg(not(target_arch = "arm"))]
23394#[cfg_attr(test, assert_instr(ld3))]
23395pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
23396 unsafe extern "unadjusted" {
23397 #[cfg_attr(
23398 any(target_arch = "aarch64", target_arch = "arm64ec"),
23399 link_name = "llvm.aarch64.neon.ld3.v8i16.p0"
23400 )]
23401 fn _vld3q_s16(ptr: *const int16x8_t) -> int16x8x3_t;
23402 }
23403 _vld3q_s16(a as _)
23404}
23405#[doc = "Load multiple 3-element structures to three registers"]
23406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
23407#[doc = "## Safety"]
23408#[doc = " * Neon instrinsic unsafe"]
23409#[inline]
23410#[target_feature(enable = "neon")]
23411#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23412#[cfg(not(target_arch = "arm"))]
23413#[cfg_attr(test, assert_instr(ld3))]
23414pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
23415 unsafe extern "unadjusted" {
23416 #[cfg_attr(
23417 any(target_arch = "aarch64", target_arch = "arm64ec"),
23418 link_name = "llvm.aarch64.neon.ld3.v2i32.p0"
23419 )]
23420 fn _vld3_s32(ptr: *const int32x2_t) -> int32x2x3_t;
23421 }
23422 _vld3_s32(a as _)
23423}
23424#[doc = "Load multiple 3-element structures to three registers"]
23425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
23426#[doc = "## Safety"]
23427#[doc = " * Neon instrinsic unsafe"]
23428#[inline]
23429#[target_feature(enable = "neon")]
23430#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23431#[cfg(not(target_arch = "arm"))]
23432#[cfg_attr(test, assert_instr(ld3))]
23433pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
23434 unsafe extern "unadjusted" {
23435 #[cfg_attr(
23436 any(target_arch = "aarch64", target_arch = "arm64ec"),
23437 link_name = "llvm.aarch64.neon.ld3.v4i32.p0"
23438 )]
23439 fn _vld3q_s32(ptr: *const int32x4_t) -> int32x4x3_t;
23440 }
23441 _vld3q_s32(a as _)
23442}
23443#[doc = "Load multiple 3-element structures to three registers"]
23444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
23445#[doc = "## Safety"]
23446#[doc = " * Neon instrinsic unsafe"]
23447#[inline]
23448#[cfg(target_arch = "arm")]
23449#[target_feature(enable = "neon,v7")]
23450#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23451#[cfg_attr(test, assert_instr(vld3))]
23452pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
23453 unsafe extern "unadjusted" {
23454 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2f32.p0")]
23455 fn _vld3_f32(ptr: *const i8, size: i32) -> float32x2x3_t;
23456 }
23457 _vld3_f32(a as *const i8, 4)
23458}
23459#[doc = "Load multiple 3-element structures to three registers"]
23460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
23461#[doc = "## Safety"]
23462#[doc = " * Neon instrinsic unsafe"]
23463#[inline]
23464#[cfg(target_arch = "arm")]
23465#[target_feature(enable = "neon,v7")]
23466#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23467#[cfg_attr(test, assert_instr(vld3))]
23468pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
23469 unsafe extern "unadjusted" {
23470 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f32.p0")]
23471 fn _vld3q_f32(ptr: *const i8, size: i32) -> float32x4x3_t;
23472 }
23473 _vld3q_f32(a as *const i8, 4)
23474}
23475#[doc = "Load multiple 3-element structures to three registers"]
23476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
23477#[doc = "## Safety"]
23478#[doc = " * Neon instrinsic unsafe"]
23479#[inline]
23480#[cfg(target_arch = "arm")]
23481#[target_feature(enable = "neon,v7")]
23482#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23483#[cfg_attr(test, assert_instr(vld3))]
23484pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
23485 unsafe extern "unadjusted" {
23486 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i8.p0")]
23487 fn _vld3_s8(ptr: *const i8, size: i32) -> int8x8x3_t;
23488 }
23489 _vld3_s8(a as *const i8, 1)
23490}
23491#[doc = "Load multiple 3-element structures to three registers"]
23492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
23493#[doc = "## Safety"]
23494#[doc = " * Neon instrinsic unsafe"]
23495#[inline]
23496#[cfg(target_arch = "arm")]
23497#[target_feature(enable = "neon,v7")]
23498#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23499#[cfg_attr(test, assert_instr(vld3))]
23500pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
23501 unsafe extern "unadjusted" {
23502 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v16i8.p0")]
23503 fn _vld3q_s8(ptr: *const i8, size: i32) -> int8x16x3_t;
23504 }
23505 _vld3q_s8(a as *const i8, 1)
23506}
23507#[doc = "Load multiple 3-element structures to three registers"]
23508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
23509#[doc = "## Safety"]
23510#[doc = " * Neon instrinsic unsafe"]
23511#[inline]
23512#[cfg(target_arch = "arm")]
23513#[target_feature(enable = "neon,v7")]
23514#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23515#[cfg_attr(test, assert_instr(vld3))]
23516pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
23517 unsafe extern "unadjusted" {
23518 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i16.p0")]
23519 fn _vld3_s16(ptr: *const i8, size: i32) -> int16x4x3_t;
23520 }
23521 _vld3_s16(a as *const i8, 2)
23522}
23523#[doc = "Load multiple 3-element structures to three registers"]
23524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
23525#[doc = "## Safety"]
23526#[doc = " * Neon instrinsic unsafe"]
23527#[inline]
23528#[cfg(target_arch = "arm")]
23529#[target_feature(enable = "neon,v7")]
23530#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23531#[cfg_attr(test, assert_instr(vld3))]
23532pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
23533 unsafe extern "unadjusted" {
23534 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i16.p0")]
23535 fn _vld3q_s16(ptr: *const i8, size: i32) -> int16x8x3_t;
23536 }
23537 _vld3q_s16(a as *const i8, 2)
23538}
23539#[doc = "Load multiple 3-element structures to three registers"]
23540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
23541#[doc = "## Safety"]
23542#[doc = " * Neon instrinsic unsafe"]
23543#[inline]
23544#[cfg(target_arch = "arm")]
23545#[target_feature(enable = "neon,v7")]
23546#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23547#[cfg_attr(test, assert_instr(vld3))]
23548pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
23549 unsafe extern "unadjusted" {
23550 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2i32.p0")]
23551 fn _vld3_s32(ptr: *const i8, size: i32) -> int32x2x3_t;
23552 }
23553 _vld3_s32(a as *const i8, 4)
23554}
23555#[doc = "Load multiple 3-element structures to three registers"]
23556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
23557#[doc = "## Safety"]
23558#[doc = " * Neon instrinsic unsafe"]
23559#[inline]
23560#[cfg(target_arch = "arm")]
23561#[target_feature(enable = "neon,v7")]
23562#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23563#[cfg_attr(test, assert_instr(vld3))]
23564pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
23565 unsafe extern "unadjusted" {
23566 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i32.p0")]
23567 fn _vld3q_s32(ptr: *const i8, size: i32) -> int32x4x3_t;
23568 }
23569 _vld3q_s32(a as *const i8, 4)
23570}
23571#[doc = "Load multiple 3-element structures to two registers"]
23572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
23573#[doc = "## Safety"]
23574#[doc = " * Neon instrinsic unsafe"]
23575#[inline]
23576#[target_feature(enable = "neon,v7")]
23577#[cfg(target_arch = "arm")]
23578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23579#[rustc_legacy_const_generics(2)]
23580#[target_feature(enable = "neon,fp16")]
23581#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23582pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
23583 static_assert_uimm_bits!(LANE, 2);
23584 unsafe extern "unadjusted" {
23585 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f16.p0")]
23586 fn _vld3_lane_f16(
23587 ptr: *const f16,
23588 a: float16x4_t,
23589 b: float16x4_t,
23590 c: float16x4_t,
23591 n: i32,
23592 size: i32,
23593 ) -> float16x4x3_t;
23594 }
23595 _vld3_lane_f16(a as _, b.0, b.1, b.2, LANE, 2)
23596}
23597#[doc = "Load multiple 3-element structures to two registers"]
23598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
23599#[doc = "## Safety"]
23600#[doc = " * Neon instrinsic unsafe"]
23601#[inline]
23602#[target_feature(enable = "neon,v7")]
23603#[cfg(target_arch = "arm")]
23604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23605#[rustc_legacy_const_generics(2)]
23606#[target_feature(enable = "neon,fp16")]
23607#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23608pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
23609 static_assert_uimm_bits!(LANE, 3);
23610 unsafe extern "unadjusted" {
23611 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8f16.p0")]
23612 fn _vld3q_lane_f16(
23613 ptr: *const f16,
23614 a: float16x8_t,
23615 b: float16x8_t,
23616 c: float16x8_t,
23617 n: i32,
23618 size: i32,
23619 ) -> float16x8x3_t;
23620 }
23621 _vld3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 2)
23622}
23623#[doc = "Load multiple 3-element structures to two registers"]
23624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
23625#[doc = "## Safety"]
23626#[doc = " * Neon instrinsic unsafe"]
23627#[inline]
23628#[cfg(not(target_arch = "arm"))]
23629#[cfg_attr(
23630 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23631 assert_instr(ld3, LANE = 0)
23632)]
23633#[rustc_legacy_const_generics(2)]
23634#[target_feature(enable = "neon,fp16")]
23635#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23636pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
23637 static_assert_uimm_bits!(LANE, 2);
23638 unsafe extern "unadjusted" {
23639 #[cfg_attr(
23640 any(target_arch = "aarch64", target_arch = "arm64ec"),
23641 link_name = "llvm.aarch64.neon.ld3lane.v4f16.p0"
23642 )]
23643 fn _vld3_lane_f16(
23644 a: float16x4_t,
23645 b: float16x4_t,
23646 c: float16x4_t,
23647 n: i64,
23648 ptr: *const f16,
23649 ) -> float16x4x3_t;
23650 }
23651 _vld3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
23652}
23653#[doc = "Load multiple 3-element structures to two registers"]
23654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
23655#[doc = "## Safety"]
23656#[doc = " * Neon instrinsic unsafe"]
23657#[inline]
23658#[cfg(not(target_arch = "arm"))]
23659#[cfg_attr(
23660 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23661 assert_instr(ld3, LANE = 0)
23662)]
23663#[rustc_legacy_const_generics(2)]
23664#[target_feature(enable = "neon,fp16")]
23665#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23666pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
23667 static_assert_uimm_bits!(LANE, 3);
23668 unsafe extern "unadjusted" {
23669 #[cfg_attr(
23670 any(target_arch = "aarch64", target_arch = "arm64ec"),
23671 link_name = "llvm.aarch64.neon.ld3lane.v8f16.p0"
23672 )]
23673 fn _vld3q_lane_f16(
23674 a: float16x8_t,
23675 b: float16x8_t,
23676 c: float16x8_t,
23677 n: i64,
23678 ptr: *const f16,
23679 ) -> float16x8x3_t;
23680 }
23681 _vld3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
23682}
23683#[doc = "Load multiple 3-element structures to three registers"]
23684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
23685#[doc = "## Safety"]
23686#[doc = " * Neon instrinsic unsafe"]
23687#[inline]
23688#[target_feature(enable = "neon")]
23689#[cfg(not(target_arch = "arm"))]
23690#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23691#[rustc_legacy_const_generics(2)]
23692#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23693pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) -> float32x2x3_t {
23694 static_assert_uimm_bits!(LANE, 1);
23695 unsafe extern "unadjusted" {
23696 #[cfg_attr(
23697 any(target_arch = "aarch64", target_arch = "arm64ec"),
23698 link_name = "llvm.aarch64.neon.ld3lane.v2f32.p0"
23699 )]
23700 fn _vld3_lane_f32(
23701 a: float32x2_t,
23702 b: float32x2_t,
23703 c: float32x2_t,
23704 n: i64,
23705 ptr: *const i8,
23706 ) -> float32x2x3_t;
23707 }
23708 _vld3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
23709}
23710#[doc = "Load multiple 3-element structures to three registers"]
23711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
23712#[doc = "## Safety"]
23713#[doc = " * Neon instrinsic unsafe"]
23714#[inline]
23715#[target_feature(enable = "neon")]
23716#[cfg(not(target_arch = "arm"))]
23717#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23718#[rustc_legacy_const_generics(2)]
23719#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23720pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
23721 static_assert_uimm_bits!(LANE, 2);
23722 unsafe extern "unadjusted" {
23723 #[cfg_attr(
23724 any(target_arch = "aarch64", target_arch = "arm64ec"),
23725 link_name = "llvm.aarch64.neon.ld3lane.v4f32.p0"
23726 )]
23727 fn _vld3q_lane_f32(
23728 a: float32x4_t,
23729 b: float32x4_t,
23730 c: float32x4_t,
23731 n: i64,
23732 ptr: *const i8,
23733 ) -> float32x4x3_t;
23734 }
23735 _vld3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
23736}
23737#[doc = "Load multiple 3-element structures to three registers"]
23738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
23739#[doc = "## Safety"]
23740#[doc = " * Neon instrinsic unsafe"]
23741#[inline]
23742#[cfg(target_arch = "arm")]
23743#[target_feature(enable = "neon,v7")]
23744#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23745#[rustc_legacy_const_generics(2)]
23746#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23747pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) -> float32x2x3_t {
23748 static_assert_uimm_bits!(LANE, 1);
23749 unsafe extern "unadjusted" {
23750 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2f32.p0")]
23751 fn _vld3_lane_f32(
23752 ptr: *const i8,
23753 a: float32x2_t,
23754 b: float32x2_t,
23755 c: float32x2_t,
23756 n: i32,
23757 size: i32,
23758 ) -> float32x2x3_t;
23759 }
23760 _vld3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
23761}
23762#[doc = "Load multiple 3-element structures to two registers"]
23763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
23764#[doc = "## Safety"]
23765#[doc = " * Neon instrinsic unsafe"]
23766#[inline]
23767#[target_feature(enable = "neon")]
23768#[cfg(not(target_arch = "arm"))]
23769#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23770#[rustc_legacy_const_generics(2)]
23771#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23772pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8x8x3_t {
23773 static_assert_uimm_bits!(LANE, 3);
23774 unsafe extern "unadjusted" {
23775 #[cfg_attr(
23776 any(target_arch = "aarch64", target_arch = "arm64ec"),
23777 link_name = "llvm.aarch64.neon.ld3lane.v8i8.p0"
23778 )]
23779 fn _vld3_lane_s8(
23780 a: int8x8_t,
23781 b: int8x8_t,
23782 c: int8x8_t,
23783 n: i64,
23784 ptr: *const i8,
23785 ) -> int8x8x3_t;
23786 }
23787 _vld3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
23788}
23789#[doc = "Load multiple 3-element structures to two registers"]
23790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
23791#[doc = "## Safety"]
23792#[doc = " * Neon instrinsic unsafe"]
23793#[inline]
23794#[target_feature(enable = "neon")]
23795#[cfg(not(target_arch = "arm"))]
23796#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23797#[rustc_legacy_const_generics(2)]
23798#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23799pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> int16x4x3_t {
23800 static_assert_uimm_bits!(LANE, 2);
23801 unsafe extern "unadjusted" {
23802 #[cfg_attr(
23803 any(target_arch = "aarch64", target_arch = "arm64ec"),
23804 link_name = "llvm.aarch64.neon.ld3lane.v4i16.p0"
23805 )]
23806 fn _vld3_lane_s16(
23807 a: int16x4_t,
23808 b: int16x4_t,
23809 c: int16x4_t,
23810 n: i64,
23811 ptr: *const i8,
23812 ) -> int16x4x3_t;
23813 }
23814 _vld3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
23815}
23816#[doc = "Load multiple 3-element structures to two registers"]
23817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
23818#[doc = "## Safety"]
23819#[doc = " * Neon instrinsic unsafe"]
23820#[inline]
23821#[target_feature(enable = "neon")]
23822#[cfg(not(target_arch = "arm"))]
23823#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23824#[rustc_legacy_const_generics(2)]
23825#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23826pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) -> int16x8x3_t {
23827 static_assert_uimm_bits!(LANE, 4);
23828 unsafe extern "unadjusted" {
23829 #[cfg_attr(
23830 any(target_arch = "aarch64", target_arch = "arm64ec"),
23831 link_name = "llvm.aarch64.neon.ld3lane.v8i16.p0"
23832 )]
23833 fn _vld3q_lane_s16(
23834 a: int16x8_t,
23835 b: int16x8_t,
23836 c: int16x8_t,
23837 n: i64,
23838 ptr: *const i8,
23839 ) -> int16x8x3_t;
23840 }
23841 _vld3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
23842}
23843#[doc = "Load multiple 3-element structures to two registers"]
23844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
23845#[doc = "## Safety"]
23846#[doc = " * Neon instrinsic unsafe"]
23847#[inline]
23848#[target_feature(enable = "neon")]
23849#[cfg(not(target_arch = "arm"))]
23850#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23851#[rustc_legacy_const_generics(2)]
23852#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23853pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> int32x2x3_t {
23854 static_assert_uimm_bits!(LANE, 1);
23855 unsafe extern "unadjusted" {
23856 #[cfg_attr(
23857 any(target_arch = "aarch64", target_arch = "arm64ec"),
23858 link_name = "llvm.aarch64.neon.ld3lane.v2i32.p0"
23859 )]
23860 fn _vld3_lane_s32(
23861 a: int32x2_t,
23862 b: int32x2_t,
23863 c: int32x2_t,
23864 n: i64,
23865 ptr: *const i8,
23866 ) -> int32x2x3_t;
23867 }
23868 _vld3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
23869}
23870#[doc = "Load multiple 3-element structures to two registers"]
23871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
23872#[doc = "## Safety"]
23873#[doc = " * Neon instrinsic unsafe"]
23874#[inline]
23875#[target_feature(enable = "neon")]
23876#[cfg(not(target_arch = "arm"))]
23877#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23878#[rustc_legacy_const_generics(2)]
23879#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23880pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) -> int32x4x3_t {
23881 static_assert_uimm_bits!(LANE, 2);
23882 unsafe extern "unadjusted" {
23883 #[cfg_attr(
23884 any(target_arch = "aarch64", target_arch = "arm64ec"),
23885 link_name = "llvm.aarch64.neon.ld3lane.v4i32.p0"
23886 )]
23887 fn _vld3q_lane_s32(
23888 a: int32x4_t,
23889 b: int32x4_t,
23890 c: int32x4_t,
23891 n: i64,
23892 ptr: *const i8,
23893 ) -> int32x4x3_t;
23894 }
23895 _vld3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
23896}
23897#[doc = "Load multiple 3-element structures to two registers"]
23898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
23899#[doc = "## Safety"]
23900#[doc = " * Neon instrinsic unsafe"]
23901#[inline]
23902#[cfg(target_arch = "arm")]
23903#[target_feature(enable = "neon,v7")]
23904#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23905#[rustc_legacy_const_generics(2)]
23906#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23907pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8x8x3_t {
23908 static_assert_uimm_bits!(LANE, 3);
23909 unsafe extern "unadjusted" {
23910 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i8.p0")]
23911 fn _vld3_lane_s8(
23912 ptr: *const i8,
23913 a: int8x8_t,
23914 b: int8x8_t,
23915 c: int8x8_t,
23916 n: i32,
23917 size: i32,
23918 ) -> int8x8x3_t;
23919 }
23920 _vld3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1)
23921}
23922#[doc = "Load multiple 3-element structures to two registers"]
23923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
23924#[doc = "## Safety"]
23925#[doc = " * Neon instrinsic unsafe"]
23926#[inline]
23927#[cfg(target_arch = "arm")]
23928#[target_feature(enable = "neon,v7")]
23929#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23930#[rustc_legacy_const_generics(2)]
23931#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23932pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> int16x4x3_t {
23933 static_assert_uimm_bits!(LANE, 2);
23934 unsafe extern "unadjusted" {
23935 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i16.p0")]
23936 fn _vld3_lane_s16(
23937 ptr: *const i8,
23938 a: int16x4_t,
23939 b: int16x4_t,
23940 c: int16x4_t,
23941 n: i32,
23942 size: i32,
23943 ) -> int16x4x3_t;
23944 }
23945 _vld3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
23946}
23947#[doc = "Load multiple 3-element structures to two registers"]
23948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
23949#[doc = "## Safety"]
23950#[doc = " * Neon instrinsic unsafe"]
23951#[inline]
23952#[cfg(target_arch = "arm")]
23953#[target_feature(enable = "neon,v7")]
23954#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23955#[rustc_legacy_const_generics(2)]
23956#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23957pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) -> int16x8x3_t {
23958 static_assert_uimm_bits!(LANE, 3);
23959 unsafe extern "unadjusted" {
23960 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i16.p0")]
23961 fn _vld3q_lane_s16(
23962 ptr: *const i8,
23963 a: int16x8_t,
23964 b: int16x8_t,
23965 c: int16x8_t,
23966 n: i32,
23967 size: i32,
23968 ) -> int16x8x3_t;
23969 }
23970 _vld3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
23971}
23972#[doc = "Load multiple 3-element structures to two registers"]
23973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
23974#[doc = "## Safety"]
23975#[doc = " * Neon instrinsic unsafe"]
23976#[inline]
23977#[cfg(target_arch = "arm")]
23978#[target_feature(enable = "neon,v7")]
23979#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23980#[rustc_legacy_const_generics(2)]
23981#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23982pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> int32x2x3_t {
23983 static_assert_uimm_bits!(LANE, 1);
23984 unsafe extern "unadjusted" {
23985 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2i32.p0")]
23986 fn _vld3_lane_s32(
23987 ptr: *const i8,
23988 a: int32x2_t,
23989 b: int32x2_t,
23990 c: int32x2_t,
23991 n: i32,
23992 size: i32,
23993 ) -> int32x2x3_t;
23994 }
23995 _vld3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
23996}
23997#[doc = "Load multiple 3-element structures to two registers"]
23998#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
23999#[doc = "## Safety"]
24000#[doc = " * Neon instrinsic unsafe"]
24001#[inline]
24002#[cfg(target_arch = "arm")]
24003#[target_feature(enable = "neon,v7")]
24004#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
24005#[rustc_legacy_const_generics(2)]
24006#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24007pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) -> int32x4x3_t {
24008 static_assert_uimm_bits!(LANE, 2);
24009 unsafe extern "unadjusted" {
24010 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i32.p0")]
24011 fn _vld3q_lane_s32(
24012 ptr: *const i8,
24013 a: int32x4_t,
24014 b: int32x4_t,
24015 c: int32x4_t,
24016 n: i32,
24017 size: i32,
24018 ) -> int32x4x3_t;
24019 }
24020 _vld3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
24021}
24022#[doc = "Load multiple 3-element structures to three registers"]
24023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"]
24024#[doc = "## Safety"]
24025#[doc = " * Neon instrinsic unsafe"]
24026#[inline]
24027#[target_feature(enable = "neon")]
24028#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24029#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24030#[cfg_attr(
24031 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24032 assert_instr(ld3, LANE = 0)
24033)]
24034#[rustc_legacy_const_generics(2)]
24035#[cfg_attr(
24036 not(target_arch = "arm"),
24037 stable(feature = "neon_intrinsics", since = "1.59.0")
24038)]
24039#[cfg_attr(
24040 target_arch = "arm",
24041 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24042)]
24043pub unsafe fn vld3_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x3_t) -> uint8x8x3_t {
24044 static_assert_uimm_bits!(LANE, 3);
24045 transmute(vld3_lane_s8::<LANE>(transmute(a), transmute(b)))
24046}
24047#[doc = "Load multiple 3-element structures to three registers"]
24048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"]
24049#[doc = "## Safety"]
24050#[doc = " * Neon instrinsic unsafe"]
24051#[inline]
24052#[target_feature(enable = "neon")]
24053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24055#[cfg_attr(
24056 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24057 assert_instr(ld3, LANE = 0)
24058)]
24059#[rustc_legacy_const_generics(2)]
24060#[cfg_attr(
24061 not(target_arch = "arm"),
24062 stable(feature = "neon_intrinsics", since = "1.59.0")
24063)]
24064#[cfg_attr(
24065 target_arch = "arm",
24066 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24067)]
24068pub unsafe fn vld3_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x3_t) -> uint16x4x3_t {
24069 static_assert_uimm_bits!(LANE, 2);
24070 transmute(vld3_lane_s16::<LANE>(transmute(a), transmute(b)))
24071}
24072#[doc = "Load multiple 3-element structures to three registers"]
24073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"]
24074#[doc = "## Safety"]
24075#[doc = " * Neon instrinsic unsafe"]
24076#[inline]
24077#[target_feature(enable = "neon")]
24078#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24079#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24080#[cfg_attr(
24081 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24082 assert_instr(ld3, LANE = 0)
24083)]
24084#[rustc_legacy_const_generics(2)]
24085#[cfg_attr(
24086 not(target_arch = "arm"),
24087 stable(feature = "neon_intrinsics", since = "1.59.0")
24088)]
24089#[cfg_attr(
24090 target_arch = "arm",
24091 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24092)]
24093pub unsafe fn vld3q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x3_t) -> uint16x8x3_t {
24094 static_assert_uimm_bits!(LANE, 3);
24095 transmute(vld3q_lane_s16::<LANE>(transmute(a), transmute(b)))
24096}
24097#[doc = "Load multiple 3-element structures to three registers"]
24098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"]
24099#[doc = "## Safety"]
24100#[doc = " * Neon instrinsic unsafe"]
24101#[inline]
24102#[target_feature(enable = "neon")]
24103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24105#[cfg_attr(
24106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24107 assert_instr(ld3, LANE = 0)
24108)]
24109#[rustc_legacy_const_generics(2)]
24110#[cfg_attr(
24111 not(target_arch = "arm"),
24112 stable(feature = "neon_intrinsics", since = "1.59.0")
24113)]
24114#[cfg_attr(
24115 target_arch = "arm",
24116 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24117)]
24118pub unsafe fn vld3_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x3_t) -> uint32x2x3_t {
24119 static_assert_uimm_bits!(LANE, 1);
24120 transmute(vld3_lane_s32::<LANE>(transmute(a), transmute(b)))
24121}
24122#[doc = "Load multiple 3-element structures to three registers"]
24123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"]
24124#[doc = "## Safety"]
24125#[doc = " * Neon instrinsic unsafe"]
24126#[inline]
24127#[target_feature(enable = "neon")]
24128#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24129#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24130#[cfg_attr(
24131 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24132 assert_instr(ld3, LANE = 0)
24133)]
24134#[rustc_legacy_const_generics(2)]
24135#[cfg_attr(
24136 not(target_arch = "arm"),
24137 stable(feature = "neon_intrinsics", since = "1.59.0")
24138)]
24139#[cfg_attr(
24140 target_arch = "arm",
24141 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24142)]
24143pub unsafe fn vld3q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x3_t) -> uint32x4x3_t {
24144 static_assert_uimm_bits!(LANE, 2);
24145 transmute(vld3q_lane_s32::<LANE>(transmute(a), transmute(b)))
24146}
24147#[doc = "Load multiple 3-element structures to three registers"]
24148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"]
24149#[doc = "## Safety"]
24150#[doc = " * Neon instrinsic unsafe"]
24151#[inline]
24152#[target_feature(enable = "neon")]
24153#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24154#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24155#[cfg_attr(
24156 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24157 assert_instr(ld3, LANE = 0)
24158)]
24159#[rustc_legacy_const_generics(2)]
24160#[cfg_attr(
24161 not(target_arch = "arm"),
24162 stable(feature = "neon_intrinsics", since = "1.59.0")
24163)]
24164#[cfg_attr(
24165 target_arch = "arm",
24166 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24167)]
24168pub unsafe fn vld3_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x3_t) -> poly8x8x3_t {
24169 static_assert_uimm_bits!(LANE, 3);
24170 transmute(vld3_lane_s8::<LANE>(transmute(a), transmute(b)))
24171}
24172#[doc = "Load multiple 3-element structures to three registers"]
24173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"]
24174#[doc = "## Safety"]
24175#[doc = " * Neon instrinsic unsafe"]
24176#[inline]
24177#[target_feature(enable = "neon")]
24178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24180#[cfg_attr(
24181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24182 assert_instr(ld3, LANE = 0)
24183)]
24184#[rustc_legacy_const_generics(2)]
24185#[cfg_attr(
24186 not(target_arch = "arm"),
24187 stable(feature = "neon_intrinsics", since = "1.59.0")
24188)]
24189#[cfg_attr(
24190 target_arch = "arm",
24191 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24192)]
24193pub unsafe fn vld3_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x3_t) -> poly16x4x3_t {
24194 static_assert_uimm_bits!(LANE, 2);
24195 transmute(vld3_lane_s16::<LANE>(transmute(a), transmute(b)))
24196}
24197#[doc = "Load multiple 3-element structures to three registers"]
24198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"]
24199#[doc = "## Safety"]
24200#[doc = " * Neon instrinsic unsafe"]
24201#[inline]
24202#[target_feature(enable = "neon")]
24203#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24204#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24205#[cfg_attr(
24206 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24207 assert_instr(ld3, LANE = 0)
24208)]
24209#[rustc_legacy_const_generics(2)]
24210#[cfg_attr(
24211 not(target_arch = "arm"),
24212 stable(feature = "neon_intrinsics", since = "1.59.0")
24213)]
24214#[cfg_attr(
24215 target_arch = "arm",
24216 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24217)]
24218pub unsafe fn vld3q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x3_t) -> poly16x8x3_t {
24219 static_assert_uimm_bits!(LANE, 3);
24220 transmute(vld3q_lane_s16::<LANE>(transmute(a), transmute(b)))
24221}
24222#[doc = "Load multiple 3-element structures to three registers"]
24223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"]
24224#[doc = "## Safety"]
24225#[doc = " * Neon instrinsic unsafe"]
24226#[inline]
24227#[target_feature(enable = "neon,aes")]
24228#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
24229#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
24230#[cfg_attr(
24231 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24232 assert_instr(nop)
24233)]
24234#[cfg_attr(
24235 not(target_arch = "arm"),
24236 stable(feature = "neon_intrinsics", since = "1.59.0")
24237)]
24238#[cfg_attr(
24239 target_arch = "arm",
24240 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24241)]
24242pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
24243 transmute(vld3_s64(transmute(a)))
24244}
24245#[doc = "Load multiple 3-element structures to three registers"]
24246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
24247#[doc = "## Safety"]
24248#[doc = " * Neon instrinsic unsafe"]
24249#[inline]
24250#[target_feature(enable = "neon")]
24251#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24252#[cfg(not(target_arch = "arm"))]
24253#[cfg_attr(test, assert_instr(nop))]
24254pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
24255 unsafe extern "unadjusted" {
24256 #[cfg_attr(
24257 any(target_arch = "aarch64", target_arch = "arm64ec"),
24258 link_name = "llvm.aarch64.neon.ld3.v1i64.p0"
24259 )]
24260 fn _vld3_s64(ptr: *const int64x1_t) -> int64x1x3_t;
24261 }
24262 _vld3_s64(a as _)
24263}
24264#[doc = "Load multiple 3-element structures to three registers"]
24265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
24266#[doc = "## Safety"]
24267#[doc = " * Neon instrinsic unsafe"]
24268#[inline]
24269#[cfg(target_arch = "arm")]
24270#[target_feature(enable = "neon,v7")]
24271#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24272#[cfg_attr(test, assert_instr(nop))]
24273pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
24274 unsafe extern "unadjusted" {
24275 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v1i64.p0")]
24276 fn _vld3_s64(ptr: *const i8, size: i32) -> int64x1x3_t;
24277 }
24278 _vld3_s64(a as *const i8, 8)
24279}
24280#[doc = "Load multiple 3-element structures to three registers"]
24281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"]
24282#[doc = "## Safety"]
24283#[doc = " * Neon instrinsic unsafe"]
24284#[inline]
24285#[target_feature(enable = "neon")]
24286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24287#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
24288#[cfg_attr(
24289 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24290 assert_instr(nop)
24291)]
24292#[cfg_attr(
24293 not(target_arch = "arm"),
24294 stable(feature = "neon_intrinsics", since = "1.59.0")
24295)]
24296#[cfg_attr(
24297 target_arch = "arm",
24298 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24299)]
24300pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t {
24301 transmute(vld3_s64(transmute(a)))
24302}
24303#[doc = "Load multiple 3-element structures to three registers"]
24304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
24305#[doc = "## Safety"]
24306#[doc = " * Neon instrinsic unsafe"]
24307#[inline]
24308#[cfg(target_endian = "little")]
24309#[target_feature(enable = "neon")]
24310#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24311#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24312#[cfg_attr(
24313 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24314 assert_instr(ld3)
24315)]
24316#[cfg_attr(
24317 not(target_arch = "arm"),
24318 stable(feature = "neon_intrinsics", since = "1.59.0")
24319)]
24320#[cfg_attr(
24321 target_arch = "arm",
24322 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24323)]
24324pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
24325 transmute(vld3_s8(transmute(a)))
24326}
24327#[doc = "Load multiple 3-element structures to three registers"]
24328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
24329#[doc = "## Safety"]
24330#[doc = " * Neon instrinsic unsafe"]
24331#[inline]
24332#[cfg(target_endian = "big")]
24333#[target_feature(enable = "neon")]
24334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24335#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24336#[cfg_attr(
24337 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24338 assert_instr(ld3)
24339)]
24340#[cfg_attr(
24341 not(target_arch = "arm"),
24342 stable(feature = "neon_intrinsics", since = "1.59.0")
24343)]
24344#[cfg_attr(
24345 target_arch = "arm",
24346 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24347)]
24348pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
24349 let mut ret_val: uint8x8x3_t = transmute(vld3_s8(transmute(a)));
24350 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24351 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24352 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24353 ret_val
24354}
24355#[doc = "Load multiple 3-element structures to three registers"]
24356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
24357#[doc = "## Safety"]
24358#[doc = " * Neon instrinsic unsafe"]
24359#[inline]
24360#[cfg(target_endian = "little")]
24361#[target_feature(enable = "neon")]
24362#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24363#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24364#[cfg_attr(
24365 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24366 assert_instr(ld3)
24367)]
24368#[cfg_attr(
24369 not(target_arch = "arm"),
24370 stable(feature = "neon_intrinsics", since = "1.59.0")
24371)]
24372#[cfg_attr(
24373 target_arch = "arm",
24374 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24375)]
24376pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
24377 transmute(vld3q_s8(transmute(a)))
24378}
24379#[doc = "Load multiple 3-element structures to three registers"]
24380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
24381#[doc = "## Safety"]
24382#[doc = " * Neon instrinsic unsafe"]
24383#[inline]
24384#[cfg(target_endian = "big")]
24385#[target_feature(enable = "neon")]
24386#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24387#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24388#[cfg_attr(
24389 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24390 assert_instr(ld3)
24391)]
24392#[cfg_attr(
24393 not(target_arch = "arm"),
24394 stable(feature = "neon_intrinsics", since = "1.59.0")
24395)]
24396#[cfg_attr(
24397 target_arch = "arm",
24398 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24399)]
24400pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
24401 let mut ret_val: uint8x16x3_t = transmute(vld3q_s8(transmute(a)));
24402 ret_val.0 = unsafe {
24403 simd_shuffle!(
24404 ret_val.0,
24405 ret_val.0,
24406 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24407 )
24408 };
24409 ret_val.1 = unsafe {
24410 simd_shuffle!(
24411 ret_val.1,
24412 ret_val.1,
24413 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24414 )
24415 };
24416 ret_val.2 = unsafe {
24417 simd_shuffle!(
24418 ret_val.2,
24419 ret_val.2,
24420 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24421 )
24422 };
24423 ret_val
24424}
24425#[doc = "Load multiple 3-element structures to three registers"]
24426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
24427#[doc = "## Safety"]
24428#[doc = " * Neon instrinsic unsafe"]
24429#[inline]
24430#[cfg(target_endian = "little")]
24431#[target_feature(enable = "neon")]
24432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24433#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24434#[cfg_attr(
24435 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24436 assert_instr(ld3)
24437)]
24438#[cfg_attr(
24439 not(target_arch = "arm"),
24440 stable(feature = "neon_intrinsics", since = "1.59.0")
24441)]
24442#[cfg_attr(
24443 target_arch = "arm",
24444 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24445)]
24446pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
24447 transmute(vld3_s16(transmute(a)))
24448}
24449#[doc = "Load multiple 3-element structures to three registers"]
24450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
24451#[doc = "## Safety"]
24452#[doc = " * Neon instrinsic unsafe"]
24453#[inline]
24454#[cfg(target_endian = "big")]
24455#[target_feature(enable = "neon")]
24456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24458#[cfg_attr(
24459 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24460 assert_instr(ld3)
24461)]
24462#[cfg_attr(
24463 not(target_arch = "arm"),
24464 stable(feature = "neon_intrinsics", since = "1.59.0")
24465)]
24466#[cfg_attr(
24467 target_arch = "arm",
24468 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24469)]
24470pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
24471 let mut ret_val: uint16x4x3_t = transmute(vld3_s16(transmute(a)));
24472 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24473 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24474 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24475 ret_val
24476}
24477#[doc = "Load multiple 3-element structures to three registers"]
24478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
24479#[doc = "## Safety"]
24480#[doc = " * Neon instrinsic unsafe"]
24481#[inline]
24482#[cfg(target_endian = "little")]
24483#[target_feature(enable = "neon")]
24484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24486#[cfg_attr(
24487 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24488 assert_instr(ld3)
24489)]
24490#[cfg_attr(
24491 not(target_arch = "arm"),
24492 stable(feature = "neon_intrinsics", since = "1.59.0")
24493)]
24494#[cfg_attr(
24495 target_arch = "arm",
24496 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24497)]
24498pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
24499 transmute(vld3q_s16(transmute(a)))
24500}
24501#[doc = "Load multiple 3-element structures to three registers"]
24502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
24503#[doc = "## Safety"]
24504#[doc = " * Neon instrinsic unsafe"]
24505#[inline]
24506#[cfg(target_endian = "big")]
24507#[target_feature(enable = "neon")]
24508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24509#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24510#[cfg_attr(
24511 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24512 assert_instr(ld3)
24513)]
24514#[cfg_attr(
24515 not(target_arch = "arm"),
24516 stable(feature = "neon_intrinsics", since = "1.59.0")
24517)]
24518#[cfg_attr(
24519 target_arch = "arm",
24520 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24521)]
24522pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
24523 let mut ret_val: uint16x8x3_t = transmute(vld3q_s16(transmute(a)));
24524 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24525 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24526 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24527 ret_val
24528}
24529#[doc = "Load multiple 3-element structures to three registers"]
24530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
24531#[doc = "## Safety"]
24532#[doc = " * Neon instrinsic unsafe"]
24533#[inline]
24534#[cfg(target_endian = "little")]
24535#[target_feature(enable = "neon")]
24536#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24537#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24538#[cfg_attr(
24539 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24540 assert_instr(ld3)
24541)]
24542#[cfg_attr(
24543 not(target_arch = "arm"),
24544 stable(feature = "neon_intrinsics", since = "1.59.0")
24545)]
24546#[cfg_attr(
24547 target_arch = "arm",
24548 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24549)]
24550pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
24551 transmute(vld3_s32(transmute(a)))
24552}
24553#[doc = "Load multiple 3-element structures to three registers"]
24554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
24555#[doc = "## Safety"]
24556#[doc = " * Neon instrinsic unsafe"]
24557#[inline]
24558#[cfg(target_endian = "big")]
24559#[target_feature(enable = "neon")]
24560#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24561#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24562#[cfg_attr(
24563 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24564 assert_instr(ld3)
24565)]
24566#[cfg_attr(
24567 not(target_arch = "arm"),
24568 stable(feature = "neon_intrinsics", since = "1.59.0")
24569)]
24570#[cfg_attr(
24571 target_arch = "arm",
24572 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24573)]
24574pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
24575 let mut ret_val: uint32x2x3_t = transmute(vld3_s32(transmute(a)));
24576 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
24577 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
24578 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
24579 ret_val
24580}
24581#[doc = "Load multiple 3-element structures to three registers"]
24582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
24583#[doc = "## Safety"]
24584#[doc = " * Neon instrinsic unsafe"]
24585#[inline]
24586#[cfg(target_endian = "little")]
24587#[target_feature(enable = "neon")]
24588#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24589#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24590#[cfg_attr(
24591 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24592 assert_instr(ld3)
24593)]
24594#[cfg_attr(
24595 not(target_arch = "arm"),
24596 stable(feature = "neon_intrinsics", since = "1.59.0")
24597)]
24598#[cfg_attr(
24599 target_arch = "arm",
24600 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24601)]
24602pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
24603 transmute(vld3q_s32(transmute(a)))
24604}
24605#[doc = "Load multiple 3-element structures to three registers"]
24606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
24607#[doc = "## Safety"]
24608#[doc = " * Neon instrinsic unsafe"]
24609#[inline]
24610#[cfg(target_endian = "big")]
24611#[target_feature(enable = "neon")]
24612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24614#[cfg_attr(
24615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24616 assert_instr(ld3)
24617)]
24618#[cfg_attr(
24619 not(target_arch = "arm"),
24620 stable(feature = "neon_intrinsics", since = "1.59.0")
24621)]
24622#[cfg_attr(
24623 target_arch = "arm",
24624 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24625)]
24626pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
24627 let mut ret_val: uint32x4x3_t = transmute(vld3q_s32(transmute(a)));
24628 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24629 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24630 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24631 ret_val
24632}
24633#[doc = "Load multiple 3-element structures to three registers"]
24634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
24635#[doc = "## Safety"]
24636#[doc = " * Neon instrinsic unsafe"]
24637#[inline]
24638#[cfg(target_endian = "little")]
24639#[target_feature(enable = "neon")]
24640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24642#[cfg_attr(
24643 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24644 assert_instr(ld3)
24645)]
24646#[cfg_attr(
24647 not(target_arch = "arm"),
24648 stable(feature = "neon_intrinsics", since = "1.59.0")
24649)]
24650#[cfg_attr(
24651 target_arch = "arm",
24652 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24653)]
24654pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
24655 transmute(vld3_s8(transmute(a)))
24656}
24657#[doc = "Load multiple 3-element structures to three registers"]
24658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
24659#[doc = "## Safety"]
24660#[doc = " * Neon instrinsic unsafe"]
24661#[inline]
24662#[cfg(target_endian = "big")]
24663#[target_feature(enable = "neon")]
24664#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24665#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24666#[cfg_attr(
24667 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24668 assert_instr(ld3)
24669)]
24670#[cfg_attr(
24671 not(target_arch = "arm"),
24672 stable(feature = "neon_intrinsics", since = "1.59.0")
24673)]
24674#[cfg_attr(
24675 target_arch = "arm",
24676 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24677)]
24678pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
24679 let mut ret_val: poly8x8x3_t = transmute(vld3_s8(transmute(a)));
24680 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24681 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24682 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24683 ret_val
24684}
24685#[doc = "Load multiple 3-element structures to three registers"]
24686#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
24687#[doc = "## Safety"]
24688#[doc = " * Neon instrinsic unsafe"]
24689#[inline]
24690#[cfg(target_endian = "little")]
24691#[target_feature(enable = "neon")]
24692#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24693#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24694#[cfg_attr(
24695 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24696 assert_instr(ld3)
24697)]
24698#[cfg_attr(
24699 not(target_arch = "arm"),
24700 stable(feature = "neon_intrinsics", since = "1.59.0")
24701)]
24702#[cfg_attr(
24703 target_arch = "arm",
24704 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24705)]
24706pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
24707 transmute(vld3q_s8(transmute(a)))
24708}
24709#[doc = "Load multiple 3-element structures to three registers"]
24710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
24711#[doc = "## Safety"]
24712#[doc = " * Neon instrinsic unsafe"]
24713#[inline]
24714#[cfg(target_endian = "big")]
24715#[target_feature(enable = "neon")]
24716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24717#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24718#[cfg_attr(
24719 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24720 assert_instr(ld3)
24721)]
24722#[cfg_attr(
24723 not(target_arch = "arm"),
24724 stable(feature = "neon_intrinsics", since = "1.59.0")
24725)]
24726#[cfg_attr(
24727 target_arch = "arm",
24728 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24729)]
24730pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
24731 let mut ret_val: poly8x16x3_t = transmute(vld3q_s8(transmute(a)));
24732 ret_val.0 = unsafe {
24733 simd_shuffle!(
24734 ret_val.0,
24735 ret_val.0,
24736 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24737 )
24738 };
24739 ret_val.1 = unsafe {
24740 simd_shuffle!(
24741 ret_val.1,
24742 ret_val.1,
24743 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24744 )
24745 };
24746 ret_val.2 = unsafe {
24747 simd_shuffle!(
24748 ret_val.2,
24749 ret_val.2,
24750 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24751 )
24752 };
24753 ret_val
24754}
24755#[doc = "Load multiple 3-element structures to three registers"]
24756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
24757#[doc = "## Safety"]
24758#[doc = " * Neon instrinsic unsafe"]
24759#[inline]
24760#[cfg(target_endian = "little")]
24761#[target_feature(enable = "neon")]
24762#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24763#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24764#[cfg_attr(
24765 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24766 assert_instr(ld3)
24767)]
24768#[cfg_attr(
24769 not(target_arch = "arm"),
24770 stable(feature = "neon_intrinsics", since = "1.59.0")
24771)]
24772#[cfg_attr(
24773 target_arch = "arm",
24774 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24775)]
24776pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
24777 transmute(vld3_s16(transmute(a)))
24778}
24779#[doc = "Load multiple 3-element structures to three registers"]
24780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
24781#[doc = "## Safety"]
24782#[doc = " * Neon instrinsic unsafe"]
24783#[inline]
24784#[cfg(target_endian = "big")]
24785#[target_feature(enable = "neon")]
24786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24787#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24788#[cfg_attr(
24789 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24790 assert_instr(ld3)
24791)]
24792#[cfg_attr(
24793 not(target_arch = "arm"),
24794 stable(feature = "neon_intrinsics", since = "1.59.0")
24795)]
24796#[cfg_attr(
24797 target_arch = "arm",
24798 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24799)]
24800pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
24801 let mut ret_val: poly16x4x3_t = transmute(vld3_s16(transmute(a)));
24802 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24803 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24804 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24805 ret_val
24806}
24807#[doc = "Load multiple 3-element structures to three registers"]
24808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
24809#[doc = "## Safety"]
24810#[doc = " * Neon instrinsic unsafe"]
24811#[inline]
24812#[cfg(target_endian = "little")]
24813#[target_feature(enable = "neon")]
24814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24815#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24816#[cfg_attr(
24817 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24818 assert_instr(ld3)
24819)]
24820#[cfg_attr(
24821 not(target_arch = "arm"),
24822 stable(feature = "neon_intrinsics", since = "1.59.0")
24823)]
24824#[cfg_attr(
24825 target_arch = "arm",
24826 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24827)]
24828pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
24829 transmute(vld3q_s16(transmute(a)))
24830}
24831#[doc = "Load multiple 3-element structures to three registers"]
24832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
24833#[doc = "## Safety"]
24834#[doc = " * Neon instrinsic unsafe"]
24835#[inline]
24836#[cfg(target_endian = "big")]
24837#[target_feature(enable = "neon")]
24838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24839#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24840#[cfg_attr(
24841 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24842 assert_instr(ld3)
24843)]
24844#[cfg_attr(
24845 not(target_arch = "arm"),
24846 stable(feature = "neon_intrinsics", since = "1.59.0")
24847)]
24848#[cfg_attr(
24849 target_arch = "arm",
24850 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24851)]
24852pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
24853 let mut ret_val: poly16x8x3_t = transmute(vld3q_s16(transmute(a)));
24854 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24855 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24856 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24857 ret_val
24858}
24859#[doc = "Load multiple 3-element structures to three registers"]
24860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
24861#[doc = "## Safety"]
24862#[doc = " * Neon instrinsic unsafe"]
24863#[inline]
24864#[cfg(target_arch = "arm")]
24865#[target_feature(enable = "neon,v7")]
24866#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
24867#[rustc_legacy_const_generics(2)]
24868#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24869pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
24870 static_assert_uimm_bits!(LANE, 2);
24871 unsafe extern "unadjusted" {
24872 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0")]
24873 fn _vld3q_lane_f32(
24874 ptr: *const i8,
24875 a: float32x4_t,
24876 b: float32x4_t,
24877 c: float32x4_t,
24878 n: i32,
24879 size: i32,
24880 ) -> float32x4x3_t;
24881 }
24882 _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
24883}
24884#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
24886#[doc = "## Safety"]
24887#[doc = " * Neon instrinsic unsafe"]
24888#[inline]
24889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24890#[cfg(target_arch = "arm")]
24891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
24892#[target_feature(enable = "neon,fp16")]
24893#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24894pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
24895 unsafe extern "unadjusted" {
24896 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f16.p0f16")]
24897 fn _vld4_dup_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
24898 }
24899 _vld4_dup_f16(a as _, 2)
24900}
24901#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
24903#[doc = "## Safety"]
24904#[doc = " * Neon instrinsic unsafe"]
24905#[inline]
24906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24907#[cfg(target_arch = "arm")]
24908#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
24909#[target_feature(enable = "neon,fp16")]
24910#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24911pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
24912 unsafe extern "unadjusted" {
24913 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8f16.p0f16")]
24914 fn _vld4q_dup_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
24915 }
24916 _vld4q_dup_f16(a as _, 2)
24917}
24918#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
24920#[doc = "## Safety"]
24921#[doc = " * Neon instrinsic unsafe"]
24922#[inline]
24923#[cfg(not(target_arch = "arm"))]
24924#[cfg_attr(
24925 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24926 assert_instr(ld4r)
24927)]
24928#[target_feature(enable = "neon,fp16")]
24929#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24930pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
24931 unsafe extern "unadjusted" {
24932 #[cfg_attr(
24933 any(target_arch = "aarch64", target_arch = "arm64ec"),
24934 link_name = "llvm.aarch64.neon.ld4r.v4f16.p0f16"
24935 )]
24936 fn _vld4_dup_f16(ptr: *const f16) -> float16x4x4_t;
24937 }
24938 _vld4_dup_f16(a as _)
24939}
24940#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
24942#[doc = "## Safety"]
24943#[doc = " * Neon instrinsic unsafe"]
24944#[inline]
24945#[cfg(not(target_arch = "arm"))]
24946#[cfg_attr(
24947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24948 assert_instr(ld4r)
24949)]
24950#[target_feature(enable = "neon,fp16")]
24951#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24952pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
24953 unsafe extern "unadjusted" {
24954 #[cfg_attr(
24955 any(target_arch = "aarch64", target_arch = "arm64ec"),
24956 link_name = "llvm.aarch64.neon.ld4r.v8f16.p0f16"
24957 )]
24958 fn _vld4q_dup_f16(ptr: *const f16) -> float16x8x4_t;
24959 }
24960 _vld4q_dup_f16(a as _)
24961}
24962#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
24964#[doc = "## Safety"]
24965#[doc = " * Neon instrinsic unsafe"]
24966#[inline]
24967#[cfg(target_arch = "arm")]
24968#[target_feature(enable = "neon,v7")]
24969#[cfg_attr(test, assert_instr(vld4))]
24970#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24971pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
24972 unsafe extern "unadjusted" {
24973 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2f32.p0")]
24974 fn _vld4_dup_f32(ptr: *const i8, size: i32) -> float32x2x4_t;
24975 }
24976 _vld4_dup_f32(a as *const i8, 4)
24977}
24978#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
24980#[doc = "## Safety"]
24981#[doc = " * Neon instrinsic unsafe"]
24982#[inline]
24983#[cfg(target_arch = "arm")]
24984#[target_feature(enable = "neon,v7")]
24985#[cfg_attr(test, assert_instr(vld4))]
24986#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24987pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
24988 unsafe extern "unadjusted" {
24989 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f32.p0")]
24990 fn _vld4q_dup_f32(ptr: *const i8, size: i32) -> float32x4x4_t;
24991 }
24992 _vld4q_dup_f32(a as *const i8, 4)
24993}
24994#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
24996#[doc = "## Safety"]
24997#[doc = " * Neon instrinsic unsafe"]
24998#[inline]
24999#[cfg(target_arch = "arm")]
25000#[target_feature(enable = "neon,v7")]
25001#[cfg_attr(test, assert_instr(vld4))]
25002#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25003pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
25004 unsafe extern "unadjusted" {
25005 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i8.p0")]
25006 fn _vld4_dup_s8(ptr: *const i8, size: i32) -> int8x8x4_t;
25007 }
25008 _vld4_dup_s8(a as *const i8, 1)
25009}
25010#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
25012#[doc = "## Safety"]
25013#[doc = " * Neon instrinsic unsafe"]
25014#[inline]
25015#[cfg(target_arch = "arm")]
25016#[target_feature(enable = "neon,v7")]
25017#[cfg_attr(test, assert_instr(vld4))]
25018#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25019pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
25020 unsafe extern "unadjusted" {
25021 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v16i8.p0")]
25022 fn _vld4q_dup_s8(ptr: *const i8, size: i32) -> int8x16x4_t;
25023 }
25024 _vld4q_dup_s8(a as *const i8, 1)
25025}
25026#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
25028#[doc = "## Safety"]
25029#[doc = " * Neon instrinsic unsafe"]
25030#[inline]
25031#[cfg(target_arch = "arm")]
25032#[target_feature(enable = "neon,v7")]
25033#[cfg_attr(test, assert_instr(vld4))]
25034#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25035pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
25036 unsafe extern "unadjusted" {
25037 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i16.p0")]
25038 fn _vld4_dup_s16(ptr: *const i8, size: i32) -> int16x4x4_t;
25039 }
25040 _vld4_dup_s16(a as *const i8, 2)
25041}
25042#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
25044#[doc = "## Safety"]
25045#[doc = " * Neon instrinsic unsafe"]
25046#[inline]
25047#[cfg(target_arch = "arm")]
25048#[target_feature(enable = "neon,v7")]
25049#[cfg_attr(test, assert_instr(vld4))]
25050#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25051pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
25052 unsafe extern "unadjusted" {
25053 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i16.p0")]
25054 fn _vld4q_dup_s16(ptr: *const i8, size: i32) -> int16x8x4_t;
25055 }
25056 _vld4q_dup_s16(a as *const i8, 2)
25057}
25058#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
25060#[doc = "## Safety"]
25061#[doc = " * Neon instrinsic unsafe"]
25062#[inline]
25063#[cfg(target_arch = "arm")]
25064#[target_feature(enable = "neon,v7")]
25065#[cfg_attr(test, assert_instr(vld4))]
25066#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25067pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
25068 unsafe extern "unadjusted" {
25069 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2i32.p0")]
25070 fn _vld4_dup_s32(ptr: *const i8, size: i32) -> int32x2x4_t;
25071 }
25072 _vld4_dup_s32(a as *const i8, 4)
25073}
25074#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
25076#[doc = "## Safety"]
25077#[doc = " * Neon instrinsic unsafe"]
25078#[inline]
25079#[cfg(target_arch = "arm")]
25080#[target_feature(enable = "neon,v7")]
25081#[cfg_attr(test, assert_instr(vld4))]
25082#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25083pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
25084 unsafe extern "unadjusted" {
25085 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i32.p0")]
25086 fn _vld4q_dup_s32(ptr: *const i8, size: i32) -> int32x4x4_t;
25087 }
25088 _vld4q_dup_s32(a as *const i8, 4)
25089}
25090#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
25092#[doc = "## Safety"]
25093#[doc = " * Neon instrinsic unsafe"]
25094#[inline]
25095#[target_feature(enable = "neon")]
25096#[cfg(not(target_arch = "arm"))]
25097#[cfg_attr(test, assert_instr(ld4r))]
25098#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25099pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
25100 unsafe extern "unadjusted" {
25101 #[cfg_attr(
25102 any(target_arch = "aarch64", target_arch = "arm64ec"),
25103 link_name = "llvm.aarch64.neon.ld4r.v2f32.p0f32.p0"
25104 )]
25105 fn _vld4_dup_f32(ptr: *const f32) -> float32x2x4_t;
25106 }
25107 _vld4_dup_f32(a as _)
25108}
25109#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
25111#[doc = "## Safety"]
25112#[doc = " * Neon instrinsic unsafe"]
25113#[inline]
25114#[target_feature(enable = "neon")]
25115#[cfg(not(target_arch = "arm"))]
25116#[cfg_attr(test, assert_instr(ld4r))]
25117#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25118pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
25119 unsafe extern "unadjusted" {
25120 #[cfg_attr(
25121 any(target_arch = "aarch64", target_arch = "arm64ec"),
25122 link_name = "llvm.aarch64.neon.ld4r.v4f32.p0f32.p0"
25123 )]
25124 fn _vld4q_dup_f32(ptr: *const f32) -> float32x4x4_t;
25125 }
25126 _vld4q_dup_f32(a as _)
25127}
25128#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
25130#[doc = "## Safety"]
25131#[doc = " * Neon instrinsic unsafe"]
25132#[inline]
25133#[target_feature(enable = "neon")]
25134#[cfg(not(target_arch = "arm"))]
25135#[cfg_attr(test, assert_instr(ld4r))]
25136#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25137pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
25138 unsafe extern "unadjusted" {
25139 #[cfg_attr(
25140 any(target_arch = "aarch64", target_arch = "arm64ec"),
25141 link_name = "llvm.aarch64.neon.ld4r.v8i8.p0i8.p0"
25142 )]
25143 fn _vld4_dup_s8(ptr: *const i8) -> int8x8x4_t;
25144 }
25145 _vld4_dup_s8(a as _)
25146}
25147#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
25149#[doc = "## Safety"]
25150#[doc = " * Neon instrinsic unsafe"]
25151#[inline]
25152#[target_feature(enable = "neon")]
25153#[cfg(not(target_arch = "arm"))]
25154#[cfg_attr(test, assert_instr(ld4r))]
25155#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25156pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
25157 unsafe extern "unadjusted" {
25158 #[cfg_attr(
25159 any(target_arch = "aarch64", target_arch = "arm64ec"),
25160 link_name = "llvm.aarch64.neon.ld4r.v16i8.p0i8.p0"
25161 )]
25162 fn _vld4q_dup_s8(ptr: *const i8) -> int8x16x4_t;
25163 }
25164 _vld4q_dup_s8(a as _)
25165}
25166#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
25168#[doc = "## Safety"]
25169#[doc = " * Neon instrinsic unsafe"]
25170#[inline]
25171#[target_feature(enable = "neon")]
25172#[cfg(not(target_arch = "arm"))]
25173#[cfg_attr(test, assert_instr(ld4r))]
25174#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25175pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
25176 unsafe extern "unadjusted" {
25177 #[cfg_attr(
25178 any(target_arch = "aarch64", target_arch = "arm64ec"),
25179 link_name = "llvm.aarch64.neon.ld4r.v4i16.p0i16.p0"
25180 )]
25181 fn _vld4_dup_s16(ptr: *const i16) -> int16x4x4_t;
25182 }
25183 _vld4_dup_s16(a as _)
25184}
25185#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
25187#[doc = "## Safety"]
25188#[doc = " * Neon instrinsic unsafe"]
25189#[inline]
25190#[target_feature(enable = "neon")]
25191#[cfg(not(target_arch = "arm"))]
25192#[cfg_attr(test, assert_instr(ld4r))]
25193#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25194pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
25195 unsafe extern "unadjusted" {
25196 #[cfg_attr(
25197 any(target_arch = "aarch64", target_arch = "arm64ec"),
25198 link_name = "llvm.aarch64.neon.ld4r.v8i16.p0i16.p0"
25199 )]
25200 fn _vld4q_dup_s16(ptr: *const i16) -> int16x8x4_t;
25201 }
25202 _vld4q_dup_s16(a as _)
25203}
25204#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
25206#[doc = "## Safety"]
25207#[doc = " * Neon instrinsic unsafe"]
25208#[inline]
25209#[target_feature(enable = "neon")]
25210#[cfg(not(target_arch = "arm"))]
25211#[cfg_attr(test, assert_instr(ld4r))]
25212#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25213pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
25214 unsafe extern "unadjusted" {
25215 #[cfg_attr(
25216 any(target_arch = "aarch64", target_arch = "arm64ec"),
25217 link_name = "llvm.aarch64.neon.ld4r.v2i32.p0i32.p0"
25218 )]
25219 fn _vld4_dup_s32(ptr: *const i32) -> int32x2x4_t;
25220 }
25221 _vld4_dup_s32(a as _)
25222}
25223#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
25225#[doc = "## Safety"]
25226#[doc = " * Neon instrinsic unsafe"]
25227#[inline]
25228#[target_feature(enable = "neon")]
25229#[cfg(not(target_arch = "arm"))]
25230#[cfg_attr(test, assert_instr(ld4r))]
25231#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25232pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
25233 unsafe extern "unadjusted" {
25234 #[cfg_attr(
25235 any(target_arch = "aarch64", target_arch = "arm64ec"),
25236 link_name = "llvm.aarch64.neon.ld4r.v4i32.p0i32.p0"
25237 )]
25238 fn _vld4q_dup_s32(ptr: *const i32) -> int32x4x4_t;
25239 }
25240 _vld4q_dup_s32(a as _)
25241}
25242#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
25244#[doc = "## Safety"]
25245#[doc = " * Neon instrinsic unsafe"]
25246#[inline]
25247#[target_feature(enable = "neon")]
25248#[cfg(not(target_arch = "arm"))]
25249#[cfg_attr(test, assert_instr(ld4r))]
25250#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25251pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
25252 unsafe extern "unadjusted" {
25253 #[cfg_attr(
25254 any(target_arch = "aarch64", target_arch = "arm64ec"),
25255 link_name = "llvm.aarch64.neon.ld4r.v1i64.p0i64.p0"
25256 )]
25257 fn _vld4_dup_s64(ptr: *const i64) -> int64x1x4_t;
25258 }
25259 _vld4_dup_s64(a as _)
25260}
25261#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"]
25263#[doc = "## Safety"]
25264#[doc = " * Neon instrinsic unsafe"]
25265#[inline]
25266#[target_feature(enable = "neon,aes")]
25267#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
25268#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
25269#[cfg_attr(
25270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25271 assert_instr(ld4r)
25272)]
25273#[cfg_attr(
25274 not(target_arch = "arm"),
25275 stable(feature = "neon_intrinsics", since = "1.59.0")
25276)]
25277#[cfg_attr(
25278 target_arch = "arm",
25279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25280)]
25281pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t {
25282 transmute(vld4_dup_s64(transmute(a)))
25283}
25284#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
25286#[doc = "## Safety"]
25287#[doc = " * Neon instrinsic unsafe"]
25288#[inline]
25289#[cfg(target_arch = "arm")]
25290#[target_feature(enable = "neon,v7")]
25291#[cfg_attr(test, assert_instr(nop))]
25292#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25293pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
25294 unsafe extern "unadjusted" {
25295 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v1i64.p0")]
25296 fn _vld4_dup_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
25297 }
25298 _vld4_dup_s64(a as *const i8, 8)
25299}
25300#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"]
25302#[doc = "## Safety"]
25303#[doc = " * Neon instrinsic unsafe"]
25304#[inline]
25305#[target_feature(enable = "neon")]
25306#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25307#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
25308#[cfg_attr(
25309 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25310 assert_instr(ld4r)
25311)]
25312#[cfg_attr(
25313 not(target_arch = "arm"),
25314 stable(feature = "neon_intrinsics", since = "1.59.0")
25315)]
25316#[cfg_attr(
25317 target_arch = "arm",
25318 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25319)]
25320pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t {
25321 transmute(vld4_dup_s64(transmute(a)))
25322}
25323#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
25325#[doc = "## Safety"]
25326#[doc = " * Neon instrinsic unsafe"]
25327#[inline]
25328#[cfg(target_endian = "little")]
25329#[target_feature(enable = "neon")]
25330#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25331#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25332#[cfg_attr(
25333 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25334 assert_instr(ld4r)
25335)]
25336#[cfg_attr(
25337 not(target_arch = "arm"),
25338 stable(feature = "neon_intrinsics", since = "1.59.0")
25339)]
25340#[cfg_attr(
25341 target_arch = "arm",
25342 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25343)]
25344pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
25345 transmute(vld4_dup_s8(transmute(a)))
25346}
25347#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
25349#[doc = "## Safety"]
25350#[doc = " * Neon instrinsic unsafe"]
25351#[inline]
25352#[cfg(target_endian = "big")]
25353#[target_feature(enable = "neon")]
25354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25355#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25356#[cfg_attr(
25357 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25358 assert_instr(ld4r)
25359)]
25360#[cfg_attr(
25361 not(target_arch = "arm"),
25362 stable(feature = "neon_intrinsics", since = "1.59.0")
25363)]
25364#[cfg_attr(
25365 target_arch = "arm",
25366 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25367)]
25368pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
25369 let mut ret_val: uint8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
25370 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25371 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25372 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25373 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25374 ret_val
25375}
25376#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
25378#[doc = "## Safety"]
25379#[doc = " * Neon instrinsic unsafe"]
25380#[inline]
25381#[cfg(target_endian = "little")]
25382#[target_feature(enable = "neon")]
25383#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25384#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25385#[cfg_attr(
25386 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25387 assert_instr(ld4r)
25388)]
25389#[cfg_attr(
25390 not(target_arch = "arm"),
25391 stable(feature = "neon_intrinsics", since = "1.59.0")
25392)]
25393#[cfg_attr(
25394 target_arch = "arm",
25395 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25396)]
25397pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
25398 transmute(vld4q_dup_s8(transmute(a)))
25399}
25400#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
25402#[doc = "## Safety"]
25403#[doc = " * Neon instrinsic unsafe"]
25404#[inline]
25405#[cfg(target_endian = "big")]
25406#[target_feature(enable = "neon")]
25407#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25408#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25409#[cfg_attr(
25410 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25411 assert_instr(ld4r)
25412)]
25413#[cfg_attr(
25414 not(target_arch = "arm"),
25415 stable(feature = "neon_intrinsics", since = "1.59.0")
25416)]
25417#[cfg_attr(
25418 target_arch = "arm",
25419 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25420)]
25421pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
25422 let mut ret_val: uint8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
25423 ret_val.0 = unsafe {
25424 simd_shuffle!(
25425 ret_val.0,
25426 ret_val.0,
25427 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25428 )
25429 };
25430 ret_val.1 = unsafe {
25431 simd_shuffle!(
25432 ret_val.1,
25433 ret_val.1,
25434 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25435 )
25436 };
25437 ret_val.2 = unsafe {
25438 simd_shuffle!(
25439 ret_val.2,
25440 ret_val.2,
25441 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25442 )
25443 };
25444 ret_val.3 = unsafe {
25445 simd_shuffle!(
25446 ret_val.3,
25447 ret_val.3,
25448 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25449 )
25450 };
25451 ret_val
25452}
25453#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
25455#[doc = "## Safety"]
25456#[doc = " * Neon instrinsic unsafe"]
25457#[inline]
25458#[cfg(target_endian = "little")]
25459#[target_feature(enable = "neon")]
25460#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25461#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25462#[cfg_attr(
25463 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25464 assert_instr(ld4r)
25465)]
25466#[cfg_attr(
25467 not(target_arch = "arm"),
25468 stable(feature = "neon_intrinsics", since = "1.59.0")
25469)]
25470#[cfg_attr(
25471 target_arch = "arm",
25472 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25473)]
25474pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
25475 transmute(vld4_dup_s16(transmute(a)))
25476}
25477#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
25479#[doc = "## Safety"]
25480#[doc = " * Neon instrinsic unsafe"]
25481#[inline]
25482#[cfg(target_endian = "big")]
25483#[target_feature(enable = "neon")]
25484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25485#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25486#[cfg_attr(
25487 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25488 assert_instr(ld4r)
25489)]
25490#[cfg_attr(
25491 not(target_arch = "arm"),
25492 stable(feature = "neon_intrinsics", since = "1.59.0")
25493)]
25494#[cfg_attr(
25495 target_arch = "arm",
25496 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25497)]
25498pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
25499 let mut ret_val: uint16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
25500 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25501 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25502 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25503 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25504 ret_val
25505}
25506#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
25508#[doc = "## Safety"]
25509#[doc = " * Neon instrinsic unsafe"]
25510#[inline]
25511#[cfg(target_endian = "little")]
25512#[target_feature(enable = "neon")]
25513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25515#[cfg_attr(
25516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25517 assert_instr(ld4r)
25518)]
25519#[cfg_attr(
25520 not(target_arch = "arm"),
25521 stable(feature = "neon_intrinsics", since = "1.59.0")
25522)]
25523#[cfg_attr(
25524 target_arch = "arm",
25525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25526)]
25527pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
25528 transmute(vld4q_dup_s16(transmute(a)))
25529}
25530#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
25532#[doc = "## Safety"]
25533#[doc = " * Neon instrinsic unsafe"]
25534#[inline]
25535#[cfg(target_endian = "big")]
25536#[target_feature(enable = "neon")]
25537#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25538#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25539#[cfg_attr(
25540 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25541 assert_instr(ld4r)
25542)]
25543#[cfg_attr(
25544 not(target_arch = "arm"),
25545 stable(feature = "neon_intrinsics", since = "1.59.0")
25546)]
25547#[cfg_attr(
25548 target_arch = "arm",
25549 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25550)]
25551pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
25552 let mut ret_val: uint16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
25553 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25554 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25555 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25556 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25557 ret_val
25558}
25559#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
25561#[doc = "## Safety"]
25562#[doc = " * Neon instrinsic unsafe"]
25563#[inline]
25564#[cfg(target_endian = "little")]
25565#[target_feature(enable = "neon")]
25566#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25567#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25568#[cfg_attr(
25569 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25570 assert_instr(ld4r)
25571)]
25572#[cfg_attr(
25573 not(target_arch = "arm"),
25574 stable(feature = "neon_intrinsics", since = "1.59.0")
25575)]
25576#[cfg_attr(
25577 target_arch = "arm",
25578 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25579)]
25580pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
25581 transmute(vld4_dup_s32(transmute(a)))
25582}
25583#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
25585#[doc = "## Safety"]
25586#[doc = " * Neon instrinsic unsafe"]
25587#[inline]
25588#[cfg(target_endian = "big")]
25589#[target_feature(enable = "neon")]
25590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25591#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25592#[cfg_attr(
25593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25594 assert_instr(ld4r)
25595)]
25596#[cfg_attr(
25597 not(target_arch = "arm"),
25598 stable(feature = "neon_intrinsics", since = "1.59.0")
25599)]
25600#[cfg_attr(
25601 target_arch = "arm",
25602 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25603)]
25604pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
25605 let mut ret_val: uint32x2x4_t = transmute(vld4_dup_s32(transmute(a)));
25606 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
25607 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
25608 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
25609 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
25610 ret_val
25611}
25612#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
25614#[doc = "## Safety"]
25615#[doc = " * Neon instrinsic unsafe"]
25616#[inline]
25617#[cfg(target_endian = "little")]
25618#[target_feature(enable = "neon")]
25619#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25621#[cfg_attr(
25622 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25623 assert_instr(ld4r)
25624)]
25625#[cfg_attr(
25626 not(target_arch = "arm"),
25627 stable(feature = "neon_intrinsics", since = "1.59.0")
25628)]
25629#[cfg_attr(
25630 target_arch = "arm",
25631 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25632)]
25633pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
25634 transmute(vld4q_dup_s32(transmute(a)))
25635}
25636#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
25638#[doc = "## Safety"]
25639#[doc = " * Neon instrinsic unsafe"]
25640#[inline]
25641#[cfg(target_endian = "big")]
25642#[target_feature(enable = "neon")]
25643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25645#[cfg_attr(
25646 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25647 assert_instr(ld4r)
25648)]
25649#[cfg_attr(
25650 not(target_arch = "arm"),
25651 stable(feature = "neon_intrinsics", since = "1.59.0")
25652)]
25653#[cfg_attr(
25654 target_arch = "arm",
25655 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25656)]
25657pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
25658 let mut ret_val: uint32x4x4_t = transmute(vld4q_dup_s32(transmute(a)));
25659 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25660 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25661 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25662 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25663 ret_val
25664}
25665#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
25667#[doc = "## Safety"]
25668#[doc = " * Neon instrinsic unsafe"]
25669#[inline]
25670#[cfg(target_endian = "little")]
25671#[target_feature(enable = "neon")]
25672#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25673#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25674#[cfg_attr(
25675 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25676 assert_instr(ld4r)
25677)]
25678#[cfg_attr(
25679 not(target_arch = "arm"),
25680 stable(feature = "neon_intrinsics", since = "1.59.0")
25681)]
25682#[cfg_attr(
25683 target_arch = "arm",
25684 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25685)]
25686pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
25687 transmute(vld4_dup_s8(transmute(a)))
25688}
25689#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
25691#[doc = "## Safety"]
25692#[doc = " * Neon instrinsic unsafe"]
25693#[inline]
25694#[cfg(target_endian = "big")]
25695#[target_feature(enable = "neon")]
25696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25697#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25698#[cfg_attr(
25699 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25700 assert_instr(ld4r)
25701)]
25702#[cfg_attr(
25703 not(target_arch = "arm"),
25704 stable(feature = "neon_intrinsics", since = "1.59.0")
25705)]
25706#[cfg_attr(
25707 target_arch = "arm",
25708 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25709)]
25710pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
25711 let mut ret_val: poly8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
25712 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25713 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25714 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25715 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25716 ret_val
25717}
25718#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
25720#[doc = "## Safety"]
25721#[doc = " * Neon instrinsic unsafe"]
25722#[inline]
25723#[cfg(target_endian = "little")]
25724#[target_feature(enable = "neon")]
25725#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25726#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25727#[cfg_attr(
25728 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25729 assert_instr(ld4r)
25730)]
25731#[cfg_attr(
25732 not(target_arch = "arm"),
25733 stable(feature = "neon_intrinsics", since = "1.59.0")
25734)]
25735#[cfg_attr(
25736 target_arch = "arm",
25737 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25738)]
25739pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
25740 transmute(vld4q_dup_s8(transmute(a)))
25741}
25742#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
25744#[doc = "## Safety"]
25745#[doc = " * Neon instrinsic unsafe"]
25746#[inline]
25747#[cfg(target_endian = "big")]
25748#[target_feature(enable = "neon")]
25749#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25750#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25751#[cfg_attr(
25752 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25753 assert_instr(ld4r)
25754)]
25755#[cfg_attr(
25756 not(target_arch = "arm"),
25757 stable(feature = "neon_intrinsics", since = "1.59.0")
25758)]
25759#[cfg_attr(
25760 target_arch = "arm",
25761 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25762)]
25763pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
25764 let mut ret_val: poly8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
25765 ret_val.0 = unsafe {
25766 simd_shuffle!(
25767 ret_val.0,
25768 ret_val.0,
25769 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25770 )
25771 };
25772 ret_val.1 = unsafe {
25773 simd_shuffle!(
25774 ret_val.1,
25775 ret_val.1,
25776 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25777 )
25778 };
25779 ret_val.2 = unsafe {
25780 simd_shuffle!(
25781 ret_val.2,
25782 ret_val.2,
25783 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25784 )
25785 };
25786 ret_val.3 = unsafe {
25787 simd_shuffle!(
25788 ret_val.3,
25789 ret_val.3,
25790 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25791 )
25792 };
25793 ret_val
25794}
25795#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
25797#[doc = "## Safety"]
25798#[doc = " * Neon instrinsic unsafe"]
25799#[inline]
25800#[cfg(target_endian = "little")]
25801#[target_feature(enable = "neon")]
25802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25803#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25804#[cfg_attr(
25805 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25806 assert_instr(ld4r)
25807)]
25808#[cfg_attr(
25809 not(target_arch = "arm"),
25810 stable(feature = "neon_intrinsics", since = "1.59.0")
25811)]
25812#[cfg_attr(
25813 target_arch = "arm",
25814 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25815)]
25816pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
25817 transmute(vld4_dup_s16(transmute(a)))
25818}
25819#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
25821#[doc = "## Safety"]
25822#[doc = " * Neon instrinsic unsafe"]
25823#[inline]
25824#[cfg(target_endian = "big")]
25825#[target_feature(enable = "neon")]
25826#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25827#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25828#[cfg_attr(
25829 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25830 assert_instr(ld4r)
25831)]
25832#[cfg_attr(
25833 not(target_arch = "arm"),
25834 stable(feature = "neon_intrinsics", since = "1.59.0")
25835)]
25836#[cfg_attr(
25837 target_arch = "arm",
25838 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25839)]
25840pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
25841 let mut ret_val: poly16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
25842 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25843 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25844 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25845 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25846 ret_val
25847}
25848#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
25850#[doc = "## Safety"]
25851#[doc = " * Neon instrinsic unsafe"]
25852#[inline]
25853#[cfg(target_endian = "little")]
25854#[target_feature(enable = "neon")]
25855#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25856#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25857#[cfg_attr(
25858 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25859 assert_instr(ld4r)
25860)]
25861#[cfg_attr(
25862 not(target_arch = "arm"),
25863 stable(feature = "neon_intrinsics", since = "1.59.0")
25864)]
25865#[cfg_attr(
25866 target_arch = "arm",
25867 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25868)]
25869pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
25870 transmute(vld4q_dup_s16(transmute(a)))
25871}
25872#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
25874#[doc = "## Safety"]
25875#[doc = " * Neon instrinsic unsafe"]
25876#[inline]
25877#[cfg(target_endian = "big")]
25878#[target_feature(enable = "neon")]
25879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25881#[cfg_attr(
25882 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25883 assert_instr(ld4r)
25884)]
25885#[cfg_attr(
25886 not(target_arch = "arm"),
25887 stable(feature = "neon_intrinsics", since = "1.59.0")
25888)]
25889#[cfg_attr(
25890 target_arch = "arm",
25891 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25892)]
25893pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
25894 let mut ret_val: poly16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
25895 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25896 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25897 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25898 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25899 ret_val
25900}
25901#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
25903#[doc = "## Safety"]
25904#[doc = " * Neon instrinsic unsafe"]
25905#[inline]
25906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25907#[cfg(target_arch = "arm")]
25908#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25909#[target_feature(enable = "neon,fp16")]
25910#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25911pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
25912 unsafe extern "unadjusted" {
25913 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f16.p0f16")]
25914 fn _vld4_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
25915 }
25916 _vld4_f16(a as _, 2)
25917}
25918#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
25920#[doc = "## Safety"]
25921#[doc = " * Neon instrinsic unsafe"]
25922#[inline]
25923#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25924#[cfg(target_arch = "arm")]
25925#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25926#[target_feature(enable = "neon,fp16")]
25927#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25928pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
25929 unsafe extern "unadjusted" {
25930 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8f16.p0f16")]
25931 fn _vld4q_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
25932 }
25933 _vld4q_f16(a as _, 2)
25934}
25935#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
25937#[doc = "## Safety"]
25938#[doc = " * Neon instrinsic unsafe"]
25939#[inline]
25940#[cfg(not(target_arch = "arm"))]
25941#[cfg_attr(
25942 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25943 assert_instr(ld4)
25944)]
25945#[target_feature(enable = "neon,fp16")]
25946#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25947pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
25948 unsafe extern "unadjusted" {
25949 #[cfg_attr(
25950 any(target_arch = "aarch64", target_arch = "arm64ec"),
25951 link_name = "llvm.aarch64.neon.ld4.v4f16.p0f16"
25952 )]
25953 fn _vld4_f16(ptr: *const f16) -> float16x4x4_t;
25954 }
25955 _vld4_f16(a as _)
25956}
25957#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
25959#[doc = "## Safety"]
25960#[doc = " * Neon instrinsic unsafe"]
25961#[inline]
25962#[cfg(not(target_arch = "arm"))]
25963#[cfg_attr(
25964 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25965 assert_instr(ld4)
25966)]
25967#[target_feature(enable = "neon,fp16")]
25968#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25969pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
25970 unsafe extern "unadjusted" {
25971 #[cfg_attr(
25972 any(target_arch = "aarch64", target_arch = "arm64ec"),
25973 link_name = "llvm.aarch64.neon.ld4.v8f16.p0f16"
25974 )]
25975 fn _vld4q_f16(ptr: *const f16) -> float16x8x4_t;
25976 }
25977 _vld4q_f16(a as _)
25978}
25979#[doc = "Load multiple 4-element structures to four registers"]
25980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
25981#[doc = "## Safety"]
25982#[doc = " * Neon instrinsic unsafe"]
25983#[inline]
25984#[target_feature(enable = "neon")]
25985#[cfg(not(target_arch = "arm"))]
25986#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25987#[cfg_attr(test, assert_instr(ld4))]
25988pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
25989 unsafe extern "unadjusted" {
25990 #[cfg_attr(
25991 any(target_arch = "aarch64", target_arch = "arm64ec"),
25992 link_name = "llvm.aarch64.neon.ld4.v2f32.p0"
25993 )]
25994 fn _vld4_f32(ptr: *const float32x2_t) -> float32x2x4_t;
25995 }
25996 _vld4_f32(a as _)
25997}
25998#[doc = "Load multiple 4-element structures to four registers"]
25999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
26000#[doc = "## Safety"]
26001#[doc = " * Neon instrinsic unsafe"]
26002#[inline]
26003#[target_feature(enable = "neon")]
26004#[cfg(not(target_arch = "arm"))]
26005#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26006#[cfg_attr(test, assert_instr(ld4))]
26007pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
26008 unsafe extern "unadjusted" {
26009 #[cfg_attr(
26010 any(target_arch = "aarch64", target_arch = "arm64ec"),
26011 link_name = "llvm.aarch64.neon.ld4.v4f32.p0"
26012 )]
26013 fn _vld4q_f32(ptr: *const float32x4_t) -> float32x4x4_t;
26014 }
26015 _vld4q_f32(a as _)
26016}
26017#[doc = "Load multiple 4-element structures to four registers"]
26018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
26019#[doc = "## Safety"]
26020#[doc = " * Neon instrinsic unsafe"]
26021#[inline]
26022#[target_feature(enable = "neon")]
26023#[cfg(not(target_arch = "arm"))]
26024#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26025#[cfg_attr(test, assert_instr(ld4))]
26026pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
26027 unsafe extern "unadjusted" {
26028 #[cfg_attr(
26029 any(target_arch = "aarch64", target_arch = "arm64ec"),
26030 link_name = "llvm.aarch64.neon.ld4.v8i8.p0"
26031 )]
26032 fn _vld4_s8(ptr: *const int8x8_t) -> int8x8x4_t;
26033 }
26034 _vld4_s8(a as _)
26035}
26036#[doc = "Load multiple 4-element structures to four registers"]
26037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
26038#[doc = "## Safety"]
26039#[doc = " * Neon instrinsic unsafe"]
26040#[inline]
26041#[target_feature(enable = "neon")]
26042#[cfg(not(target_arch = "arm"))]
26043#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26044#[cfg_attr(test, assert_instr(ld4))]
26045pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
26046 unsafe extern "unadjusted" {
26047 #[cfg_attr(
26048 any(target_arch = "aarch64", target_arch = "arm64ec"),
26049 link_name = "llvm.aarch64.neon.ld4.v16i8.p0"
26050 )]
26051 fn _vld4q_s8(ptr: *const int8x16_t) -> int8x16x4_t;
26052 }
26053 _vld4q_s8(a as _)
26054}
26055#[doc = "Load multiple 4-element structures to four registers"]
26056#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
26057#[doc = "## Safety"]
26058#[doc = " * Neon instrinsic unsafe"]
26059#[inline]
26060#[target_feature(enable = "neon")]
26061#[cfg(not(target_arch = "arm"))]
26062#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26063#[cfg_attr(test, assert_instr(ld4))]
26064pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
26065 unsafe extern "unadjusted" {
26066 #[cfg_attr(
26067 any(target_arch = "aarch64", target_arch = "arm64ec"),
26068 link_name = "llvm.aarch64.neon.ld4.v4i16.p0"
26069 )]
26070 fn _vld4_s16(ptr: *const int16x4_t) -> int16x4x4_t;
26071 }
26072 _vld4_s16(a as _)
26073}
26074#[doc = "Load multiple 4-element structures to four registers"]
26075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
26076#[doc = "## Safety"]
26077#[doc = " * Neon instrinsic unsafe"]
26078#[inline]
26079#[target_feature(enable = "neon")]
26080#[cfg(not(target_arch = "arm"))]
26081#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26082#[cfg_attr(test, assert_instr(ld4))]
26083pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
26084 unsafe extern "unadjusted" {
26085 #[cfg_attr(
26086 any(target_arch = "aarch64", target_arch = "arm64ec"),
26087 link_name = "llvm.aarch64.neon.ld4.v8i16.p0"
26088 )]
26089 fn _vld4q_s16(ptr: *const int16x8_t) -> int16x8x4_t;
26090 }
26091 _vld4q_s16(a as _)
26092}
26093#[doc = "Load multiple 4-element structures to four registers"]
26094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
26095#[doc = "## Safety"]
26096#[doc = " * Neon instrinsic unsafe"]
26097#[inline]
26098#[target_feature(enable = "neon")]
26099#[cfg(not(target_arch = "arm"))]
26100#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26101#[cfg_attr(test, assert_instr(ld4))]
26102pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
26103 unsafe extern "unadjusted" {
26104 #[cfg_attr(
26105 any(target_arch = "aarch64", target_arch = "arm64ec"),
26106 link_name = "llvm.aarch64.neon.ld4.v2i32.p0"
26107 )]
26108 fn _vld4_s32(ptr: *const int32x2_t) -> int32x2x4_t;
26109 }
26110 _vld4_s32(a as _)
26111}
26112#[doc = "Load multiple 4-element structures to four registers"]
26113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
26114#[doc = "## Safety"]
26115#[doc = " * Neon instrinsic unsafe"]
26116#[inline]
26117#[target_feature(enable = "neon")]
26118#[cfg(not(target_arch = "arm"))]
26119#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26120#[cfg_attr(test, assert_instr(ld4))]
26121pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
26122 unsafe extern "unadjusted" {
26123 #[cfg_attr(
26124 any(target_arch = "aarch64", target_arch = "arm64ec"),
26125 link_name = "llvm.aarch64.neon.ld4.v4i32.p0"
26126 )]
26127 fn _vld4q_s32(ptr: *const int32x4_t) -> int32x4x4_t;
26128 }
26129 _vld4q_s32(a as _)
26130}
26131#[doc = "Load multiple 4-element structures to four registers"]
26132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
26133#[doc = "## Safety"]
26134#[doc = " * Neon instrinsic unsafe"]
26135#[inline]
26136#[target_feature(enable = "neon,v7")]
26137#[cfg(target_arch = "arm")]
26138#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26139#[cfg_attr(test, assert_instr(vld4))]
26140pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
26141 unsafe extern "unadjusted" {
26142 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2f32.p0")]
26143 fn _vld4_f32(ptr: *const i8, size: i32) -> float32x2x4_t;
26144 }
26145 _vld4_f32(a as *const i8, 4)
26146}
26147#[doc = "Load multiple 4-element structures to four registers"]
26148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
26149#[doc = "## Safety"]
26150#[doc = " * Neon instrinsic unsafe"]
26151#[inline]
26152#[target_feature(enable = "neon,v7")]
26153#[cfg(target_arch = "arm")]
26154#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26155#[cfg_attr(test, assert_instr(vld4))]
26156pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
26157 unsafe extern "unadjusted" {
26158 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f32.p0")]
26159 fn _vld4q_f32(ptr: *const i8, size: i32) -> float32x4x4_t;
26160 }
26161 _vld4q_f32(a as *const i8, 4)
26162}
26163#[doc = "Load multiple 4-element structures to four registers"]
26164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
26165#[doc = "## Safety"]
26166#[doc = " * Neon instrinsic unsafe"]
26167#[inline]
26168#[target_feature(enable = "neon,v7")]
26169#[cfg(target_arch = "arm")]
26170#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26171#[cfg_attr(test, assert_instr(vld4))]
26172pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
26173 unsafe extern "unadjusted" {
26174 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i8.p0")]
26175 fn _vld4_s8(ptr: *const i8, size: i32) -> int8x8x4_t;
26176 }
26177 _vld4_s8(a as *const i8, 1)
26178}
26179#[doc = "Load multiple 4-element structures to four registers"]
26180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
26181#[doc = "## Safety"]
26182#[doc = " * Neon instrinsic unsafe"]
26183#[inline]
26184#[target_feature(enable = "neon,v7")]
26185#[cfg(target_arch = "arm")]
26186#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26187#[cfg_attr(test, assert_instr(vld4))]
26188pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
26189 unsafe extern "unadjusted" {
26190 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v16i8.p0")]
26191 fn _vld4q_s8(ptr: *const i8, size: i32) -> int8x16x4_t;
26192 }
26193 _vld4q_s8(a as *const i8, 1)
26194}
26195#[doc = "Load multiple 4-element structures to four registers"]
26196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
26197#[doc = "## Safety"]
26198#[doc = " * Neon instrinsic unsafe"]
26199#[inline]
26200#[target_feature(enable = "neon,v7")]
26201#[cfg(target_arch = "arm")]
26202#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26203#[cfg_attr(test, assert_instr(vld4))]
26204pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
26205 unsafe extern "unadjusted" {
26206 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i16.p0")]
26207 fn _vld4_s16(ptr: *const i8, size: i32) -> int16x4x4_t;
26208 }
26209 _vld4_s16(a as *const i8, 2)
26210}
26211#[doc = "Load multiple 4-element structures to four registers"]
26212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
26213#[doc = "## Safety"]
26214#[doc = " * Neon instrinsic unsafe"]
26215#[inline]
26216#[target_feature(enable = "neon,v7")]
26217#[cfg(target_arch = "arm")]
26218#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26219#[cfg_attr(test, assert_instr(vld4))]
26220pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
26221 unsafe extern "unadjusted" {
26222 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i16.p0")]
26223 fn _vld4q_s16(ptr: *const i8, size: i32) -> int16x8x4_t;
26224 }
26225 _vld4q_s16(a as *const i8, 2)
26226}
26227#[doc = "Load multiple 4-element structures to four registers"]
26228#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
26229#[doc = "## Safety"]
26230#[doc = " * Neon instrinsic unsafe"]
26231#[inline]
26232#[target_feature(enable = "neon,v7")]
26233#[cfg(target_arch = "arm")]
26234#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26235#[cfg_attr(test, assert_instr(vld4))]
26236pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
26237 unsafe extern "unadjusted" {
26238 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2i32.p0")]
26239 fn _vld4_s32(ptr: *const i8, size: i32) -> int32x2x4_t;
26240 }
26241 _vld4_s32(a as *const i8, 4)
26242}
26243#[doc = "Load multiple 4-element structures to four registers"]
26244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
26245#[doc = "## Safety"]
26246#[doc = " * Neon instrinsic unsafe"]
26247#[inline]
26248#[target_feature(enable = "neon,v7")]
26249#[cfg(target_arch = "arm")]
26250#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26251#[cfg_attr(test, assert_instr(vld4))]
26252pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
26253 unsafe extern "unadjusted" {
26254 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i32.p0")]
26255 fn _vld4q_s32(ptr: *const i8, size: i32) -> int32x4x4_t;
26256 }
26257 _vld4q_s32(a as *const i8, 4)
26258}
26259#[doc = "Load multiple 4-element structures to two registers"]
26260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
26261#[doc = "## Safety"]
26262#[doc = " * Neon instrinsic unsafe"]
26263#[inline]
26264#[target_feature(enable = "neon,v7")]
26265#[cfg(target_arch = "arm")]
26266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26267#[rustc_legacy_const_generics(2)]
26268#[target_feature(enable = "neon,fp16")]
26269#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26270pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) -> float16x4x4_t {
26271 static_assert_uimm_bits!(LANE, 2);
26272 unsafe extern "unadjusted" {
26273 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f16.p0")]
26274 fn _vld4_lane_f16(
26275 ptr: *const f16,
26276 a: float16x4_t,
26277 b: float16x4_t,
26278 c: float16x4_t,
26279 d: float16x4_t,
26280 n: i32,
26281 size: i32,
26282 ) -> float16x4x4_t;
26283 }
26284 _vld4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26285}
26286#[doc = "Load multiple 4-element structures to two registers"]
26287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
26288#[doc = "## Safety"]
26289#[doc = " * Neon instrinsic unsafe"]
26290#[inline]
26291#[target_feature(enable = "neon,v7")]
26292#[cfg(target_arch = "arm")]
26293#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26294#[rustc_legacy_const_generics(2)]
26295#[target_feature(enable = "neon,fp16")]
26296#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26297pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -> float16x8x4_t {
26298 static_assert_uimm_bits!(LANE, 3);
26299 unsafe extern "unadjusted" {
26300 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8f16.p0")]
26301 fn _vld4q_lane_f16(
26302 ptr: *const f16,
26303 a: float16x8_t,
26304 b: float16x8_t,
26305 c: float16x8_t,
26306 d: float16x8_t,
26307 n: i32,
26308 size: i32,
26309 ) -> float16x8x4_t;
26310 }
26311 _vld4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26312}
26313#[doc = "Load multiple 4-element structures to two registers"]
26314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
26315#[doc = "## Safety"]
26316#[doc = " * Neon instrinsic unsafe"]
26317#[inline]
26318#[cfg(not(target_arch = "arm"))]
26319#[cfg_attr(
26320 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26321 assert_instr(ld4, LANE = 0)
26322)]
26323#[rustc_legacy_const_generics(2)]
26324#[target_feature(enable = "neon,fp16")]
26325#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26326pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) -> float16x4x4_t {
26327 static_assert_uimm_bits!(LANE, 2);
26328 unsafe extern "unadjusted" {
26329 #[cfg_attr(
26330 any(target_arch = "aarch64", target_arch = "arm64ec"),
26331 link_name = "llvm.aarch64.neon.ld4lane.v4f16.p0"
26332 )]
26333 fn _vld4_lane_f16(
26334 a: float16x4_t,
26335 b: float16x4_t,
26336 c: float16x4_t,
26337 d: float16x4_t,
26338 n: i64,
26339 ptr: *const f16,
26340 ) -> float16x4x4_t;
26341 }
26342 _vld4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26343}
26344#[doc = "Load multiple 4-element structures to two registers"]
26345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
26346#[doc = "## Safety"]
26347#[doc = " * Neon instrinsic unsafe"]
26348#[inline]
26349#[cfg(not(target_arch = "arm"))]
26350#[cfg_attr(
26351 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26352 assert_instr(ld4, LANE = 0)
26353)]
26354#[rustc_legacy_const_generics(2)]
26355#[target_feature(enable = "neon,fp16")]
26356#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26357pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -> float16x8x4_t {
26358 static_assert_uimm_bits!(LANE, 3);
26359 unsafe extern "unadjusted" {
26360 #[cfg_attr(
26361 any(target_arch = "aarch64", target_arch = "arm64ec"),
26362 link_name = "llvm.aarch64.neon.ld4lane.v8f16.p0"
26363 )]
26364 fn _vld4q_lane_f16(
26365 a: float16x8_t,
26366 b: float16x8_t,
26367 c: float16x8_t,
26368 d: float16x8_t,
26369 n: i64,
26370 ptr: *const f16,
26371 ) -> float16x8x4_t;
26372 }
26373 _vld4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26374}
26375#[doc = "Load multiple 4-element structures to four registers"]
26376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
26377#[doc = "## Safety"]
26378#[doc = " * Neon instrinsic unsafe"]
26379#[inline]
26380#[target_feature(enable = "neon")]
26381#[cfg(not(target_arch = "arm"))]
26382#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26383#[rustc_legacy_const_generics(2)]
26384#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26385pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) -> float32x2x4_t {
26386 static_assert_uimm_bits!(LANE, 1);
26387 unsafe extern "unadjusted" {
26388 #[cfg_attr(
26389 any(target_arch = "aarch64", target_arch = "arm64ec"),
26390 link_name = "llvm.aarch64.neon.ld4lane.v2f32.p0"
26391 )]
26392 fn _vld4_lane_f32(
26393 a: float32x2_t,
26394 b: float32x2_t,
26395 c: float32x2_t,
26396 d: float32x2_t,
26397 n: i64,
26398 ptr: *const i8,
26399 ) -> float32x2x4_t;
26400 }
26401 _vld4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26402}
26403#[doc = "Load multiple 4-element structures to four registers"]
26404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
26405#[doc = "## Safety"]
26406#[doc = " * Neon instrinsic unsafe"]
26407#[inline]
26408#[target_feature(enable = "neon")]
26409#[cfg(not(target_arch = "arm"))]
26410#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26411#[rustc_legacy_const_generics(2)]
26412#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26413pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -> float32x4x4_t {
26414 static_assert_uimm_bits!(LANE, 2);
26415 unsafe extern "unadjusted" {
26416 #[cfg_attr(
26417 any(target_arch = "aarch64", target_arch = "arm64ec"),
26418 link_name = "llvm.aarch64.neon.ld4lane.v4f32.p0"
26419 )]
26420 fn _vld4q_lane_f32(
26421 a: float32x4_t,
26422 b: float32x4_t,
26423 c: float32x4_t,
26424 d: float32x4_t,
26425 n: i64,
26426 ptr: *const i8,
26427 ) -> float32x4x4_t;
26428 }
26429 _vld4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26430}
26431#[doc = "Load multiple 4-element structures to four registers"]
26432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
26433#[doc = "## Safety"]
26434#[doc = " * Neon instrinsic unsafe"]
26435#[inline]
26436#[target_feature(enable = "neon")]
26437#[cfg(not(target_arch = "arm"))]
26438#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26439#[rustc_legacy_const_generics(2)]
26440#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26441pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8x8x4_t {
26442 static_assert_uimm_bits!(LANE, 3);
26443 unsafe extern "unadjusted" {
26444 #[cfg_attr(
26445 any(target_arch = "aarch64", target_arch = "arm64ec"),
26446 link_name = "llvm.aarch64.neon.ld4lane.v8i8.p0"
26447 )]
26448 fn _vld4_lane_s8(
26449 a: int8x8_t,
26450 b: int8x8_t,
26451 c: int8x8_t,
26452 d: int8x8_t,
26453 n: i64,
26454 ptr: *const i8,
26455 ) -> int8x8x4_t;
26456 }
26457 _vld4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26458}
26459#[doc = "Load multiple 4-element structures to four registers"]
26460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
26461#[doc = "## Safety"]
26462#[doc = " * Neon instrinsic unsafe"]
26463#[inline]
26464#[target_feature(enable = "neon")]
26465#[cfg(not(target_arch = "arm"))]
26466#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26467#[rustc_legacy_const_generics(2)]
26468#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26469pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> int16x4x4_t {
26470 static_assert_uimm_bits!(LANE, 2);
26471 unsafe extern "unadjusted" {
26472 #[cfg_attr(
26473 any(target_arch = "aarch64", target_arch = "arm64ec"),
26474 link_name = "llvm.aarch64.neon.ld4lane.v4i16.p0"
26475 )]
26476 fn _vld4_lane_s16(
26477 a: int16x4_t,
26478 b: int16x4_t,
26479 c: int16x4_t,
26480 d: int16x4_t,
26481 n: i64,
26482 ptr: *const i8,
26483 ) -> int16x4x4_t;
26484 }
26485 _vld4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26486}
26487#[doc = "Load multiple 4-element structures to four registers"]
26488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
26489#[doc = "## Safety"]
26490#[doc = " * Neon instrinsic unsafe"]
26491#[inline]
26492#[target_feature(enable = "neon")]
26493#[cfg(not(target_arch = "arm"))]
26494#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26495#[rustc_legacy_const_generics(2)]
26496#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26497pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) -> int16x8x4_t {
26498 static_assert_uimm_bits!(LANE, 3);
26499 unsafe extern "unadjusted" {
26500 #[cfg_attr(
26501 any(target_arch = "aarch64", target_arch = "arm64ec"),
26502 link_name = "llvm.aarch64.neon.ld4lane.v8i16.p0"
26503 )]
26504 fn _vld4q_lane_s16(
26505 a: int16x8_t,
26506 b: int16x8_t,
26507 c: int16x8_t,
26508 d: int16x8_t,
26509 n: i64,
26510 ptr: *const i8,
26511 ) -> int16x8x4_t;
26512 }
26513 _vld4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26514}
26515#[doc = "Load multiple 4-element structures to four registers"]
26516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
26517#[doc = "## Safety"]
26518#[doc = " * Neon instrinsic unsafe"]
26519#[inline]
26520#[target_feature(enable = "neon")]
26521#[cfg(not(target_arch = "arm"))]
26522#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26523#[rustc_legacy_const_generics(2)]
26524#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26525pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> int32x2x4_t {
26526 static_assert_uimm_bits!(LANE, 1);
26527 unsafe extern "unadjusted" {
26528 #[cfg_attr(
26529 any(target_arch = "aarch64", target_arch = "arm64ec"),
26530 link_name = "llvm.aarch64.neon.ld4lane.v2i32.p0"
26531 )]
26532 fn _vld4_lane_s32(
26533 a: int32x2_t,
26534 b: int32x2_t,
26535 c: int32x2_t,
26536 d: int32x2_t,
26537 n: i64,
26538 ptr: *const i8,
26539 ) -> int32x2x4_t;
26540 }
26541 _vld4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26542}
26543#[doc = "Load multiple 4-element structures to four registers"]
26544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
26545#[doc = "## Safety"]
26546#[doc = " * Neon instrinsic unsafe"]
26547#[inline]
26548#[target_feature(enable = "neon")]
26549#[cfg(not(target_arch = "arm"))]
26550#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26551#[rustc_legacy_const_generics(2)]
26552#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26553pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) -> int32x4x4_t {
26554 static_assert_uimm_bits!(LANE, 2);
26555 unsafe extern "unadjusted" {
26556 #[cfg_attr(
26557 any(target_arch = "aarch64", target_arch = "arm64ec"),
26558 link_name = "llvm.aarch64.neon.ld4lane.v4i32.p0"
26559 )]
26560 fn _vld4q_lane_s32(
26561 a: int32x4_t,
26562 b: int32x4_t,
26563 c: int32x4_t,
26564 d: int32x4_t,
26565 n: i64,
26566 ptr: *const i8,
26567 ) -> int32x4x4_t;
26568 }
26569 _vld4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26570}
26571#[doc = "Load multiple 4-element structures to four registers"]
26572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
26573#[doc = "## Safety"]
26574#[doc = " * Neon instrinsic unsafe"]
26575#[inline]
26576#[target_feature(enable = "neon,v7")]
26577#[cfg(target_arch = "arm")]
26578#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26579#[rustc_legacy_const_generics(2)]
26580#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26581pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) -> float32x2x4_t {
26582 static_assert_uimm_bits!(LANE, 1);
26583 unsafe extern "unadjusted" {
26584 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2f32.p0")]
26585 fn _vld4_lane_f32(
26586 ptr: *const i8,
26587 a: float32x2_t,
26588 b: float32x2_t,
26589 c: float32x2_t,
26590 d: float32x2_t,
26591 n: i32,
26592 size: i32,
26593 ) -> float32x2x4_t;
26594 }
26595 _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26596}
26597#[doc = "Load multiple 4-element structures to four registers"]
26598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
26599#[doc = "## Safety"]
26600#[doc = " * Neon instrinsic unsafe"]
26601#[inline]
26602#[target_feature(enable = "neon,v7")]
26603#[cfg(target_arch = "arm")]
26604#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26605#[rustc_legacy_const_generics(2)]
26606#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26607pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -> float32x4x4_t {
26608 static_assert_uimm_bits!(LANE, 2);
26609 unsafe extern "unadjusted" {
26610 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f32.p0")]
26611 fn _vld4q_lane_f32(
26612 ptr: *const i8,
26613 a: float32x4_t,
26614 b: float32x4_t,
26615 c: float32x4_t,
26616 d: float32x4_t,
26617 n: i32,
26618 size: i32,
26619 ) -> float32x4x4_t;
26620 }
26621 _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26622}
26623#[doc = "Load multiple 4-element structures to four registers"]
26624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
26625#[doc = "## Safety"]
26626#[doc = " * Neon instrinsic unsafe"]
26627#[inline]
26628#[target_feature(enable = "neon,v7")]
26629#[cfg(target_arch = "arm")]
26630#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26631#[rustc_legacy_const_generics(2)]
26632#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26633pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8x8x4_t {
26634 static_assert_uimm_bits!(LANE, 3);
26635 unsafe extern "unadjusted" {
26636 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i8.p0")]
26637 fn _vld4_lane_s8(
26638 ptr: *const i8,
26639 a: int8x8_t,
26640 b: int8x8_t,
26641 c: int8x8_t,
26642 d: int8x8_t,
26643 n: i32,
26644 size: i32,
26645 ) -> int8x8x4_t;
26646 }
26647 _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
26648}
26649#[doc = "Load multiple 4-element structures to four registers"]
26650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
26651#[doc = "## Safety"]
26652#[doc = " * Neon instrinsic unsafe"]
26653#[inline]
26654#[target_feature(enable = "neon,v7")]
26655#[cfg(target_arch = "arm")]
26656#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26657#[rustc_legacy_const_generics(2)]
26658#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26659pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> int16x4x4_t {
26660 static_assert_uimm_bits!(LANE, 2);
26661 unsafe extern "unadjusted" {
26662 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i16.p0")]
26663 fn _vld4_lane_s16(
26664 ptr: *const i8,
26665 a: int16x4_t,
26666 b: int16x4_t,
26667 c: int16x4_t,
26668 d: int16x4_t,
26669 n: i32,
26670 size: i32,
26671 ) -> int16x4x4_t;
26672 }
26673 _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26674}
26675#[doc = "Load multiple 4-element structures to four registers"]
26676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
26677#[doc = "## Safety"]
26678#[doc = " * Neon instrinsic unsafe"]
26679#[inline]
26680#[target_feature(enable = "neon,v7")]
26681#[cfg(target_arch = "arm")]
26682#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26683#[rustc_legacy_const_generics(2)]
26684#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26685pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) -> int16x8x4_t {
26686 static_assert_uimm_bits!(LANE, 3);
26687 unsafe extern "unadjusted" {
26688 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i16.p0")]
26689 fn _vld4q_lane_s16(
26690 ptr: *const i8,
26691 a: int16x8_t,
26692 b: int16x8_t,
26693 c: int16x8_t,
26694 d: int16x8_t,
26695 n: i32,
26696 size: i32,
26697 ) -> int16x8x4_t;
26698 }
26699 _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26700}
26701#[doc = "Load multiple 4-element structures to four registers"]
26702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
26703#[doc = "## Safety"]
26704#[doc = " * Neon instrinsic unsafe"]
26705#[inline]
26706#[target_feature(enable = "neon,v7")]
26707#[cfg(target_arch = "arm")]
26708#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26709#[rustc_legacy_const_generics(2)]
26710#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26711pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> int32x2x4_t {
26712 static_assert_uimm_bits!(LANE, 1);
26713 unsafe extern "unadjusted" {
26714 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2i32.p0")]
26715 fn _vld4_lane_s32(
26716 ptr: *const i8,
26717 a: int32x2_t,
26718 b: int32x2_t,
26719 c: int32x2_t,
26720 d: int32x2_t,
26721 n: i32,
26722 size: i32,
26723 ) -> int32x2x4_t;
26724 }
26725 _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26726}
26727#[doc = "Load multiple 4-element structures to four registers"]
26728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
26729#[doc = "## Safety"]
26730#[doc = " * Neon instrinsic unsafe"]
26731#[inline]
26732#[target_feature(enable = "neon,v7")]
26733#[cfg(target_arch = "arm")]
26734#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26735#[rustc_legacy_const_generics(2)]
26736#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26737pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) -> int32x4x4_t {
26738 static_assert_uimm_bits!(LANE, 2);
26739 unsafe extern "unadjusted" {
26740 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i32.p0")]
26741 fn _vld4q_lane_s32(
26742 ptr: *const i8,
26743 a: int32x4_t,
26744 b: int32x4_t,
26745 c: int32x4_t,
26746 d: int32x4_t,
26747 n: i32,
26748 size: i32,
26749 ) -> int32x4x4_t;
26750 }
26751 _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26752}
26753#[doc = "Load multiple 4-element structures to four registers"]
26754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"]
26755#[doc = "## Safety"]
26756#[doc = " * Neon instrinsic unsafe"]
26757#[inline]
26758#[target_feature(enable = "neon")]
26759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26761#[cfg_attr(
26762 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26763 assert_instr(ld4, LANE = 0)
26764)]
26765#[rustc_legacy_const_generics(2)]
26766#[cfg_attr(
26767 not(target_arch = "arm"),
26768 stable(feature = "neon_intrinsics", since = "1.59.0")
26769)]
26770#[cfg_attr(
26771 target_arch = "arm",
26772 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26773)]
26774pub unsafe fn vld4_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t {
26775 static_assert_uimm_bits!(LANE, 3);
26776 transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
26777}
26778#[doc = "Load multiple 4-element structures to four registers"]
26779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"]
26780#[doc = "## Safety"]
26781#[doc = " * Neon instrinsic unsafe"]
26782#[inline]
26783#[target_feature(enable = "neon")]
26784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26785#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26786#[cfg_attr(
26787 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26788 assert_instr(ld4, LANE = 0)
26789)]
26790#[rustc_legacy_const_generics(2)]
26791#[cfg_attr(
26792 not(target_arch = "arm"),
26793 stable(feature = "neon_intrinsics", since = "1.59.0")
26794)]
26795#[cfg_attr(
26796 target_arch = "arm",
26797 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26798)]
26799pub unsafe fn vld4_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t {
26800 static_assert_uimm_bits!(LANE, 2);
26801 transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
26802}
26803#[doc = "Load multiple 4-element structures to four registers"]
26804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"]
26805#[doc = "## Safety"]
26806#[doc = " * Neon instrinsic unsafe"]
26807#[inline]
26808#[target_feature(enable = "neon")]
26809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26811#[cfg_attr(
26812 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26813 assert_instr(ld4, LANE = 0)
26814)]
26815#[rustc_legacy_const_generics(2)]
26816#[cfg_attr(
26817 not(target_arch = "arm"),
26818 stable(feature = "neon_intrinsics", since = "1.59.0")
26819)]
26820#[cfg_attr(
26821 target_arch = "arm",
26822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26823)]
26824pub unsafe fn vld4q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t {
26825 static_assert_uimm_bits!(LANE, 3);
26826 transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
26827}
26828#[doc = "Load multiple 4-element structures to four registers"]
26829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
26830#[doc = "## Safety"]
26831#[doc = " * Neon instrinsic unsafe"]
26832#[inline]
26833#[target_feature(enable = "neon")]
26834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26835#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26836#[cfg_attr(
26837 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26838 assert_instr(ld4, LANE = 0)
26839)]
26840#[rustc_legacy_const_generics(2)]
26841#[cfg_attr(
26842 not(target_arch = "arm"),
26843 stable(feature = "neon_intrinsics", since = "1.59.0")
26844)]
26845#[cfg_attr(
26846 target_arch = "arm",
26847 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26848)]
26849pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t {
26850 static_assert_uimm_bits!(LANE, 1);
26851 transmute(vld4_lane_s32::<LANE>(transmute(a), transmute(b)))
26852}
26853#[doc = "Load multiple 4-element structures to four registers"]
26854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
26855#[doc = "## Safety"]
26856#[doc = " * Neon instrinsic unsafe"]
26857#[inline]
26858#[target_feature(enable = "neon")]
26859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26860#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26861#[cfg_attr(
26862 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26863 assert_instr(ld4, LANE = 0)
26864)]
26865#[rustc_legacy_const_generics(2)]
26866#[cfg_attr(
26867 not(target_arch = "arm"),
26868 stable(feature = "neon_intrinsics", since = "1.59.0")
26869)]
26870#[cfg_attr(
26871 target_arch = "arm",
26872 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26873)]
26874pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t {
26875 static_assert_uimm_bits!(LANE, 2);
26876 transmute(vld4q_lane_s32::<LANE>(transmute(a), transmute(b)))
26877}
26878#[doc = "Load multiple 4-element structures to four registers"]
26879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
26880#[doc = "## Safety"]
26881#[doc = " * Neon instrinsic unsafe"]
26882#[inline]
26883#[target_feature(enable = "neon")]
26884#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26885#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26886#[cfg_attr(
26887 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26888 assert_instr(ld4, LANE = 0)
26889)]
26890#[rustc_legacy_const_generics(2)]
26891#[cfg_attr(
26892 not(target_arch = "arm"),
26893 stable(feature = "neon_intrinsics", since = "1.59.0")
26894)]
26895#[cfg_attr(
26896 target_arch = "arm",
26897 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26898)]
26899pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t {
26900 static_assert_uimm_bits!(LANE, 3);
26901 transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
26902}
26903#[doc = "Load multiple 4-element structures to four registers"]
26904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
26905#[doc = "## Safety"]
26906#[doc = " * Neon instrinsic unsafe"]
26907#[inline]
26908#[target_feature(enable = "neon")]
26909#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26910#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26911#[cfg_attr(
26912 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26913 assert_instr(ld4, LANE = 0)
26914)]
26915#[rustc_legacy_const_generics(2)]
26916#[cfg_attr(
26917 not(target_arch = "arm"),
26918 stable(feature = "neon_intrinsics", since = "1.59.0")
26919)]
26920#[cfg_attr(
26921 target_arch = "arm",
26922 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26923)]
26924pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t {
26925 static_assert_uimm_bits!(LANE, 2);
26926 transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
26927}
26928#[doc = "Load multiple 4-element structures to four registers"]
26929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
26930#[doc = "## Safety"]
26931#[doc = " * Neon instrinsic unsafe"]
26932#[inline]
26933#[target_feature(enable = "neon")]
26934#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26935#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26936#[cfg_attr(
26937 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26938 assert_instr(ld4, LANE = 0)
26939)]
26940#[rustc_legacy_const_generics(2)]
26941#[cfg_attr(
26942 not(target_arch = "arm"),
26943 stable(feature = "neon_intrinsics", since = "1.59.0")
26944)]
26945#[cfg_attr(
26946 target_arch = "arm",
26947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26948)]
26949pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t {
26950 static_assert_uimm_bits!(LANE, 3);
26951 transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
26952}
26953#[doc = "Load multiple 4-element structures to four registers"]
26954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
26955#[doc = "## Safety"]
26956#[doc = " * Neon instrinsic unsafe"]
26957#[inline]
26958#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
26959#[target_feature(enable = "neon,aes")]
26960#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
26961#[cfg_attr(
26962 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26963 assert_instr(nop)
26964)]
26965#[cfg_attr(
26966 not(target_arch = "arm"),
26967 stable(feature = "neon_intrinsics", since = "1.59.0")
26968)]
26969#[cfg_attr(
26970 target_arch = "arm",
26971 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26972)]
26973pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
26974 transmute(vld4_s64(transmute(a)))
26975}
26976#[doc = "Load multiple 4-element structures to four registers"]
26977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
26978#[doc = "## Safety"]
26979#[doc = " * Neon instrinsic unsafe"]
26980#[inline]
26981#[target_feature(enable = "neon")]
26982#[cfg(not(target_arch = "arm"))]
26983#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26984#[cfg_attr(test, assert_instr(nop))]
26985pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
26986 unsafe extern "unadjusted" {
26987 #[cfg_attr(
26988 any(target_arch = "aarch64", target_arch = "arm64ec"),
26989 link_name = "llvm.aarch64.neon.ld4.v1i64.p0"
26990 )]
26991 fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t;
26992 }
26993 _vld4_s64(a as _)
26994}
26995#[doc = "Load multiple 4-element structures to four registers"]
26996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
26997#[doc = "## Safety"]
26998#[doc = " * Neon instrinsic unsafe"]
26999#[inline]
27000#[target_feature(enable = "neon,v7")]
27001#[cfg(target_arch = "arm")]
27002#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
27003#[cfg_attr(test, assert_instr(nop))]
27004pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
27005 unsafe extern "unadjusted" {
27006 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")]
27007 fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
27008 }
27009 _vld4_s64(a as *const i8, 8)
27010}
27011#[doc = "Load multiple 4-element structures to four registers"]
27012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
27013#[doc = "## Safety"]
27014#[doc = " * Neon instrinsic unsafe"]
27015#[inline]
27016#[target_feature(enable = "neon")]
27017#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27018#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
27019#[cfg_attr(
27020 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27021 assert_instr(nop)
27022)]
27023#[cfg_attr(
27024 not(target_arch = "arm"),
27025 stable(feature = "neon_intrinsics", since = "1.59.0")
27026)]
27027#[cfg_attr(
27028 target_arch = "arm",
27029 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27030)]
27031pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
27032 transmute(vld4_s64(transmute(a)))
27033}
27034#[doc = "Load multiple 4-element structures to four registers"]
27035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
27036#[doc = "## Safety"]
27037#[doc = " * Neon instrinsic unsafe"]
27038#[inline]
27039#[cfg(target_endian = "little")]
27040#[target_feature(enable = "neon")]
27041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27043#[cfg_attr(
27044 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27045 assert_instr(ld4)
27046)]
27047#[cfg_attr(
27048 not(target_arch = "arm"),
27049 stable(feature = "neon_intrinsics", since = "1.59.0")
27050)]
27051#[cfg_attr(
27052 target_arch = "arm",
27053 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27054)]
27055pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
27056 transmute(vld4_s8(transmute(a)))
27057}
27058#[doc = "Load multiple 4-element structures to four registers"]
27059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
27060#[doc = "## Safety"]
27061#[doc = " * Neon instrinsic unsafe"]
27062#[inline]
27063#[cfg(target_endian = "big")]
27064#[target_feature(enable = "neon")]
27065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27067#[cfg_attr(
27068 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27069 assert_instr(ld4)
27070)]
27071#[cfg_attr(
27072 not(target_arch = "arm"),
27073 stable(feature = "neon_intrinsics", since = "1.59.0")
27074)]
27075#[cfg_attr(
27076 target_arch = "arm",
27077 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27078)]
27079pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
27080 let mut ret_val: uint8x8x4_t = transmute(vld4_s8(transmute(a)));
27081 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27082 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27083 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27084 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27085 ret_val
27086}
27087#[doc = "Load multiple 4-element structures to four registers"]
27088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
27089#[doc = "## Safety"]
27090#[doc = " * Neon instrinsic unsafe"]
27091#[inline]
27092#[cfg(target_endian = "little")]
27093#[target_feature(enable = "neon")]
27094#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27095#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27096#[cfg_attr(
27097 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27098 assert_instr(ld4)
27099)]
27100#[cfg_attr(
27101 not(target_arch = "arm"),
27102 stable(feature = "neon_intrinsics", since = "1.59.0")
27103)]
27104#[cfg_attr(
27105 target_arch = "arm",
27106 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27107)]
27108pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
27109 transmute(vld4q_s8(transmute(a)))
27110}
27111#[doc = "Load multiple 4-element structures to four registers"]
27112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
27113#[doc = "## Safety"]
27114#[doc = " * Neon instrinsic unsafe"]
27115#[inline]
27116#[cfg(target_endian = "big")]
27117#[target_feature(enable = "neon")]
27118#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27119#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27120#[cfg_attr(
27121 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27122 assert_instr(ld4)
27123)]
27124#[cfg_attr(
27125 not(target_arch = "arm"),
27126 stable(feature = "neon_intrinsics", since = "1.59.0")
27127)]
27128#[cfg_attr(
27129 target_arch = "arm",
27130 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27131)]
27132pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
27133 let mut ret_val: uint8x16x4_t = transmute(vld4q_s8(transmute(a)));
27134 ret_val.0 = unsafe {
27135 simd_shuffle!(
27136 ret_val.0,
27137 ret_val.0,
27138 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27139 )
27140 };
27141 ret_val.1 = unsafe {
27142 simd_shuffle!(
27143 ret_val.1,
27144 ret_val.1,
27145 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27146 )
27147 };
27148 ret_val.2 = unsafe {
27149 simd_shuffle!(
27150 ret_val.2,
27151 ret_val.2,
27152 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27153 )
27154 };
27155 ret_val.3 = unsafe {
27156 simd_shuffle!(
27157 ret_val.3,
27158 ret_val.3,
27159 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27160 )
27161 };
27162 ret_val
27163}
27164#[doc = "Load multiple 4-element structures to four registers"]
27165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
27166#[doc = "## Safety"]
27167#[doc = " * Neon instrinsic unsafe"]
27168#[inline]
27169#[cfg(target_endian = "little")]
27170#[target_feature(enable = "neon")]
27171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27172#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27173#[cfg_attr(
27174 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27175 assert_instr(ld4)
27176)]
27177#[cfg_attr(
27178 not(target_arch = "arm"),
27179 stable(feature = "neon_intrinsics", since = "1.59.0")
27180)]
27181#[cfg_attr(
27182 target_arch = "arm",
27183 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27184)]
27185pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
27186 transmute(vld4_s16(transmute(a)))
27187}
27188#[doc = "Load multiple 4-element structures to four registers"]
27189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
27190#[doc = "## Safety"]
27191#[doc = " * Neon instrinsic unsafe"]
27192#[inline]
27193#[cfg(target_endian = "big")]
27194#[target_feature(enable = "neon")]
27195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27196#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27197#[cfg_attr(
27198 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27199 assert_instr(ld4)
27200)]
27201#[cfg_attr(
27202 not(target_arch = "arm"),
27203 stable(feature = "neon_intrinsics", since = "1.59.0")
27204)]
27205#[cfg_attr(
27206 target_arch = "arm",
27207 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27208)]
27209pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
27210 let mut ret_val: uint16x4x4_t = transmute(vld4_s16(transmute(a)));
27211 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27212 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27213 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27214 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27215 ret_val
27216}
27217#[doc = "Load multiple 4-element structures to four registers"]
27218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
27219#[doc = "## Safety"]
27220#[doc = " * Neon instrinsic unsafe"]
27221#[inline]
27222#[cfg(target_endian = "little")]
27223#[target_feature(enable = "neon")]
27224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27225#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27226#[cfg_attr(
27227 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27228 assert_instr(ld4)
27229)]
27230#[cfg_attr(
27231 not(target_arch = "arm"),
27232 stable(feature = "neon_intrinsics", since = "1.59.0")
27233)]
27234#[cfg_attr(
27235 target_arch = "arm",
27236 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27237)]
27238pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
27239 transmute(vld4q_s16(transmute(a)))
27240}
27241#[doc = "Load multiple 4-element structures to four registers"]
27242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
27243#[doc = "## Safety"]
27244#[doc = " * Neon instrinsic unsafe"]
27245#[inline]
27246#[cfg(target_endian = "big")]
27247#[target_feature(enable = "neon")]
27248#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27249#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27250#[cfg_attr(
27251 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27252 assert_instr(ld4)
27253)]
27254#[cfg_attr(
27255 not(target_arch = "arm"),
27256 stable(feature = "neon_intrinsics", since = "1.59.0")
27257)]
27258#[cfg_attr(
27259 target_arch = "arm",
27260 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27261)]
27262pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
27263 let mut ret_val: uint16x8x4_t = transmute(vld4q_s16(transmute(a)));
27264 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27265 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27266 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27267 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27268 ret_val
27269}
27270#[doc = "Load multiple 4-element structures to four registers"]
27271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
27272#[doc = "## Safety"]
27273#[doc = " * Neon instrinsic unsafe"]
27274#[inline]
27275#[cfg(target_endian = "little")]
27276#[target_feature(enable = "neon")]
27277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27278#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27279#[cfg_attr(
27280 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27281 assert_instr(ld4)
27282)]
27283#[cfg_attr(
27284 not(target_arch = "arm"),
27285 stable(feature = "neon_intrinsics", since = "1.59.0")
27286)]
27287#[cfg_attr(
27288 target_arch = "arm",
27289 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27290)]
27291pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
27292 transmute(vld4_s32(transmute(a)))
27293}
27294#[doc = "Load multiple 4-element structures to four registers"]
27295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
27296#[doc = "## Safety"]
27297#[doc = " * Neon instrinsic unsafe"]
27298#[inline]
27299#[cfg(target_endian = "big")]
27300#[target_feature(enable = "neon")]
27301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27302#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27303#[cfg_attr(
27304 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27305 assert_instr(ld4)
27306)]
27307#[cfg_attr(
27308 not(target_arch = "arm"),
27309 stable(feature = "neon_intrinsics", since = "1.59.0")
27310)]
27311#[cfg_attr(
27312 target_arch = "arm",
27313 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27314)]
27315pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
27316 let mut ret_val: uint32x2x4_t = transmute(vld4_s32(transmute(a)));
27317 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
27318 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
27319 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
27320 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
27321 ret_val
27322}
27323#[doc = "Load multiple 4-element structures to four registers"]
27324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
27325#[doc = "## Safety"]
27326#[doc = " * Neon instrinsic unsafe"]
27327#[inline]
27328#[cfg(target_endian = "little")]
27329#[target_feature(enable = "neon")]
27330#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27331#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27332#[cfg_attr(
27333 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27334 assert_instr(ld4)
27335)]
27336#[cfg_attr(
27337 not(target_arch = "arm"),
27338 stable(feature = "neon_intrinsics", since = "1.59.0")
27339)]
27340#[cfg_attr(
27341 target_arch = "arm",
27342 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27343)]
27344pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
27345 transmute(vld4q_s32(transmute(a)))
27346}
27347#[doc = "Load multiple 4-element structures to four registers"]
27348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
27349#[doc = "## Safety"]
27350#[doc = " * Neon instrinsic unsafe"]
27351#[inline]
27352#[cfg(target_endian = "big")]
27353#[target_feature(enable = "neon")]
27354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27355#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27356#[cfg_attr(
27357 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27358 assert_instr(ld4)
27359)]
27360#[cfg_attr(
27361 not(target_arch = "arm"),
27362 stable(feature = "neon_intrinsics", since = "1.59.0")
27363)]
27364#[cfg_attr(
27365 target_arch = "arm",
27366 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27367)]
27368pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
27369 let mut ret_val: uint32x4x4_t = transmute(vld4q_s32(transmute(a)));
27370 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27371 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27372 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27373 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27374 ret_val
27375}
27376#[doc = "Load multiple 4-element structures to four registers"]
27377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
27378#[doc = "## Safety"]
27379#[doc = " * Neon instrinsic unsafe"]
27380#[inline]
27381#[cfg(target_endian = "little")]
27382#[target_feature(enable = "neon")]
27383#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27384#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27385#[cfg_attr(
27386 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27387 assert_instr(ld4)
27388)]
27389#[cfg_attr(
27390 not(target_arch = "arm"),
27391 stable(feature = "neon_intrinsics", since = "1.59.0")
27392)]
27393#[cfg_attr(
27394 target_arch = "arm",
27395 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27396)]
27397pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
27398 transmute(vld4_s8(transmute(a)))
27399}
27400#[doc = "Load multiple 4-element structures to four registers"]
27401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
27402#[doc = "## Safety"]
27403#[doc = " * Neon instrinsic unsafe"]
27404#[inline]
27405#[cfg(target_endian = "big")]
27406#[target_feature(enable = "neon")]
27407#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27408#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27409#[cfg_attr(
27410 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27411 assert_instr(ld4)
27412)]
27413#[cfg_attr(
27414 not(target_arch = "arm"),
27415 stable(feature = "neon_intrinsics", since = "1.59.0")
27416)]
27417#[cfg_attr(
27418 target_arch = "arm",
27419 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27420)]
27421pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
27422 let mut ret_val: poly8x8x4_t = transmute(vld4_s8(transmute(a)));
27423 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27424 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27425 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27426 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27427 ret_val
27428}
27429#[doc = "Load multiple 4-element structures to four registers"]
27430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
27431#[doc = "## Safety"]
27432#[doc = " * Neon instrinsic unsafe"]
27433#[inline]
27434#[cfg(target_endian = "little")]
27435#[target_feature(enable = "neon")]
27436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27437#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27438#[cfg_attr(
27439 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27440 assert_instr(ld4)
27441)]
27442#[cfg_attr(
27443 not(target_arch = "arm"),
27444 stable(feature = "neon_intrinsics", since = "1.59.0")
27445)]
27446#[cfg_attr(
27447 target_arch = "arm",
27448 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27449)]
27450pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
27451 transmute(vld4q_s8(transmute(a)))
27452}
27453#[doc = "Load multiple 4-element structures to four registers"]
27454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
27455#[doc = "## Safety"]
27456#[doc = " * Neon instrinsic unsafe"]
27457#[inline]
27458#[cfg(target_endian = "big")]
27459#[target_feature(enable = "neon")]
27460#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27461#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27462#[cfg_attr(
27463 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27464 assert_instr(ld4)
27465)]
27466#[cfg_attr(
27467 not(target_arch = "arm"),
27468 stable(feature = "neon_intrinsics", since = "1.59.0")
27469)]
27470#[cfg_attr(
27471 target_arch = "arm",
27472 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27473)]
27474pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
27475 let mut ret_val: poly8x16x4_t = transmute(vld4q_s8(transmute(a)));
27476 ret_val.0 = unsafe {
27477 simd_shuffle!(
27478 ret_val.0,
27479 ret_val.0,
27480 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27481 )
27482 };
27483 ret_val.1 = unsafe {
27484 simd_shuffle!(
27485 ret_val.1,
27486 ret_val.1,
27487 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27488 )
27489 };
27490 ret_val.2 = unsafe {
27491 simd_shuffle!(
27492 ret_val.2,
27493 ret_val.2,
27494 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27495 )
27496 };
27497 ret_val.3 = unsafe {
27498 simd_shuffle!(
27499 ret_val.3,
27500 ret_val.3,
27501 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27502 )
27503 };
27504 ret_val
27505}
27506#[doc = "Load multiple 4-element structures to four registers"]
27507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
27508#[doc = "## Safety"]
27509#[doc = " * Neon instrinsic unsafe"]
27510#[inline]
27511#[cfg(target_endian = "little")]
27512#[target_feature(enable = "neon")]
27513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27515#[cfg_attr(
27516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27517 assert_instr(ld4)
27518)]
27519#[cfg_attr(
27520 not(target_arch = "arm"),
27521 stable(feature = "neon_intrinsics", since = "1.59.0")
27522)]
27523#[cfg_attr(
27524 target_arch = "arm",
27525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27526)]
27527pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
27528 transmute(vld4_s16(transmute(a)))
27529}
27530#[doc = "Load multiple 4-element structures to four registers"]
27531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
27532#[doc = "## Safety"]
27533#[doc = " * Neon instrinsic unsafe"]
27534#[inline]
27535#[cfg(target_endian = "big")]
27536#[target_feature(enable = "neon")]
27537#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27538#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27539#[cfg_attr(
27540 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27541 assert_instr(ld4)
27542)]
27543#[cfg_attr(
27544 not(target_arch = "arm"),
27545 stable(feature = "neon_intrinsics", since = "1.59.0")
27546)]
27547#[cfg_attr(
27548 target_arch = "arm",
27549 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27550)]
27551pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
27552 let mut ret_val: poly16x4x4_t = transmute(vld4_s16(transmute(a)));
27553 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27554 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27555 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27556 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27557 ret_val
27558}
27559#[doc = "Load multiple 4-element structures to four registers"]
27560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
27561#[doc = "## Safety"]
27562#[doc = " * Neon instrinsic unsafe"]
27563#[inline]
27564#[cfg(target_endian = "little")]
27565#[target_feature(enable = "neon")]
27566#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27567#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27568#[cfg_attr(
27569 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27570 assert_instr(ld4)
27571)]
27572#[cfg_attr(
27573 not(target_arch = "arm"),
27574 stable(feature = "neon_intrinsics", since = "1.59.0")
27575)]
27576#[cfg_attr(
27577 target_arch = "arm",
27578 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27579)]
27580pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
27581 transmute(vld4q_s16(transmute(a)))
27582}
27583#[doc = "Load multiple 4-element structures to four registers"]
27584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
27585#[doc = "## Safety"]
27586#[doc = " * Neon instrinsic unsafe"]
27587#[inline]
27588#[cfg(target_endian = "big")]
27589#[target_feature(enable = "neon")]
27590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27591#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27592#[cfg_attr(
27593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27594 assert_instr(ld4)
27595)]
27596#[cfg_attr(
27597 not(target_arch = "arm"),
27598 stable(feature = "neon_intrinsics", since = "1.59.0")
27599)]
27600#[cfg_attr(
27601 target_arch = "arm",
27602 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27603)]
27604pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
27605 let mut ret_val: poly16x8x4_t = transmute(vld4q_s16(transmute(a)));
27606 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27607 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27608 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27609 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27610 ret_val
27611}
27612#[doc = "Store SIMD&FP register (immediate offset)"]
27613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"]
27614#[doc = "## Safety"]
27615#[doc = " * Neon instrinsic unsafe"]
27616#[inline]
27617#[target_feature(enable = "neon")]
27618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27619#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
27620#[cfg_attr(
27621 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27622 assert_instr(nop)
27623)]
27624#[cfg_attr(
27625 not(target_arch = "arm"),
27626 stable(feature = "neon_intrinsics", since = "1.59.0")
27627)]
27628#[cfg_attr(
27629 target_arch = "arm",
27630 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27631)]
27632pub unsafe fn vldrq_p128(a: *const p128) -> p128 {
27633 *a
27634}
27635#[doc = "Maximum (vector)"]
27636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"]
27637#[inline]
27638#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
27639#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27640#[cfg_attr(
27641 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27642 assert_instr(fmax)
27643)]
27644#[target_feature(enable = "neon,fp16")]
27645#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27646pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
27647 unsafe extern "unadjusted" {
27648 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f16")]
27649 #[cfg_attr(
27650 any(target_arch = "aarch64", target_arch = "arm64ec"),
27651 link_name = "llvm.aarch64.neon.fmax.v4f16"
27652 )]
27653 fn _vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
27654 }
27655 unsafe { _vmax_f16(a, b) }
27656}
27657#[doc = "Maximum (vector)"]
27658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"]
27659#[inline]
27660#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
27661#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27662#[cfg_attr(
27663 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27664 assert_instr(fmax)
27665)]
27666#[target_feature(enable = "neon,fp16")]
27667#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27668pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
27669 unsafe extern "unadjusted" {
27670 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8f16")]
27671 #[cfg_attr(
27672 any(target_arch = "aarch64", target_arch = "arm64ec"),
27673 link_name = "llvm.aarch64.neon.fmax.v8f16"
27674 )]
27675 fn _vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
27676 }
27677 unsafe { _vmaxq_f16(a, b) }
27678}
27679#[doc = "Maximum (vector)"]
27680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"]
27681#[inline]
27682#[target_feature(enable = "neon")]
27683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27685#[cfg_attr(
27686 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27687 assert_instr(fmax)
27688)]
27689#[cfg_attr(
27690 not(target_arch = "arm"),
27691 stable(feature = "neon_intrinsics", since = "1.59.0")
27692)]
27693#[cfg_attr(
27694 target_arch = "arm",
27695 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27696)]
27697pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
27698 unsafe extern "unadjusted" {
27699 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")]
27700 #[cfg_attr(
27701 any(target_arch = "aarch64", target_arch = "arm64ec"),
27702 link_name = "llvm.aarch64.neon.fmax.v2f32"
27703 )]
27704 fn _vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
27705 }
27706 unsafe { _vmax_f32(a, b) }
27707}
27708#[doc = "Maximum (vector)"]
27709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"]
27710#[inline]
27711#[target_feature(enable = "neon")]
27712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27713#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27714#[cfg_attr(
27715 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27716 assert_instr(fmax)
27717)]
27718#[cfg_attr(
27719 not(target_arch = "arm"),
27720 stable(feature = "neon_intrinsics", since = "1.59.0")
27721)]
27722#[cfg_attr(
27723 target_arch = "arm",
27724 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27725)]
27726pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
27727 unsafe extern "unadjusted" {
27728 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")]
27729 #[cfg_attr(
27730 any(target_arch = "aarch64", target_arch = "arm64ec"),
27731 link_name = "llvm.aarch64.neon.fmax.v4f32"
27732 )]
27733 fn _vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
27734 }
27735 unsafe { _vmaxq_f32(a, b) }
27736}
27737#[doc = "Maximum (vector)"]
27738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"]
27739#[inline]
27740#[target_feature(enable = "neon")]
27741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27742#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27743#[cfg_attr(
27744 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27745 assert_instr(smax)
27746)]
27747#[cfg_attr(
27748 not(target_arch = "arm"),
27749 stable(feature = "neon_intrinsics", since = "1.59.0")
27750)]
27751#[cfg_attr(
27752 target_arch = "arm",
27753 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27754)]
27755pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
27756 unsafe extern "unadjusted" {
27757 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i8")]
27758 #[cfg_attr(
27759 any(target_arch = "aarch64", target_arch = "arm64ec"),
27760 link_name = "llvm.aarch64.neon.smax.v8i8"
27761 )]
27762 fn _vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
27763 }
27764 unsafe { _vmax_s8(a, b) }
27765}
27766#[doc = "Maximum (vector)"]
27767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"]
27768#[inline]
27769#[target_feature(enable = "neon")]
27770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27771#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27772#[cfg_attr(
27773 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27774 assert_instr(smax)
27775)]
27776#[cfg_attr(
27777 not(target_arch = "arm"),
27778 stable(feature = "neon_intrinsics", since = "1.59.0")
27779)]
27780#[cfg_attr(
27781 target_arch = "arm",
27782 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27783)]
27784pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
27785 unsafe extern "unadjusted" {
27786 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v16i8")]
27787 #[cfg_attr(
27788 any(target_arch = "aarch64", target_arch = "arm64ec"),
27789 link_name = "llvm.aarch64.neon.smax.v16i8"
27790 )]
27791 fn _vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
27792 }
27793 unsafe { _vmaxq_s8(a, b) }
27794}
27795#[doc = "Maximum (vector)"]
27796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"]
27797#[inline]
27798#[target_feature(enable = "neon")]
27799#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27800#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27801#[cfg_attr(
27802 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27803 assert_instr(smax)
27804)]
27805#[cfg_attr(
27806 not(target_arch = "arm"),
27807 stable(feature = "neon_intrinsics", since = "1.59.0")
27808)]
27809#[cfg_attr(
27810 target_arch = "arm",
27811 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27812)]
27813pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
27814 unsafe extern "unadjusted" {
27815 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i16")]
27816 #[cfg_attr(
27817 any(target_arch = "aarch64", target_arch = "arm64ec"),
27818 link_name = "llvm.aarch64.neon.smax.v4i16"
27819 )]
27820 fn _vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
27821 }
27822 unsafe { _vmax_s16(a, b) }
27823}
27824#[doc = "Maximum (vector)"]
27825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"]
27826#[inline]
27827#[target_feature(enable = "neon")]
27828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27829#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27830#[cfg_attr(
27831 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27832 assert_instr(smax)
27833)]
27834#[cfg_attr(
27835 not(target_arch = "arm"),
27836 stable(feature = "neon_intrinsics", since = "1.59.0")
27837)]
27838#[cfg_attr(
27839 target_arch = "arm",
27840 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27841)]
27842pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
27843 unsafe extern "unadjusted" {
27844 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i16")]
27845 #[cfg_attr(
27846 any(target_arch = "aarch64", target_arch = "arm64ec"),
27847 link_name = "llvm.aarch64.neon.smax.v8i16"
27848 )]
27849 fn _vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
27850 }
27851 unsafe { _vmaxq_s16(a, b) }
27852}
27853#[doc = "Maximum (vector)"]
27854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"]
27855#[inline]
27856#[target_feature(enable = "neon")]
27857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27858#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27859#[cfg_attr(
27860 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27861 assert_instr(smax)
27862)]
27863#[cfg_attr(
27864 not(target_arch = "arm"),
27865 stable(feature = "neon_intrinsics", since = "1.59.0")
27866)]
27867#[cfg_attr(
27868 target_arch = "arm",
27869 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27870)]
27871pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
27872 unsafe extern "unadjusted" {
27873 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2i32")]
27874 #[cfg_attr(
27875 any(target_arch = "aarch64", target_arch = "arm64ec"),
27876 link_name = "llvm.aarch64.neon.smax.v2i32"
27877 )]
27878 fn _vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
27879 }
27880 unsafe { _vmax_s32(a, b) }
27881}
27882#[doc = "Maximum (vector)"]
27883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"]
27884#[inline]
27885#[target_feature(enable = "neon")]
27886#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27887#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27888#[cfg_attr(
27889 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27890 assert_instr(smax)
27891)]
27892#[cfg_attr(
27893 not(target_arch = "arm"),
27894 stable(feature = "neon_intrinsics", since = "1.59.0")
27895)]
27896#[cfg_attr(
27897 target_arch = "arm",
27898 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27899)]
27900pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
27901 unsafe extern "unadjusted" {
27902 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i32")]
27903 #[cfg_attr(
27904 any(target_arch = "aarch64", target_arch = "arm64ec"),
27905 link_name = "llvm.aarch64.neon.smax.v4i32"
27906 )]
27907 fn _vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
27908 }
27909 unsafe { _vmaxq_s32(a, b) }
27910}
27911#[doc = "Maximum (vector)"]
27912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"]
27913#[inline]
27914#[target_feature(enable = "neon")]
27915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27917#[cfg_attr(
27918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27919 assert_instr(umax)
27920)]
27921#[cfg_attr(
27922 not(target_arch = "arm"),
27923 stable(feature = "neon_intrinsics", since = "1.59.0")
27924)]
27925#[cfg_attr(
27926 target_arch = "arm",
27927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27928)]
27929pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
27930 unsafe extern "unadjusted" {
27931 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i8")]
27932 #[cfg_attr(
27933 any(target_arch = "aarch64", target_arch = "arm64ec"),
27934 link_name = "llvm.aarch64.neon.umax.v8i8"
27935 )]
27936 fn _vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
27937 }
27938 unsafe { _vmax_u8(a, b) }
27939}
27940#[doc = "Maximum (vector)"]
27941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"]
27942#[inline]
27943#[target_feature(enable = "neon")]
27944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27946#[cfg_attr(
27947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27948 assert_instr(umax)
27949)]
27950#[cfg_attr(
27951 not(target_arch = "arm"),
27952 stable(feature = "neon_intrinsics", since = "1.59.0")
27953)]
27954#[cfg_attr(
27955 target_arch = "arm",
27956 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27957)]
27958pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
27959 unsafe extern "unadjusted" {
27960 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v16i8")]
27961 #[cfg_attr(
27962 any(target_arch = "aarch64", target_arch = "arm64ec"),
27963 link_name = "llvm.aarch64.neon.umax.v16i8"
27964 )]
27965 fn _vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
27966 }
27967 unsafe { _vmaxq_u8(a, b) }
27968}
27969#[doc = "Maximum (vector)"]
27970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"]
27971#[inline]
27972#[target_feature(enable = "neon")]
27973#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27974#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27975#[cfg_attr(
27976 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27977 assert_instr(umax)
27978)]
27979#[cfg_attr(
27980 not(target_arch = "arm"),
27981 stable(feature = "neon_intrinsics", since = "1.59.0")
27982)]
27983#[cfg_attr(
27984 target_arch = "arm",
27985 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27986)]
27987pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
27988 unsafe extern "unadjusted" {
27989 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i16")]
27990 #[cfg_attr(
27991 any(target_arch = "aarch64", target_arch = "arm64ec"),
27992 link_name = "llvm.aarch64.neon.umax.v4i16"
27993 )]
27994 fn _vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
27995 }
27996 unsafe { _vmax_u16(a, b) }
27997}
27998#[doc = "Maximum (vector)"]
27999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"]
28000#[inline]
28001#[target_feature(enable = "neon")]
28002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28003#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
28004#[cfg_attr(
28005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28006 assert_instr(umax)
28007)]
28008#[cfg_attr(
28009 not(target_arch = "arm"),
28010 stable(feature = "neon_intrinsics", since = "1.59.0")
28011)]
28012#[cfg_attr(
28013 target_arch = "arm",
28014 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28015)]
28016pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
28017 unsafe extern "unadjusted" {
28018 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i16")]
28019 #[cfg_attr(
28020 any(target_arch = "aarch64", target_arch = "arm64ec"),
28021 link_name = "llvm.aarch64.neon.umax.v8i16"
28022 )]
28023 fn _vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
28024 }
28025 unsafe { _vmaxq_u16(a, b) }
28026}
28027#[doc = "Maximum (vector)"]
28028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"]
28029#[inline]
28030#[target_feature(enable = "neon")]
28031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
28033#[cfg_attr(
28034 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28035 assert_instr(umax)
28036)]
28037#[cfg_attr(
28038 not(target_arch = "arm"),
28039 stable(feature = "neon_intrinsics", since = "1.59.0")
28040)]
28041#[cfg_attr(
28042 target_arch = "arm",
28043 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28044)]
28045pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
28046 unsafe extern "unadjusted" {
28047 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v2i32")]
28048 #[cfg_attr(
28049 any(target_arch = "aarch64", target_arch = "arm64ec"),
28050 link_name = "llvm.aarch64.neon.umax.v2i32"
28051 )]
28052 fn _vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
28053 }
28054 unsafe { _vmax_u32(a, b) }
28055}
28056#[doc = "Maximum (vector)"]
28057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"]
28058#[inline]
28059#[target_feature(enable = "neon")]
28060#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28061#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
28062#[cfg_attr(
28063 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28064 assert_instr(umax)
28065)]
28066#[cfg_attr(
28067 not(target_arch = "arm"),
28068 stable(feature = "neon_intrinsics", since = "1.59.0")
28069)]
28070#[cfg_attr(
28071 target_arch = "arm",
28072 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28073)]
28074pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
28075 unsafe extern "unadjusted" {
28076 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i32")]
28077 #[cfg_attr(
28078 any(target_arch = "aarch64", target_arch = "arm64ec"),
28079 link_name = "llvm.aarch64.neon.umax.v4i32"
28080 )]
28081 fn _vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
28082 }
28083 unsafe { _vmaxq_u32(a, b) }
28084}
28085#[doc = "Floating-point Maximum Number (vector)"]
28086#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"]
28087#[inline]
28088#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28089#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28090#[cfg_attr(
28091 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28092 assert_instr(fmaxnm)
28093)]
28094#[target_feature(enable = "neon,fp16")]
28095#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28096pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28097 unsafe extern "unadjusted" {
28098 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")]
28099 #[cfg_attr(
28100 any(target_arch = "aarch64", target_arch = "arm64ec"),
28101 link_name = "llvm.aarch64.neon.fmaxnm.v4f16"
28102 )]
28103 fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
28104 }
28105 unsafe { _vmaxnm_f16(a, b) }
28106}
28107#[doc = "Floating-point Maximum Number (vector)"]
28108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"]
28109#[inline]
28110#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28111#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28112#[cfg_attr(
28113 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28114 assert_instr(fmaxnm)
28115)]
28116#[target_feature(enable = "neon,fp16")]
28117#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28118pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28119 unsafe extern "unadjusted" {
28120 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")]
28121 #[cfg_attr(
28122 any(target_arch = "aarch64", target_arch = "arm64ec"),
28123 link_name = "llvm.aarch64.neon.fmaxnm.v8f16"
28124 )]
28125 fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
28126 }
28127 unsafe { _vmaxnmq_f16(a, b) }
28128}
28129#[doc = "Floating-point Maximum Number (vector)"]
28130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"]
28131#[inline]
28132#[target_feature(enable = "neon")]
28133#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28135#[cfg_attr(
28136 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28137 assert_instr(fmaxnm)
28138)]
28139#[cfg_attr(
28140 not(target_arch = "arm"),
28141 stable(feature = "neon_intrinsics", since = "1.59.0")
28142)]
28143#[cfg_attr(
28144 target_arch = "arm",
28145 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28146)]
28147pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28148 unsafe extern "unadjusted" {
28149 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")]
28150 #[cfg_attr(
28151 any(target_arch = "aarch64", target_arch = "arm64ec"),
28152 link_name = "llvm.aarch64.neon.fmaxnm.v2f32"
28153 )]
28154 fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
28155 }
28156 unsafe { _vmaxnm_f32(a, b) }
28157}
28158#[doc = "Floating-point Maximum Number (vector)"]
28159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"]
28160#[inline]
28161#[target_feature(enable = "neon")]
28162#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28163#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
28164#[cfg_attr(
28165 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28166 assert_instr(fmaxnm)
28167)]
28168#[cfg_attr(
28169 not(target_arch = "arm"),
28170 stable(feature = "neon_intrinsics", since = "1.59.0")
28171)]
28172#[cfg_attr(
28173 target_arch = "arm",
28174 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28175)]
28176pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28177 unsafe extern "unadjusted" {
28178 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")]
28179 #[cfg_attr(
28180 any(target_arch = "aarch64", target_arch = "arm64ec"),
28181 link_name = "llvm.aarch64.neon.fmaxnm.v4f32"
28182 )]
28183 fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
28184 }
28185 unsafe { _vmaxnmq_f32(a, b) }
28186}
28187#[doc = "Minimum (vector)"]
28188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"]
28189#[inline]
28190#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
28191#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28192#[cfg_attr(
28193 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28194 assert_instr(fmin)
28195)]
28196#[target_feature(enable = "neon,fp16")]
28197#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28198pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28199 unsafe extern "unadjusted" {
28200 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f16")]
28201 #[cfg_attr(
28202 any(target_arch = "aarch64", target_arch = "arm64ec"),
28203 link_name = "llvm.aarch64.neon.fmin.v4f16"
28204 )]
28205 fn _vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
28206 }
28207 unsafe { _vmin_f16(a, b) }
28208}
28209#[doc = "Minimum (vector)"]
28210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"]
28211#[inline]
28212#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
28213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28214#[cfg_attr(
28215 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28216 assert_instr(fmin)
28217)]
28218#[target_feature(enable = "neon,fp16")]
28219#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28220pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28221 unsafe extern "unadjusted" {
28222 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8f16")]
28223 #[cfg_attr(
28224 any(target_arch = "aarch64", target_arch = "arm64ec"),
28225 link_name = "llvm.aarch64.neon.fmin.v8f16"
28226 )]
28227 fn _vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
28228 }
28229 unsafe { _vminq_f16(a, b) }
28230}
28231#[doc = "Minimum (vector)"]
28232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"]
28233#[inline]
28234#[target_feature(enable = "neon")]
28235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28237#[cfg_attr(
28238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28239 assert_instr(fmin)
28240)]
28241#[cfg_attr(
28242 not(target_arch = "arm"),
28243 stable(feature = "neon_intrinsics", since = "1.59.0")
28244)]
28245#[cfg_attr(
28246 target_arch = "arm",
28247 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28248)]
28249pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28250 unsafe extern "unadjusted" {
28251 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")]
28252 #[cfg_attr(
28253 any(target_arch = "aarch64", target_arch = "arm64ec"),
28254 link_name = "llvm.aarch64.neon.fmin.v2f32"
28255 )]
28256 fn _vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
28257 }
28258 unsafe { _vmin_f32(a, b) }
28259}
28260#[doc = "Minimum (vector)"]
28261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"]
28262#[inline]
28263#[target_feature(enable = "neon")]
28264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28266#[cfg_attr(
28267 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28268 assert_instr(fmin)
28269)]
28270#[cfg_attr(
28271 not(target_arch = "arm"),
28272 stable(feature = "neon_intrinsics", since = "1.59.0")
28273)]
28274#[cfg_attr(
28275 target_arch = "arm",
28276 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28277)]
28278pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28279 unsafe extern "unadjusted" {
28280 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")]
28281 #[cfg_attr(
28282 any(target_arch = "aarch64", target_arch = "arm64ec"),
28283 link_name = "llvm.aarch64.neon.fmin.v4f32"
28284 )]
28285 fn _vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
28286 }
28287 unsafe { _vminq_f32(a, b) }
28288}
28289#[doc = "Minimum (vector)"]
28290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"]
28291#[inline]
28292#[target_feature(enable = "neon")]
28293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28294#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28295#[cfg_attr(
28296 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28297 assert_instr(smin)
28298)]
28299#[cfg_attr(
28300 not(target_arch = "arm"),
28301 stable(feature = "neon_intrinsics", since = "1.59.0")
28302)]
28303#[cfg_attr(
28304 target_arch = "arm",
28305 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28306)]
28307pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
28308 unsafe extern "unadjusted" {
28309 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i8")]
28310 #[cfg_attr(
28311 any(target_arch = "aarch64", target_arch = "arm64ec"),
28312 link_name = "llvm.aarch64.neon.smin.v8i8"
28313 )]
28314 fn _vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
28315 }
28316 unsafe { _vmin_s8(a, b) }
28317}
28318#[doc = "Minimum (vector)"]
28319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"]
28320#[inline]
28321#[target_feature(enable = "neon")]
28322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28323#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28324#[cfg_attr(
28325 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28326 assert_instr(smin)
28327)]
28328#[cfg_attr(
28329 not(target_arch = "arm"),
28330 stable(feature = "neon_intrinsics", since = "1.59.0")
28331)]
28332#[cfg_attr(
28333 target_arch = "arm",
28334 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28335)]
28336pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
28337 unsafe extern "unadjusted" {
28338 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v16i8")]
28339 #[cfg_attr(
28340 any(target_arch = "aarch64", target_arch = "arm64ec"),
28341 link_name = "llvm.aarch64.neon.smin.v16i8"
28342 )]
28343 fn _vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
28344 }
28345 unsafe { _vminq_s8(a, b) }
28346}
28347#[doc = "Minimum (vector)"]
28348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"]
28349#[inline]
28350#[target_feature(enable = "neon")]
28351#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28352#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28353#[cfg_attr(
28354 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28355 assert_instr(smin)
28356)]
28357#[cfg_attr(
28358 not(target_arch = "arm"),
28359 stable(feature = "neon_intrinsics", since = "1.59.0")
28360)]
28361#[cfg_attr(
28362 target_arch = "arm",
28363 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28364)]
28365pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
28366 unsafe extern "unadjusted" {
28367 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i16")]
28368 #[cfg_attr(
28369 any(target_arch = "aarch64", target_arch = "arm64ec"),
28370 link_name = "llvm.aarch64.neon.smin.v4i16"
28371 )]
28372 fn _vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
28373 }
28374 unsafe { _vmin_s16(a, b) }
28375}
28376#[doc = "Minimum (vector)"]
28377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"]
28378#[inline]
28379#[target_feature(enable = "neon")]
28380#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28381#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28382#[cfg_attr(
28383 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28384 assert_instr(smin)
28385)]
28386#[cfg_attr(
28387 not(target_arch = "arm"),
28388 stable(feature = "neon_intrinsics", since = "1.59.0")
28389)]
28390#[cfg_attr(
28391 target_arch = "arm",
28392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28393)]
28394pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
28395 unsafe extern "unadjusted" {
28396 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i16")]
28397 #[cfg_attr(
28398 any(target_arch = "aarch64", target_arch = "arm64ec"),
28399 link_name = "llvm.aarch64.neon.smin.v8i16"
28400 )]
28401 fn _vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
28402 }
28403 unsafe { _vminq_s16(a, b) }
28404}
28405#[doc = "Minimum (vector)"]
28406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"]
28407#[inline]
28408#[target_feature(enable = "neon")]
28409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28410#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28411#[cfg_attr(
28412 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28413 assert_instr(smin)
28414)]
28415#[cfg_attr(
28416 not(target_arch = "arm"),
28417 stable(feature = "neon_intrinsics", since = "1.59.0")
28418)]
28419#[cfg_attr(
28420 target_arch = "arm",
28421 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28422)]
28423pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
28424 unsafe extern "unadjusted" {
28425 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2i32")]
28426 #[cfg_attr(
28427 any(target_arch = "aarch64", target_arch = "arm64ec"),
28428 link_name = "llvm.aarch64.neon.smin.v2i32"
28429 )]
28430 fn _vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
28431 }
28432 unsafe { _vmin_s32(a, b) }
28433}
28434#[doc = "Minimum (vector)"]
28435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"]
28436#[inline]
28437#[target_feature(enable = "neon")]
28438#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28439#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28440#[cfg_attr(
28441 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28442 assert_instr(smin)
28443)]
28444#[cfg_attr(
28445 not(target_arch = "arm"),
28446 stable(feature = "neon_intrinsics", since = "1.59.0")
28447)]
28448#[cfg_attr(
28449 target_arch = "arm",
28450 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28451)]
28452pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
28453 unsafe extern "unadjusted" {
28454 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i32")]
28455 #[cfg_attr(
28456 any(target_arch = "aarch64", target_arch = "arm64ec"),
28457 link_name = "llvm.aarch64.neon.smin.v4i32"
28458 )]
28459 fn _vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
28460 }
28461 unsafe { _vminq_s32(a, b) }
28462}
28463#[doc = "Minimum (vector)"]
28464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"]
28465#[inline]
28466#[target_feature(enable = "neon")]
28467#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28468#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28469#[cfg_attr(
28470 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28471 assert_instr(umin)
28472)]
28473#[cfg_attr(
28474 not(target_arch = "arm"),
28475 stable(feature = "neon_intrinsics", since = "1.59.0")
28476)]
28477#[cfg_attr(
28478 target_arch = "arm",
28479 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28480)]
28481pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
28482 unsafe extern "unadjusted" {
28483 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i8")]
28484 #[cfg_attr(
28485 any(target_arch = "aarch64", target_arch = "arm64ec"),
28486 link_name = "llvm.aarch64.neon.umin.v8i8"
28487 )]
28488 fn _vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
28489 }
28490 unsafe { _vmin_u8(a, b) }
28491}
28492#[doc = "Minimum (vector)"]
28493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"]
28494#[inline]
28495#[target_feature(enable = "neon")]
28496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28497#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28498#[cfg_attr(
28499 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28500 assert_instr(umin)
28501)]
28502#[cfg_attr(
28503 not(target_arch = "arm"),
28504 stable(feature = "neon_intrinsics", since = "1.59.0")
28505)]
28506#[cfg_attr(
28507 target_arch = "arm",
28508 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28509)]
28510pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
28511 unsafe extern "unadjusted" {
28512 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v16i8")]
28513 #[cfg_attr(
28514 any(target_arch = "aarch64", target_arch = "arm64ec"),
28515 link_name = "llvm.aarch64.neon.umin.v16i8"
28516 )]
28517 fn _vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
28518 }
28519 unsafe { _vminq_u8(a, b) }
28520}
28521#[doc = "Minimum (vector)"]
28522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"]
28523#[inline]
28524#[target_feature(enable = "neon")]
28525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28527#[cfg_attr(
28528 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28529 assert_instr(umin)
28530)]
28531#[cfg_attr(
28532 not(target_arch = "arm"),
28533 stable(feature = "neon_intrinsics", since = "1.59.0")
28534)]
28535#[cfg_attr(
28536 target_arch = "arm",
28537 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28538)]
28539pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
28540 unsafe extern "unadjusted" {
28541 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i16")]
28542 #[cfg_attr(
28543 any(target_arch = "aarch64", target_arch = "arm64ec"),
28544 link_name = "llvm.aarch64.neon.umin.v4i16"
28545 )]
28546 fn _vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
28547 }
28548 unsafe { _vmin_u16(a, b) }
28549}
28550#[doc = "Minimum (vector)"]
28551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"]
28552#[inline]
28553#[target_feature(enable = "neon")]
28554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28555#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28556#[cfg_attr(
28557 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28558 assert_instr(umin)
28559)]
28560#[cfg_attr(
28561 not(target_arch = "arm"),
28562 stable(feature = "neon_intrinsics", since = "1.59.0")
28563)]
28564#[cfg_attr(
28565 target_arch = "arm",
28566 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28567)]
28568pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
28569 unsafe extern "unadjusted" {
28570 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i16")]
28571 #[cfg_attr(
28572 any(target_arch = "aarch64", target_arch = "arm64ec"),
28573 link_name = "llvm.aarch64.neon.umin.v8i16"
28574 )]
28575 fn _vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
28576 }
28577 unsafe { _vminq_u16(a, b) }
28578}
28579#[doc = "Minimum (vector)"]
28580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"]
28581#[inline]
28582#[target_feature(enable = "neon")]
28583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28585#[cfg_attr(
28586 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28587 assert_instr(umin)
28588)]
28589#[cfg_attr(
28590 not(target_arch = "arm"),
28591 stable(feature = "neon_intrinsics", since = "1.59.0")
28592)]
28593#[cfg_attr(
28594 target_arch = "arm",
28595 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28596)]
28597pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
28598 unsafe extern "unadjusted" {
28599 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v2i32")]
28600 #[cfg_attr(
28601 any(target_arch = "aarch64", target_arch = "arm64ec"),
28602 link_name = "llvm.aarch64.neon.umin.v2i32"
28603 )]
28604 fn _vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
28605 }
28606 unsafe { _vmin_u32(a, b) }
28607}
28608#[doc = "Minimum (vector)"]
28609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"]
28610#[inline]
28611#[target_feature(enable = "neon")]
28612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28614#[cfg_attr(
28615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28616 assert_instr(umin)
28617)]
28618#[cfg_attr(
28619 not(target_arch = "arm"),
28620 stable(feature = "neon_intrinsics", since = "1.59.0")
28621)]
28622#[cfg_attr(
28623 target_arch = "arm",
28624 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28625)]
28626pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
28627 unsafe extern "unadjusted" {
28628 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i32")]
28629 #[cfg_attr(
28630 any(target_arch = "aarch64", target_arch = "arm64ec"),
28631 link_name = "llvm.aarch64.neon.umin.v4i32"
28632 )]
28633 fn _vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
28634 }
28635 unsafe { _vminq_u32(a, b) }
28636}
28637#[doc = "Floating-point Minimum Number (vector)"]
28638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"]
28639#[inline]
28640#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28642#[cfg_attr(
28643 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28644 assert_instr(fminnm)
28645)]
28646#[target_feature(enable = "neon,fp16")]
28647#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28648pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28649 unsafe extern "unadjusted" {
28650 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")]
28651 #[cfg_attr(
28652 any(target_arch = "aarch64", target_arch = "arm64ec"),
28653 link_name = "llvm.aarch64.neon.fminnm.v4f16"
28654 )]
28655 fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
28656 }
28657 unsafe { _vminnm_f16(a, b) }
28658}
28659#[doc = "Floating-point Minimum Number (vector)"]
28660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"]
28661#[inline]
28662#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28663#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28664#[cfg_attr(
28665 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28666 assert_instr(fminnm)
28667)]
28668#[target_feature(enable = "neon,fp16")]
28669#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28670pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28671 unsafe extern "unadjusted" {
28672 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")]
28673 #[cfg_attr(
28674 any(target_arch = "aarch64", target_arch = "arm64ec"),
28675 link_name = "llvm.aarch64.neon.fminnm.v8f16"
28676 )]
28677 fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
28678 }
28679 unsafe { _vminnmq_f16(a, b) }
28680}
28681#[doc = "Floating-point Minimum Number (vector)"]
28682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"]
28683#[inline]
28684#[target_feature(enable = "neon")]
28685#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28686#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28687#[cfg_attr(
28688 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28689 assert_instr(fminnm)
28690)]
28691#[cfg_attr(
28692 not(target_arch = "arm"),
28693 stable(feature = "neon_intrinsics", since = "1.59.0")
28694)]
28695#[cfg_attr(
28696 target_arch = "arm",
28697 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28698)]
28699pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28700 unsafe extern "unadjusted" {
28701 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")]
28702 #[cfg_attr(
28703 any(target_arch = "aarch64", target_arch = "arm64ec"),
28704 link_name = "llvm.aarch64.neon.fminnm.v2f32"
28705 )]
28706 fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
28707 }
28708 unsafe { _vminnm_f32(a, b) }
28709}
28710#[doc = "Floating-point Minimum Number (vector)"]
28711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"]
28712#[inline]
28713#[target_feature(enable = "neon")]
28714#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28715#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28716#[cfg_attr(
28717 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28718 assert_instr(fminnm)
28719)]
28720#[cfg_attr(
28721 not(target_arch = "arm"),
28722 stable(feature = "neon_intrinsics", since = "1.59.0")
28723)]
28724#[cfg_attr(
28725 target_arch = "arm",
28726 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28727)]
28728pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28729 unsafe extern "unadjusted" {
28730 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")]
28731 #[cfg_attr(
28732 any(target_arch = "aarch64", target_arch = "arm64ec"),
28733 link_name = "llvm.aarch64.neon.fminnm.v4f32"
28734 )]
28735 fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
28736 }
28737 unsafe { _vminnmq_f32(a, b) }
28738}
28739#[doc = "Floating-point multiply-add to accumulator"]
28740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"]
28741#[inline]
28742#[target_feature(enable = "neon")]
28743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28744#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
28745#[cfg_attr(
28746 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28747 assert_instr(fmul)
28748)]
28749#[cfg_attr(
28750 not(target_arch = "arm"),
28751 stable(feature = "neon_intrinsics", since = "1.59.0")
28752)]
28753#[cfg_attr(
28754 target_arch = "arm",
28755 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28756)]
28757pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
28758 unsafe { simd_add(a, simd_mul(b, c)) }
28759}
28760#[doc = "Floating-point multiply-add to accumulator"]
28761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"]
28762#[inline]
28763#[target_feature(enable = "neon")]
28764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28765#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
28766#[cfg_attr(
28767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28768 assert_instr(fmul)
28769)]
28770#[cfg_attr(
28771 not(target_arch = "arm"),
28772 stable(feature = "neon_intrinsics", since = "1.59.0")
28773)]
28774#[cfg_attr(
28775 target_arch = "arm",
28776 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28777)]
28778pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
28779 unsafe { simd_add(a, simd_mul(b, c)) }
28780}
28781#[doc = "Vector multiply accumulate with scalar"]
28782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"]
28783#[inline]
28784#[target_feature(enable = "neon")]
28785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28786#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28787#[cfg_attr(
28788 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28789 assert_instr(fmul, LANE = 1)
28790)]
28791#[rustc_legacy_const_generics(3)]
28792#[cfg_attr(
28793 not(target_arch = "arm"),
28794 stable(feature = "neon_intrinsics", since = "1.59.0")
28795)]
28796#[cfg_attr(
28797 target_arch = "arm",
28798 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28799)]
28800pub fn vmla_lane_f32<const LANE: i32>(
28801 a: float32x2_t,
28802 b: float32x2_t,
28803 c: float32x2_t,
28804) -> float32x2_t {
28805 static_assert_uimm_bits!(LANE, 1);
28806 unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28807}
28808#[doc = "Vector multiply accumulate with scalar"]
28809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"]
28810#[inline]
28811#[target_feature(enable = "neon")]
28812#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28813#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28814#[cfg_attr(
28815 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28816 assert_instr(fmul, LANE = 1)
28817)]
28818#[rustc_legacy_const_generics(3)]
28819#[cfg_attr(
28820 not(target_arch = "arm"),
28821 stable(feature = "neon_intrinsics", since = "1.59.0")
28822)]
28823#[cfg_attr(
28824 target_arch = "arm",
28825 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28826)]
28827pub fn vmla_laneq_f32<const LANE: i32>(
28828 a: float32x2_t,
28829 b: float32x2_t,
28830 c: float32x4_t,
28831) -> float32x2_t {
28832 static_assert_uimm_bits!(LANE, 2);
28833 unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28834}
28835#[doc = "Vector multiply accumulate with scalar"]
28836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"]
28837#[inline]
28838#[target_feature(enable = "neon")]
28839#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28840#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28841#[cfg_attr(
28842 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28843 assert_instr(fmul, LANE = 1)
28844)]
28845#[rustc_legacy_const_generics(3)]
28846#[cfg_attr(
28847 not(target_arch = "arm"),
28848 stable(feature = "neon_intrinsics", since = "1.59.0")
28849)]
28850#[cfg_attr(
28851 target_arch = "arm",
28852 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28853)]
28854pub fn vmlaq_lane_f32<const LANE: i32>(
28855 a: float32x4_t,
28856 b: float32x4_t,
28857 c: float32x2_t,
28858) -> float32x4_t {
28859 static_assert_uimm_bits!(LANE, 1);
28860 unsafe {
28861 vmlaq_f32(
28862 a,
28863 b,
28864 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28865 )
28866 }
28867}
28868#[doc = "Vector multiply accumulate with scalar"]
28869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"]
28870#[inline]
28871#[target_feature(enable = "neon")]
28872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28873#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28874#[cfg_attr(
28875 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28876 assert_instr(fmul, LANE = 1)
28877)]
28878#[rustc_legacy_const_generics(3)]
28879#[cfg_attr(
28880 not(target_arch = "arm"),
28881 stable(feature = "neon_intrinsics", since = "1.59.0")
28882)]
28883#[cfg_attr(
28884 target_arch = "arm",
28885 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28886)]
28887pub fn vmlaq_laneq_f32<const LANE: i32>(
28888 a: float32x4_t,
28889 b: float32x4_t,
28890 c: float32x4_t,
28891) -> float32x4_t {
28892 static_assert_uimm_bits!(LANE, 2);
28893 unsafe {
28894 vmlaq_f32(
28895 a,
28896 b,
28897 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28898 )
28899 }
28900}
28901#[doc = "Vector multiply accumulate with scalar"]
28902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"]
28903#[inline]
28904#[target_feature(enable = "neon")]
28905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28906#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28907#[cfg_attr(
28908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28909 assert_instr(mla, LANE = 1)
28910)]
28911#[rustc_legacy_const_generics(3)]
28912#[cfg_attr(
28913 not(target_arch = "arm"),
28914 stable(feature = "neon_intrinsics", since = "1.59.0")
28915)]
28916#[cfg_attr(
28917 target_arch = "arm",
28918 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28919)]
28920pub fn vmla_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
28921 static_assert_uimm_bits!(LANE, 2);
28922 unsafe {
28923 vmla_s16(
28924 a,
28925 b,
28926 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28927 )
28928 }
28929}
28930#[doc = "Vector multiply accumulate with scalar"]
28931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"]
28932#[inline]
28933#[target_feature(enable = "neon")]
28934#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28935#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28936#[cfg_attr(
28937 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28938 assert_instr(mla, LANE = 1)
28939)]
28940#[rustc_legacy_const_generics(3)]
28941#[cfg_attr(
28942 not(target_arch = "arm"),
28943 stable(feature = "neon_intrinsics", since = "1.59.0")
28944)]
28945#[cfg_attr(
28946 target_arch = "arm",
28947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28948)]
28949pub fn vmla_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
28950 static_assert_uimm_bits!(LANE, 2);
28951 unsafe {
28952 vmla_u16(
28953 a,
28954 b,
28955 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28956 )
28957 }
28958}
28959#[doc = "Vector multiply accumulate with scalar"]
28960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"]
28961#[inline]
28962#[target_feature(enable = "neon")]
28963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28964#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28965#[cfg_attr(
28966 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28967 assert_instr(mla, LANE = 1)
28968)]
28969#[rustc_legacy_const_generics(3)]
28970#[cfg_attr(
28971 not(target_arch = "arm"),
28972 stable(feature = "neon_intrinsics", since = "1.59.0")
28973)]
28974#[cfg_attr(
28975 target_arch = "arm",
28976 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28977)]
28978pub fn vmla_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
28979 static_assert_uimm_bits!(LANE, 3);
28980 unsafe {
28981 vmla_s16(
28982 a,
28983 b,
28984 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28985 )
28986 }
28987}
28988#[doc = "Vector multiply accumulate with scalar"]
28989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"]
28990#[inline]
28991#[target_feature(enable = "neon")]
28992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28993#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28994#[cfg_attr(
28995 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28996 assert_instr(mla, LANE = 1)
28997)]
28998#[rustc_legacy_const_generics(3)]
28999#[cfg_attr(
29000 not(target_arch = "arm"),
29001 stable(feature = "neon_intrinsics", since = "1.59.0")
29002)]
29003#[cfg_attr(
29004 target_arch = "arm",
29005 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29006)]
29007pub fn vmla_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
29008 static_assert_uimm_bits!(LANE, 3);
29009 unsafe {
29010 vmla_u16(
29011 a,
29012 b,
29013 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29014 )
29015 }
29016}
29017#[doc = "Vector multiply accumulate with scalar"]
29018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"]
29019#[inline]
29020#[target_feature(enable = "neon")]
29021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29022#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
29023#[cfg_attr(
29024 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29025 assert_instr(mla, LANE = 1)
29026)]
29027#[rustc_legacy_const_generics(3)]
29028#[cfg_attr(
29029 not(target_arch = "arm"),
29030 stable(feature = "neon_intrinsics", since = "1.59.0")
29031)]
29032#[cfg_attr(
29033 target_arch = "arm",
29034 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29035)]
29036pub fn vmlaq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
29037 static_assert_uimm_bits!(LANE, 2);
29038 unsafe {
29039 vmlaq_s16(
29040 a,
29041 b,
29042 simd_shuffle!(
29043 c,
29044 c,
29045 [
29046 LANE as u32,
29047 LANE as u32,
29048 LANE as u32,
29049 LANE as u32,
29050 LANE as u32,
29051 LANE as u32,
29052 LANE as u32,
29053 LANE as u32
29054 ]
29055 ),
29056 )
29057 }
29058}
29059#[doc = "Vector multiply accumulate with scalar"]
29060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"]
29061#[inline]
29062#[target_feature(enable = "neon")]
29063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29064#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
29065#[cfg_attr(
29066 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29067 assert_instr(mla, LANE = 1)
29068)]
29069#[rustc_legacy_const_generics(3)]
29070#[cfg_attr(
29071 not(target_arch = "arm"),
29072 stable(feature = "neon_intrinsics", since = "1.59.0")
29073)]
29074#[cfg_attr(
29075 target_arch = "arm",
29076 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29077)]
29078pub fn vmlaq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
29079 static_assert_uimm_bits!(LANE, 2);
29080 unsafe {
29081 vmlaq_u16(
29082 a,
29083 b,
29084 simd_shuffle!(
29085 c,
29086 c,
29087 [
29088 LANE as u32,
29089 LANE as u32,
29090 LANE as u32,
29091 LANE as u32,
29092 LANE as u32,
29093 LANE as u32,
29094 LANE as u32,
29095 LANE as u32
29096 ]
29097 ),
29098 )
29099 }
29100}
29101#[doc = "Vector multiply accumulate with scalar"]
29102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"]
29103#[inline]
29104#[target_feature(enable = "neon")]
29105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29106#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
29107#[cfg_attr(
29108 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29109 assert_instr(mla, LANE = 1)
29110)]
29111#[rustc_legacy_const_generics(3)]
29112#[cfg_attr(
29113 not(target_arch = "arm"),
29114 stable(feature = "neon_intrinsics", since = "1.59.0")
29115)]
29116#[cfg_attr(
29117 target_arch = "arm",
29118 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29119)]
29120pub fn vmlaq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
29121 static_assert_uimm_bits!(LANE, 3);
29122 unsafe {
29123 vmlaq_s16(
29124 a,
29125 b,
29126 simd_shuffle!(
29127 c,
29128 c,
29129 [
29130 LANE as u32,
29131 LANE as u32,
29132 LANE as u32,
29133 LANE as u32,
29134 LANE as u32,
29135 LANE as u32,
29136 LANE as u32,
29137 LANE as u32
29138 ]
29139 ),
29140 )
29141 }
29142}
29143#[doc = "Vector multiply accumulate with scalar"]
29144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"]
29145#[inline]
29146#[target_feature(enable = "neon")]
29147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29148#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
29149#[cfg_attr(
29150 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29151 assert_instr(mla, LANE = 1)
29152)]
29153#[rustc_legacy_const_generics(3)]
29154#[cfg_attr(
29155 not(target_arch = "arm"),
29156 stable(feature = "neon_intrinsics", since = "1.59.0")
29157)]
29158#[cfg_attr(
29159 target_arch = "arm",
29160 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29161)]
29162pub fn vmlaq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
29163 static_assert_uimm_bits!(LANE, 3);
29164 unsafe {
29165 vmlaq_u16(
29166 a,
29167 b,
29168 simd_shuffle!(
29169 c,
29170 c,
29171 [
29172 LANE as u32,
29173 LANE as u32,
29174 LANE as u32,
29175 LANE as u32,
29176 LANE as u32,
29177 LANE as u32,
29178 LANE as u32,
29179 LANE as u32
29180 ]
29181 ),
29182 )
29183 }
29184}
29185#[doc = "Vector multiply accumulate with scalar"]
29186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"]
29187#[inline]
29188#[target_feature(enable = "neon")]
29189#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29190#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29191#[cfg_attr(
29192 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29193 assert_instr(mla, LANE = 1)
29194)]
29195#[rustc_legacy_const_generics(3)]
29196#[cfg_attr(
29197 not(target_arch = "arm"),
29198 stable(feature = "neon_intrinsics", since = "1.59.0")
29199)]
29200#[cfg_attr(
29201 target_arch = "arm",
29202 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29203)]
29204pub fn vmla_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
29205 static_assert_uimm_bits!(LANE, 1);
29206 unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29207}
29208#[doc = "Vector multiply accumulate with scalar"]
29209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"]
29210#[inline]
29211#[target_feature(enable = "neon")]
29212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29213#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29214#[cfg_attr(
29215 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29216 assert_instr(mla, LANE = 1)
29217)]
29218#[rustc_legacy_const_generics(3)]
29219#[cfg_attr(
29220 not(target_arch = "arm"),
29221 stable(feature = "neon_intrinsics", since = "1.59.0")
29222)]
29223#[cfg_attr(
29224 target_arch = "arm",
29225 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29226)]
29227pub fn vmla_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
29228 static_assert_uimm_bits!(LANE, 1);
29229 unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29230}
29231#[doc = "Vector multiply accumulate with scalar"]
29232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"]
29233#[inline]
29234#[target_feature(enable = "neon")]
29235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29236#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29237#[cfg_attr(
29238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29239 assert_instr(mla, LANE = 1)
29240)]
29241#[rustc_legacy_const_generics(3)]
29242#[cfg_attr(
29243 not(target_arch = "arm"),
29244 stable(feature = "neon_intrinsics", since = "1.59.0")
29245)]
29246#[cfg_attr(
29247 target_arch = "arm",
29248 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29249)]
29250pub fn vmla_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
29251 static_assert_uimm_bits!(LANE, 2);
29252 unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29253}
29254#[doc = "Vector multiply accumulate with scalar"]
29255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"]
29256#[inline]
29257#[target_feature(enable = "neon")]
29258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29259#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29260#[cfg_attr(
29261 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29262 assert_instr(mla, LANE = 1)
29263)]
29264#[rustc_legacy_const_generics(3)]
29265#[cfg_attr(
29266 not(target_arch = "arm"),
29267 stable(feature = "neon_intrinsics", since = "1.59.0")
29268)]
29269#[cfg_attr(
29270 target_arch = "arm",
29271 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29272)]
29273pub fn vmla_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
29274 static_assert_uimm_bits!(LANE, 2);
29275 unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29276}
29277#[doc = "Vector multiply accumulate with scalar"]
29278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"]
29279#[inline]
29280#[target_feature(enable = "neon")]
29281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29282#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29283#[cfg_attr(
29284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29285 assert_instr(mla, LANE = 1)
29286)]
29287#[rustc_legacy_const_generics(3)]
29288#[cfg_attr(
29289 not(target_arch = "arm"),
29290 stable(feature = "neon_intrinsics", since = "1.59.0")
29291)]
29292#[cfg_attr(
29293 target_arch = "arm",
29294 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29295)]
29296pub fn vmlaq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
29297 static_assert_uimm_bits!(LANE, 1);
29298 unsafe {
29299 vmlaq_s32(
29300 a,
29301 b,
29302 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29303 )
29304 }
29305}
29306#[doc = "Vector multiply accumulate with scalar"]
29307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"]
29308#[inline]
29309#[target_feature(enable = "neon")]
29310#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29311#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29312#[cfg_attr(
29313 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29314 assert_instr(mla, LANE = 1)
29315)]
29316#[rustc_legacy_const_generics(3)]
29317#[cfg_attr(
29318 not(target_arch = "arm"),
29319 stable(feature = "neon_intrinsics", since = "1.59.0")
29320)]
29321#[cfg_attr(
29322 target_arch = "arm",
29323 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29324)]
29325pub fn vmlaq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
29326 static_assert_uimm_bits!(LANE, 1);
29327 unsafe {
29328 vmlaq_u32(
29329 a,
29330 b,
29331 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29332 )
29333 }
29334}
29335#[doc = "Vector multiply accumulate with scalar"]
29336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"]
29337#[inline]
29338#[target_feature(enable = "neon")]
29339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29340#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29341#[cfg_attr(
29342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29343 assert_instr(mla, LANE = 1)
29344)]
29345#[rustc_legacy_const_generics(3)]
29346#[cfg_attr(
29347 not(target_arch = "arm"),
29348 stable(feature = "neon_intrinsics", since = "1.59.0")
29349)]
29350#[cfg_attr(
29351 target_arch = "arm",
29352 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29353)]
29354pub fn vmlaq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
29355 static_assert_uimm_bits!(LANE, 2);
29356 unsafe {
29357 vmlaq_s32(
29358 a,
29359 b,
29360 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29361 )
29362 }
29363}
29364#[doc = "Vector multiply accumulate with scalar"]
29365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"]
29366#[inline]
29367#[target_feature(enable = "neon")]
29368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29369#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29370#[cfg_attr(
29371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29372 assert_instr(mla, LANE = 1)
29373)]
29374#[rustc_legacy_const_generics(3)]
29375#[cfg_attr(
29376 not(target_arch = "arm"),
29377 stable(feature = "neon_intrinsics", since = "1.59.0")
29378)]
29379#[cfg_attr(
29380 target_arch = "arm",
29381 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29382)]
29383pub fn vmlaq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
29384 static_assert_uimm_bits!(LANE, 2);
29385 unsafe {
29386 vmlaq_u32(
29387 a,
29388 b,
29389 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29390 )
29391 }
29392}
29393#[doc = "Vector multiply accumulate with scalar"]
29394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"]
29395#[inline]
29396#[target_feature(enable = "neon")]
29397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29398#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
29399#[cfg_attr(
29400 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29401 assert_instr(fmul)
29402)]
29403#[cfg_attr(
29404 not(target_arch = "arm"),
29405 stable(feature = "neon_intrinsics", since = "1.59.0")
29406)]
29407#[cfg_attr(
29408 target_arch = "arm",
29409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29410)]
29411pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
29412 vmla_f32(a, b, vdup_n_f32(c))
29413}
29414#[doc = "Vector multiply accumulate with scalar"]
29415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"]
29416#[inline]
29417#[target_feature(enable = "neon")]
29418#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29419#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
29420#[cfg_attr(
29421 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29422 assert_instr(fmul)
29423)]
29424#[cfg_attr(
29425 not(target_arch = "arm"),
29426 stable(feature = "neon_intrinsics", since = "1.59.0")
29427)]
29428#[cfg_attr(
29429 target_arch = "arm",
29430 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29431)]
29432pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
29433 vmlaq_f32(a, b, vdupq_n_f32(c))
29434}
29435#[doc = "Vector multiply accumulate with scalar"]
29436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"]
29437#[inline]
29438#[target_feature(enable = "neon")]
29439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29440#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29441#[cfg_attr(
29442 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29443 assert_instr(mla)
29444)]
29445#[cfg_attr(
29446 not(target_arch = "arm"),
29447 stable(feature = "neon_intrinsics", since = "1.59.0")
29448)]
29449#[cfg_attr(
29450 target_arch = "arm",
29451 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29452)]
29453pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
29454 vmla_s16(a, b, vdup_n_s16(c))
29455}
29456#[doc = "Vector multiply accumulate with scalar"]
29457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"]
29458#[inline]
29459#[target_feature(enable = "neon")]
29460#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29461#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29462#[cfg_attr(
29463 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29464 assert_instr(mla)
29465)]
29466#[cfg_attr(
29467 not(target_arch = "arm"),
29468 stable(feature = "neon_intrinsics", since = "1.59.0")
29469)]
29470#[cfg_attr(
29471 target_arch = "arm",
29472 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29473)]
29474pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
29475 vmlaq_s16(a, b, vdupq_n_s16(c))
29476}
29477#[doc = "Vector multiply accumulate with scalar"]
29478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"]
29479#[inline]
29480#[target_feature(enable = "neon")]
29481#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29482#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29483#[cfg_attr(
29484 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29485 assert_instr(mla)
29486)]
29487#[cfg_attr(
29488 not(target_arch = "arm"),
29489 stable(feature = "neon_intrinsics", since = "1.59.0")
29490)]
29491#[cfg_attr(
29492 target_arch = "arm",
29493 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29494)]
29495pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
29496 vmla_u16(a, b, vdup_n_u16(c))
29497}
29498#[doc = "Vector multiply accumulate with scalar"]
29499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"]
29500#[inline]
29501#[target_feature(enable = "neon")]
29502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29503#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29504#[cfg_attr(
29505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29506 assert_instr(mla)
29507)]
29508#[cfg_attr(
29509 not(target_arch = "arm"),
29510 stable(feature = "neon_intrinsics", since = "1.59.0")
29511)]
29512#[cfg_attr(
29513 target_arch = "arm",
29514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29515)]
29516pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
29517 vmlaq_u16(a, b, vdupq_n_u16(c))
29518}
29519#[doc = "Vector multiply accumulate with scalar"]
29520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"]
29521#[inline]
29522#[target_feature(enable = "neon")]
29523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29524#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29525#[cfg_attr(
29526 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29527 assert_instr(mla)
29528)]
29529#[cfg_attr(
29530 not(target_arch = "arm"),
29531 stable(feature = "neon_intrinsics", since = "1.59.0")
29532)]
29533#[cfg_attr(
29534 target_arch = "arm",
29535 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29536)]
29537pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
29538 vmla_s32(a, b, vdup_n_s32(c))
29539}
29540#[doc = "Vector multiply accumulate with scalar"]
29541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"]
29542#[inline]
29543#[target_feature(enable = "neon")]
29544#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29545#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29546#[cfg_attr(
29547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29548 assert_instr(mla)
29549)]
29550#[cfg_attr(
29551 not(target_arch = "arm"),
29552 stable(feature = "neon_intrinsics", since = "1.59.0")
29553)]
29554#[cfg_attr(
29555 target_arch = "arm",
29556 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29557)]
29558pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
29559 vmlaq_s32(a, b, vdupq_n_s32(c))
29560}
29561#[doc = "Vector multiply accumulate with scalar"]
29562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"]
29563#[inline]
29564#[target_feature(enable = "neon")]
29565#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29566#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29567#[cfg_attr(
29568 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29569 assert_instr(mla)
29570)]
29571#[cfg_attr(
29572 not(target_arch = "arm"),
29573 stable(feature = "neon_intrinsics", since = "1.59.0")
29574)]
29575#[cfg_attr(
29576 target_arch = "arm",
29577 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29578)]
29579pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
29580 vmla_u32(a, b, vdup_n_u32(c))
29581}
29582#[doc = "Vector multiply accumulate with scalar"]
29583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"]
29584#[inline]
29585#[target_feature(enable = "neon")]
29586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29587#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29588#[cfg_attr(
29589 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29590 assert_instr(mla)
29591)]
29592#[cfg_attr(
29593 not(target_arch = "arm"),
29594 stable(feature = "neon_intrinsics", since = "1.59.0")
29595)]
29596#[cfg_attr(
29597 target_arch = "arm",
29598 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29599)]
29600pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
29601 vmlaq_u32(a, b, vdupq_n_u32(c))
29602}
29603#[doc = "Multiply-add to accumulator"]
29604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"]
29605#[inline]
29606#[target_feature(enable = "neon")]
29607#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29608#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29609#[cfg_attr(
29610 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29611 assert_instr(mla)
29612)]
29613#[cfg_attr(
29614 not(target_arch = "arm"),
29615 stable(feature = "neon_intrinsics", since = "1.59.0")
29616)]
29617#[cfg_attr(
29618 target_arch = "arm",
29619 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29620)]
29621pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
29622 unsafe { simd_add(a, simd_mul(b, c)) }
29623}
29624#[doc = "Multiply-add to accumulator"]
29625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"]
29626#[inline]
29627#[target_feature(enable = "neon")]
29628#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29629#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29630#[cfg_attr(
29631 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29632 assert_instr(mla)
29633)]
29634#[cfg_attr(
29635 not(target_arch = "arm"),
29636 stable(feature = "neon_intrinsics", since = "1.59.0")
29637)]
29638#[cfg_attr(
29639 target_arch = "arm",
29640 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29641)]
29642pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
29643 unsafe { simd_add(a, simd_mul(b, c)) }
29644}
29645#[doc = "Multiply-add to accumulator"]
29646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"]
29647#[inline]
29648#[target_feature(enable = "neon")]
29649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29650#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29651#[cfg_attr(
29652 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29653 assert_instr(mla)
29654)]
29655#[cfg_attr(
29656 not(target_arch = "arm"),
29657 stable(feature = "neon_intrinsics", since = "1.59.0")
29658)]
29659#[cfg_attr(
29660 target_arch = "arm",
29661 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29662)]
29663pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
29664 unsafe { simd_add(a, simd_mul(b, c)) }
29665}
29666#[doc = "Multiply-add to accumulator"]
29667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"]
29668#[inline]
29669#[target_feature(enable = "neon")]
29670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29671#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29672#[cfg_attr(
29673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29674 assert_instr(mla)
29675)]
29676#[cfg_attr(
29677 not(target_arch = "arm"),
29678 stable(feature = "neon_intrinsics", since = "1.59.0")
29679)]
29680#[cfg_attr(
29681 target_arch = "arm",
29682 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29683)]
29684pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
29685 unsafe { simd_add(a, simd_mul(b, c)) }
29686}
29687#[doc = "Multiply-add to accumulator"]
29688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"]
29689#[inline]
29690#[target_feature(enable = "neon")]
29691#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29692#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29693#[cfg_attr(
29694 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29695 assert_instr(mla)
29696)]
29697#[cfg_attr(
29698 not(target_arch = "arm"),
29699 stable(feature = "neon_intrinsics", since = "1.59.0")
29700)]
29701#[cfg_attr(
29702 target_arch = "arm",
29703 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29704)]
29705pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
29706 unsafe { simd_add(a, simd_mul(b, c)) }
29707}
29708#[doc = "Multiply-add to accumulator"]
29709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"]
29710#[inline]
29711#[target_feature(enable = "neon")]
29712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29713#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29714#[cfg_attr(
29715 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29716 assert_instr(mla)
29717)]
29718#[cfg_attr(
29719 not(target_arch = "arm"),
29720 stable(feature = "neon_intrinsics", since = "1.59.0")
29721)]
29722#[cfg_attr(
29723 target_arch = "arm",
29724 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29725)]
29726pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
29727 unsafe { simd_add(a, simd_mul(b, c)) }
29728}
29729#[doc = "Multiply-add to accumulator"]
29730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"]
29731#[inline]
29732#[target_feature(enable = "neon")]
29733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29734#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29735#[cfg_attr(
29736 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29737 assert_instr(mla)
29738)]
29739#[cfg_attr(
29740 not(target_arch = "arm"),
29741 stable(feature = "neon_intrinsics", since = "1.59.0")
29742)]
29743#[cfg_attr(
29744 target_arch = "arm",
29745 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29746)]
29747pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
29748 unsafe { simd_add(a, simd_mul(b, c)) }
29749}
29750#[doc = "Multiply-add to accumulator"]
29751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"]
29752#[inline]
29753#[target_feature(enable = "neon")]
29754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29755#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29756#[cfg_attr(
29757 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29758 assert_instr(mla)
29759)]
29760#[cfg_attr(
29761 not(target_arch = "arm"),
29762 stable(feature = "neon_intrinsics", since = "1.59.0")
29763)]
29764#[cfg_attr(
29765 target_arch = "arm",
29766 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29767)]
29768pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
29769 unsafe { simd_add(a, simd_mul(b, c)) }
29770}
29771#[doc = "Multiply-add to accumulator"]
29772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"]
29773#[inline]
29774#[target_feature(enable = "neon")]
29775#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29776#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29777#[cfg_attr(
29778 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29779 assert_instr(mla)
29780)]
29781#[cfg_attr(
29782 not(target_arch = "arm"),
29783 stable(feature = "neon_intrinsics", since = "1.59.0")
29784)]
29785#[cfg_attr(
29786 target_arch = "arm",
29787 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29788)]
29789pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
29790 unsafe { simd_add(a, simd_mul(b, c)) }
29791}
29792#[doc = "Multiply-add to accumulator"]
29793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"]
29794#[inline]
29795#[target_feature(enable = "neon")]
29796#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29797#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29798#[cfg_attr(
29799 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29800 assert_instr(mla)
29801)]
29802#[cfg_attr(
29803 not(target_arch = "arm"),
29804 stable(feature = "neon_intrinsics", since = "1.59.0")
29805)]
29806#[cfg_attr(
29807 target_arch = "arm",
29808 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29809)]
29810pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
29811 unsafe { simd_add(a, simd_mul(b, c)) }
29812}
29813#[doc = "Multiply-add to accumulator"]
29814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"]
29815#[inline]
29816#[target_feature(enable = "neon")]
29817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29818#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29819#[cfg_attr(
29820 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29821 assert_instr(mla)
29822)]
29823#[cfg_attr(
29824 not(target_arch = "arm"),
29825 stable(feature = "neon_intrinsics", since = "1.59.0")
29826)]
29827#[cfg_attr(
29828 target_arch = "arm",
29829 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29830)]
29831pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
29832 unsafe { simd_add(a, simd_mul(b, c)) }
29833}
29834#[doc = "Multiply-add to accumulator"]
29835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"]
29836#[inline]
29837#[target_feature(enable = "neon")]
29838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29839#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29840#[cfg_attr(
29841 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29842 assert_instr(mla)
29843)]
29844#[cfg_attr(
29845 not(target_arch = "arm"),
29846 stable(feature = "neon_intrinsics", since = "1.59.0")
29847)]
29848#[cfg_attr(
29849 target_arch = "arm",
29850 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29851)]
29852pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
29853 unsafe { simd_add(a, simd_mul(b, c)) }
29854}
29855#[doc = "Vector widening multiply accumulate with scalar"]
29856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"]
29857#[inline]
29858#[target_feature(enable = "neon")]
29859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29860#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
29861#[cfg_attr(
29862 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29863 assert_instr(smlal, LANE = 1)
29864)]
29865#[rustc_legacy_const_generics(3)]
29866#[cfg_attr(
29867 not(target_arch = "arm"),
29868 stable(feature = "neon_intrinsics", since = "1.59.0")
29869)]
29870#[cfg_attr(
29871 target_arch = "arm",
29872 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29873)]
29874pub fn vmlal_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
29875 static_assert_uimm_bits!(LANE, 2);
29876 unsafe {
29877 vmlal_s16(
29878 a,
29879 b,
29880 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29881 )
29882 }
29883}
29884#[doc = "Vector widening multiply accumulate with scalar"]
29885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"]
29886#[inline]
29887#[target_feature(enable = "neon")]
29888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29889#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
29890#[cfg_attr(
29891 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29892 assert_instr(smlal, LANE = 1)
29893)]
29894#[rustc_legacy_const_generics(3)]
29895#[cfg_attr(
29896 not(target_arch = "arm"),
29897 stable(feature = "neon_intrinsics", since = "1.59.0")
29898)]
29899#[cfg_attr(
29900 target_arch = "arm",
29901 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29902)]
29903pub fn vmlal_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
29904 static_assert_uimm_bits!(LANE, 3);
29905 unsafe {
29906 vmlal_s16(
29907 a,
29908 b,
29909 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29910 )
29911 }
29912}
29913#[doc = "Vector widening multiply accumulate with scalar"]
29914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"]
29915#[inline]
29916#[target_feature(enable = "neon")]
29917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29918#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
29919#[cfg_attr(
29920 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29921 assert_instr(smlal, LANE = 1)
29922)]
29923#[rustc_legacy_const_generics(3)]
29924#[cfg_attr(
29925 not(target_arch = "arm"),
29926 stable(feature = "neon_intrinsics", since = "1.59.0")
29927)]
29928#[cfg_attr(
29929 target_arch = "arm",
29930 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29931)]
29932pub fn vmlal_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
29933 static_assert_uimm_bits!(LANE, 1);
29934 unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29935}
29936#[doc = "Vector widening multiply accumulate with scalar"]
29937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"]
29938#[inline]
29939#[target_feature(enable = "neon")]
29940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29941#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
29942#[cfg_attr(
29943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29944 assert_instr(smlal, LANE = 1)
29945)]
29946#[rustc_legacy_const_generics(3)]
29947#[cfg_attr(
29948 not(target_arch = "arm"),
29949 stable(feature = "neon_intrinsics", since = "1.59.0")
29950)]
29951#[cfg_attr(
29952 target_arch = "arm",
29953 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29954)]
29955pub fn vmlal_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
29956 static_assert_uimm_bits!(LANE, 2);
29957 unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29958}
29959#[doc = "Vector widening multiply accumulate with scalar"]
29960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"]
29961#[inline]
29962#[target_feature(enable = "neon")]
29963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29964#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
29965#[cfg_attr(
29966 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29967 assert_instr(umlal, LANE = 1)
29968)]
29969#[rustc_legacy_const_generics(3)]
29970#[cfg_attr(
29971 not(target_arch = "arm"),
29972 stable(feature = "neon_intrinsics", since = "1.59.0")
29973)]
29974#[cfg_attr(
29975 target_arch = "arm",
29976 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29977)]
29978pub fn vmlal_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
29979 static_assert_uimm_bits!(LANE, 2);
29980 unsafe {
29981 vmlal_u16(
29982 a,
29983 b,
29984 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29985 )
29986 }
29987}
29988#[doc = "Vector widening multiply accumulate with scalar"]
29989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"]
29990#[inline]
29991#[target_feature(enable = "neon")]
29992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29993#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
29994#[cfg_attr(
29995 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29996 assert_instr(umlal, LANE = 1)
29997)]
29998#[rustc_legacy_const_generics(3)]
29999#[cfg_attr(
30000 not(target_arch = "arm"),
30001 stable(feature = "neon_intrinsics", since = "1.59.0")
30002)]
30003#[cfg_attr(
30004 target_arch = "arm",
30005 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30006)]
30007pub fn vmlal_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
30008 static_assert_uimm_bits!(LANE, 3);
30009 unsafe {
30010 vmlal_u16(
30011 a,
30012 b,
30013 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30014 )
30015 }
30016}
30017#[doc = "Vector widening multiply accumulate with scalar"]
30018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"]
30019#[inline]
30020#[target_feature(enable = "neon")]
30021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30022#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
30023#[cfg_attr(
30024 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30025 assert_instr(umlal, LANE = 1)
30026)]
30027#[rustc_legacy_const_generics(3)]
30028#[cfg_attr(
30029 not(target_arch = "arm"),
30030 stable(feature = "neon_intrinsics", since = "1.59.0")
30031)]
30032#[cfg_attr(
30033 target_arch = "arm",
30034 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30035)]
30036pub fn vmlal_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
30037 static_assert_uimm_bits!(LANE, 1);
30038 unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30039}
30040#[doc = "Vector widening multiply accumulate with scalar"]
30041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"]
30042#[inline]
30043#[target_feature(enable = "neon")]
30044#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30045#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
30046#[cfg_attr(
30047 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30048 assert_instr(umlal, LANE = 1)
30049)]
30050#[rustc_legacy_const_generics(3)]
30051#[cfg_attr(
30052 not(target_arch = "arm"),
30053 stable(feature = "neon_intrinsics", since = "1.59.0")
30054)]
30055#[cfg_attr(
30056 target_arch = "arm",
30057 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30058)]
30059pub fn vmlal_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
30060 static_assert_uimm_bits!(LANE, 2);
30061 unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30062}
30063#[doc = "Vector widening multiply accumulate with scalar"]
30064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"]
30065#[inline]
30066#[target_feature(enable = "neon")]
30067#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30068#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
30069#[cfg_attr(
30070 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30071 assert_instr(smlal)
30072)]
30073#[cfg_attr(
30074 not(target_arch = "arm"),
30075 stable(feature = "neon_intrinsics", since = "1.59.0")
30076)]
30077#[cfg_attr(
30078 target_arch = "arm",
30079 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30080)]
30081pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
30082 vmlal_s16(a, b, vdup_n_s16(c))
30083}
30084#[doc = "Vector widening multiply accumulate with scalar"]
30085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"]
30086#[inline]
30087#[target_feature(enable = "neon")]
30088#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30089#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
30090#[cfg_attr(
30091 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30092 assert_instr(smlal)
30093)]
30094#[cfg_attr(
30095 not(target_arch = "arm"),
30096 stable(feature = "neon_intrinsics", since = "1.59.0")
30097)]
30098#[cfg_attr(
30099 target_arch = "arm",
30100 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30101)]
30102pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
30103 vmlal_s32(a, b, vdup_n_s32(c))
30104}
30105#[doc = "Vector widening multiply accumulate with scalar"]
30106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"]
30107#[inline]
30108#[target_feature(enable = "neon")]
30109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30110#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
30111#[cfg_attr(
30112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30113 assert_instr(umlal)
30114)]
30115#[cfg_attr(
30116 not(target_arch = "arm"),
30117 stable(feature = "neon_intrinsics", since = "1.59.0")
30118)]
30119#[cfg_attr(
30120 target_arch = "arm",
30121 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30122)]
30123pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
30124 vmlal_u16(a, b, vdup_n_u16(c))
30125}
30126#[doc = "Vector widening multiply accumulate with scalar"]
30127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"]
30128#[inline]
30129#[target_feature(enable = "neon")]
30130#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30131#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
30132#[cfg_attr(
30133 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30134 assert_instr(umlal)
30135)]
30136#[cfg_attr(
30137 not(target_arch = "arm"),
30138 stable(feature = "neon_intrinsics", since = "1.59.0")
30139)]
30140#[cfg_attr(
30141 target_arch = "arm",
30142 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30143)]
30144pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
30145 vmlal_u32(a, b, vdup_n_u32(c))
30146}
30147#[doc = "Signed multiply-add long"]
30148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"]
30149#[inline]
30150#[target_feature(enable = "neon")]
30151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30152#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))]
30153#[cfg_attr(
30154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30155 assert_instr(smlal)
30156)]
30157#[cfg_attr(
30158 not(target_arch = "arm"),
30159 stable(feature = "neon_intrinsics", since = "1.59.0")
30160)]
30161#[cfg_attr(
30162 target_arch = "arm",
30163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30164)]
30165pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
30166 unsafe { simd_add(a, vmull_s8(b, c)) }
30167}
30168#[doc = "Signed multiply-add long"]
30169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"]
30170#[inline]
30171#[target_feature(enable = "neon")]
30172#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30173#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
30174#[cfg_attr(
30175 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30176 assert_instr(smlal)
30177)]
30178#[cfg_attr(
30179 not(target_arch = "arm"),
30180 stable(feature = "neon_intrinsics", since = "1.59.0")
30181)]
30182#[cfg_attr(
30183 target_arch = "arm",
30184 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30185)]
30186pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
30187 unsafe { simd_add(a, vmull_s16(b, c)) }
30188}
30189#[doc = "Signed multiply-add long"]
30190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"]
30191#[inline]
30192#[target_feature(enable = "neon")]
30193#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30194#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
30195#[cfg_attr(
30196 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30197 assert_instr(smlal)
30198)]
30199#[cfg_attr(
30200 not(target_arch = "arm"),
30201 stable(feature = "neon_intrinsics", since = "1.59.0")
30202)]
30203#[cfg_attr(
30204 target_arch = "arm",
30205 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30206)]
30207pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
30208 unsafe { simd_add(a, vmull_s32(b, c)) }
30209}
30210#[doc = "Unsigned multiply-add long"]
30211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"]
30212#[inline]
30213#[target_feature(enable = "neon")]
30214#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30215#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))]
30216#[cfg_attr(
30217 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30218 assert_instr(umlal)
30219)]
30220#[cfg_attr(
30221 not(target_arch = "arm"),
30222 stable(feature = "neon_intrinsics", since = "1.59.0")
30223)]
30224#[cfg_attr(
30225 target_arch = "arm",
30226 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30227)]
30228pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
30229 unsafe { simd_add(a, vmull_u8(b, c)) }
30230}
30231#[doc = "Unsigned multiply-add long"]
30232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"]
30233#[inline]
30234#[target_feature(enable = "neon")]
30235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30236#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
30237#[cfg_attr(
30238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30239 assert_instr(umlal)
30240)]
30241#[cfg_attr(
30242 not(target_arch = "arm"),
30243 stable(feature = "neon_intrinsics", since = "1.59.0")
30244)]
30245#[cfg_attr(
30246 target_arch = "arm",
30247 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30248)]
30249pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
30250 unsafe { simd_add(a, vmull_u16(b, c)) }
30251}
30252#[doc = "Unsigned multiply-add long"]
30253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"]
30254#[inline]
30255#[target_feature(enable = "neon")]
30256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30257#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
30258#[cfg_attr(
30259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30260 assert_instr(umlal)
30261)]
30262#[cfg_attr(
30263 not(target_arch = "arm"),
30264 stable(feature = "neon_intrinsics", since = "1.59.0")
30265)]
30266#[cfg_attr(
30267 target_arch = "arm",
30268 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30269)]
30270pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
30271 unsafe { simd_add(a, vmull_u32(b, c)) }
30272}
30273#[doc = "Floating-point multiply-subtract from accumulator"]
30274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"]
30275#[inline]
30276#[target_feature(enable = "neon")]
30277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30278#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30279#[cfg_attr(
30280 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30281 assert_instr(fmul)
30282)]
30283#[cfg_attr(
30284 not(target_arch = "arm"),
30285 stable(feature = "neon_intrinsics", since = "1.59.0")
30286)]
30287#[cfg_attr(
30288 target_arch = "arm",
30289 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30290)]
30291pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
30292 unsafe { simd_sub(a, simd_mul(b, c)) }
30293}
30294#[doc = "Floating-point multiply-subtract from accumulator"]
30295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"]
30296#[inline]
30297#[target_feature(enable = "neon")]
30298#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30299#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30300#[cfg_attr(
30301 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30302 assert_instr(fmul)
30303)]
30304#[cfg_attr(
30305 not(target_arch = "arm"),
30306 stable(feature = "neon_intrinsics", since = "1.59.0")
30307)]
30308#[cfg_attr(
30309 target_arch = "arm",
30310 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30311)]
30312pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
30313 unsafe { simd_sub(a, simd_mul(b, c)) }
30314}
30315#[doc = "Vector multiply subtract with scalar"]
30316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"]
30317#[inline]
30318#[target_feature(enable = "neon")]
30319#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30320#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30321#[cfg_attr(
30322 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30323 assert_instr(fmul, LANE = 1)
30324)]
30325#[rustc_legacy_const_generics(3)]
30326#[cfg_attr(
30327 not(target_arch = "arm"),
30328 stable(feature = "neon_intrinsics", since = "1.59.0")
30329)]
30330#[cfg_attr(
30331 target_arch = "arm",
30332 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30333)]
30334pub fn vmls_lane_f32<const LANE: i32>(
30335 a: float32x2_t,
30336 b: float32x2_t,
30337 c: float32x2_t,
30338) -> float32x2_t {
30339 static_assert_uimm_bits!(LANE, 1);
30340 unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30341}
30342#[doc = "Vector multiply subtract with scalar"]
30343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"]
30344#[inline]
30345#[target_feature(enable = "neon")]
30346#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30347#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30348#[cfg_attr(
30349 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30350 assert_instr(fmul, LANE = 1)
30351)]
30352#[rustc_legacy_const_generics(3)]
30353#[cfg_attr(
30354 not(target_arch = "arm"),
30355 stable(feature = "neon_intrinsics", since = "1.59.0")
30356)]
30357#[cfg_attr(
30358 target_arch = "arm",
30359 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30360)]
30361pub fn vmls_laneq_f32<const LANE: i32>(
30362 a: float32x2_t,
30363 b: float32x2_t,
30364 c: float32x4_t,
30365) -> float32x2_t {
30366 static_assert_uimm_bits!(LANE, 2);
30367 unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30368}
30369#[doc = "Vector multiply subtract with scalar"]
30370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"]
30371#[inline]
30372#[target_feature(enable = "neon")]
30373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30374#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30375#[cfg_attr(
30376 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30377 assert_instr(fmul, LANE = 1)
30378)]
30379#[rustc_legacy_const_generics(3)]
30380#[cfg_attr(
30381 not(target_arch = "arm"),
30382 stable(feature = "neon_intrinsics", since = "1.59.0")
30383)]
30384#[cfg_attr(
30385 target_arch = "arm",
30386 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30387)]
30388pub fn vmlsq_lane_f32<const LANE: i32>(
30389 a: float32x4_t,
30390 b: float32x4_t,
30391 c: float32x2_t,
30392) -> float32x4_t {
30393 static_assert_uimm_bits!(LANE, 1);
30394 unsafe {
30395 vmlsq_f32(
30396 a,
30397 b,
30398 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30399 )
30400 }
30401}
30402#[doc = "Vector multiply subtract with scalar"]
30403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"]
30404#[inline]
30405#[target_feature(enable = "neon")]
30406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30407#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30408#[cfg_attr(
30409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30410 assert_instr(fmul, LANE = 1)
30411)]
30412#[rustc_legacy_const_generics(3)]
30413#[cfg_attr(
30414 not(target_arch = "arm"),
30415 stable(feature = "neon_intrinsics", since = "1.59.0")
30416)]
30417#[cfg_attr(
30418 target_arch = "arm",
30419 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30420)]
30421pub fn vmlsq_laneq_f32<const LANE: i32>(
30422 a: float32x4_t,
30423 b: float32x4_t,
30424 c: float32x4_t,
30425) -> float32x4_t {
30426 static_assert_uimm_bits!(LANE, 2);
30427 unsafe {
30428 vmlsq_f32(
30429 a,
30430 b,
30431 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30432 )
30433 }
30434}
30435#[doc = "Vector multiply subtract with scalar"]
30436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"]
30437#[inline]
30438#[target_feature(enable = "neon")]
30439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30440#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30441#[cfg_attr(
30442 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30443 assert_instr(mls, LANE = 1)
30444)]
30445#[rustc_legacy_const_generics(3)]
30446#[cfg_attr(
30447 not(target_arch = "arm"),
30448 stable(feature = "neon_intrinsics", since = "1.59.0")
30449)]
30450#[cfg_attr(
30451 target_arch = "arm",
30452 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30453)]
30454pub fn vmls_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
30455 static_assert_uimm_bits!(LANE, 2);
30456 unsafe {
30457 vmls_s16(
30458 a,
30459 b,
30460 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30461 )
30462 }
30463}
30464#[doc = "Vector multiply subtract with scalar"]
30465#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"]
30466#[inline]
30467#[target_feature(enable = "neon")]
30468#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30469#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30470#[cfg_attr(
30471 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30472 assert_instr(mls, LANE = 1)
30473)]
30474#[rustc_legacy_const_generics(3)]
30475#[cfg_attr(
30476 not(target_arch = "arm"),
30477 stable(feature = "neon_intrinsics", since = "1.59.0")
30478)]
30479#[cfg_attr(
30480 target_arch = "arm",
30481 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30482)]
30483pub fn vmls_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
30484 static_assert_uimm_bits!(LANE, 2);
30485 unsafe {
30486 vmls_u16(
30487 a,
30488 b,
30489 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30490 )
30491 }
30492}
30493#[doc = "Vector multiply subtract with scalar"]
30494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"]
30495#[inline]
30496#[target_feature(enable = "neon")]
30497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30498#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30499#[cfg_attr(
30500 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30501 assert_instr(mls, LANE = 1)
30502)]
30503#[rustc_legacy_const_generics(3)]
30504#[cfg_attr(
30505 not(target_arch = "arm"),
30506 stable(feature = "neon_intrinsics", since = "1.59.0")
30507)]
30508#[cfg_attr(
30509 target_arch = "arm",
30510 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30511)]
30512pub fn vmls_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
30513 static_assert_uimm_bits!(LANE, 3);
30514 unsafe {
30515 vmls_s16(
30516 a,
30517 b,
30518 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30519 )
30520 }
30521}
30522#[doc = "Vector multiply subtract with scalar"]
30523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"]
30524#[inline]
30525#[target_feature(enable = "neon")]
30526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30527#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30528#[cfg_attr(
30529 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30530 assert_instr(mls, LANE = 1)
30531)]
30532#[rustc_legacy_const_generics(3)]
30533#[cfg_attr(
30534 not(target_arch = "arm"),
30535 stable(feature = "neon_intrinsics", since = "1.59.0")
30536)]
30537#[cfg_attr(
30538 target_arch = "arm",
30539 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30540)]
30541pub fn vmls_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
30542 static_assert_uimm_bits!(LANE, 3);
30543 unsafe {
30544 vmls_u16(
30545 a,
30546 b,
30547 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30548 )
30549 }
30550}
30551#[doc = "Vector multiply subtract with scalar"]
30552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"]
30553#[inline]
30554#[target_feature(enable = "neon")]
30555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30556#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30557#[cfg_attr(
30558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30559 assert_instr(mls, LANE = 1)
30560)]
30561#[rustc_legacy_const_generics(3)]
30562#[cfg_attr(
30563 not(target_arch = "arm"),
30564 stable(feature = "neon_intrinsics", since = "1.59.0")
30565)]
30566#[cfg_attr(
30567 target_arch = "arm",
30568 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30569)]
30570pub fn vmlsq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
30571 static_assert_uimm_bits!(LANE, 2);
30572 unsafe {
30573 vmlsq_s16(
30574 a,
30575 b,
30576 simd_shuffle!(
30577 c,
30578 c,
30579 [
30580 LANE as u32,
30581 LANE as u32,
30582 LANE as u32,
30583 LANE as u32,
30584 LANE as u32,
30585 LANE as u32,
30586 LANE as u32,
30587 LANE as u32
30588 ]
30589 ),
30590 )
30591 }
30592}
30593#[doc = "Vector multiply subtract with scalar"]
30594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"]
30595#[inline]
30596#[target_feature(enable = "neon")]
30597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30598#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30599#[cfg_attr(
30600 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30601 assert_instr(mls, LANE = 1)
30602)]
30603#[rustc_legacy_const_generics(3)]
30604#[cfg_attr(
30605 not(target_arch = "arm"),
30606 stable(feature = "neon_intrinsics", since = "1.59.0")
30607)]
30608#[cfg_attr(
30609 target_arch = "arm",
30610 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30611)]
30612pub fn vmlsq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
30613 static_assert_uimm_bits!(LANE, 2);
30614 unsafe {
30615 vmlsq_u16(
30616 a,
30617 b,
30618 simd_shuffle!(
30619 c,
30620 c,
30621 [
30622 LANE as u32,
30623 LANE as u32,
30624 LANE as u32,
30625 LANE as u32,
30626 LANE as u32,
30627 LANE as u32,
30628 LANE as u32,
30629 LANE as u32
30630 ]
30631 ),
30632 )
30633 }
30634}
30635#[doc = "Vector multiply subtract with scalar"]
30636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"]
30637#[inline]
30638#[target_feature(enable = "neon")]
30639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30640#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30641#[cfg_attr(
30642 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30643 assert_instr(mls, LANE = 1)
30644)]
30645#[rustc_legacy_const_generics(3)]
30646#[cfg_attr(
30647 not(target_arch = "arm"),
30648 stable(feature = "neon_intrinsics", since = "1.59.0")
30649)]
30650#[cfg_attr(
30651 target_arch = "arm",
30652 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30653)]
30654pub fn vmlsq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
30655 static_assert_uimm_bits!(LANE, 3);
30656 unsafe {
30657 vmlsq_s16(
30658 a,
30659 b,
30660 simd_shuffle!(
30661 c,
30662 c,
30663 [
30664 LANE as u32,
30665 LANE as u32,
30666 LANE as u32,
30667 LANE as u32,
30668 LANE as u32,
30669 LANE as u32,
30670 LANE as u32,
30671 LANE as u32
30672 ]
30673 ),
30674 )
30675 }
30676}
30677#[doc = "Vector multiply subtract with scalar"]
30678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"]
30679#[inline]
30680#[target_feature(enable = "neon")]
30681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30682#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30683#[cfg_attr(
30684 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30685 assert_instr(mls, LANE = 1)
30686)]
30687#[rustc_legacy_const_generics(3)]
30688#[cfg_attr(
30689 not(target_arch = "arm"),
30690 stable(feature = "neon_intrinsics", since = "1.59.0")
30691)]
30692#[cfg_attr(
30693 target_arch = "arm",
30694 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30695)]
30696pub fn vmlsq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
30697 static_assert_uimm_bits!(LANE, 3);
30698 unsafe {
30699 vmlsq_u16(
30700 a,
30701 b,
30702 simd_shuffle!(
30703 c,
30704 c,
30705 [
30706 LANE as u32,
30707 LANE as u32,
30708 LANE as u32,
30709 LANE as u32,
30710 LANE as u32,
30711 LANE as u32,
30712 LANE as u32,
30713 LANE as u32
30714 ]
30715 ),
30716 )
30717 }
30718}
30719#[doc = "Vector multiply subtract with scalar"]
30720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"]
30721#[inline]
30722#[target_feature(enable = "neon")]
30723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30724#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30725#[cfg_attr(
30726 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30727 assert_instr(mls, LANE = 1)
30728)]
30729#[rustc_legacy_const_generics(3)]
30730#[cfg_attr(
30731 not(target_arch = "arm"),
30732 stable(feature = "neon_intrinsics", since = "1.59.0")
30733)]
30734#[cfg_attr(
30735 target_arch = "arm",
30736 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30737)]
30738pub fn vmls_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
30739 static_assert_uimm_bits!(LANE, 1);
30740 unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30741}
30742#[doc = "Vector multiply subtract with scalar"]
30743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"]
30744#[inline]
30745#[target_feature(enable = "neon")]
30746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30747#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30748#[cfg_attr(
30749 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30750 assert_instr(mls, LANE = 1)
30751)]
30752#[rustc_legacy_const_generics(3)]
30753#[cfg_attr(
30754 not(target_arch = "arm"),
30755 stable(feature = "neon_intrinsics", since = "1.59.0")
30756)]
30757#[cfg_attr(
30758 target_arch = "arm",
30759 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30760)]
30761pub fn vmls_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
30762 static_assert_uimm_bits!(LANE, 1);
30763 unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30764}
30765#[doc = "Vector multiply subtract with scalar"]
30766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"]
30767#[inline]
30768#[target_feature(enable = "neon")]
30769#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30770#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30771#[cfg_attr(
30772 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30773 assert_instr(mls, LANE = 1)
30774)]
30775#[rustc_legacy_const_generics(3)]
30776#[cfg_attr(
30777 not(target_arch = "arm"),
30778 stable(feature = "neon_intrinsics", since = "1.59.0")
30779)]
30780#[cfg_attr(
30781 target_arch = "arm",
30782 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30783)]
30784pub fn vmls_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
30785 static_assert_uimm_bits!(LANE, 2);
30786 unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30787}
30788#[doc = "Vector multiply subtract with scalar"]
30789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"]
30790#[inline]
30791#[target_feature(enable = "neon")]
30792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30793#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30794#[cfg_attr(
30795 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30796 assert_instr(mls, LANE = 1)
30797)]
30798#[rustc_legacy_const_generics(3)]
30799#[cfg_attr(
30800 not(target_arch = "arm"),
30801 stable(feature = "neon_intrinsics", since = "1.59.0")
30802)]
30803#[cfg_attr(
30804 target_arch = "arm",
30805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30806)]
30807pub fn vmls_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
30808 static_assert_uimm_bits!(LANE, 2);
30809 unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30810}
30811#[doc = "Vector multiply subtract with scalar"]
30812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"]
30813#[inline]
30814#[target_feature(enable = "neon")]
30815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30816#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30817#[cfg_attr(
30818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30819 assert_instr(mls, LANE = 1)
30820)]
30821#[rustc_legacy_const_generics(3)]
30822#[cfg_attr(
30823 not(target_arch = "arm"),
30824 stable(feature = "neon_intrinsics", since = "1.59.0")
30825)]
30826#[cfg_attr(
30827 target_arch = "arm",
30828 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30829)]
30830pub fn vmlsq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
30831 static_assert_uimm_bits!(LANE, 1);
30832 unsafe {
30833 vmlsq_s32(
30834 a,
30835 b,
30836 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30837 )
30838 }
30839}
30840#[doc = "Vector multiply subtract with scalar"]
30841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"]
30842#[inline]
30843#[target_feature(enable = "neon")]
30844#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30845#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30846#[cfg_attr(
30847 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30848 assert_instr(mls, LANE = 1)
30849)]
30850#[rustc_legacy_const_generics(3)]
30851#[cfg_attr(
30852 not(target_arch = "arm"),
30853 stable(feature = "neon_intrinsics", since = "1.59.0")
30854)]
30855#[cfg_attr(
30856 target_arch = "arm",
30857 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30858)]
30859pub fn vmlsq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
30860 static_assert_uimm_bits!(LANE, 1);
30861 unsafe {
30862 vmlsq_u32(
30863 a,
30864 b,
30865 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30866 )
30867 }
30868}
30869#[doc = "Vector multiply subtract with scalar"]
30870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"]
30871#[inline]
30872#[target_feature(enable = "neon")]
30873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30874#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30875#[cfg_attr(
30876 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30877 assert_instr(mls, LANE = 1)
30878)]
30879#[rustc_legacy_const_generics(3)]
30880#[cfg_attr(
30881 not(target_arch = "arm"),
30882 stable(feature = "neon_intrinsics", since = "1.59.0")
30883)]
30884#[cfg_attr(
30885 target_arch = "arm",
30886 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30887)]
30888pub fn vmlsq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
30889 static_assert_uimm_bits!(LANE, 2);
30890 unsafe {
30891 vmlsq_s32(
30892 a,
30893 b,
30894 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30895 )
30896 }
30897}
30898#[doc = "Vector multiply subtract with scalar"]
30899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"]
30900#[inline]
30901#[target_feature(enable = "neon")]
30902#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30903#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30904#[cfg_attr(
30905 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30906 assert_instr(mls, LANE = 1)
30907)]
30908#[rustc_legacy_const_generics(3)]
30909#[cfg_attr(
30910 not(target_arch = "arm"),
30911 stable(feature = "neon_intrinsics", since = "1.59.0")
30912)]
30913#[cfg_attr(
30914 target_arch = "arm",
30915 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30916)]
30917pub fn vmlsq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
30918 static_assert_uimm_bits!(LANE, 2);
30919 unsafe {
30920 vmlsq_u32(
30921 a,
30922 b,
30923 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30924 )
30925 }
30926}
30927#[doc = "Vector multiply subtract with scalar"]
30928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"]
30929#[inline]
30930#[target_feature(enable = "neon")]
30931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30932#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30933#[cfg_attr(
30934 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30935 assert_instr(fmul)
30936)]
30937#[cfg_attr(
30938 not(target_arch = "arm"),
30939 stable(feature = "neon_intrinsics", since = "1.59.0")
30940)]
30941#[cfg_attr(
30942 target_arch = "arm",
30943 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30944)]
30945pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
30946 vmls_f32(a, b, vdup_n_f32(c))
30947}
30948#[doc = "Vector multiply subtract with scalar"]
30949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"]
30950#[inline]
30951#[target_feature(enable = "neon")]
30952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30953#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30954#[cfg_attr(
30955 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30956 assert_instr(fmul)
30957)]
30958#[cfg_attr(
30959 not(target_arch = "arm"),
30960 stable(feature = "neon_intrinsics", since = "1.59.0")
30961)]
30962#[cfg_attr(
30963 target_arch = "arm",
30964 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30965)]
30966pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
30967 vmlsq_f32(a, b, vdupq_n_f32(c))
30968}
30969#[doc = "Vector multiply subtract with scalar"]
30970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"]
30971#[inline]
30972#[target_feature(enable = "neon")]
30973#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30974#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30975#[cfg_attr(
30976 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30977 assert_instr(mls)
30978)]
30979#[cfg_attr(
30980 not(target_arch = "arm"),
30981 stable(feature = "neon_intrinsics", since = "1.59.0")
30982)]
30983#[cfg_attr(
30984 target_arch = "arm",
30985 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30986)]
30987pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
30988 vmls_s16(a, b, vdup_n_s16(c))
30989}
30990#[doc = "Vector multiply subtract with scalar"]
30991#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"]
30992#[inline]
30993#[target_feature(enable = "neon")]
30994#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30995#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30996#[cfg_attr(
30997 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30998 assert_instr(mls)
30999)]
31000#[cfg_attr(
31001 not(target_arch = "arm"),
31002 stable(feature = "neon_intrinsics", since = "1.59.0")
31003)]
31004#[cfg_attr(
31005 target_arch = "arm",
31006 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31007)]
31008pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
31009 vmlsq_s16(a, b, vdupq_n_s16(c))
31010}
31011#[doc = "Vector multiply subtract with scalar"]
31012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"]
31013#[inline]
31014#[target_feature(enable = "neon")]
31015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31016#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31017#[cfg_attr(
31018 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31019 assert_instr(mls)
31020)]
31021#[cfg_attr(
31022 not(target_arch = "arm"),
31023 stable(feature = "neon_intrinsics", since = "1.59.0")
31024)]
31025#[cfg_attr(
31026 target_arch = "arm",
31027 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31028)]
31029pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
31030 vmls_u16(a, b, vdup_n_u16(c))
31031}
31032#[doc = "Vector multiply subtract with scalar"]
31033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"]
31034#[inline]
31035#[target_feature(enable = "neon")]
31036#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31037#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31038#[cfg_attr(
31039 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31040 assert_instr(mls)
31041)]
31042#[cfg_attr(
31043 not(target_arch = "arm"),
31044 stable(feature = "neon_intrinsics", since = "1.59.0")
31045)]
31046#[cfg_attr(
31047 target_arch = "arm",
31048 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31049)]
31050pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
31051 vmlsq_u16(a, b, vdupq_n_u16(c))
31052}
31053#[doc = "Vector multiply subtract with scalar"]
31054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"]
31055#[inline]
31056#[target_feature(enable = "neon")]
31057#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31058#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31059#[cfg_attr(
31060 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31061 assert_instr(mls)
31062)]
31063#[cfg_attr(
31064 not(target_arch = "arm"),
31065 stable(feature = "neon_intrinsics", since = "1.59.0")
31066)]
31067#[cfg_attr(
31068 target_arch = "arm",
31069 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31070)]
31071pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
31072 vmls_s32(a, b, vdup_n_s32(c))
31073}
31074#[doc = "Vector multiply subtract with scalar"]
31075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"]
31076#[inline]
31077#[target_feature(enable = "neon")]
31078#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31079#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31080#[cfg_attr(
31081 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31082 assert_instr(mls)
31083)]
31084#[cfg_attr(
31085 not(target_arch = "arm"),
31086 stable(feature = "neon_intrinsics", since = "1.59.0")
31087)]
31088#[cfg_attr(
31089 target_arch = "arm",
31090 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31091)]
31092pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
31093 vmlsq_s32(a, b, vdupq_n_s32(c))
31094}
31095#[doc = "Vector multiply subtract with scalar"]
31096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"]
31097#[inline]
31098#[target_feature(enable = "neon")]
31099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31100#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31101#[cfg_attr(
31102 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31103 assert_instr(mls)
31104)]
31105#[cfg_attr(
31106 not(target_arch = "arm"),
31107 stable(feature = "neon_intrinsics", since = "1.59.0")
31108)]
31109#[cfg_attr(
31110 target_arch = "arm",
31111 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31112)]
31113pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
31114 vmls_u32(a, b, vdup_n_u32(c))
31115}
31116#[doc = "Vector multiply subtract with scalar"]
31117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"]
31118#[inline]
31119#[target_feature(enable = "neon")]
31120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31121#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31122#[cfg_attr(
31123 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31124 assert_instr(mls)
31125)]
31126#[cfg_attr(
31127 not(target_arch = "arm"),
31128 stable(feature = "neon_intrinsics", since = "1.59.0")
31129)]
31130#[cfg_attr(
31131 target_arch = "arm",
31132 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31133)]
31134pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
31135 vmlsq_u32(a, b, vdupq_n_u32(c))
31136}
31137#[doc = "Multiply-subtract from accumulator"]
31138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"]
31139#[inline]
31140#[target_feature(enable = "neon")]
31141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31142#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31143#[cfg_attr(
31144 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31145 assert_instr(mls)
31146)]
31147#[cfg_attr(
31148 not(target_arch = "arm"),
31149 stable(feature = "neon_intrinsics", since = "1.59.0")
31150)]
31151#[cfg_attr(
31152 target_arch = "arm",
31153 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31154)]
31155pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
31156 unsafe { simd_sub(a, simd_mul(b, c)) }
31157}
31158#[doc = "Multiply-subtract from accumulator"]
31159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"]
31160#[inline]
31161#[target_feature(enable = "neon")]
31162#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31163#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31164#[cfg_attr(
31165 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31166 assert_instr(mls)
31167)]
31168#[cfg_attr(
31169 not(target_arch = "arm"),
31170 stable(feature = "neon_intrinsics", since = "1.59.0")
31171)]
31172#[cfg_attr(
31173 target_arch = "arm",
31174 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31175)]
31176pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
31177 unsafe { simd_sub(a, simd_mul(b, c)) }
31178}
31179#[doc = "Multiply-subtract from accumulator"]
31180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"]
31181#[inline]
31182#[target_feature(enable = "neon")]
31183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31184#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31185#[cfg_attr(
31186 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31187 assert_instr(mls)
31188)]
31189#[cfg_attr(
31190 not(target_arch = "arm"),
31191 stable(feature = "neon_intrinsics", since = "1.59.0")
31192)]
31193#[cfg_attr(
31194 target_arch = "arm",
31195 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31196)]
31197pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
31198 unsafe { simd_sub(a, simd_mul(b, c)) }
31199}
31200#[doc = "Multiply-subtract from accumulator"]
31201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"]
31202#[inline]
31203#[target_feature(enable = "neon")]
31204#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31205#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31206#[cfg_attr(
31207 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31208 assert_instr(mls)
31209)]
31210#[cfg_attr(
31211 not(target_arch = "arm"),
31212 stable(feature = "neon_intrinsics", since = "1.59.0")
31213)]
31214#[cfg_attr(
31215 target_arch = "arm",
31216 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31217)]
31218pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
31219 unsafe { simd_sub(a, simd_mul(b, c)) }
31220}
31221#[doc = "Multiply-subtract from accumulator"]
31222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"]
31223#[inline]
31224#[target_feature(enable = "neon")]
31225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31226#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31227#[cfg_attr(
31228 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31229 assert_instr(mls)
31230)]
31231#[cfg_attr(
31232 not(target_arch = "arm"),
31233 stable(feature = "neon_intrinsics", since = "1.59.0")
31234)]
31235#[cfg_attr(
31236 target_arch = "arm",
31237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31238)]
31239pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
31240 unsafe { simd_sub(a, simd_mul(b, c)) }
31241}
31242#[doc = "Multiply-subtract from accumulator"]
31243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"]
31244#[inline]
31245#[target_feature(enable = "neon")]
31246#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31247#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31248#[cfg_attr(
31249 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31250 assert_instr(mls)
31251)]
31252#[cfg_attr(
31253 not(target_arch = "arm"),
31254 stable(feature = "neon_intrinsics", since = "1.59.0")
31255)]
31256#[cfg_attr(
31257 target_arch = "arm",
31258 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31259)]
31260pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
31261 unsafe { simd_sub(a, simd_mul(b, c)) }
31262}
31263#[doc = "Multiply-subtract from accumulator"]
31264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"]
31265#[inline]
31266#[target_feature(enable = "neon")]
31267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31268#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31269#[cfg_attr(
31270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31271 assert_instr(mls)
31272)]
31273#[cfg_attr(
31274 not(target_arch = "arm"),
31275 stable(feature = "neon_intrinsics", since = "1.59.0")
31276)]
31277#[cfg_attr(
31278 target_arch = "arm",
31279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31280)]
31281pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
31282 unsafe { simd_sub(a, simd_mul(b, c)) }
31283}
31284#[doc = "Multiply-subtract from accumulator"]
31285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"]
31286#[inline]
31287#[target_feature(enable = "neon")]
31288#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31289#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
31290#[cfg_attr(
31291 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31292 assert_instr(mls)
31293)]
31294#[cfg_attr(
31295 not(target_arch = "arm"),
31296 stable(feature = "neon_intrinsics", since = "1.59.0")
31297)]
31298#[cfg_attr(
31299 target_arch = "arm",
31300 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31301)]
31302pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
31303 unsafe { simd_sub(a, simd_mul(b, c)) }
31304}
31305#[doc = "Multiply-subtract from accumulator"]
31306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"]
31307#[inline]
31308#[target_feature(enable = "neon")]
31309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31310#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31311#[cfg_attr(
31312 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31313 assert_instr(mls)
31314)]
31315#[cfg_attr(
31316 not(target_arch = "arm"),
31317 stable(feature = "neon_intrinsics", since = "1.59.0")
31318)]
31319#[cfg_attr(
31320 target_arch = "arm",
31321 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31322)]
31323pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
31324 unsafe { simd_sub(a, simd_mul(b, c)) }
31325}
31326#[doc = "Multiply-subtract from accumulator"]
31327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"]
31328#[inline]
31329#[target_feature(enable = "neon")]
31330#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31331#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31332#[cfg_attr(
31333 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31334 assert_instr(mls)
31335)]
31336#[cfg_attr(
31337 not(target_arch = "arm"),
31338 stable(feature = "neon_intrinsics", since = "1.59.0")
31339)]
31340#[cfg_attr(
31341 target_arch = "arm",
31342 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31343)]
31344pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
31345 unsafe { simd_sub(a, simd_mul(b, c)) }
31346}
31347#[doc = "Multiply-subtract from accumulator"]
31348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"]
31349#[inline]
31350#[target_feature(enable = "neon")]
31351#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31352#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31353#[cfg_attr(
31354 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31355 assert_instr(mls)
31356)]
31357#[cfg_attr(
31358 not(target_arch = "arm"),
31359 stable(feature = "neon_intrinsics", since = "1.59.0")
31360)]
31361#[cfg_attr(
31362 target_arch = "arm",
31363 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31364)]
31365pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
31366 unsafe { simd_sub(a, simd_mul(b, c)) }
31367}
31368#[doc = "Multiply-subtract from accumulator"]
31369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"]
31370#[inline]
31371#[target_feature(enable = "neon")]
31372#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31373#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31374#[cfg_attr(
31375 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31376 assert_instr(mls)
31377)]
31378#[cfg_attr(
31379 not(target_arch = "arm"),
31380 stable(feature = "neon_intrinsics", since = "1.59.0")
31381)]
31382#[cfg_attr(
31383 target_arch = "arm",
31384 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31385)]
31386pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
31387 unsafe { simd_sub(a, simd_mul(b, c)) }
31388}
31389#[doc = "Vector widening multiply subtract with scalar"]
31390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"]
31391#[inline]
31392#[target_feature(enable = "neon")]
31393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31394#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
31395#[cfg_attr(
31396 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31397 assert_instr(smlsl, LANE = 1)
31398)]
31399#[rustc_legacy_const_generics(3)]
31400#[cfg_attr(
31401 not(target_arch = "arm"),
31402 stable(feature = "neon_intrinsics", since = "1.59.0")
31403)]
31404#[cfg_attr(
31405 target_arch = "arm",
31406 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31407)]
31408pub fn vmlsl_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31409 static_assert_uimm_bits!(LANE, 2);
31410 unsafe {
31411 vmlsl_s16(
31412 a,
31413 b,
31414 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31415 )
31416 }
31417}
31418#[doc = "Vector widening multiply subtract with scalar"]
31419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"]
31420#[inline]
31421#[target_feature(enable = "neon")]
31422#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31423#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
31424#[cfg_attr(
31425 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31426 assert_instr(smlsl, LANE = 1)
31427)]
31428#[rustc_legacy_const_generics(3)]
31429#[cfg_attr(
31430 not(target_arch = "arm"),
31431 stable(feature = "neon_intrinsics", since = "1.59.0")
31432)]
31433#[cfg_attr(
31434 target_arch = "arm",
31435 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31436)]
31437pub fn vmlsl_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
31438 static_assert_uimm_bits!(LANE, 3);
31439 unsafe {
31440 vmlsl_s16(
31441 a,
31442 b,
31443 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31444 )
31445 }
31446}
31447#[doc = "Vector widening multiply subtract with scalar"]
31448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"]
31449#[inline]
31450#[target_feature(enable = "neon")]
31451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31452#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
31453#[cfg_attr(
31454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31455 assert_instr(smlsl, LANE = 1)
31456)]
31457#[rustc_legacy_const_generics(3)]
31458#[cfg_attr(
31459 not(target_arch = "arm"),
31460 stable(feature = "neon_intrinsics", since = "1.59.0")
31461)]
31462#[cfg_attr(
31463 target_arch = "arm",
31464 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31465)]
31466pub fn vmlsl_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31467 static_assert_uimm_bits!(LANE, 1);
31468 unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31469}
31470#[doc = "Vector widening multiply subtract with scalar"]
31471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"]
31472#[inline]
31473#[target_feature(enable = "neon")]
31474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31475#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
31476#[cfg_attr(
31477 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31478 assert_instr(smlsl, LANE = 1)
31479)]
31480#[rustc_legacy_const_generics(3)]
31481#[cfg_attr(
31482 not(target_arch = "arm"),
31483 stable(feature = "neon_intrinsics", since = "1.59.0")
31484)]
31485#[cfg_attr(
31486 target_arch = "arm",
31487 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31488)]
31489pub fn vmlsl_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
31490 static_assert_uimm_bits!(LANE, 2);
31491 unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31492}
31493#[doc = "Vector widening multiply subtract with scalar"]
31494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"]
31495#[inline]
31496#[target_feature(enable = "neon")]
31497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31498#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
31499#[cfg_attr(
31500 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31501 assert_instr(umlsl, LANE = 1)
31502)]
31503#[rustc_legacy_const_generics(3)]
31504#[cfg_attr(
31505 not(target_arch = "arm"),
31506 stable(feature = "neon_intrinsics", since = "1.59.0")
31507)]
31508#[cfg_attr(
31509 target_arch = "arm",
31510 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31511)]
31512pub fn vmlsl_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
31513 static_assert_uimm_bits!(LANE, 2);
31514 unsafe {
31515 vmlsl_u16(
31516 a,
31517 b,
31518 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31519 )
31520 }
31521}
31522#[doc = "Vector widening multiply subtract with scalar"]
31523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"]
31524#[inline]
31525#[target_feature(enable = "neon")]
31526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31527#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
31528#[cfg_attr(
31529 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31530 assert_instr(umlsl, LANE = 1)
31531)]
31532#[rustc_legacy_const_generics(3)]
31533#[cfg_attr(
31534 not(target_arch = "arm"),
31535 stable(feature = "neon_intrinsics", since = "1.59.0")
31536)]
31537#[cfg_attr(
31538 target_arch = "arm",
31539 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31540)]
31541pub fn vmlsl_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
31542 static_assert_uimm_bits!(LANE, 3);
31543 unsafe {
31544 vmlsl_u16(
31545 a,
31546 b,
31547 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31548 )
31549 }
31550}
31551#[doc = "Vector widening multiply subtract with scalar"]
31552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"]
31553#[inline]
31554#[target_feature(enable = "neon")]
31555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31556#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
31557#[cfg_attr(
31558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31559 assert_instr(umlsl, LANE = 1)
31560)]
31561#[rustc_legacy_const_generics(3)]
31562#[cfg_attr(
31563 not(target_arch = "arm"),
31564 stable(feature = "neon_intrinsics", since = "1.59.0")
31565)]
31566#[cfg_attr(
31567 target_arch = "arm",
31568 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31569)]
31570pub fn vmlsl_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
31571 static_assert_uimm_bits!(LANE, 1);
31572 unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31573}
31574#[doc = "Vector widening multiply subtract with scalar"]
31575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"]
31576#[inline]
31577#[target_feature(enable = "neon")]
31578#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31579#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
31580#[cfg_attr(
31581 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31582 assert_instr(umlsl, LANE = 1)
31583)]
31584#[rustc_legacy_const_generics(3)]
31585#[cfg_attr(
31586 not(target_arch = "arm"),
31587 stable(feature = "neon_intrinsics", since = "1.59.0")
31588)]
31589#[cfg_attr(
31590 target_arch = "arm",
31591 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31592)]
31593pub fn vmlsl_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
31594 static_assert_uimm_bits!(LANE, 2);
31595 unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31596}
31597#[doc = "Vector widening multiply subtract with scalar"]
31598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"]
31599#[inline]
31600#[target_feature(enable = "neon")]
31601#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31602#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
31603#[cfg_attr(
31604 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31605 assert_instr(smlsl)
31606)]
31607#[cfg_attr(
31608 not(target_arch = "arm"),
31609 stable(feature = "neon_intrinsics", since = "1.59.0")
31610)]
31611#[cfg_attr(
31612 target_arch = "arm",
31613 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31614)]
31615pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
31616 vmlsl_s16(a, b, vdup_n_s16(c))
31617}
31618#[doc = "Vector widening multiply subtract with scalar"]
31619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"]
31620#[inline]
31621#[target_feature(enable = "neon")]
31622#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31623#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
31624#[cfg_attr(
31625 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31626 assert_instr(smlsl)
31627)]
31628#[cfg_attr(
31629 not(target_arch = "arm"),
31630 stable(feature = "neon_intrinsics", since = "1.59.0")
31631)]
31632#[cfg_attr(
31633 target_arch = "arm",
31634 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31635)]
31636pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
31637 vmlsl_s32(a, b, vdup_n_s32(c))
31638}
31639#[doc = "Vector widening multiply subtract with scalar"]
31640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"]
31641#[inline]
31642#[target_feature(enable = "neon")]
31643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31644#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
31645#[cfg_attr(
31646 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31647 assert_instr(umlsl)
31648)]
31649#[cfg_attr(
31650 not(target_arch = "arm"),
31651 stable(feature = "neon_intrinsics", since = "1.59.0")
31652)]
31653#[cfg_attr(
31654 target_arch = "arm",
31655 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31656)]
31657pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
31658 vmlsl_u16(a, b, vdup_n_u16(c))
31659}
31660#[doc = "Vector widening multiply subtract with scalar"]
31661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"]
31662#[inline]
31663#[target_feature(enable = "neon")]
31664#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31665#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
31666#[cfg_attr(
31667 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31668 assert_instr(umlsl)
31669)]
31670#[cfg_attr(
31671 not(target_arch = "arm"),
31672 stable(feature = "neon_intrinsics", since = "1.59.0")
31673)]
31674#[cfg_attr(
31675 target_arch = "arm",
31676 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31677)]
31678pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
31679 vmlsl_u32(a, b, vdup_n_u32(c))
31680}
31681#[doc = "Signed multiply-subtract long"]
31682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"]
31683#[inline]
31684#[target_feature(enable = "neon")]
31685#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31686#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))]
31687#[cfg_attr(
31688 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31689 assert_instr(smlsl)
31690)]
31691#[cfg_attr(
31692 not(target_arch = "arm"),
31693 stable(feature = "neon_intrinsics", since = "1.59.0")
31694)]
31695#[cfg_attr(
31696 target_arch = "arm",
31697 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31698)]
31699pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
31700 unsafe { simd_sub(a, vmull_s8(b, c)) }
31701}
31702#[doc = "Signed multiply-subtract long"]
31703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"]
31704#[inline]
31705#[target_feature(enable = "neon")]
31706#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31707#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
31708#[cfg_attr(
31709 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31710 assert_instr(smlsl)
31711)]
31712#[cfg_attr(
31713 not(target_arch = "arm"),
31714 stable(feature = "neon_intrinsics", since = "1.59.0")
31715)]
31716#[cfg_attr(
31717 target_arch = "arm",
31718 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31719)]
31720pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31721 unsafe { simd_sub(a, vmull_s16(b, c)) }
31722}
31723#[doc = "Signed multiply-subtract long"]
31724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"]
31725#[inline]
31726#[target_feature(enable = "neon")]
31727#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31728#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
31729#[cfg_attr(
31730 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31731 assert_instr(smlsl)
31732)]
31733#[cfg_attr(
31734 not(target_arch = "arm"),
31735 stable(feature = "neon_intrinsics", since = "1.59.0")
31736)]
31737#[cfg_attr(
31738 target_arch = "arm",
31739 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31740)]
31741pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31742 unsafe { simd_sub(a, vmull_s32(b, c)) }
31743}
31744#[doc = "Unsigned multiply-subtract long"]
31745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"]
31746#[inline]
31747#[target_feature(enable = "neon")]
31748#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31749#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))]
31750#[cfg_attr(
31751 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31752 assert_instr(umlsl)
31753)]
31754#[cfg_attr(
31755 not(target_arch = "arm"),
31756 stable(feature = "neon_intrinsics", since = "1.59.0")
31757)]
31758#[cfg_attr(
31759 target_arch = "arm",
31760 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31761)]
31762pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
31763 unsafe { simd_sub(a, vmull_u8(b, c)) }
31764}
31765#[doc = "Unsigned multiply-subtract long"]
31766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"]
31767#[inline]
31768#[target_feature(enable = "neon")]
31769#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31770#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
31771#[cfg_attr(
31772 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31773 assert_instr(umlsl)
31774)]
31775#[cfg_attr(
31776 not(target_arch = "arm"),
31777 stable(feature = "neon_intrinsics", since = "1.59.0")
31778)]
31779#[cfg_attr(
31780 target_arch = "arm",
31781 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31782)]
31783pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
31784 unsafe { simd_sub(a, vmull_u16(b, c)) }
31785}
31786#[doc = "Unsigned multiply-subtract long"]
31787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"]
31788#[inline]
31789#[target_feature(enable = "neon")]
31790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31791#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
31792#[cfg_attr(
31793 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31794 assert_instr(umlsl)
31795)]
31796#[cfg_attr(
31797 not(target_arch = "arm"),
31798 stable(feature = "neon_intrinsics", since = "1.59.0")
31799)]
31800#[cfg_attr(
31801 target_arch = "arm",
31802 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31803)]
31804pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
31805 unsafe { simd_sub(a, vmull_u32(b, c)) }
31806}
31807#[doc = "8-bit integer matrix multiply-accumulate"]
31808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"]
31809#[inline]
31810#[target_feature(enable = "neon,i8mm")]
31811#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
31812#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
31813#[cfg_attr(
31814 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31815 assert_instr(smmla)
31816)]
31817#[cfg_attr(
31818 not(target_arch = "arm"),
31819 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
31820)]
31821#[cfg_attr(
31822 target_arch = "arm",
31823 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31824)]
31825pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
31826 unsafe extern "unadjusted" {
31827 #[cfg_attr(
31828 any(target_arch = "aarch64", target_arch = "arm64ec"),
31829 link_name = "llvm.aarch64.neon.smmla.v4i32.v16i8"
31830 )]
31831 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.smmla.v4i32.v16i8")]
31832 fn _vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t;
31833 }
31834 unsafe { _vmmlaq_s32(a, b, c) }
31835}
31836#[doc = "8-bit integer matrix multiply-accumulate"]
31837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"]
31838#[inline]
31839#[target_feature(enable = "neon,i8mm")]
31840#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
31841#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
31842#[cfg_attr(
31843 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31844 assert_instr(ummla)
31845)]
31846#[cfg_attr(
31847 not(target_arch = "arm"),
31848 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
31849)]
31850#[cfg_attr(
31851 target_arch = "arm",
31852 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31853)]
31854pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
31855 unsafe extern "unadjusted" {
31856 #[cfg_attr(
31857 any(target_arch = "aarch64", target_arch = "arm64ec"),
31858 link_name = "llvm.aarch64.neon.ummla.v4i32.v16i8"
31859 )]
31860 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.ummla.v4i32.v16i8")]
31861 fn _vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t;
31862 }
31863 unsafe { _vmmlaq_u32(a, b, c) }
31864}
31865#[doc = "Duplicate element to vector"]
31866#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"]
31867#[inline]
31868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31869#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31870#[cfg_attr(
31871 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31872 assert_instr(dup)
31873)]
31874#[target_feature(enable = "neon,fp16")]
31875#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
31876pub fn vmov_n_f16(a: f16) -> float16x4_t {
31877 vdup_n_f16(a)
31878}
31879#[doc = "Duplicate element to vector"]
31880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"]
31881#[inline]
31882#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31883#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31884#[cfg_attr(
31885 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31886 assert_instr(dup)
31887)]
31888#[target_feature(enable = "neon,fp16")]
31889#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
31890pub fn vmovq_n_f16(a: f16) -> float16x8_t {
31891 vdupq_n_f16(a)
31892}
31893#[doc = "Duplicate vector element to vector or scalar"]
31894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f32)"]
31895#[inline]
31896#[target_feature(enable = "neon")]
31897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31898#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31899#[cfg_attr(
31900 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31901 assert_instr(dup)
31902)]
31903#[cfg_attr(
31904 not(target_arch = "arm"),
31905 stable(feature = "neon_intrinsics", since = "1.59.0")
31906)]
31907#[cfg_attr(
31908 target_arch = "arm",
31909 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31910)]
31911pub fn vmov_n_f32(value: f32) -> float32x2_t {
31912 vdup_n_f32(value)
31913}
31914#[doc = "Duplicate vector element to vector or scalar"]
31915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16)"]
31916#[inline]
31917#[target_feature(enable = "neon")]
31918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31919#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31920#[cfg_attr(
31921 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31922 assert_instr(dup)
31923)]
31924#[cfg_attr(
31925 not(target_arch = "arm"),
31926 stable(feature = "neon_intrinsics", since = "1.59.0")
31927)]
31928#[cfg_attr(
31929 target_arch = "arm",
31930 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31931)]
31932pub fn vmov_n_p16(value: p16) -> poly16x4_t {
31933 vdup_n_p16(value)
31934}
31935#[doc = "Duplicate vector element to vector or scalar"]
31936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p8)"]
31937#[inline]
31938#[target_feature(enable = "neon")]
31939#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31940#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
31941#[cfg_attr(
31942 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31943 assert_instr(dup)
31944)]
31945#[cfg_attr(
31946 not(target_arch = "arm"),
31947 stable(feature = "neon_intrinsics", since = "1.59.0")
31948)]
31949#[cfg_attr(
31950 target_arch = "arm",
31951 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31952)]
31953pub fn vmov_n_p8(value: p8) -> poly8x8_t {
31954 vdup_n_p8(value)
31955}
31956#[doc = "Duplicate vector element to vector or scalar"]
31957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s16)"]
31958#[inline]
31959#[target_feature(enable = "neon")]
31960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31961#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31962#[cfg_attr(
31963 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31964 assert_instr(dup)
31965)]
31966#[cfg_attr(
31967 not(target_arch = "arm"),
31968 stable(feature = "neon_intrinsics", since = "1.59.0")
31969)]
31970#[cfg_attr(
31971 target_arch = "arm",
31972 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31973)]
31974pub fn vmov_n_s16(value: i16) -> int16x4_t {
31975 vdup_n_s16(value)
31976}
31977#[doc = "Duplicate vector element to vector or scalar"]
31978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s32)"]
31979#[inline]
31980#[target_feature(enable = "neon")]
31981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31982#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31983#[cfg_attr(
31984 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31985 assert_instr(dup)
31986)]
31987#[cfg_attr(
31988 not(target_arch = "arm"),
31989 stable(feature = "neon_intrinsics", since = "1.59.0")
31990)]
31991#[cfg_attr(
31992 target_arch = "arm",
31993 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31994)]
31995pub fn vmov_n_s32(value: i32) -> int32x2_t {
31996 vdup_n_s32(value)
31997}
31998#[doc = "Duplicate vector element to vector or scalar"]
31999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s64)"]
32000#[inline]
32001#[target_feature(enable = "neon")]
32002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32003#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32004#[cfg_attr(
32005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32006 assert_instr(fmov)
32007)]
32008#[cfg_attr(
32009 not(target_arch = "arm"),
32010 stable(feature = "neon_intrinsics", since = "1.59.0")
32011)]
32012#[cfg_attr(
32013 target_arch = "arm",
32014 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32015)]
32016pub fn vmov_n_s64(value: i64) -> int64x1_t {
32017 vdup_n_s64(value)
32018}
32019#[doc = "Duplicate vector element to vector or scalar"]
32020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s8)"]
32021#[inline]
32022#[target_feature(enable = "neon")]
32023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32024#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32025#[cfg_attr(
32026 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32027 assert_instr(dup)
32028)]
32029#[cfg_attr(
32030 not(target_arch = "arm"),
32031 stable(feature = "neon_intrinsics", since = "1.59.0")
32032)]
32033#[cfg_attr(
32034 target_arch = "arm",
32035 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32036)]
32037pub fn vmov_n_s8(value: i8) -> int8x8_t {
32038 vdup_n_s8(value)
32039}
32040#[doc = "Duplicate vector element to vector or scalar"]
32041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u16)"]
32042#[inline]
32043#[target_feature(enable = "neon")]
32044#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32045#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32046#[cfg_attr(
32047 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32048 assert_instr(dup)
32049)]
32050#[cfg_attr(
32051 not(target_arch = "arm"),
32052 stable(feature = "neon_intrinsics", since = "1.59.0")
32053)]
32054#[cfg_attr(
32055 target_arch = "arm",
32056 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32057)]
32058pub fn vmov_n_u16(value: u16) -> uint16x4_t {
32059 vdup_n_u16(value)
32060}
32061#[doc = "Duplicate vector element to vector or scalar"]
32062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u32)"]
32063#[inline]
32064#[target_feature(enable = "neon")]
32065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32066#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32067#[cfg_attr(
32068 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32069 assert_instr(dup)
32070)]
32071#[cfg_attr(
32072 not(target_arch = "arm"),
32073 stable(feature = "neon_intrinsics", since = "1.59.0")
32074)]
32075#[cfg_attr(
32076 target_arch = "arm",
32077 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32078)]
32079pub fn vmov_n_u32(value: u32) -> uint32x2_t {
32080 vdup_n_u32(value)
32081}
32082#[doc = "Duplicate vector element to vector or scalar"]
32083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u64)"]
32084#[inline]
32085#[target_feature(enable = "neon")]
32086#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32087#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32088#[cfg_attr(
32089 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32090 assert_instr(fmov)
32091)]
32092#[cfg_attr(
32093 not(target_arch = "arm"),
32094 stable(feature = "neon_intrinsics", since = "1.59.0")
32095)]
32096#[cfg_attr(
32097 target_arch = "arm",
32098 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32099)]
32100pub fn vmov_n_u64(value: u64) -> uint64x1_t {
32101 vdup_n_u64(value)
32102}
32103#[doc = "Duplicate vector element to vector or scalar"]
32104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u8)"]
32105#[inline]
32106#[target_feature(enable = "neon")]
32107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32108#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32109#[cfg_attr(
32110 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32111 assert_instr(dup)
32112)]
32113#[cfg_attr(
32114 not(target_arch = "arm"),
32115 stable(feature = "neon_intrinsics", since = "1.59.0")
32116)]
32117#[cfg_attr(
32118 target_arch = "arm",
32119 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32120)]
32121pub fn vmov_n_u8(value: u8) -> uint8x8_t {
32122 vdup_n_u8(value)
32123}
32124#[doc = "Duplicate vector element to vector or scalar"]
32125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f32)"]
32126#[inline]
32127#[target_feature(enable = "neon")]
32128#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32129#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32130#[cfg_attr(
32131 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32132 assert_instr(dup)
32133)]
32134#[cfg_attr(
32135 not(target_arch = "arm"),
32136 stable(feature = "neon_intrinsics", since = "1.59.0")
32137)]
32138#[cfg_attr(
32139 target_arch = "arm",
32140 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32141)]
32142pub fn vmovq_n_f32(value: f32) -> float32x4_t {
32143 vdupq_n_f32(value)
32144}
32145#[doc = "Duplicate vector element to vector or scalar"]
32146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16)"]
32147#[inline]
32148#[target_feature(enable = "neon")]
32149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32150#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32151#[cfg_attr(
32152 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32153 assert_instr(dup)
32154)]
32155#[cfg_attr(
32156 not(target_arch = "arm"),
32157 stable(feature = "neon_intrinsics", since = "1.59.0")
32158)]
32159#[cfg_attr(
32160 target_arch = "arm",
32161 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32162)]
32163pub fn vmovq_n_p16(value: p16) -> poly16x8_t {
32164 vdupq_n_p16(value)
32165}
32166#[doc = "Duplicate vector element to vector or scalar"]
32167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8)"]
32168#[inline]
32169#[target_feature(enable = "neon")]
32170#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32171#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32172#[cfg_attr(
32173 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32174 assert_instr(dup)
32175)]
32176#[cfg_attr(
32177 not(target_arch = "arm"),
32178 stable(feature = "neon_intrinsics", since = "1.59.0")
32179)]
32180#[cfg_attr(
32181 target_arch = "arm",
32182 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32183)]
32184pub fn vmovq_n_p8(value: p8) -> poly8x16_t {
32185 vdupq_n_p8(value)
32186}
32187#[doc = "Duplicate vector element to vector or scalar"]
32188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s16)"]
32189#[inline]
32190#[target_feature(enable = "neon")]
32191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32192#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32193#[cfg_attr(
32194 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32195 assert_instr(dup)
32196)]
32197#[cfg_attr(
32198 not(target_arch = "arm"),
32199 stable(feature = "neon_intrinsics", since = "1.59.0")
32200)]
32201#[cfg_attr(
32202 target_arch = "arm",
32203 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32204)]
32205pub fn vmovq_n_s16(value: i16) -> int16x8_t {
32206 vdupq_n_s16(value)
32207}
32208#[doc = "Duplicate vector element to vector or scalar"]
32209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s32)"]
32210#[inline]
32211#[target_feature(enable = "neon")]
32212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32213#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32214#[cfg_attr(
32215 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32216 assert_instr(dup)
32217)]
32218#[cfg_attr(
32219 not(target_arch = "arm"),
32220 stable(feature = "neon_intrinsics", since = "1.59.0")
32221)]
32222#[cfg_attr(
32223 target_arch = "arm",
32224 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32225)]
32226pub fn vmovq_n_s32(value: i32) -> int32x4_t {
32227 vdupq_n_s32(value)
32228}
32229#[doc = "Duplicate vector element to vector or scalar"]
32230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s64)"]
32231#[inline]
32232#[target_feature(enable = "neon")]
32233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32234#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32235#[cfg_attr(
32236 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32237 assert_instr(dup)
32238)]
32239#[cfg_attr(
32240 not(target_arch = "arm"),
32241 stable(feature = "neon_intrinsics", since = "1.59.0")
32242)]
32243#[cfg_attr(
32244 target_arch = "arm",
32245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32246)]
32247pub fn vmovq_n_s64(value: i64) -> int64x2_t {
32248 vdupq_n_s64(value)
32249}
32250#[doc = "Duplicate vector element to vector or scalar"]
32251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s8)"]
32252#[inline]
32253#[target_feature(enable = "neon")]
32254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32255#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32256#[cfg_attr(
32257 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32258 assert_instr(dup)
32259)]
32260#[cfg_attr(
32261 not(target_arch = "arm"),
32262 stable(feature = "neon_intrinsics", since = "1.59.0")
32263)]
32264#[cfg_attr(
32265 target_arch = "arm",
32266 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32267)]
32268pub fn vmovq_n_s8(value: i8) -> int8x16_t {
32269 vdupq_n_s8(value)
32270}
32271#[doc = "Duplicate vector element to vector or scalar"]
32272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u16)"]
32273#[inline]
32274#[target_feature(enable = "neon")]
32275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32276#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
32277#[cfg_attr(
32278 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32279 assert_instr(dup)
32280)]
32281#[cfg_attr(
32282 not(target_arch = "arm"),
32283 stable(feature = "neon_intrinsics", since = "1.59.0")
32284)]
32285#[cfg_attr(
32286 target_arch = "arm",
32287 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32288)]
32289pub fn vmovq_n_u16(value: u16) -> uint16x8_t {
32290 vdupq_n_u16(value)
32291}
32292#[doc = "Duplicate vector element to vector or scalar"]
32293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u32)"]
32294#[inline]
32295#[target_feature(enable = "neon")]
32296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32297#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
32298#[cfg_attr(
32299 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32300 assert_instr(dup)
32301)]
32302#[cfg_attr(
32303 not(target_arch = "arm"),
32304 stable(feature = "neon_intrinsics", since = "1.59.0")
32305)]
32306#[cfg_attr(
32307 target_arch = "arm",
32308 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32309)]
32310pub fn vmovq_n_u32(value: u32) -> uint32x4_t {
32311 vdupq_n_u32(value)
32312}
32313#[doc = "Duplicate vector element to vector or scalar"]
32314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u64)"]
32315#[inline]
32316#[target_feature(enable = "neon")]
32317#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32318#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32319#[cfg_attr(
32320 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32321 assert_instr(dup)
32322)]
32323#[cfg_attr(
32324 not(target_arch = "arm"),
32325 stable(feature = "neon_intrinsics", since = "1.59.0")
32326)]
32327#[cfg_attr(
32328 target_arch = "arm",
32329 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32330)]
32331pub fn vmovq_n_u64(value: u64) -> uint64x2_t {
32332 vdupq_n_u64(value)
32333}
32334#[doc = "Duplicate vector element to vector or scalar"]
32335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u8)"]
32336#[inline]
32337#[target_feature(enable = "neon")]
32338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32339#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32340#[cfg_attr(
32341 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32342 assert_instr(dup)
32343)]
32344#[cfg_attr(
32345 not(target_arch = "arm"),
32346 stable(feature = "neon_intrinsics", since = "1.59.0")
32347)]
32348#[cfg_attr(
32349 target_arch = "arm",
32350 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32351)]
32352pub fn vmovq_n_u8(value: u8) -> uint8x16_t {
32353 vdupq_n_u8(value)
32354}
32355#[doc = "Vector long move."]
32356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s16)"]
32357#[inline]
32358#[target_feature(enable = "neon")]
32359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32360#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32361#[cfg_attr(
32362 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32363 assert_instr(sxtl)
32364)]
32365#[cfg_attr(
32366 not(target_arch = "arm"),
32367 stable(feature = "neon_intrinsics", since = "1.59.0")
32368)]
32369#[cfg_attr(
32370 target_arch = "arm",
32371 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32372)]
32373pub fn vmovl_s16(a: int16x4_t) -> int32x4_t {
32374 unsafe { simd_cast(a) }
32375}
32376#[doc = "Vector long move."]
32377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s32)"]
32378#[inline]
32379#[target_feature(enable = "neon")]
32380#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32381#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32382#[cfg_attr(
32383 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32384 assert_instr(sxtl)
32385)]
32386#[cfg_attr(
32387 not(target_arch = "arm"),
32388 stable(feature = "neon_intrinsics", since = "1.59.0")
32389)]
32390#[cfg_attr(
32391 target_arch = "arm",
32392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32393)]
32394pub fn vmovl_s32(a: int32x2_t) -> int64x2_t {
32395 unsafe { simd_cast(a) }
32396}
32397#[doc = "Vector long move."]
32398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s8)"]
32399#[inline]
32400#[target_feature(enable = "neon")]
32401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32403#[cfg_attr(
32404 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32405 assert_instr(sxtl)
32406)]
32407#[cfg_attr(
32408 not(target_arch = "arm"),
32409 stable(feature = "neon_intrinsics", since = "1.59.0")
32410)]
32411#[cfg_attr(
32412 target_arch = "arm",
32413 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32414)]
32415pub fn vmovl_s8(a: int8x8_t) -> int16x8_t {
32416 unsafe { simd_cast(a) }
32417}
32418#[doc = "Vector long move."]
32419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u16)"]
32420#[inline]
32421#[target_feature(enable = "neon")]
32422#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32423#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32424#[cfg_attr(
32425 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32426 assert_instr(uxtl)
32427)]
32428#[cfg_attr(
32429 not(target_arch = "arm"),
32430 stable(feature = "neon_intrinsics", since = "1.59.0")
32431)]
32432#[cfg_attr(
32433 target_arch = "arm",
32434 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32435)]
32436pub fn vmovl_u16(a: uint16x4_t) -> uint32x4_t {
32437 unsafe { simd_cast(a) }
32438}
32439#[doc = "Vector long move."]
32440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u32)"]
32441#[inline]
32442#[target_feature(enable = "neon")]
32443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32445#[cfg_attr(
32446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32447 assert_instr(uxtl)
32448)]
32449#[cfg_attr(
32450 not(target_arch = "arm"),
32451 stable(feature = "neon_intrinsics", since = "1.59.0")
32452)]
32453#[cfg_attr(
32454 target_arch = "arm",
32455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32456)]
32457pub fn vmovl_u32(a: uint32x2_t) -> uint64x2_t {
32458 unsafe { simd_cast(a) }
32459}
32460#[doc = "Vector long move."]
32461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u8)"]
32462#[inline]
32463#[target_feature(enable = "neon")]
32464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32465#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32466#[cfg_attr(
32467 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32468 assert_instr(uxtl)
32469)]
32470#[cfg_attr(
32471 not(target_arch = "arm"),
32472 stable(feature = "neon_intrinsics", since = "1.59.0")
32473)]
32474#[cfg_attr(
32475 target_arch = "arm",
32476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32477)]
32478pub fn vmovl_u8(a: uint8x8_t) -> uint16x8_t {
32479 unsafe { simd_cast(a) }
32480}
32481#[doc = "Vector narrow integer."]
32482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s16)"]
32483#[inline]
32484#[target_feature(enable = "neon")]
32485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32486#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32487#[cfg_attr(
32488 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32489 assert_instr(xtn)
32490)]
32491#[cfg_attr(
32492 not(target_arch = "arm"),
32493 stable(feature = "neon_intrinsics", since = "1.59.0")
32494)]
32495#[cfg_attr(
32496 target_arch = "arm",
32497 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32498)]
32499pub fn vmovn_s16(a: int16x8_t) -> int8x8_t {
32500 unsafe { simd_cast(a) }
32501}
32502#[doc = "Vector narrow integer."]
32503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s32)"]
32504#[inline]
32505#[target_feature(enable = "neon")]
32506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32508#[cfg_attr(
32509 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32510 assert_instr(xtn)
32511)]
32512#[cfg_attr(
32513 not(target_arch = "arm"),
32514 stable(feature = "neon_intrinsics", since = "1.59.0")
32515)]
32516#[cfg_attr(
32517 target_arch = "arm",
32518 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32519)]
32520pub fn vmovn_s32(a: int32x4_t) -> int16x4_t {
32521 unsafe { simd_cast(a) }
32522}
32523#[doc = "Vector narrow integer."]
32524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s64)"]
32525#[inline]
32526#[target_feature(enable = "neon")]
32527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32529#[cfg_attr(
32530 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32531 assert_instr(xtn)
32532)]
32533#[cfg_attr(
32534 not(target_arch = "arm"),
32535 stable(feature = "neon_intrinsics", since = "1.59.0")
32536)]
32537#[cfg_attr(
32538 target_arch = "arm",
32539 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32540)]
32541pub fn vmovn_s64(a: int64x2_t) -> int32x2_t {
32542 unsafe { simd_cast(a) }
32543}
32544#[doc = "Vector narrow integer."]
32545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u16)"]
32546#[inline]
32547#[target_feature(enable = "neon")]
32548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32550#[cfg_attr(
32551 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32552 assert_instr(xtn)
32553)]
32554#[cfg_attr(
32555 not(target_arch = "arm"),
32556 stable(feature = "neon_intrinsics", since = "1.59.0")
32557)]
32558#[cfg_attr(
32559 target_arch = "arm",
32560 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32561)]
32562pub fn vmovn_u16(a: uint16x8_t) -> uint8x8_t {
32563 unsafe { simd_cast(a) }
32564}
32565#[doc = "Vector narrow integer."]
32566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u32)"]
32567#[inline]
32568#[target_feature(enable = "neon")]
32569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32570#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32571#[cfg_attr(
32572 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32573 assert_instr(xtn)
32574)]
32575#[cfg_attr(
32576 not(target_arch = "arm"),
32577 stable(feature = "neon_intrinsics", since = "1.59.0")
32578)]
32579#[cfg_attr(
32580 target_arch = "arm",
32581 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32582)]
32583pub fn vmovn_u32(a: uint32x4_t) -> uint16x4_t {
32584 unsafe { simd_cast(a) }
32585}
32586#[doc = "Vector narrow integer."]
32587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u64)"]
32588#[inline]
32589#[target_feature(enable = "neon")]
32590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32591#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32592#[cfg_attr(
32593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32594 assert_instr(xtn)
32595)]
32596#[cfg_attr(
32597 not(target_arch = "arm"),
32598 stable(feature = "neon_intrinsics", since = "1.59.0")
32599)]
32600#[cfg_attr(
32601 target_arch = "arm",
32602 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32603)]
32604pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t {
32605 unsafe { simd_cast(a) }
32606}
32607#[doc = "Multiply"]
32608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"]
32609#[inline]
32610#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32611#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
32612#[cfg_attr(
32613 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32614 assert_instr(fmul)
32615)]
32616#[target_feature(enable = "neon,fp16")]
32617#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32618pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
32619 unsafe { simd_mul(a, b) }
32620}
32621#[doc = "Multiply"]
32622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"]
32623#[inline]
32624#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32625#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
32626#[cfg_attr(
32627 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32628 assert_instr(fmul)
32629)]
32630#[target_feature(enable = "neon,fp16")]
32631#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32632pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
32633 unsafe { simd_mul(a, b) }
32634}
32635#[doc = "Multiply"]
32636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"]
32637#[inline]
32638#[target_feature(enable = "neon")]
32639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32640#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
32641#[cfg_attr(
32642 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32643 assert_instr(fmul)
32644)]
32645#[cfg_attr(
32646 not(target_arch = "arm"),
32647 stable(feature = "neon_intrinsics", since = "1.59.0")
32648)]
32649#[cfg_attr(
32650 target_arch = "arm",
32651 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32652)]
32653pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
32654 unsafe { simd_mul(a, b) }
32655}
32656#[doc = "Multiply"]
32657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"]
32658#[inline]
32659#[target_feature(enable = "neon")]
32660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32661#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
32662#[cfg_attr(
32663 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32664 assert_instr(fmul)
32665)]
32666#[cfg_attr(
32667 not(target_arch = "arm"),
32668 stable(feature = "neon_intrinsics", since = "1.59.0")
32669)]
32670#[cfg_attr(
32671 target_arch = "arm",
32672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32673)]
32674pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
32675 unsafe { simd_mul(a, b) }
32676}
32677#[doc = "Multiply"]
32678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"]
32679#[inline]
32680#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32681#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32682#[cfg_attr(
32683 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32684 assert_instr(fmul, LANE = 1)
32685)]
32686#[rustc_legacy_const_generics(2)]
32687#[target_feature(enable = "neon,fp16")]
32688#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32689pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16x4_t {
32690 static_assert_uimm_bits!(LANE, 2);
32691 unsafe {
32692 simd_mul(
32693 a,
32694 simd_shuffle!(v, v, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32695 )
32696 }
32697}
32698#[doc = "Multiply"]
32699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"]
32700#[inline]
32701#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32702#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32703#[cfg_attr(
32704 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32705 assert_instr(fmul, LANE = 1)
32706)]
32707#[rustc_legacy_const_generics(2)]
32708#[target_feature(enable = "neon,fp16")]
32709#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32710pub fn vmulq_lane_f16<const LANE: i32>(a: float16x8_t, v: float16x4_t) -> float16x8_t {
32711 static_assert_uimm_bits!(LANE, 2);
32712 unsafe {
32713 simd_mul(
32714 a,
32715 simd_shuffle!(
32716 v,
32717 v,
32718 [
32719 LANE as u32,
32720 LANE as u32,
32721 LANE as u32,
32722 LANE as u32,
32723 LANE as u32,
32724 LANE as u32,
32725 LANE as u32,
32726 LANE as u32
32727 ]
32728 ),
32729 )
32730 }
32731}
32732#[doc = "Floating-point multiply"]
32733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"]
32734#[inline]
32735#[target_feature(enable = "neon")]
32736#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32737#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32738#[cfg_attr(
32739 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32740 assert_instr(fmul, LANE = 0)
32741)]
32742#[rustc_legacy_const_generics(2)]
32743#[cfg_attr(
32744 not(target_arch = "arm"),
32745 stable(feature = "neon_intrinsics", since = "1.59.0")
32746)]
32747#[cfg_attr(
32748 target_arch = "arm",
32749 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32750)]
32751pub fn vmul_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
32752 static_assert_uimm_bits!(LANE, 1);
32753 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32754}
32755#[doc = "Floating-point multiply"]
32756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"]
32757#[inline]
32758#[target_feature(enable = "neon")]
32759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32761#[cfg_attr(
32762 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32763 assert_instr(fmul, LANE = 0)
32764)]
32765#[rustc_legacy_const_generics(2)]
32766#[cfg_attr(
32767 not(target_arch = "arm"),
32768 stable(feature = "neon_intrinsics", since = "1.59.0")
32769)]
32770#[cfg_attr(
32771 target_arch = "arm",
32772 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32773)]
32774pub fn vmul_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t {
32775 static_assert_uimm_bits!(LANE, 2);
32776 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32777}
32778#[doc = "Floating-point multiply"]
32779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"]
32780#[inline]
32781#[target_feature(enable = "neon")]
32782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32783#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32784#[cfg_attr(
32785 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32786 assert_instr(fmul, LANE = 0)
32787)]
32788#[rustc_legacy_const_generics(2)]
32789#[cfg_attr(
32790 not(target_arch = "arm"),
32791 stable(feature = "neon_intrinsics", since = "1.59.0")
32792)]
32793#[cfg_attr(
32794 target_arch = "arm",
32795 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32796)]
32797pub fn vmulq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t {
32798 static_assert_uimm_bits!(LANE, 1);
32799 unsafe {
32800 simd_mul(
32801 a,
32802 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32803 )
32804 }
32805}
32806#[doc = "Floating-point multiply"]
32807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"]
32808#[inline]
32809#[target_feature(enable = "neon")]
32810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32812#[cfg_attr(
32813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32814 assert_instr(fmul, LANE = 0)
32815)]
32816#[rustc_legacy_const_generics(2)]
32817#[cfg_attr(
32818 not(target_arch = "arm"),
32819 stable(feature = "neon_intrinsics", since = "1.59.0")
32820)]
32821#[cfg_attr(
32822 target_arch = "arm",
32823 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32824)]
32825pub fn vmulq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
32826 static_assert_uimm_bits!(LANE, 2);
32827 unsafe {
32828 simd_mul(
32829 a,
32830 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32831 )
32832 }
32833}
32834#[doc = "Multiply"]
32835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"]
32836#[inline]
32837#[target_feature(enable = "neon")]
32838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32839#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32840#[cfg_attr(
32841 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32842 assert_instr(mul, LANE = 1)
32843)]
32844#[rustc_legacy_const_generics(2)]
32845#[cfg_attr(
32846 not(target_arch = "arm"),
32847 stable(feature = "neon_intrinsics", since = "1.59.0")
32848)]
32849#[cfg_attr(
32850 target_arch = "arm",
32851 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32852)]
32853pub fn vmul_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
32854 static_assert_uimm_bits!(LANE, 2);
32855 unsafe {
32856 simd_mul(
32857 a,
32858 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32859 )
32860 }
32861}
32862#[doc = "Multiply"]
32863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"]
32864#[inline]
32865#[target_feature(enable = "neon")]
32866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32868#[cfg_attr(
32869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32870 assert_instr(mul, LANE = 1)
32871)]
32872#[rustc_legacy_const_generics(2)]
32873#[cfg_attr(
32874 not(target_arch = "arm"),
32875 stable(feature = "neon_intrinsics", since = "1.59.0")
32876)]
32877#[cfg_attr(
32878 target_arch = "arm",
32879 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32880)]
32881pub fn vmulq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
32882 static_assert_uimm_bits!(LANE, 2);
32883 unsafe {
32884 simd_mul(
32885 a,
32886 simd_shuffle!(
32887 b,
32888 b,
32889 [
32890 LANE as u32,
32891 LANE as u32,
32892 LANE as u32,
32893 LANE as u32,
32894 LANE as u32,
32895 LANE as u32,
32896 LANE as u32,
32897 LANE as u32
32898 ]
32899 ),
32900 )
32901 }
32902}
32903#[doc = "Multiply"]
32904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"]
32905#[inline]
32906#[target_feature(enable = "neon")]
32907#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32908#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32909#[cfg_attr(
32910 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32911 assert_instr(mul, LANE = 1)
32912)]
32913#[rustc_legacy_const_generics(2)]
32914#[cfg_attr(
32915 not(target_arch = "arm"),
32916 stable(feature = "neon_intrinsics", since = "1.59.0")
32917)]
32918#[cfg_attr(
32919 target_arch = "arm",
32920 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32921)]
32922pub fn vmul_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
32923 static_assert_uimm_bits!(LANE, 1);
32924 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32925}
32926#[doc = "Multiply"]
32927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"]
32928#[inline]
32929#[target_feature(enable = "neon")]
32930#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32931#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32932#[cfg_attr(
32933 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32934 assert_instr(mul, LANE = 1)
32935)]
32936#[rustc_legacy_const_generics(2)]
32937#[cfg_attr(
32938 not(target_arch = "arm"),
32939 stable(feature = "neon_intrinsics", since = "1.59.0")
32940)]
32941#[cfg_attr(
32942 target_arch = "arm",
32943 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32944)]
32945pub fn vmulq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
32946 static_assert_uimm_bits!(LANE, 1);
32947 unsafe {
32948 simd_mul(
32949 a,
32950 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32951 )
32952 }
32953}
32954#[doc = "Multiply"]
32955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"]
32956#[inline]
32957#[target_feature(enable = "neon")]
32958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32960#[cfg_attr(
32961 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32962 assert_instr(mul, LANE = 1)
32963)]
32964#[rustc_legacy_const_generics(2)]
32965#[cfg_attr(
32966 not(target_arch = "arm"),
32967 stable(feature = "neon_intrinsics", since = "1.59.0")
32968)]
32969#[cfg_attr(
32970 target_arch = "arm",
32971 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32972)]
32973pub fn vmul_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
32974 static_assert_uimm_bits!(LANE, 2);
32975 unsafe {
32976 simd_mul(
32977 a,
32978 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32979 )
32980 }
32981}
32982#[doc = "Multiply"]
32983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"]
32984#[inline]
32985#[target_feature(enable = "neon")]
32986#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32987#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32988#[cfg_attr(
32989 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32990 assert_instr(mul, LANE = 1)
32991)]
32992#[rustc_legacy_const_generics(2)]
32993#[cfg_attr(
32994 not(target_arch = "arm"),
32995 stable(feature = "neon_intrinsics", since = "1.59.0")
32996)]
32997#[cfg_attr(
32998 target_arch = "arm",
32999 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33000)]
33001pub fn vmulq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t {
33002 static_assert_uimm_bits!(LANE, 2);
33003 unsafe {
33004 simd_mul(
33005 a,
33006 simd_shuffle!(
33007 b,
33008 b,
33009 [
33010 LANE as u32,
33011 LANE as u32,
33012 LANE as u32,
33013 LANE as u32,
33014 LANE as u32,
33015 LANE as u32,
33016 LANE as u32,
33017 LANE as u32
33018 ]
33019 ),
33020 )
33021 }
33022}
33023#[doc = "Multiply"]
33024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"]
33025#[inline]
33026#[target_feature(enable = "neon")]
33027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33029#[cfg_attr(
33030 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33031 assert_instr(mul, LANE = 1)
33032)]
33033#[rustc_legacy_const_generics(2)]
33034#[cfg_attr(
33035 not(target_arch = "arm"),
33036 stable(feature = "neon_intrinsics", since = "1.59.0")
33037)]
33038#[cfg_attr(
33039 target_arch = "arm",
33040 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33041)]
33042pub fn vmul_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
33043 static_assert_uimm_bits!(LANE, 1);
33044 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33045}
33046#[doc = "Multiply"]
33047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"]
33048#[inline]
33049#[target_feature(enable = "neon")]
33050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33051#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33052#[cfg_attr(
33053 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33054 assert_instr(mul, LANE = 1)
33055)]
33056#[rustc_legacy_const_generics(2)]
33057#[cfg_attr(
33058 not(target_arch = "arm"),
33059 stable(feature = "neon_intrinsics", since = "1.59.0")
33060)]
33061#[cfg_attr(
33062 target_arch = "arm",
33063 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33064)]
33065pub fn vmulq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t {
33066 static_assert_uimm_bits!(LANE, 1);
33067 unsafe {
33068 simd_mul(
33069 a,
33070 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33071 )
33072 }
33073}
33074#[doc = "Multiply"]
33075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"]
33076#[inline]
33077#[target_feature(enable = "neon")]
33078#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33079#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33080#[cfg_attr(
33081 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33082 assert_instr(mul, LANE = 1)
33083)]
33084#[rustc_legacy_const_generics(2)]
33085#[cfg_attr(
33086 not(target_arch = "arm"),
33087 stable(feature = "neon_intrinsics", since = "1.59.0")
33088)]
33089#[cfg_attr(
33090 target_arch = "arm",
33091 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33092)]
33093pub fn vmul_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
33094 static_assert_uimm_bits!(LANE, 3);
33095 unsafe {
33096 simd_mul(
33097 a,
33098 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33099 )
33100 }
33101}
33102#[doc = "Multiply"]
33103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"]
33104#[inline]
33105#[target_feature(enable = "neon")]
33106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33108#[cfg_attr(
33109 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33110 assert_instr(mul, LANE = 1)
33111)]
33112#[rustc_legacy_const_generics(2)]
33113#[cfg_attr(
33114 not(target_arch = "arm"),
33115 stable(feature = "neon_intrinsics", since = "1.59.0")
33116)]
33117#[cfg_attr(
33118 target_arch = "arm",
33119 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33120)]
33121pub fn vmulq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
33122 static_assert_uimm_bits!(LANE, 3);
33123 unsafe {
33124 simd_mul(
33125 a,
33126 simd_shuffle!(
33127 b,
33128 b,
33129 [
33130 LANE as u32,
33131 LANE as u32,
33132 LANE as u32,
33133 LANE as u32,
33134 LANE as u32,
33135 LANE as u32,
33136 LANE as u32,
33137 LANE as u32
33138 ]
33139 ),
33140 )
33141 }
33142}
33143#[doc = "Multiply"]
33144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"]
33145#[inline]
33146#[target_feature(enable = "neon")]
33147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33149#[cfg_attr(
33150 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33151 assert_instr(mul, LANE = 1)
33152)]
33153#[rustc_legacy_const_generics(2)]
33154#[cfg_attr(
33155 not(target_arch = "arm"),
33156 stable(feature = "neon_intrinsics", since = "1.59.0")
33157)]
33158#[cfg_attr(
33159 target_arch = "arm",
33160 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33161)]
33162pub fn vmul_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
33163 static_assert_uimm_bits!(LANE, 2);
33164 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33165}
33166#[doc = "Multiply"]
33167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"]
33168#[inline]
33169#[target_feature(enable = "neon")]
33170#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33171#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33172#[cfg_attr(
33173 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33174 assert_instr(mul, LANE = 1)
33175)]
33176#[rustc_legacy_const_generics(2)]
33177#[cfg_attr(
33178 not(target_arch = "arm"),
33179 stable(feature = "neon_intrinsics", since = "1.59.0")
33180)]
33181#[cfg_attr(
33182 target_arch = "arm",
33183 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33184)]
33185pub fn vmulq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
33186 static_assert_uimm_bits!(LANE, 2);
33187 unsafe {
33188 simd_mul(
33189 a,
33190 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33191 )
33192 }
33193}
33194#[doc = "Multiply"]
33195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"]
33196#[inline]
33197#[target_feature(enable = "neon")]
33198#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33199#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33200#[cfg_attr(
33201 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33202 assert_instr(mul, LANE = 1)
33203)]
33204#[rustc_legacy_const_generics(2)]
33205#[cfg_attr(
33206 not(target_arch = "arm"),
33207 stable(feature = "neon_intrinsics", since = "1.59.0")
33208)]
33209#[cfg_attr(
33210 target_arch = "arm",
33211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33212)]
33213pub fn vmul_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t {
33214 static_assert_uimm_bits!(LANE, 3);
33215 unsafe {
33216 simd_mul(
33217 a,
33218 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33219 )
33220 }
33221}
33222#[doc = "Multiply"]
33223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"]
33224#[inline]
33225#[target_feature(enable = "neon")]
33226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33227#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33228#[cfg_attr(
33229 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33230 assert_instr(mul, LANE = 1)
33231)]
33232#[rustc_legacy_const_generics(2)]
33233#[cfg_attr(
33234 not(target_arch = "arm"),
33235 stable(feature = "neon_intrinsics", since = "1.59.0")
33236)]
33237#[cfg_attr(
33238 target_arch = "arm",
33239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33240)]
33241pub fn vmulq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
33242 static_assert_uimm_bits!(LANE, 3);
33243 unsafe {
33244 simd_mul(
33245 a,
33246 simd_shuffle!(
33247 b,
33248 b,
33249 [
33250 LANE as u32,
33251 LANE as u32,
33252 LANE as u32,
33253 LANE as u32,
33254 LANE as u32,
33255 LANE as u32,
33256 LANE as u32,
33257 LANE as u32
33258 ]
33259 ),
33260 )
33261 }
33262}
33263#[doc = "Multiply"]
33264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"]
33265#[inline]
33266#[target_feature(enable = "neon")]
33267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33268#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33269#[cfg_attr(
33270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33271 assert_instr(mul, LANE = 1)
33272)]
33273#[rustc_legacy_const_generics(2)]
33274#[cfg_attr(
33275 not(target_arch = "arm"),
33276 stable(feature = "neon_intrinsics", since = "1.59.0")
33277)]
33278#[cfg_attr(
33279 target_arch = "arm",
33280 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33281)]
33282pub fn vmul_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t {
33283 static_assert_uimm_bits!(LANE, 2);
33284 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33285}
33286#[doc = "Multiply"]
33287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"]
33288#[inline]
33289#[target_feature(enable = "neon")]
33290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
33292#[cfg_attr(
33293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33294 assert_instr(mul, LANE = 1)
33295)]
33296#[rustc_legacy_const_generics(2)]
33297#[cfg_attr(
33298 not(target_arch = "arm"),
33299 stable(feature = "neon_intrinsics", since = "1.59.0")
33300)]
33301#[cfg_attr(
33302 target_arch = "arm",
33303 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33304)]
33305pub fn vmulq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
33306 static_assert_uimm_bits!(LANE, 2);
33307 unsafe {
33308 simd_mul(
33309 a,
33310 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33311 )
33312 }
33313}
33314#[doc = "Vector multiply by scalar"]
33315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"]
33316#[inline]
33317#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
33318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33319#[cfg_attr(
33320 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33321 assert_instr(fmul)
33322)]
33323#[target_feature(enable = "neon,fp16")]
33324#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
33325pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
33326 unsafe { simd_mul(a, vdup_n_f16(b)) }
33327}
33328#[doc = "Vector multiply by scalar"]
33329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"]
33330#[inline]
33331#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
33332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33333#[cfg_attr(
33334 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33335 assert_instr(fmul)
33336)]
33337#[target_feature(enable = "neon,fp16")]
33338#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
33339pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
33340 unsafe { simd_mul(a, vdupq_n_f16(b)) }
33341}
33342#[doc = "Vector multiply by scalar"]
33343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"]
33344#[inline]
33345#[target_feature(enable = "neon")]
33346#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33347#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33348#[cfg_attr(
33349 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33350 assert_instr(fmul)
33351)]
33352#[cfg_attr(
33353 not(target_arch = "arm"),
33354 stable(feature = "neon_intrinsics", since = "1.59.0")
33355)]
33356#[cfg_attr(
33357 target_arch = "arm",
33358 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33359)]
33360pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t {
33361 unsafe { simd_mul(a, vdup_n_f32(b)) }
33362}
33363#[doc = "Vector multiply by scalar"]
33364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"]
33365#[inline]
33366#[target_feature(enable = "neon")]
33367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33369#[cfg_attr(
33370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33371 assert_instr(fmul)
33372)]
33373#[cfg_attr(
33374 not(target_arch = "arm"),
33375 stable(feature = "neon_intrinsics", since = "1.59.0")
33376)]
33377#[cfg_attr(
33378 target_arch = "arm",
33379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33380)]
33381pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t {
33382 unsafe { simd_mul(a, vdupq_n_f32(b)) }
33383}
33384#[doc = "Vector multiply by scalar"]
33385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"]
33386#[inline]
33387#[target_feature(enable = "neon")]
33388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33390#[cfg_attr(
33391 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33392 assert_instr(mul)
33393)]
33394#[cfg_attr(
33395 not(target_arch = "arm"),
33396 stable(feature = "neon_intrinsics", since = "1.59.0")
33397)]
33398#[cfg_attr(
33399 target_arch = "arm",
33400 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33401)]
33402pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
33403 unsafe { simd_mul(a, vdup_n_s16(b)) }
33404}
33405#[doc = "Vector multiply by scalar"]
33406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"]
33407#[inline]
33408#[target_feature(enable = "neon")]
33409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33410#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33411#[cfg_attr(
33412 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33413 assert_instr(mul)
33414)]
33415#[cfg_attr(
33416 not(target_arch = "arm"),
33417 stable(feature = "neon_intrinsics", since = "1.59.0")
33418)]
33419#[cfg_attr(
33420 target_arch = "arm",
33421 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33422)]
33423pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
33424 unsafe { simd_mul(a, vdupq_n_s16(b)) }
33425}
33426#[doc = "Vector multiply by scalar"]
33427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"]
33428#[inline]
33429#[target_feature(enable = "neon")]
33430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33431#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33432#[cfg_attr(
33433 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33434 assert_instr(mul)
33435)]
33436#[cfg_attr(
33437 not(target_arch = "arm"),
33438 stable(feature = "neon_intrinsics", since = "1.59.0")
33439)]
33440#[cfg_attr(
33441 target_arch = "arm",
33442 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33443)]
33444pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
33445 unsafe { simd_mul(a, vdup_n_s32(b)) }
33446}
33447#[doc = "Vector multiply by scalar"]
33448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"]
33449#[inline]
33450#[target_feature(enable = "neon")]
33451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33453#[cfg_attr(
33454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33455 assert_instr(mul)
33456)]
33457#[cfg_attr(
33458 not(target_arch = "arm"),
33459 stable(feature = "neon_intrinsics", since = "1.59.0")
33460)]
33461#[cfg_attr(
33462 target_arch = "arm",
33463 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33464)]
33465pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
33466 unsafe { simd_mul(a, vdupq_n_s32(b)) }
33467}
33468#[doc = "Vector multiply by scalar"]
33469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"]
33470#[inline]
33471#[target_feature(enable = "neon")]
33472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33474#[cfg_attr(
33475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33476 assert_instr(mul)
33477)]
33478#[cfg_attr(
33479 not(target_arch = "arm"),
33480 stable(feature = "neon_intrinsics", since = "1.59.0")
33481)]
33482#[cfg_attr(
33483 target_arch = "arm",
33484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33485)]
33486pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t {
33487 unsafe { simd_mul(a, vdup_n_u16(b)) }
33488}
33489#[doc = "Vector multiply by scalar"]
33490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"]
33491#[inline]
33492#[target_feature(enable = "neon")]
33493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33494#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33495#[cfg_attr(
33496 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33497 assert_instr(mul)
33498)]
33499#[cfg_attr(
33500 not(target_arch = "arm"),
33501 stable(feature = "neon_intrinsics", since = "1.59.0")
33502)]
33503#[cfg_attr(
33504 target_arch = "arm",
33505 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33506)]
33507pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t {
33508 unsafe { simd_mul(a, vdupq_n_u16(b)) }
33509}
33510#[doc = "Vector multiply by scalar"]
33511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"]
33512#[inline]
33513#[target_feature(enable = "neon")]
33514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33515#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33516#[cfg_attr(
33517 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33518 assert_instr(mul)
33519)]
33520#[cfg_attr(
33521 not(target_arch = "arm"),
33522 stable(feature = "neon_intrinsics", since = "1.59.0")
33523)]
33524#[cfg_attr(
33525 target_arch = "arm",
33526 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33527)]
33528pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t {
33529 unsafe { simd_mul(a, vdup_n_u32(b)) }
33530}
33531#[doc = "Vector multiply by scalar"]
33532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"]
33533#[inline]
33534#[target_feature(enable = "neon")]
33535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33536#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33537#[cfg_attr(
33538 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33539 assert_instr(mul)
33540)]
33541#[cfg_attr(
33542 not(target_arch = "arm"),
33543 stable(feature = "neon_intrinsics", since = "1.59.0")
33544)]
33545#[cfg_attr(
33546 target_arch = "arm",
33547 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33548)]
33549pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t {
33550 unsafe { simd_mul(a, vdupq_n_u32(b)) }
33551}
33552#[doc = "Polynomial multiply"]
33553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"]
33554#[inline]
33555#[target_feature(enable = "neon")]
33556#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33558#[cfg_attr(
33559 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33560 assert_instr(pmul)
33561)]
33562#[cfg_attr(
33563 not(target_arch = "arm"),
33564 stable(feature = "neon_intrinsics", since = "1.59.0")
33565)]
33566#[cfg_attr(
33567 target_arch = "arm",
33568 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33569)]
33570pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
33571 unsafe extern "unadjusted" {
33572 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v8i8")]
33573 #[cfg_attr(
33574 any(target_arch = "aarch64", target_arch = "arm64ec"),
33575 link_name = "llvm.aarch64.neon.pmul.v8i8"
33576 )]
33577 fn _vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t;
33578 }
33579 unsafe { _vmul_p8(a, b) }
33580}
33581#[doc = "Polynomial multiply"]
33582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"]
33583#[inline]
33584#[target_feature(enable = "neon")]
33585#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33586#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33587#[cfg_attr(
33588 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33589 assert_instr(pmul)
33590)]
33591#[cfg_attr(
33592 not(target_arch = "arm"),
33593 stable(feature = "neon_intrinsics", since = "1.59.0")
33594)]
33595#[cfg_attr(
33596 target_arch = "arm",
33597 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33598)]
33599pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
33600 unsafe extern "unadjusted" {
33601 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v16i8")]
33602 #[cfg_attr(
33603 any(target_arch = "aarch64", target_arch = "arm64ec"),
33604 link_name = "llvm.aarch64.neon.pmul.v16i8"
33605 )]
33606 fn _vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t;
33607 }
33608 unsafe { _vmulq_p8(a, b) }
33609}
33610#[doc = "Multiply"]
33611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"]
33612#[inline]
33613#[target_feature(enable = "neon")]
33614#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33615#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33616#[cfg_attr(
33617 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33618 assert_instr(mul)
33619)]
33620#[cfg_attr(
33621 not(target_arch = "arm"),
33622 stable(feature = "neon_intrinsics", since = "1.59.0")
33623)]
33624#[cfg_attr(
33625 target_arch = "arm",
33626 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33627)]
33628pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
33629 unsafe { simd_mul(a, b) }
33630}
33631#[doc = "Multiply"]
33632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"]
33633#[inline]
33634#[target_feature(enable = "neon")]
33635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33636#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33637#[cfg_attr(
33638 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33639 assert_instr(mul)
33640)]
33641#[cfg_attr(
33642 not(target_arch = "arm"),
33643 stable(feature = "neon_intrinsics", since = "1.59.0")
33644)]
33645#[cfg_attr(
33646 target_arch = "arm",
33647 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33648)]
33649pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
33650 unsafe { simd_mul(a, b) }
33651}
33652#[doc = "Multiply"]
33653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"]
33654#[inline]
33655#[target_feature(enable = "neon")]
33656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33657#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33658#[cfg_attr(
33659 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33660 assert_instr(mul)
33661)]
33662#[cfg_attr(
33663 not(target_arch = "arm"),
33664 stable(feature = "neon_intrinsics", since = "1.59.0")
33665)]
33666#[cfg_attr(
33667 target_arch = "arm",
33668 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33669)]
33670pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
33671 unsafe { simd_mul(a, b) }
33672}
33673#[doc = "Multiply"]
33674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"]
33675#[inline]
33676#[target_feature(enable = "neon")]
33677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33678#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33679#[cfg_attr(
33680 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33681 assert_instr(mul)
33682)]
33683#[cfg_attr(
33684 not(target_arch = "arm"),
33685 stable(feature = "neon_intrinsics", since = "1.59.0")
33686)]
33687#[cfg_attr(
33688 target_arch = "arm",
33689 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33690)]
33691pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
33692 unsafe { simd_mul(a, b) }
33693}
33694#[doc = "Multiply"]
33695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"]
33696#[inline]
33697#[target_feature(enable = "neon")]
33698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33699#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33700#[cfg_attr(
33701 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33702 assert_instr(mul)
33703)]
33704#[cfg_attr(
33705 not(target_arch = "arm"),
33706 stable(feature = "neon_intrinsics", since = "1.59.0")
33707)]
33708#[cfg_attr(
33709 target_arch = "arm",
33710 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33711)]
33712pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
33713 unsafe { simd_mul(a, b) }
33714}
33715#[doc = "Multiply"]
33716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"]
33717#[inline]
33718#[target_feature(enable = "neon")]
33719#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33720#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33721#[cfg_attr(
33722 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33723 assert_instr(mul)
33724)]
33725#[cfg_attr(
33726 not(target_arch = "arm"),
33727 stable(feature = "neon_intrinsics", since = "1.59.0")
33728)]
33729#[cfg_attr(
33730 target_arch = "arm",
33731 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33732)]
33733pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
33734 unsafe { simd_mul(a, b) }
33735}
33736#[doc = "Multiply"]
33737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"]
33738#[inline]
33739#[target_feature(enable = "neon")]
33740#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33741#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33742#[cfg_attr(
33743 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33744 assert_instr(mul)
33745)]
33746#[cfg_attr(
33747 not(target_arch = "arm"),
33748 stable(feature = "neon_intrinsics", since = "1.59.0")
33749)]
33750#[cfg_attr(
33751 target_arch = "arm",
33752 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33753)]
33754pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
33755 unsafe { simd_mul(a, b) }
33756}
33757#[doc = "Multiply"]
33758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"]
33759#[inline]
33760#[target_feature(enable = "neon")]
33761#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33762#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33763#[cfg_attr(
33764 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33765 assert_instr(mul)
33766)]
33767#[cfg_attr(
33768 not(target_arch = "arm"),
33769 stable(feature = "neon_intrinsics", since = "1.59.0")
33770)]
33771#[cfg_attr(
33772 target_arch = "arm",
33773 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33774)]
33775pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
33776 unsafe { simd_mul(a, b) }
33777}
33778#[doc = "Multiply"]
33779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"]
33780#[inline]
33781#[target_feature(enable = "neon")]
33782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33783#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33784#[cfg_attr(
33785 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33786 assert_instr(mul)
33787)]
33788#[cfg_attr(
33789 not(target_arch = "arm"),
33790 stable(feature = "neon_intrinsics", since = "1.59.0")
33791)]
33792#[cfg_attr(
33793 target_arch = "arm",
33794 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33795)]
33796pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
33797 unsafe { simd_mul(a, b) }
33798}
33799#[doc = "Multiply"]
33800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"]
33801#[inline]
33802#[target_feature(enable = "neon")]
33803#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33804#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33805#[cfg_attr(
33806 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33807 assert_instr(mul)
33808)]
33809#[cfg_attr(
33810 not(target_arch = "arm"),
33811 stable(feature = "neon_intrinsics", since = "1.59.0")
33812)]
33813#[cfg_attr(
33814 target_arch = "arm",
33815 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33816)]
33817pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
33818 unsafe { simd_mul(a, b) }
33819}
33820#[doc = "Multiply"]
33821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"]
33822#[inline]
33823#[target_feature(enable = "neon")]
33824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33825#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33826#[cfg_attr(
33827 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33828 assert_instr(mul)
33829)]
33830#[cfg_attr(
33831 not(target_arch = "arm"),
33832 stable(feature = "neon_intrinsics", since = "1.59.0")
33833)]
33834#[cfg_attr(
33835 target_arch = "arm",
33836 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33837)]
33838pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
33839 unsafe { simd_mul(a, b) }
33840}
33841#[doc = "Multiply"]
33842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"]
33843#[inline]
33844#[target_feature(enable = "neon")]
33845#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33846#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33847#[cfg_attr(
33848 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33849 assert_instr(mul)
33850)]
33851#[cfg_attr(
33852 not(target_arch = "arm"),
33853 stable(feature = "neon_intrinsics", since = "1.59.0")
33854)]
33855#[cfg_attr(
33856 target_arch = "arm",
33857 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33858)]
33859pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
33860 unsafe { simd_mul(a, b) }
33861}
33862#[doc = "Vector long multiply by scalar"]
33863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"]
33864#[inline]
33865#[target_feature(enable = "neon")]
33866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33868#[cfg_attr(
33869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33870 assert_instr(smull, LANE = 1)
33871)]
33872#[rustc_legacy_const_generics(2)]
33873#[cfg_attr(
33874 not(target_arch = "arm"),
33875 stable(feature = "neon_intrinsics", since = "1.59.0")
33876)]
33877#[cfg_attr(
33878 target_arch = "arm",
33879 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33880)]
33881pub fn vmull_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
33882 static_assert_uimm_bits!(LANE, 2);
33883 unsafe {
33884 vmull_s16(
33885 a,
33886 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33887 )
33888 }
33889}
33890#[doc = "Vector long multiply by scalar"]
33891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"]
33892#[inline]
33893#[target_feature(enable = "neon")]
33894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33896#[cfg_attr(
33897 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33898 assert_instr(smull, LANE = 1)
33899)]
33900#[rustc_legacy_const_generics(2)]
33901#[cfg_attr(
33902 not(target_arch = "arm"),
33903 stable(feature = "neon_intrinsics", since = "1.59.0")
33904)]
33905#[cfg_attr(
33906 target_arch = "arm",
33907 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33908)]
33909pub fn vmull_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t {
33910 static_assert_uimm_bits!(LANE, 3);
33911 unsafe {
33912 vmull_s16(
33913 a,
33914 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33915 )
33916 }
33917}
33918#[doc = "Vector long multiply by scalar"]
33919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"]
33920#[inline]
33921#[target_feature(enable = "neon")]
33922#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33923#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33924#[cfg_attr(
33925 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33926 assert_instr(smull, LANE = 1)
33927)]
33928#[rustc_legacy_const_generics(2)]
33929#[cfg_attr(
33930 not(target_arch = "arm"),
33931 stable(feature = "neon_intrinsics", since = "1.59.0")
33932)]
33933#[cfg_attr(
33934 target_arch = "arm",
33935 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33936)]
33937pub fn vmull_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
33938 static_assert_uimm_bits!(LANE, 1);
33939 unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33940}
33941#[doc = "Vector long multiply by scalar"]
33942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"]
33943#[inline]
33944#[target_feature(enable = "neon")]
33945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33946#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33947#[cfg_attr(
33948 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33949 assert_instr(smull, LANE = 1)
33950)]
33951#[rustc_legacy_const_generics(2)]
33952#[cfg_attr(
33953 not(target_arch = "arm"),
33954 stable(feature = "neon_intrinsics", since = "1.59.0")
33955)]
33956#[cfg_attr(
33957 target_arch = "arm",
33958 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33959)]
33960pub fn vmull_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t {
33961 static_assert_uimm_bits!(LANE, 2);
33962 unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33963}
33964#[doc = "Vector long multiply by scalar"]
33965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"]
33966#[inline]
33967#[target_feature(enable = "neon")]
33968#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33969#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33970#[cfg_attr(
33971 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33972 assert_instr(umull, LANE = 1)
33973)]
33974#[rustc_legacy_const_generics(2)]
33975#[cfg_attr(
33976 not(target_arch = "arm"),
33977 stable(feature = "neon_intrinsics", since = "1.59.0")
33978)]
33979#[cfg_attr(
33980 target_arch = "arm",
33981 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33982)]
33983pub fn vmull_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
33984 static_assert_uimm_bits!(LANE, 2);
33985 unsafe {
33986 vmull_u16(
33987 a,
33988 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33989 )
33990 }
33991}
33992#[doc = "Vector long multiply by scalar"]
33993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"]
33994#[inline]
33995#[target_feature(enable = "neon")]
33996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33997#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33998#[cfg_attr(
33999 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34000 assert_instr(umull, LANE = 1)
34001)]
34002#[rustc_legacy_const_generics(2)]
34003#[cfg_attr(
34004 not(target_arch = "arm"),
34005 stable(feature = "neon_intrinsics", since = "1.59.0")
34006)]
34007#[cfg_attr(
34008 target_arch = "arm",
34009 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34010)]
34011pub fn vmull_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t {
34012 static_assert_uimm_bits!(LANE, 3);
34013 unsafe {
34014 vmull_u16(
34015 a,
34016 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
34017 )
34018 }
34019}
34020#[doc = "Vector long multiply by scalar"]
34021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"]
34022#[inline]
34023#[target_feature(enable = "neon")]
34024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34025#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
34026#[cfg_attr(
34027 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34028 assert_instr(umull, LANE = 1)
34029)]
34030#[rustc_legacy_const_generics(2)]
34031#[cfg_attr(
34032 not(target_arch = "arm"),
34033 stable(feature = "neon_intrinsics", since = "1.59.0")
34034)]
34035#[cfg_attr(
34036 target_arch = "arm",
34037 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34038)]
34039pub fn vmull_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
34040 static_assert_uimm_bits!(LANE, 1);
34041 unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
34042}
34043#[doc = "Vector long multiply by scalar"]
34044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"]
34045#[inline]
34046#[target_feature(enable = "neon")]
34047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34048#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
34049#[cfg_attr(
34050 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34051 assert_instr(umull, LANE = 1)
34052)]
34053#[rustc_legacy_const_generics(2)]
34054#[cfg_attr(
34055 not(target_arch = "arm"),
34056 stable(feature = "neon_intrinsics", since = "1.59.0")
34057)]
34058#[cfg_attr(
34059 target_arch = "arm",
34060 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34061)]
34062pub fn vmull_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t {
34063 static_assert_uimm_bits!(LANE, 2);
34064 unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
34065}
34066#[doc = "Vector long multiply with scalar"]
34067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"]
34068#[inline]
34069#[target_feature(enable = "neon")]
34070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34071#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34072#[cfg_attr(
34073 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34074 assert_instr(smull)
34075)]
34076#[cfg_attr(
34077 not(target_arch = "arm"),
34078 stable(feature = "neon_intrinsics", since = "1.59.0")
34079)]
34080#[cfg_attr(
34081 target_arch = "arm",
34082 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34083)]
34084pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
34085 vmull_s16(a, vdup_n_s16(b))
34086}
34087#[doc = "Vector long multiply with scalar"]
34088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"]
34089#[inline]
34090#[target_feature(enable = "neon")]
34091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34093#[cfg_attr(
34094 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34095 assert_instr(smull)
34096)]
34097#[cfg_attr(
34098 not(target_arch = "arm"),
34099 stable(feature = "neon_intrinsics", since = "1.59.0")
34100)]
34101#[cfg_attr(
34102 target_arch = "arm",
34103 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34104)]
34105pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
34106 vmull_s32(a, vdup_n_s32(b))
34107}
34108#[doc = "Vector long multiply with scalar"]
34109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"]
34110#[inline]
34111#[target_feature(enable = "neon")]
34112#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34113#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34114#[cfg_attr(
34115 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34116 assert_instr(umull)
34117)]
34118#[cfg_attr(
34119 not(target_arch = "arm"),
34120 stable(feature = "neon_intrinsics", since = "1.59.0")
34121)]
34122#[cfg_attr(
34123 target_arch = "arm",
34124 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34125)]
34126pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t {
34127 vmull_u16(a, vdup_n_u16(b))
34128}
34129#[doc = "Vector long multiply with scalar"]
34130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"]
34131#[inline]
34132#[target_feature(enable = "neon")]
34133#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
34135#[cfg_attr(
34136 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34137 assert_instr(umull)
34138)]
34139#[cfg_attr(
34140 not(target_arch = "arm"),
34141 stable(feature = "neon_intrinsics", since = "1.59.0")
34142)]
34143#[cfg_attr(
34144 target_arch = "arm",
34145 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34146)]
34147pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t {
34148 vmull_u32(a, vdup_n_u32(b))
34149}
34150#[doc = "Polynomial multiply long"]
34151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"]
34152#[inline]
34153#[target_feature(enable = "neon")]
34154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34155#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))]
34156#[cfg_attr(
34157 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34158 assert_instr(pmull)
34159)]
34160#[cfg_attr(
34161 not(target_arch = "arm"),
34162 stable(feature = "neon_intrinsics", since = "1.59.0")
34163)]
34164#[cfg_attr(
34165 target_arch = "arm",
34166 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34167)]
34168pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t {
34169 unsafe extern "unadjusted" {
34170 #[cfg_attr(
34171 any(target_arch = "aarch64", target_arch = "arm64ec"),
34172 link_name = "llvm.aarch64.neon.pmull.v8i16"
34173 )]
34174 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullp.v8i16")]
34175 fn _vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t;
34176 }
34177 unsafe { _vmull_p8(a, b) }
34178}
34179#[doc = "Signed multiply long"]
34180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"]
34181#[inline]
34182#[target_feature(enable = "neon")]
34183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34184#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))]
34185#[cfg_attr(
34186 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34187 assert_instr(smull)
34188)]
34189#[cfg_attr(
34190 not(target_arch = "arm"),
34191 stable(feature = "neon_intrinsics", since = "1.59.0")
34192)]
34193#[cfg_attr(
34194 target_arch = "arm",
34195 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34196)]
34197pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
34198 unsafe extern "unadjusted" {
34199 #[cfg_attr(
34200 any(target_arch = "aarch64", target_arch = "arm64ec"),
34201 link_name = "llvm.aarch64.neon.smull.v4i16"
34202 )]
34203 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i16")]
34204 fn _vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t;
34205 }
34206 unsafe { _vmull_s16(a, b) }
34207}
34208#[doc = "Signed multiply long"]
34209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"]
34210#[inline]
34211#[target_feature(enable = "neon")]
34212#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34213#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))]
34214#[cfg_attr(
34215 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34216 assert_instr(smull)
34217)]
34218#[cfg_attr(
34219 not(target_arch = "arm"),
34220 stable(feature = "neon_intrinsics", since = "1.59.0")
34221)]
34222#[cfg_attr(
34223 target_arch = "arm",
34224 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34225)]
34226pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
34227 unsafe extern "unadjusted" {
34228 #[cfg_attr(
34229 any(target_arch = "aarch64", target_arch = "arm64ec"),
34230 link_name = "llvm.aarch64.neon.smull.v2i32"
34231 )]
34232 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i32")]
34233 fn _vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t;
34234 }
34235 unsafe { _vmull_s32(a, b) }
34236}
34237#[doc = "Signed multiply long"]
34238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"]
34239#[inline]
34240#[target_feature(enable = "neon")]
34241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34242#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))]
34243#[cfg_attr(
34244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34245 assert_instr(smull)
34246)]
34247#[cfg_attr(
34248 not(target_arch = "arm"),
34249 stable(feature = "neon_intrinsics", since = "1.59.0")
34250)]
34251#[cfg_attr(
34252 target_arch = "arm",
34253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34254)]
34255pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
34256 unsafe extern "unadjusted" {
34257 #[cfg_attr(
34258 any(target_arch = "aarch64", target_arch = "arm64ec"),
34259 link_name = "llvm.aarch64.neon.smull.v8i8"
34260 )]
34261 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i8")]
34262 fn _vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t;
34263 }
34264 unsafe { _vmull_s8(a, b) }
34265}
34266#[doc = "Unsigned multiply long"]
34267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"]
34268#[inline]
34269#[target_feature(enable = "neon")]
34270#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34271#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))]
34272#[cfg_attr(
34273 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34274 assert_instr(umull)
34275)]
34276#[cfg_attr(
34277 not(target_arch = "arm"),
34278 stable(feature = "neon_intrinsics", since = "1.59.0")
34279)]
34280#[cfg_attr(
34281 target_arch = "arm",
34282 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34283)]
34284pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
34285 unsafe extern "unadjusted" {
34286 #[cfg_attr(
34287 any(target_arch = "aarch64", target_arch = "arm64ec"),
34288 link_name = "llvm.aarch64.neon.umull.v8i8"
34289 )]
34290 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i8")]
34291 fn _vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t;
34292 }
34293 unsafe { _vmull_u8(a, b) }
34294}
34295#[doc = "Unsigned multiply long"]
34296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"]
34297#[inline]
34298#[target_feature(enable = "neon")]
34299#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34300#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))]
34301#[cfg_attr(
34302 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34303 assert_instr(umull)
34304)]
34305#[cfg_attr(
34306 not(target_arch = "arm"),
34307 stable(feature = "neon_intrinsics", since = "1.59.0")
34308)]
34309#[cfg_attr(
34310 target_arch = "arm",
34311 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34312)]
34313pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
34314 unsafe extern "unadjusted" {
34315 #[cfg_attr(
34316 any(target_arch = "aarch64", target_arch = "arm64ec"),
34317 link_name = "llvm.aarch64.neon.umull.v4i16"
34318 )]
34319 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i16")]
34320 fn _vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t;
34321 }
34322 unsafe { _vmull_u16(a, b) }
34323}
34324#[doc = "Unsigned multiply long"]
34325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"]
34326#[inline]
34327#[target_feature(enable = "neon")]
34328#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34329#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))]
34330#[cfg_attr(
34331 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34332 assert_instr(umull)
34333)]
34334#[cfg_attr(
34335 not(target_arch = "arm"),
34336 stable(feature = "neon_intrinsics", since = "1.59.0")
34337)]
34338#[cfg_attr(
34339 target_arch = "arm",
34340 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34341)]
34342pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
34343 unsafe extern "unadjusted" {
34344 #[cfg_attr(
34345 any(target_arch = "aarch64", target_arch = "arm64ec"),
34346 link_name = "llvm.aarch64.neon.umull.v2i32"
34347 )]
34348 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i32")]
34349 fn _vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t;
34350 }
34351 unsafe { _vmull_u32(a, b) }
34352}
34353#[doc = "Vector bitwise not."]
34354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"]
34355#[inline]
34356#[target_feature(enable = "neon")]
34357#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34358#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34359#[cfg_attr(
34360 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34361 assert_instr(mvn)
34362)]
34363#[cfg_attr(
34364 not(target_arch = "arm"),
34365 stable(feature = "neon_intrinsics", since = "1.59.0")
34366)]
34367#[cfg_attr(
34368 target_arch = "arm",
34369 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34370)]
34371pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t {
34372 let b = poly8x8_t::splat(255);
34373 unsafe { simd_xor(a, b) }
34374}
34375#[doc = "Vector bitwise not."]
34376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s16)"]
34377#[inline]
34378#[target_feature(enable = "neon")]
34379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34380#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34381#[cfg_attr(
34382 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34383 assert_instr(mvn)
34384)]
34385#[cfg_attr(
34386 not(target_arch = "arm"),
34387 stable(feature = "neon_intrinsics", since = "1.59.0")
34388)]
34389#[cfg_attr(
34390 target_arch = "arm",
34391 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34392)]
34393pub fn vmvn_s16(a: int16x4_t) -> int16x4_t {
34394 let b = int16x4_t::splat(-1);
34395 unsafe { simd_xor(a, b) }
34396}
34397#[doc = "Vector bitwise not."]
34398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s32)"]
34399#[inline]
34400#[target_feature(enable = "neon")]
34401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34403#[cfg_attr(
34404 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34405 assert_instr(mvn)
34406)]
34407#[cfg_attr(
34408 not(target_arch = "arm"),
34409 stable(feature = "neon_intrinsics", since = "1.59.0")
34410)]
34411#[cfg_attr(
34412 target_arch = "arm",
34413 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34414)]
34415pub fn vmvn_s32(a: int32x2_t) -> int32x2_t {
34416 let b = int32x2_t::splat(-1);
34417 unsafe { simd_xor(a, b) }
34418}
34419#[doc = "Vector bitwise not."]
34420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s8)"]
34421#[inline]
34422#[target_feature(enable = "neon")]
34423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34424#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34425#[cfg_attr(
34426 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34427 assert_instr(mvn)
34428)]
34429#[cfg_attr(
34430 not(target_arch = "arm"),
34431 stable(feature = "neon_intrinsics", since = "1.59.0")
34432)]
34433#[cfg_attr(
34434 target_arch = "arm",
34435 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34436)]
34437pub fn vmvn_s8(a: int8x8_t) -> int8x8_t {
34438 let b = int8x8_t::splat(-1);
34439 unsafe { simd_xor(a, b) }
34440}
34441#[doc = "Vector bitwise not."]
34442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u16)"]
34443#[inline]
34444#[target_feature(enable = "neon")]
34445#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34446#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34447#[cfg_attr(
34448 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34449 assert_instr(mvn)
34450)]
34451#[cfg_attr(
34452 not(target_arch = "arm"),
34453 stable(feature = "neon_intrinsics", since = "1.59.0")
34454)]
34455#[cfg_attr(
34456 target_arch = "arm",
34457 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34458)]
34459pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t {
34460 let b = uint16x4_t::splat(65_535);
34461 unsafe { simd_xor(a, b) }
34462}
34463#[doc = "Vector bitwise not."]
34464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u32)"]
34465#[inline]
34466#[target_feature(enable = "neon")]
34467#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34468#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34469#[cfg_attr(
34470 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34471 assert_instr(mvn)
34472)]
34473#[cfg_attr(
34474 not(target_arch = "arm"),
34475 stable(feature = "neon_intrinsics", since = "1.59.0")
34476)]
34477#[cfg_attr(
34478 target_arch = "arm",
34479 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34480)]
34481pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t {
34482 let b = uint32x2_t::splat(4_294_967_295);
34483 unsafe { simd_xor(a, b) }
34484}
34485#[doc = "Vector bitwise not."]
34486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u8)"]
34487#[inline]
34488#[target_feature(enable = "neon")]
34489#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34490#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34491#[cfg_attr(
34492 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34493 assert_instr(mvn)
34494)]
34495#[cfg_attr(
34496 not(target_arch = "arm"),
34497 stable(feature = "neon_intrinsics", since = "1.59.0")
34498)]
34499#[cfg_attr(
34500 target_arch = "arm",
34501 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34502)]
34503pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t {
34504 let b = uint8x8_t::splat(255);
34505 unsafe { simd_xor(a, b) }
34506}
34507#[doc = "Vector bitwise not."]
34508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_p8)"]
34509#[inline]
34510#[target_feature(enable = "neon")]
34511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34513#[cfg_attr(
34514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34515 assert_instr(mvn)
34516)]
34517#[cfg_attr(
34518 not(target_arch = "arm"),
34519 stable(feature = "neon_intrinsics", since = "1.59.0")
34520)]
34521#[cfg_attr(
34522 target_arch = "arm",
34523 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34524)]
34525pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t {
34526 let b = poly8x16_t::splat(255);
34527 unsafe { simd_xor(a, b) }
34528}
34529#[doc = "Vector bitwise not."]
34530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s16)"]
34531#[inline]
34532#[target_feature(enable = "neon")]
34533#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34534#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34535#[cfg_attr(
34536 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34537 assert_instr(mvn)
34538)]
34539#[cfg_attr(
34540 not(target_arch = "arm"),
34541 stable(feature = "neon_intrinsics", since = "1.59.0")
34542)]
34543#[cfg_attr(
34544 target_arch = "arm",
34545 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34546)]
34547pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t {
34548 let b = int16x8_t::splat(-1);
34549 unsafe { simd_xor(a, b) }
34550}
34551#[doc = "Vector bitwise not."]
34552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s32)"]
34553#[inline]
34554#[target_feature(enable = "neon")]
34555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34556#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34557#[cfg_attr(
34558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34559 assert_instr(mvn)
34560)]
34561#[cfg_attr(
34562 not(target_arch = "arm"),
34563 stable(feature = "neon_intrinsics", since = "1.59.0")
34564)]
34565#[cfg_attr(
34566 target_arch = "arm",
34567 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34568)]
34569pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t {
34570 let b = int32x4_t::splat(-1);
34571 unsafe { simd_xor(a, b) }
34572}
34573#[doc = "Vector bitwise not."]
34574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s8)"]
34575#[inline]
34576#[target_feature(enable = "neon")]
34577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34579#[cfg_attr(
34580 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34581 assert_instr(mvn)
34582)]
34583#[cfg_attr(
34584 not(target_arch = "arm"),
34585 stable(feature = "neon_intrinsics", since = "1.59.0")
34586)]
34587#[cfg_attr(
34588 target_arch = "arm",
34589 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34590)]
34591pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t {
34592 let b = int8x16_t::splat(-1);
34593 unsafe { simd_xor(a, b) }
34594}
34595#[doc = "Vector bitwise not."]
34596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u16)"]
34597#[inline]
34598#[target_feature(enable = "neon")]
34599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34600#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34601#[cfg_attr(
34602 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34603 assert_instr(mvn)
34604)]
34605#[cfg_attr(
34606 not(target_arch = "arm"),
34607 stable(feature = "neon_intrinsics", since = "1.59.0")
34608)]
34609#[cfg_attr(
34610 target_arch = "arm",
34611 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34612)]
34613pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t {
34614 let b = uint16x8_t::splat(65_535);
34615 unsafe { simd_xor(a, b) }
34616}
34617#[doc = "Vector bitwise not."]
34618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u32)"]
34619#[inline]
34620#[target_feature(enable = "neon")]
34621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34622#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34623#[cfg_attr(
34624 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34625 assert_instr(mvn)
34626)]
34627#[cfg_attr(
34628 not(target_arch = "arm"),
34629 stable(feature = "neon_intrinsics", since = "1.59.0")
34630)]
34631#[cfg_attr(
34632 target_arch = "arm",
34633 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34634)]
34635pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t {
34636 let b = uint32x4_t::splat(4_294_967_295);
34637 unsafe { simd_xor(a, b) }
34638}
34639#[doc = "Vector bitwise not."]
34640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u8)"]
34641#[inline]
34642#[target_feature(enable = "neon")]
34643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34645#[cfg_attr(
34646 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34647 assert_instr(mvn)
34648)]
34649#[cfg_attr(
34650 not(target_arch = "arm"),
34651 stable(feature = "neon_intrinsics", since = "1.59.0")
34652)]
34653#[cfg_attr(
34654 target_arch = "arm",
34655 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34656)]
34657pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t {
34658 let b = uint8x16_t::splat(255);
34659 unsafe { simd_xor(a, b) }
34660}
34661#[doc = "Negate"]
34662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"]
34663#[inline]
34664#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
34665#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
34666#[cfg_attr(
34667 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34668 assert_instr(fneg)
34669)]
34670#[target_feature(enable = "neon,fp16")]
34671#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
34672pub fn vneg_f16(a: float16x4_t) -> float16x4_t {
34673 unsafe { simd_neg(a) }
34674}
34675#[doc = "Negate"]
34676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"]
34677#[inline]
34678#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
34679#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
34680#[cfg_attr(
34681 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34682 assert_instr(fneg)
34683)]
34684#[target_feature(enable = "neon,fp16")]
34685#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
34686pub fn vnegq_f16(a: float16x8_t) -> float16x8_t {
34687 unsafe { simd_neg(a) }
34688}
34689#[doc = "Negate"]
34690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"]
34691#[inline]
34692#[target_feature(enable = "neon")]
34693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34694#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
34695#[cfg_attr(
34696 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34697 assert_instr(fneg)
34698)]
34699#[cfg_attr(
34700 not(target_arch = "arm"),
34701 stable(feature = "neon_intrinsics", since = "1.59.0")
34702)]
34703#[cfg_attr(
34704 target_arch = "arm",
34705 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34706)]
34707pub fn vneg_f32(a: float32x2_t) -> float32x2_t {
34708 unsafe { simd_neg(a) }
34709}
34710#[doc = "Negate"]
34711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"]
34712#[inline]
34713#[target_feature(enable = "neon")]
34714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34715#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
34716#[cfg_attr(
34717 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34718 assert_instr(fneg)
34719)]
34720#[cfg_attr(
34721 not(target_arch = "arm"),
34722 stable(feature = "neon_intrinsics", since = "1.59.0")
34723)]
34724#[cfg_attr(
34725 target_arch = "arm",
34726 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34727)]
34728pub fn vnegq_f32(a: float32x4_t) -> float32x4_t {
34729 unsafe { simd_neg(a) }
34730}
34731#[doc = "Negate"]
34732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"]
34733#[inline]
34734#[target_feature(enable = "neon")]
34735#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34736#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
34737#[cfg_attr(
34738 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34739 assert_instr(neg)
34740)]
34741#[cfg_attr(
34742 not(target_arch = "arm"),
34743 stable(feature = "neon_intrinsics", since = "1.59.0")
34744)]
34745#[cfg_attr(
34746 target_arch = "arm",
34747 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34748)]
34749pub fn vneg_s8(a: int8x8_t) -> int8x8_t {
34750 unsafe { simd_neg(a) }
34751}
34752#[doc = "Negate"]
34753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"]
34754#[inline]
34755#[target_feature(enable = "neon")]
34756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34757#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
34758#[cfg_attr(
34759 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34760 assert_instr(neg)
34761)]
34762#[cfg_attr(
34763 not(target_arch = "arm"),
34764 stable(feature = "neon_intrinsics", since = "1.59.0")
34765)]
34766#[cfg_attr(
34767 target_arch = "arm",
34768 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34769)]
34770pub fn vnegq_s8(a: int8x16_t) -> int8x16_t {
34771 unsafe { simd_neg(a) }
34772}
34773#[doc = "Negate"]
34774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"]
34775#[inline]
34776#[target_feature(enable = "neon")]
34777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34778#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
34779#[cfg_attr(
34780 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34781 assert_instr(neg)
34782)]
34783#[cfg_attr(
34784 not(target_arch = "arm"),
34785 stable(feature = "neon_intrinsics", since = "1.59.0")
34786)]
34787#[cfg_attr(
34788 target_arch = "arm",
34789 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34790)]
34791pub fn vneg_s16(a: int16x4_t) -> int16x4_t {
34792 unsafe { simd_neg(a) }
34793}
34794#[doc = "Negate"]
34795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"]
34796#[inline]
34797#[target_feature(enable = "neon")]
34798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34799#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
34800#[cfg_attr(
34801 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34802 assert_instr(neg)
34803)]
34804#[cfg_attr(
34805 not(target_arch = "arm"),
34806 stable(feature = "neon_intrinsics", since = "1.59.0")
34807)]
34808#[cfg_attr(
34809 target_arch = "arm",
34810 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34811)]
34812pub fn vnegq_s16(a: int16x8_t) -> int16x8_t {
34813 unsafe { simd_neg(a) }
34814}
34815#[doc = "Negate"]
34816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"]
34817#[inline]
34818#[target_feature(enable = "neon")]
34819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34820#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
34821#[cfg_attr(
34822 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34823 assert_instr(neg)
34824)]
34825#[cfg_attr(
34826 not(target_arch = "arm"),
34827 stable(feature = "neon_intrinsics", since = "1.59.0")
34828)]
34829#[cfg_attr(
34830 target_arch = "arm",
34831 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34832)]
34833pub fn vneg_s32(a: int32x2_t) -> int32x2_t {
34834 unsafe { simd_neg(a) }
34835}
34836#[doc = "Negate"]
34837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"]
34838#[inline]
34839#[target_feature(enable = "neon")]
34840#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34841#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
34842#[cfg_attr(
34843 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34844 assert_instr(neg)
34845)]
34846#[cfg_attr(
34847 not(target_arch = "arm"),
34848 stable(feature = "neon_intrinsics", since = "1.59.0")
34849)]
34850#[cfg_attr(
34851 target_arch = "arm",
34852 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34853)]
34854pub fn vnegq_s32(a: int32x4_t) -> int32x4_t {
34855 unsafe { simd_neg(a) }
34856}
34857#[doc = "Vector bitwise inclusive OR NOT"]
34858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s16)"]
34859#[inline]
34860#[target_feature(enable = "neon")]
34861#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34862#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34863#[cfg_attr(
34864 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34865 assert_instr(orn)
34866)]
34867#[cfg_attr(
34868 not(target_arch = "arm"),
34869 stable(feature = "neon_intrinsics", since = "1.59.0")
34870)]
34871#[cfg_attr(
34872 target_arch = "arm",
34873 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34874)]
34875pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
34876 let c = int16x4_t::splat(-1);
34877 unsafe { simd_or(simd_xor(b, c), a) }
34878}
34879#[doc = "Vector bitwise inclusive OR NOT"]
34880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s32)"]
34881#[inline]
34882#[target_feature(enable = "neon")]
34883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34885#[cfg_attr(
34886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34887 assert_instr(orn)
34888)]
34889#[cfg_attr(
34890 not(target_arch = "arm"),
34891 stable(feature = "neon_intrinsics", since = "1.59.0")
34892)]
34893#[cfg_attr(
34894 target_arch = "arm",
34895 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34896)]
34897pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
34898 let c = int32x2_t::splat(-1);
34899 unsafe { simd_or(simd_xor(b, c), a) }
34900}
34901#[doc = "Vector bitwise inclusive OR NOT"]
34902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s64)"]
34903#[inline]
34904#[target_feature(enable = "neon")]
34905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34907#[cfg_attr(
34908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34909 assert_instr(orn)
34910)]
34911#[cfg_attr(
34912 not(target_arch = "arm"),
34913 stable(feature = "neon_intrinsics", since = "1.59.0")
34914)]
34915#[cfg_attr(
34916 target_arch = "arm",
34917 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34918)]
34919pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
34920 let c = int64x1_t::splat(-1);
34921 unsafe { simd_or(simd_xor(b, c), a) }
34922}
34923#[doc = "Vector bitwise inclusive OR NOT"]
34924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s8)"]
34925#[inline]
34926#[target_feature(enable = "neon")]
34927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34929#[cfg_attr(
34930 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34931 assert_instr(orn)
34932)]
34933#[cfg_attr(
34934 not(target_arch = "arm"),
34935 stable(feature = "neon_intrinsics", since = "1.59.0")
34936)]
34937#[cfg_attr(
34938 target_arch = "arm",
34939 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34940)]
34941pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
34942 let c = int8x8_t::splat(-1);
34943 unsafe { simd_or(simd_xor(b, c), a) }
34944}
34945#[doc = "Vector bitwise inclusive OR NOT"]
34946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s16)"]
34947#[inline]
34948#[target_feature(enable = "neon")]
34949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34950#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34951#[cfg_attr(
34952 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34953 assert_instr(orn)
34954)]
34955#[cfg_attr(
34956 not(target_arch = "arm"),
34957 stable(feature = "neon_intrinsics", since = "1.59.0")
34958)]
34959#[cfg_attr(
34960 target_arch = "arm",
34961 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34962)]
34963pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
34964 let c = int16x8_t::splat(-1);
34965 unsafe { simd_or(simd_xor(b, c), a) }
34966}
34967#[doc = "Vector bitwise inclusive OR NOT"]
34968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s32)"]
34969#[inline]
34970#[target_feature(enable = "neon")]
34971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34972#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34973#[cfg_attr(
34974 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34975 assert_instr(orn)
34976)]
34977#[cfg_attr(
34978 not(target_arch = "arm"),
34979 stable(feature = "neon_intrinsics", since = "1.59.0")
34980)]
34981#[cfg_attr(
34982 target_arch = "arm",
34983 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34984)]
34985pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
34986 let c = int32x4_t::splat(-1);
34987 unsafe { simd_or(simd_xor(b, c), a) }
34988}
34989#[doc = "Vector bitwise inclusive OR NOT"]
34990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s64)"]
34991#[inline]
34992#[target_feature(enable = "neon")]
34993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34994#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34995#[cfg_attr(
34996 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34997 assert_instr(orn)
34998)]
34999#[cfg_attr(
35000 not(target_arch = "arm"),
35001 stable(feature = "neon_intrinsics", since = "1.59.0")
35002)]
35003#[cfg_attr(
35004 target_arch = "arm",
35005 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35006)]
35007pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
35008 let c = int64x2_t::splat(-1);
35009 unsafe { simd_or(simd_xor(b, c), a) }
35010}
35011#[doc = "Vector bitwise inclusive OR NOT"]
35012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s8)"]
35013#[inline]
35014#[target_feature(enable = "neon")]
35015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35016#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35017#[cfg_attr(
35018 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35019 assert_instr(orn)
35020)]
35021#[cfg_attr(
35022 not(target_arch = "arm"),
35023 stable(feature = "neon_intrinsics", since = "1.59.0")
35024)]
35025#[cfg_attr(
35026 target_arch = "arm",
35027 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35028)]
35029pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
35030 let c = int8x16_t::splat(-1);
35031 unsafe { simd_or(simd_xor(b, c), a) }
35032}
35033#[doc = "Vector bitwise inclusive OR NOT"]
35034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u16)"]
35035#[inline]
35036#[target_feature(enable = "neon")]
35037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35039#[cfg_attr(
35040 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35041 assert_instr(orn)
35042)]
35043#[cfg_attr(
35044 not(target_arch = "arm"),
35045 stable(feature = "neon_intrinsics", since = "1.59.0")
35046)]
35047#[cfg_attr(
35048 target_arch = "arm",
35049 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35050)]
35051pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
35052 let c = int16x4_t::splat(-1);
35053 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35054}
35055#[doc = "Vector bitwise inclusive OR NOT"]
35056#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u32)"]
35057#[inline]
35058#[target_feature(enable = "neon")]
35059#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35060#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35061#[cfg_attr(
35062 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35063 assert_instr(orn)
35064)]
35065#[cfg_attr(
35066 not(target_arch = "arm"),
35067 stable(feature = "neon_intrinsics", since = "1.59.0")
35068)]
35069#[cfg_attr(
35070 target_arch = "arm",
35071 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35072)]
35073pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
35074 let c = int32x2_t::splat(-1);
35075 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35076}
35077#[doc = "Vector bitwise inclusive OR NOT"]
35078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u64)"]
35079#[inline]
35080#[target_feature(enable = "neon")]
35081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35083#[cfg_attr(
35084 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35085 assert_instr(orn)
35086)]
35087#[cfg_attr(
35088 not(target_arch = "arm"),
35089 stable(feature = "neon_intrinsics", since = "1.59.0")
35090)]
35091#[cfg_attr(
35092 target_arch = "arm",
35093 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35094)]
35095pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
35096 let c = int64x1_t::splat(-1);
35097 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35098}
35099#[doc = "Vector bitwise inclusive OR NOT"]
35100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u8)"]
35101#[inline]
35102#[target_feature(enable = "neon")]
35103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35105#[cfg_attr(
35106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35107 assert_instr(orn)
35108)]
35109#[cfg_attr(
35110 not(target_arch = "arm"),
35111 stable(feature = "neon_intrinsics", since = "1.59.0")
35112)]
35113#[cfg_attr(
35114 target_arch = "arm",
35115 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35116)]
35117pub fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
35118 let c = int8x8_t::splat(-1);
35119 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35120}
35121#[doc = "Vector bitwise inclusive OR NOT"]
35122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u16)"]
35123#[inline]
35124#[target_feature(enable = "neon")]
35125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35127#[cfg_attr(
35128 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35129 assert_instr(orn)
35130)]
35131#[cfg_attr(
35132 not(target_arch = "arm"),
35133 stable(feature = "neon_intrinsics", since = "1.59.0")
35134)]
35135#[cfg_attr(
35136 target_arch = "arm",
35137 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35138)]
35139pub fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
35140 let c = int16x8_t::splat(-1);
35141 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35142}
35143#[doc = "Vector bitwise inclusive OR NOT"]
35144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u32)"]
35145#[inline]
35146#[target_feature(enable = "neon")]
35147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35149#[cfg_attr(
35150 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35151 assert_instr(orn)
35152)]
35153#[cfg_attr(
35154 not(target_arch = "arm"),
35155 stable(feature = "neon_intrinsics", since = "1.59.0")
35156)]
35157#[cfg_attr(
35158 target_arch = "arm",
35159 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35160)]
35161pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
35162 let c = int32x4_t::splat(-1);
35163 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35164}
35165#[doc = "Vector bitwise inclusive OR NOT"]
35166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u64)"]
35167#[inline]
35168#[target_feature(enable = "neon")]
35169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35171#[cfg_attr(
35172 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35173 assert_instr(orn)
35174)]
35175#[cfg_attr(
35176 not(target_arch = "arm"),
35177 stable(feature = "neon_intrinsics", since = "1.59.0")
35178)]
35179#[cfg_attr(
35180 target_arch = "arm",
35181 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35182)]
35183pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
35184 let c = int64x2_t::splat(-1);
35185 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35186}
35187#[doc = "Vector bitwise inclusive OR NOT"]
35188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u8)"]
35189#[inline]
35190#[target_feature(enable = "neon")]
35191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35192#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
35193#[cfg_attr(
35194 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35195 assert_instr(orn)
35196)]
35197#[cfg_attr(
35198 not(target_arch = "arm"),
35199 stable(feature = "neon_intrinsics", since = "1.59.0")
35200)]
35201#[cfg_attr(
35202 target_arch = "arm",
35203 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35204)]
35205pub fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
35206 let c = int8x16_t::splat(-1);
35207 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
35208}
35209#[doc = "Vector bitwise or (immediate, inclusive)"]
35210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"]
35211#[inline]
35212#[target_feature(enable = "neon")]
35213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35215#[cfg_attr(
35216 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35217 assert_instr(orr)
35218)]
35219#[cfg_attr(
35220 not(target_arch = "arm"),
35221 stable(feature = "neon_intrinsics", since = "1.59.0")
35222)]
35223#[cfg_attr(
35224 target_arch = "arm",
35225 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35226)]
35227pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
35228 unsafe { simd_or(a, b) }
35229}
35230#[doc = "Vector bitwise or (immediate, inclusive)"]
35231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"]
35232#[inline]
35233#[target_feature(enable = "neon")]
35234#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35235#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35236#[cfg_attr(
35237 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35238 assert_instr(orr)
35239)]
35240#[cfg_attr(
35241 not(target_arch = "arm"),
35242 stable(feature = "neon_intrinsics", since = "1.59.0")
35243)]
35244#[cfg_attr(
35245 target_arch = "arm",
35246 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35247)]
35248pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
35249 unsafe { simd_or(a, b) }
35250}
35251#[doc = "Vector bitwise or (immediate, inclusive)"]
35252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"]
35253#[inline]
35254#[target_feature(enable = "neon")]
35255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35257#[cfg_attr(
35258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35259 assert_instr(orr)
35260)]
35261#[cfg_attr(
35262 not(target_arch = "arm"),
35263 stable(feature = "neon_intrinsics", since = "1.59.0")
35264)]
35265#[cfg_attr(
35266 target_arch = "arm",
35267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35268)]
35269pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
35270 unsafe { simd_or(a, b) }
35271}
35272#[doc = "Vector bitwise or (immediate, inclusive)"]
35273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"]
35274#[inline]
35275#[target_feature(enable = "neon")]
35276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35278#[cfg_attr(
35279 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35280 assert_instr(orr)
35281)]
35282#[cfg_attr(
35283 not(target_arch = "arm"),
35284 stable(feature = "neon_intrinsics", since = "1.59.0")
35285)]
35286#[cfg_attr(
35287 target_arch = "arm",
35288 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35289)]
35290pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
35291 unsafe { simd_or(a, b) }
35292}
35293#[doc = "Vector bitwise or (immediate, inclusive)"]
35294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"]
35295#[inline]
35296#[target_feature(enable = "neon")]
35297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35299#[cfg_attr(
35300 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35301 assert_instr(orr)
35302)]
35303#[cfg_attr(
35304 not(target_arch = "arm"),
35305 stable(feature = "neon_intrinsics", since = "1.59.0")
35306)]
35307#[cfg_attr(
35308 target_arch = "arm",
35309 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35310)]
35311pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
35312 unsafe { simd_or(a, b) }
35313}
35314#[doc = "Vector bitwise or (immediate, inclusive)"]
35315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"]
35316#[inline]
35317#[target_feature(enable = "neon")]
35318#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35319#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35320#[cfg_attr(
35321 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35322 assert_instr(orr)
35323)]
35324#[cfg_attr(
35325 not(target_arch = "arm"),
35326 stable(feature = "neon_intrinsics", since = "1.59.0")
35327)]
35328#[cfg_attr(
35329 target_arch = "arm",
35330 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35331)]
35332pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
35333 unsafe { simd_or(a, b) }
35334}
35335#[doc = "Vector bitwise or (immediate, inclusive)"]
35336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"]
35337#[inline]
35338#[target_feature(enable = "neon")]
35339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35341#[cfg_attr(
35342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35343 assert_instr(orr)
35344)]
35345#[cfg_attr(
35346 not(target_arch = "arm"),
35347 stable(feature = "neon_intrinsics", since = "1.59.0")
35348)]
35349#[cfg_attr(
35350 target_arch = "arm",
35351 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35352)]
35353pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
35354 unsafe { simd_or(a, b) }
35355}
35356#[doc = "Vector bitwise or (immediate, inclusive)"]
35357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"]
35358#[inline]
35359#[target_feature(enable = "neon")]
35360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35362#[cfg_attr(
35363 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35364 assert_instr(orr)
35365)]
35366#[cfg_attr(
35367 not(target_arch = "arm"),
35368 stable(feature = "neon_intrinsics", since = "1.59.0")
35369)]
35370#[cfg_attr(
35371 target_arch = "arm",
35372 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35373)]
35374pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
35375 unsafe { simd_or(a, b) }
35376}
35377#[doc = "Vector bitwise or (immediate, inclusive)"]
35378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"]
35379#[inline]
35380#[target_feature(enable = "neon")]
35381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35383#[cfg_attr(
35384 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35385 assert_instr(orr)
35386)]
35387#[cfg_attr(
35388 not(target_arch = "arm"),
35389 stable(feature = "neon_intrinsics", since = "1.59.0")
35390)]
35391#[cfg_attr(
35392 target_arch = "arm",
35393 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35394)]
35395pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
35396 unsafe { simd_or(a, b) }
35397}
35398#[doc = "Vector bitwise or (immediate, inclusive)"]
35399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"]
35400#[inline]
35401#[target_feature(enable = "neon")]
35402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35404#[cfg_attr(
35405 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35406 assert_instr(orr)
35407)]
35408#[cfg_attr(
35409 not(target_arch = "arm"),
35410 stable(feature = "neon_intrinsics", since = "1.59.0")
35411)]
35412#[cfg_attr(
35413 target_arch = "arm",
35414 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35415)]
35416pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
35417 unsafe { simd_or(a, b) }
35418}
35419#[doc = "Vector bitwise or (immediate, inclusive)"]
35420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"]
35421#[inline]
35422#[target_feature(enable = "neon")]
35423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35424#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35425#[cfg_attr(
35426 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35427 assert_instr(orr)
35428)]
35429#[cfg_attr(
35430 not(target_arch = "arm"),
35431 stable(feature = "neon_intrinsics", since = "1.59.0")
35432)]
35433#[cfg_attr(
35434 target_arch = "arm",
35435 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35436)]
35437pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
35438 unsafe { simd_or(a, b) }
35439}
35440#[doc = "Vector bitwise or (immediate, inclusive)"]
35441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"]
35442#[inline]
35443#[target_feature(enable = "neon")]
35444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35446#[cfg_attr(
35447 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35448 assert_instr(orr)
35449)]
35450#[cfg_attr(
35451 not(target_arch = "arm"),
35452 stable(feature = "neon_intrinsics", since = "1.59.0")
35453)]
35454#[cfg_attr(
35455 target_arch = "arm",
35456 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35457)]
35458pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
35459 unsafe { simd_or(a, b) }
35460}
35461#[doc = "Vector bitwise or (immediate, inclusive)"]
35462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"]
35463#[inline]
35464#[target_feature(enable = "neon")]
35465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35467#[cfg_attr(
35468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35469 assert_instr(orr)
35470)]
35471#[cfg_attr(
35472 not(target_arch = "arm"),
35473 stable(feature = "neon_intrinsics", since = "1.59.0")
35474)]
35475#[cfg_attr(
35476 target_arch = "arm",
35477 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35478)]
35479pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
35480 unsafe { simd_or(a, b) }
35481}
35482#[doc = "Vector bitwise or (immediate, inclusive)"]
35483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"]
35484#[inline]
35485#[target_feature(enable = "neon")]
35486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35488#[cfg_attr(
35489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35490 assert_instr(orr)
35491)]
35492#[cfg_attr(
35493 not(target_arch = "arm"),
35494 stable(feature = "neon_intrinsics", since = "1.59.0")
35495)]
35496#[cfg_attr(
35497 target_arch = "arm",
35498 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35499)]
35500pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
35501 unsafe { simd_or(a, b) }
35502}
35503#[doc = "Vector bitwise or (immediate, inclusive)"]
35504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"]
35505#[inline]
35506#[target_feature(enable = "neon")]
35507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35508#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35509#[cfg_attr(
35510 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35511 assert_instr(orr)
35512)]
35513#[cfg_attr(
35514 not(target_arch = "arm"),
35515 stable(feature = "neon_intrinsics", since = "1.59.0")
35516)]
35517#[cfg_attr(
35518 target_arch = "arm",
35519 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35520)]
35521pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
35522 unsafe { simd_or(a, b) }
35523}
35524#[doc = "Vector bitwise or (immediate, inclusive)"]
35525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"]
35526#[inline]
35527#[target_feature(enable = "neon")]
35528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35530#[cfg_attr(
35531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35532 assert_instr(orr)
35533)]
35534#[cfg_attr(
35535 not(target_arch = "arm"),
35536 stable(feature = "neon_intrinsics", since = "1.59.0")
35537)]
35538#[cfg_attr(
35539 target_arch = "arm",
35540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35541)]
35542pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
35543 unsafe { simd_or(a, b) }
35544}
35545#[doc = "Signed Add and Accumulate Long Pairwise."]
35546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"]
35547#[inline]
35548#[target_feature(enable = "neon")]
35549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35550#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
35551#[cfg_attr(
35552 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35553 assert_instr(sadalp)
35554)]
35555#[cfg_attr(
35556 not(target_arch = "arm"),
35557 stable(feature = "neon_intrinsics", since = "1.59.0")
35558)]
35559#[cfg_attr(
35560 target_arch = "arm",
35561 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35562)]
35563pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
35564 let x: int16x4_t;
35565 #[cfg(target_arch = "arm")]
35566 {
35567 x = priv_vpadal_s8(a, b);
35568 }
35569 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35570 unsafe {
35571 x = simd_add(vpaddl_s8(b), a);
35572 };
35573 x
35574}
35575#[doc = "Signed Add and Accumulate Long Pairwise."]
35576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"]
35577#[inline]
35578#[target_feature(enable = "neon")]
35579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35580#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
35581#[cfg_attr(
35582 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35583 assert_instr(sadalp)
35584)]
35585#[cfg_attr(
35586 not(target_arch = "arm"),
35587 stable(feature = "neon_intrinsics", since = "1.59.0")
35588)]
35589#[cfg_attr(
35590 target_arch = "arm",
35591 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35592)]
35593pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
35594 let x: int16x8_t;
35595 #[cfg(target_arch = "arm")]
35596 {
35597 x = priv_vpadalq_s8(a, b);
35598 }
35599 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35600 unsafe {
35601 x = simd_add(vpaddlq_s8(b), a);
35602 };
35603 x
35604}
35605#[doc = "Signed Add and Accumulate Long Pairwise."]
35606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"]
35607#[inline]
35608#[target_feature(enable = "neon")]
35609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35610#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
35611#[cfg_attr(
35612 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35613 assert_instr(sadalp)
35614)]
35615#[cfg_attr(
35616 not(target_arch = "arm"),
35617 stable(feature = "neon_intrinsics", since = "1.59.0")
35618)]
35619#[cfg_attr(
35620 target_arch = "arm",
35621 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35622)]
35623pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
35624 let x: int32x2_t;
35625 #[cfg(target_arch = "arm")]
35626 {
35627 x = priv_vpadal_s16(a, b);
35628 }
35629 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35630 unsafe {
35631 x = simd_add(vpaddl_s16(b), a);
35632 };
35633 x
35634}
35635#[doc = "Signed Add and Accumulate Long Pairwise."]
35636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"]
35637#[inline]
35638#[target_feature(enable = "neon")]
35639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35640#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
35641#[cfg_attr(
35642 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35643 assert_instr(sadalp)
35644)]
35645#[cfg_attr(
35646 not(target_arch = "arm"),
35647 stable(feature = "neon_intrinsics", since = "1.59.0")
35648)]
35649#[cfg_attr(
35650 target_arch = "arm",
35651 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35652)]
35653pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
35654 let x: int32x4_t;
35655 #[cfg(target_arch = "arm")]
35656 {
35657 x = priv_vpadalq_s16(a, b);
35658 }
35659 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35660 unsafe {
35661 x = simd_add(vpaddlq_s16(b), a);
35662 };
35663 x
35664}
35665#[doc = "Signed Add and Accumulate Long Pairwise."]
35666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"]
35667#[inline]
35668#[target_feature(enable = "neon")]
35669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35670#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
35671#[cfg_attr(
35672 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35673 assert_instr(sadalp)
35674)]
35675#[cfg_attr(
35676 not(target_arch = "arm"),
35677 stable(feature = "neon_intrinsics", since = "1.59.0")
35678)]
35679#[cfg_attr(
35680 target_arch = "arm",
35681 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35682)]
35683pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
35684 let x: int64x1_t;
35685 #[cfg(target_arch = "arm")]
35686 {
35687 x = priv_vpadal_s32(a, b);
35688 }
35689 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35690 unsafe {
35691 x = simd_add(vpaddl_s32(b), a);
35692 };
35693 x
35694}
35695#[doc = "Signed Add and Accumulate Long Pairwise."]
35696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"]
35697#[inline]
35698#[target_feature(enable = "neon")]
35699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35700#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
35701#[cfg_attr(
35702 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35703 assert_instr(sadalp)
35704)]
35705#[cfg_attr(
35706 not(target_arch = "arm"),
35707 stable(feature = "neon_intrinsics", since = "1.59.0")
35708)]
35709#[cfg_attr(
35710 target_arch = "arm",
35711 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35712)]
35713pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
35714 let x: int64x2_t;
35715 #[cfg(target_arch = "arm")]
35716 {
35717 x = priv_vpadalq_s32(a, b);
35718 }
35719 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35720 unsafe {
35721 x = simd_add(vpaddlq_s32(b), a);
35722 };
35723 x
35724}
35725#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"]
35727#[inline]
35728#[target_feature(enable = "neon")]
35729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35730#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
35731#[cfg_attr(
35732 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35733 assert_instr(uadalp)
35734)]
35735#[cfg_attr(
35736 not(target_arch = "arm"),
35737 stable(feature = "neon_intrinsics", since = "1.59.0")
35738)]
35739#[cfg_attr(
35740 target_arch = "arm",
35741 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35742)]
35743pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
35744 let x: uint16x4_t;
35745 #[cfg(target_arch = "arm")]
35746 {
35747 x = priv_vpadal_u8(a, b);
35748 }
35749 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35750 unsafe {
35751 x = simd_add(vpaddl_u8(b), a);
35752 };
35753 x
35754}
35755#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"]
35757#[inline]
35758#[target_feature(enable = "neon")]
35759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35760#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
35761#[cfg_attr(
35762 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35763 assert_instr(uadalp)
35764)]
35765#[cfg_attr(
35766 not(target_arch = "arm"),
35767 stable(feature = "neon_intrinsics", since = "1.59.0")
35768)]
35769#[cfg_attr(
35770 target_arch = "arm",
35771 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35772)]
35773pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
35774 let x: uint16x8_t;
35775 #[cfg(target_arch = "arm")]
35776 {
35777 x = priv_vpadalq_u8(a, b);
35778 }
35779 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35780 unsafe {
35781 x = simd_add(vpaddlq_u8(b), a);
35782 };
35783 x
35784}
35785#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"]
35787#[inline]
35788#[target_feature(enable = "neon")]
35789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35790#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
35791#[cfg_attr(
35792 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35793 assert_instr(uadalp)
35794)]
35795#[cfg_attr(
35796 not(target_arch = "arm"),
35797 stable(feature = "neon_intrinsics", since = "1.59.0")
35798)]
35799#[cfg_attr(
35800 target_arch = "arm",
35801 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35802)]
35803pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
35804 let x: uint32x2_t;
35805 #[cfg(target_arch = "arm")]
35806 {
35807 x = priv_vpadal_u16(a, b);
35808 }
35809 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35810 unsafe {
35811 x = simd_add(vpaddl_u16(b), a);
35812 };
35813 x
35814}
35815#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"]
35817#[inline]
35818#[target_feature(enable = "neon")]
35819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35820#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
35821#[cfg_attr(
35822 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35823 assert_instr(uadalp)
35824)]
35825#[cfg_attr(
35826 not(target_arch = "arm"),
35827 stable(feature = "neon_intrinsics", since = "1.59.0")
35828)]
35829#[cfg_attr(
35830 target_arch = "arm",
35831 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35832)]
35833pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
35834 let x: uint32x4_t;
35835 #[cfg(target_arch = "arm")]
35836 {
35837 x = priv_vpadalq_u16(a, b);
35838 }
35839 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35840 unsafe {
35841 x = simd_add(vpaddlq_u16(b), a);
35842 };
35843 x
35844}
35845#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"]
35847#[inline]
35848#[target_feature(enable = "neon")]
35849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35850#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
35851#[cfg_attr(
35852 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35853 assert_instr(uadalp)
35854)]
35855#[cfg_attr(
35856 not(target_arch = "arm"),
35857 stable(feature = "neon_intrinsics", since = "1.59.0")
35858)]
35859#[cfg_attr(
35860 target_arch = "arm",
35861 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35862)]
35863pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
35864 let x: uint64x1_t;
35865 #[cfg(target_arch = "arm")]
35866 {
35867 x = priv_vpadal_u32(a, b);
35868 }
35869 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35870 unsafe {
35871 x = simd_add(vpaddl_u32(b), a);
35872 };
35873 x
35874}
35875#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"]
35877#[inline]
35878#[target_feature(enable = "neon")]
35879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35880#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
35881#[cfg_attr(
35882 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35883 assert_instr(uadalp)
35884)]
35885#[cfg_attr(
35886 not(target_arch = "arm"),
35887 stable(feature = "neon_intrinsics", since = "1.59.0")
35888)]
35889#[cfg_attr(
35890 target_arch = "arm",
35891 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35892)]
35893pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
35894 let x: uint64x2_t;
35895 #[cfg(target_arch = "arm")]
35896 {
35897 x = priv_vpadalq_u32(a, b);
35898 }
35899 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35900 unsafe {
35901 x = simd_add(vpaddlq_u32(b), a);
35902 };
35903 x
35904}
35905#[doc = "Floating-point add pairwise"]
35906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"]
35907#[inline]
35908#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
35909#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35910#[cfg_attr(
35911 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35912 assert_instr(faddp)
35913)]
35914#[target_feature(enable = "neon,fp16")]
35915#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
35916pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
35917 unsafe extern "unadjusted" {
35918 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4f16")]
35919 #[cfg_attr(
35920 any(target_arch = "aarch64", target_arch = "arm64ec"),
35921 link_name = "llvm.aarch64.neon.faddp.v4f16"
35922 )]
35923 fn _vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
35924 }
35925 unsafe { _vpadd_f16(a, b) }
35926}
35927#[doc = "Floating-point add pairwise"]
35928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"]
35929#[inline]
35930#[target_feature(enable = "neon")]
35931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35933#[cfg_attr(
35934 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35935 assert_instr(faddp)
35936)]
35937#[cfg_attr(
35938 not(target_arch = "arm"),
35939 stable(feature = "neon_intrinsics", since = "1.59.0")
35940)]
35941#[cfg_attr(
35942 target_arch = "arm",
35943 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35944)]
35945pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
35946 unsafe extern "unadjusted" {
35947 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")]
35948 #[cfg_attr(
35949 any(target_arch = "aarch64", target_arch = "arm64ec"),
35950 link_name = "llvm.aarch64.neon.faddp.v2f32"
35951 )]
35952 fn _vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
35953 }
35954 unsafe { _vpadd_f32(a, b) }
35955}
35956#[doc = "Add pairwise."]
35957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"]
35958#[inline]
35959#[target_feature(enable = "neon")]
35960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35961#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35962#[cfg_attr(
35963 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35964 assert_instr(addp)
35965)]
35966#[cfg_attr(
35967 not(target_arch = "arm"),
35968 stable(feature = "neon_intrinsics", since = "1.59.0")
35969)]
35970#[cfg_attr(
35971 target_arch = "arm",
35972 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35973)]
35974pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
35975 unsafe extern "unadjusted" {
35976 #[cfg_attr(
35977 any(target_arch = "aarch64", target_arch = "arm64ec"),
35978 link_name = "llvm.aarch64.neon.addp.v8i8"
35979 )]
35980 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v8i8")]
35981 fn _vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
35982 }
35983 unsafe { _vpadd_s8(a, b) }
35984}
35985#[doc = "Add pairwise."]
35986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"]
35987#[inline]
35988#[target_feature(enable = "neon")]
35989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35991#[cfg_attr(
35992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35993 assert_instr(addp)
35994)]
35995#[cfg_attr(
35996 not(target_arch = "arm"),
35997 stable(feature = "neon_intrinsics", since = "1.59.0")
35998)]
35999#[cfg_attr(
36000 target_arch = "arm",
36001 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36002)]
36003pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
36004 unsafe extern "unadjusted" {
36005 #[cfg_attr(
36006 any(target_arch = "aarch64", target_arch = "arm64ec"),
36007 link_name = "llvm.aarch64.neon.addp.v4i16"
36008 )]
36009 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")]
36010 fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
36011 }
36012 unsafe { _vpadd_s16(a, b) }
36013}
36014#[doc = "Add pairwise."]
36015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"]
36016#[inline]
36017#[target_feature(enable = "neon")]
36018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36019#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36020#[cfg_attr(
36021 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36022 assert_instr(addp)
36023)]
36024#[cfg_attr(
36025 not(target_arch = "arm"),
36026 stable(feature = "neon_intrinsics", since = "1.59.0")
36027)]
36028#[cfg_attr(
36029 target_arch = "arm",
36030 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36031)]
36032pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
36033 unsafe extern "unadjusted" {
36034 #[cfg_attr(
36035 any(target_arch = "aarch64", target_arch = "arm64ec"),
36036 link_name = "llvm.aarch64.neon.addp.v2i32"
36037 )]
36038 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")]
36039 fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
36040 }
36041 unsafe { _vpadd_s32(a, b) }
36042}
36043#[doc = "Add pairwise."]
36044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
36045#[inline]
36046#[cfg(target_endian = "little")]
36047#[target_feature(enable = "neon")]
36048#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36049#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36050#[cfg_attr(
36051 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36052 assert_instr(addp)
36053)]
36054#[cfg_attr(
36055 not(target_arch = "arm"),
36056 stable(feature = "neon_intrinsics", since = "1.59.0")
36057)]
36058#[cfg_attr(
36059 target_arch = "arm",
36060 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36061)]
36062pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36063 unsafe { transmute(vpadd_s8(transmute(a), transmute(b))) }
36064}
36065#[doc = "Add pairwise."]
36066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
36067#[inline]
36068#[cfg(target_endian = "big")]
36069#[target_feature(enable = "neon")]
36070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36071#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36072#[cfg_attr(
36073 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36074 assert_instr(addp)
36075)]
36076#[cfg_attr(
36077 not(target_arch = "arm"),
36078 stable(feature = "neon_intrinsics", since = "1.59.0")
36079)]
36080#[cfg_attr(
36081 target_arch = "arm",
36082 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36083)]
36084pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36085 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
36086 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
36087 unsafe {
36088 let ret_val: uint8x8_t = transmute(vpadd_s8(transmute(a), transmute(b)));
36089 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
36090 }
36091}
36092#[doc = "Add pairwise."]
36093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
36094#[inline]
36095#[cfg(target_endian = "little")]
36096#[target_feature(enable = "neon")]
36097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36099#[cfg_attr(
36100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36101 assert_instr(addp)
36102)]
36103#[cfg_attr(
36104 not(target_arch = "arm"),
36105 stable(feature = "neon_intrinsics", since = "1.59.0")
36106)]
36107#[cfg_attr(
36108 target_arch = "arm",
36109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36110)]
36111pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36112 unsafe { transmute(vpadd_s16(transmute(a), transmute(b))) }
36113}
36114#[doc = "Add pairwise."]
36115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
36116#[inline]
36117#[cfg(target_endian = "big")]
36118#[target_feature(enable = "neon")]
36119#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36120#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36121#[cfg_attr(
36122 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36123 assert_instr(addp)
36124)]
36125#[cfg_attr(
36126 not(target_arch = "arm"),
36127 stable(feature = "neon_intrinsics", since = "1.59.0")
36128)]
36129#[cfg_attr(
36130 target_arch = "arm",
36131 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36132)]
36133pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36134 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
36135 let b: uint16x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
36136 unsafe {
36137 let ret_val: uint16x4_t = transmute(vpadd_s16(transmute(a), transmute(b)));
36138 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
36139 }
36140}
36141#[doc = "Add pairwise."]
36142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
36143#[inline]
36144#[cfg(target_endian = "little")]
36145#[target_feature(enable = "neon")]
36146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36147#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36148#[cfg_attr(
36149 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36150 assert_instr(addp)
36151)]
36152#[cfg_attr(
36153 not(target_arch = "arm"),
36154 stable(feature = "neon_intrinsics", since = "1.59.0")
36155)]
36156#[cfg_attr(
36157 target_arch = "arm",
36158 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36159)]
36160pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36161 unsafe { transmute(vpadd_s32(transmute(a), transmute(b))) }
36162}
36163#[doc = "Add pairwise."]
36164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
36165#[inline]
36166#[cfg(target_endian = "big")]
36167#[target_feature(enable = "neon")]
36168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36169#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
36170#[cfg_attr(
36171 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36172 assert_instr(addp)
36173)]
36174#[cfg_attr(
36175 not(target_arch = "arm"),
36176 stable(feature = "neon_intrinsics", since = "1.59.0")
36177)]
36178#[cfg_attr(
36179 target_arch = "arm",
36180 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36181)]
36182pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36183 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
36184 let b: uint32x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
36185 unsafe {
36186 let ret_val: uint32x2_t = transmute(vpadd_s32(transmute(a), transmute(b)));
36187 simd_shuffle!(ret_val, ret_val, [1, 0])
36188 }
36189}
36190#[doc = "Signed Add and Accumulate Long Pairwise."]
36191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"]
36192#[inline]
36193#[target_feature(enable = "neon")]
36194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36195#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
36196#[cfg_attr(
36197 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36198 assert_instr(saddlp)
36199)]
36200#[cfg_attr(
36201 not(target_arch = "arm"),
36202 stable(feature = "neon_intrinsics", since = "1.59.0")
36203)]
36204#[cfg_attr(
36205 target_arch = "arm",
36206 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36207)]
36208pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t {
36209 unsafe extern "unadjusted" {
36210 #[cfg_attr(
36211 any(target_arch = "aarch64", target_arch = "arm64ec"),
36212 link_name = "llvm.aarch64.neon.saddlp.v4i16.v8i8"
36213 )]
36214 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i16.v8i8")]
36215 fn _vpaddl_s8(a: int8x8_t) -> int16x4_t;
36216 }
36217 unsafe { _vpaddl_s8(a) }
36218}
36219#[doc = "Signed Add and Accumulate Long Pairwise."]
36220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"]
36221#[inline]
36222#[target_feature(enable = "neon")]
36223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36224#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
36225#[cfg_attr(
36226 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36227 assert_instr(saddlp)
36228)]
36229#[cfg_attr(
36230 not(target_arch = "arm"),
36231 stable(feature = "neon_intrinsics", since = "1.59.0")
36232)]
36233#[cfg_attr(
36234 target_arch = "arm",
36235 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36236)]
36237pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t {
36238 unsafe extern "unadjusted" {
36239 #[cfg_attr(
36240 any(target_arch = "aarch64", target_arch = "arm64ec"),
36241 link_name = "llvm.aarch64.neon.saddlp.v8i16.v16i8"
36242 )]
36243 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v8i16.v16i8")]
36244 fn _vpaddlq_s8(a: int8x16_t) -> int16x8_t;
36245 }
36246 unsafe { _vpaddlq_s8(a) }
36247}
36248#[doc = "Signed Add and Accumulate Long Pairwise."]
36249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"]
36250#[inline]
36251#[target_feature(enable = "neon")]
36252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36253#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
36254#[cfg_attr(
36255 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36256 assert_instr(saddlp)
36257)]
36258#[cfg_attr(
36259 not(target_arch = "arm"),
36260 stable(feature = "neon_intrinsics", since = "1.59.0")
36261)]
36262#[cfg_attr(
36263 target_arch = "arm",
36264 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36265)]
36266pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t {
36267 unsafe extern "unadjusted" {
36268 #[cfg_attr(
36269 any(target_arch = "aarch64", target_arch = "arm64ec"),
36270 link_name = "llvm.aarch64.neon.saddlp.v2i32.v4i16"
36271 )]
36272 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i32.v4i16")]
36273 fn _vpaddl_s16(a: int16x4_t) -> int32x2_t;
36274 }
36275 unsafe { _vpaddl_s16(a) }
36276}
36277#[doc = "Signed Add and Accumulate Long Pairwise."]
36278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"]
36279#[inline]
36280#[target_feature(enable = "neon")]
36281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36282#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
36283#[cfg_attr(
36284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36285 assert_instr(saddlp)
36286)]
36287#[cfg_attr(
36288 not(target_arch = "arm"),
36289 stable(feature = "neon_intrinsics", since = "1.59.0")
36290)]
36291#[cfg_attr(
36292 target_arch = "arm",
36293 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36294)]
36295pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t {
36296 unsafe extern "unadjusted" {
36297 #[cfg_attr(
36298 any(target_arch = "aarch64", target_arch = "arm64ec"),
36299 link_name = "llvm.aarch64.neon.saddlp.v4i32.v8i16"
36300 )]
36301 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i32.v8i16")]
36302 fn _vpaddlq_s16(a: int16x8_t) -> int32x4_t;
36303 }
36304 unsafe { _vpaddlq_s16(a) }
36305}
36306#[doc = "Signed Add and Accumulate Long Pairwise."]
36307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"]
36308#[inline]
36309#[target_feature(enable = "neon")]
36310#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36311#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
36312#[cfg_attr(
36313 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36314 assert_instr(saddlp)
36315)]
36316#[cfg_attr(
36317 not(target_arch = "arm"),
36318 stable(feature = "neon_intrinsics", since = "1.59.0")
36319)]
36320#[cfg_attr(
36321 target_arch = "arm",
36322 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36323)]
36324pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t {
36325 unsafe extern "unadjusted" {
36326 #[cfg_attr(
36327 any(target_arch = "aarch64", target_arch = "arm64ec"),
36328 link_name = "llvm.aarch64.neon.saddlp.v1i64.v2i32"
36329 )]
36330 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v1i64.v2i32")]
36331 fn _vpaddl_s32(a: int32x2_t) -> int64x1_t;
36332 }
36333 unsafe { _vpaddl_s32(a) }
36334}
36335#[doc = "Signed Add and Accumulate Long Pairwise."]
36336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"]
36337#[inline]
36338#[target_feature(enable = "neon")]
36339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36340#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
36341#[cfg_attr(
36342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36343 assert_instr(saddlp)
36344)]
36345#[cfg_attr(
36346 not(target_arch = "arm"),
36347 stable(feature = "neon_intrinsics", since = "1.59.0")
36348)]
36349#[cfg_attr(
36350 target_arch = "arm",
36351 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36352)]
36353pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t {
36354 unsafe extern "unadjusted" {
36355 #[cfg_attr(
36356 any(target_arch = "aarch64", target_arch = "arm64ec"),
36357 link_name = "llvm.aarch64.neon.saddlp.v2i64.v4i32"
36358 )]
36359 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i64.v4i32")]
36360 fn _vpaddlq_s32(a: int32x4_t) -> int64x2_t;
36361 }
36362 unsafe { _vpaddlq_s32(a) }
36363}
36364#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"]
36366#[inline]
36367#[target_feature(enable = "neon")]
36368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36369#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
36370#[cfg_attr(
36371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36372 assert_instr(uaddlp)
36373)]
36374#[cfg_attr(
36375 not(target_arch = "arm"),
36376 stable(feature = "neon_intrinsics", since = "1.59.0")
36377)]
36378#[cfg_attr(
36379 target_arch = "arm",
36380 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36381)]
36382pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t {
36383 unsafe extern "unadjusted" {
36384 #[cfg_attr(
36385 any(target_arch = "aarch64", target_arch = "arm64ec"),
36386 link_name = "llvm.aarch64.neon.uaddlp.v4i16.v8i8"
36387 )]
36388 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i16.v8i8")]
36389 fn _vpaddl_u8(a: uint8x8_t) -> uint16x4_t;
36390 }
36391 unsafe { _vpaddl_u8(a) }
36392}
36393#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"]
36395#[inline]
36396#[target_feature(enable = "neon")]
36397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36398#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
36399#[cfg_attr(
36400 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36401 assert_instr(uaddlp)
36402)]
36403#[cfg_attr(
36404 not(target_arch = "arm"),
36405 stable(feature = "neon_intrinsics", since = "1.59.0")
36406)]
36407#[cfg_attr(
36408 target_arch = "arm",
36409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36410)]
36411pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t {
36412 unsafe extern "unadjusted" {
36413 #[cfg_attr(
36414 any(target_arch = "aarch64", target_arch = "arm64ec"),
36415 link_name = "llvm.aarch64.neon.uaddlp.v8i16.v16i8"
36416 )]
36417 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v8i16.v16i8")]
36418 fn _vpaddlq_u8(a: uint8x16_t) -> uint16x8_t;
36419 }
36420 unsafe { _vpaddlq_u8(a) }
36421}
36422#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"]
36424#[inline]
36425#[target_feature(enable = "neon")]
36426#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36427#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
36428#[cfg_attr(
36429 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36430 assert_instr(uaddlp)
36431)]
36432#[cfg_attr(
36433 not(target_arch = "arm"),
36434 stable(feature = "neon_intrinsics", since = "1.59.0")
36435)]
36436#[cfg_attr(
36437 target_arch = "arm",
36438 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36439)]
36440pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t {
36441 unsafe extern "unadjusted" {
36442 #[cfg_attr(
36443 any(target_arch = "aarch64", target_arch = "arm64ec"),
36444 link_name = "llvm.aarch64.neon.uaddlp.v2i32.v4i16"
36445 )]
36446 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i32.v4i16")]
36447 fn _vpaddl_u16(a: uint16x4_t) -> uint32x2_t;
36448 }
36449 unsafe { _vpaddl_u16(a) }
36450}
36451#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"]
36453#[inline]
36454#[target_feature(enable = "neon")]
36455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36456#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
36457#[cfg_attr(
36458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36459 assert_instr(uaddlp)
36460)]
36461#[cfg_attr(
36462 not(target_arch = "arm"),
36463 stable(feature = "neon_intrinsics", since = "1.59.0")
36464)]
36465#[cfg_attr(
36466 target_arch = "arm",
36467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36468)]
36469pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t {
36470 unsafe extern "unadjusted" {
36471 #[cfg_attr(
36472 any(target_arch = "aarch64", target_arch = "arm64ec"),
36473 link_name = "llvm.aarch64.neon.uaddlp.v4i32.v8i16"
36474 )]
36475 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i32.v8i16")]
36476 fn _vpaddlq_u16(a: uint16x8_t) -> uint32x4_t;
36477 }
36478 unsafe { _vpaddlq_u16(a) }
36479}
36480#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"]
36482#[inline]
36483#[target_feature(enable = "neon")]
36484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36485#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
36486#[cfg_attr(
36487 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36488 assert_instr(uaddlp)
36489)]
36490#[cfg_attr(
36491 not(target_arch = "arm"),
36492 stable(feature = "neon_intrinsics", since = "1.59.0")
36493)]
36494#[cfg_attr(
36495 target_arch = "arm",
36496 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36497)]
36498pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t {
36499 unsafe extern "unadjusted" {
36500 #[cfg_attr(
36501 any(target_arch = "aarch64", target_arch = "arm64ec"),
36502 link_name = "llvm.aarch64.neon.uaddlp.v1i64.v2i32"
36503 )]
36504 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v1i64.v2i32")]
36505 fn _vpaddl_u32(a: uint32x2_t) -> uint64x1_t;
36506 }
36507 unsafe { _vpaddl_u32(a) }
36508}
36509#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"]
36511#[inline]
36512#[target_feature(enable = "neon")]
36513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36514#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
36515#[cfg_attr(
36516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36517 assert_instr(uaddlp)
36518)]
36519#[cfg_attr(
36520 not(target_arch = "arm"),
36521 stable(feature = "neon_intrinsics", since = "1.59.0")
36522)]
36523#[cfg_attr(
36524 target_arch = "arm",
36525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36526)]
36527pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t {
36528 unsafe extern "unadjusted" {
36529 #[cfg_attr(
36530 any(target_arch = "aarch64", target_arch = "arm64ec"),
36531 link_name = "llvm.aarch64.neon.uaddlp.v2i64.v4i32"
36532 )]
36533 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i64.v4i32")]
36534 fn _vpaddlq_u32(a: uint32x4_t) -> uint64x2_t;
36535 }
36536 unsafe { _vpaddlq_u32(a) }
36537}
36538#[doc = "Folding maximum of adjacent pairs"]
36539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"]
36540#[inline]
36541#[target_feature(enable = "neon")]
36542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36544#[cfg_attr(
36545 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36546 assert_instr(fmaxp)
36547)]
36548#[cfg_attr(
36549 not(target_arch = "arm"),
36550 stable(feature = "neon_intrinsics", since = "1.59.0")
36551)]
36552#[cfg_attr(
36553 target_arch = "arm",
36554 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36555)]
36556pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
36557 unsafe extern "unadjusted" {
36558 #[cfg_attr(
36559 any(target_arch = "aarch64", target_arch = "arm64ec"),
36560 link_name = "llvm.aarch64.neon.fmaxp.v2f32"
36561 )]
36562 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")]
36563 fn _vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
36564 }
36565 unsafe { _vpmax_f32(a, b) }
36566}
36567#[doc = "Folding maximum of adjacent pairs"]
36568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"]
36569#[inline]
36570#[target_feature(enable = "neon")]
36571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36573#[cfg_attr(
36574 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36575 assert_instr(smaxp)
36576)]
36577#[cfg_attr(
36578 not(target_arch = "arm"),
36579 stable(feature = "neon_intrinsics", since = "1.59.0")
36580)]
36581#[cfg_attr(
36582 target_arch = "arm",
36583 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36584)]
36585pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
36586 unsafe extern "unadjusted" {
36587 #[cfg_attr(
36588 any(target_arch = "aarch64", target_arch = "arm64ec"),
36589 link_name = "llvm.aarch64.neon.smaxp.v8i8"
36590 )]
36591 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")]
36592 fn _vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
36593 }
36594 unsafe { _vpmax_s8(a, b) }
36595}
36596#[doc = "Folding maximum of adjacent pairs"]
36597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"]
36598#[inline]
36599#[target_feature(enable = "neon")]
36600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36601#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36602#[cfg_attr(
36603 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36604 assert_instr(smaxp)
36605)]
36606#[cfg_attr(
36607 not(target_arch = "arm"),
36608 stable(feature = "neon_intrinsics", since = "1.59.0")
36609)]
36610#[cfg_attr(
36611 target_arch = "arm",
36612 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36613)]
36614pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
36615 unsafe extern "unadjusted" {
36616 #[cfg_attr(
36617 any(target_arch = "aarch64", target_arch = "arm64ec"),
36618 link_name = "llvm.aarch64.neon.smaxp.v4i16"
36619 )]
36620 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")]
36621 fn _vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
36622 }
36623 unsafe { _vpmax_s16(a, b) }
36624}
36625#[doc = "Folding maximum of adjacent pairs"]
36626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"]
36627#[inline]
36628#[target_feature(enable = "neon")]
36629#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36630#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36631#[cfg_attr(
36632 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36633 assert_instr(smaxp)
36634)]
36635#[cfg_attr(
36636 not(target_arch = "arm"),
36637 stable(feature = "neon_intrinsics", since = "1.59.0")
36638)]
36639#[cfg_attr(
36640 target_arch = "arm",
36641 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36642)]
36643pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
36644 unsafe extern "unadjusted" {
36645 #[cfg_attr(
36646 any(target_arch = "aarch64", target_arch = "arm64ec"),
36647 link_name = "llvm.aarch64.neon.smaxp.v2i32"
36648 )]
36649 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")]
36650 fn _vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
36651 }
36652 unsafe { _vpmax_s32(a, b) }
36653}
36654#[doc = "Folding maximum of adjacent pairs"]
36655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"]
36656#[inline]
36657#[target_feature(enable = "neon")]
36658#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36659#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36660#[cfg_attr(
36661 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36662 assert_instr(umaxp)
36663)]
36664#[cfg_attr(
36665 not(target_arch = "arm"),
36666 stable(feature = "neon_intrinsics", since = "1.59.0")
36667)]
36668#[cfg_attr(
36669 target_arch = "arm",
36670 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36671)]
36672pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36673 unsafe extern "unadjusted" {
36674 #[cfg_attr(
36675 any(target_arch = "aarch64", target_arch = "arm64ec"),
36676 link_name = "llvm.aarch64.neon.umaxp.v8i8"
36677 )]
36678 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")]
36679 fn _vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
36680 }
36681 unsafe { _vpmax_u8(a, b) }
36682}
36683#[doc = "Folding maximum of adjacent pairs"]
36684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"]
36685#[inline]
36686#[target_feature(enable = "neon")]
36687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36689#[cfg_attr(
36690 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36691 assert_instr(umaxp)
36692)]
36693#[cfg_attr(
36694 not(target_arch = "arm"),
36695 stable(feature = "neon_intrinsics", since = "1.59.0")
36696)]
36697#[cfg_attr(
36698 target_arch = "arm",
36699 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36700)]
36701pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36702 unsafe extern "unadjusted" {
36703 #[cfg_attr(
36704 any(target_arch = "aarch64", target_arch = "arm64ec"),
36705 link_name = "llvm.aarch64.neon.umaxp.v4i16"
36706 )]
36707 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")]
36708 fn _vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
36709 }
36710 unsafe { _vpmax_u16(a, b) }
36711}
36712#[doc = "Folding maximum of adjacent pairs"]
36713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"]
36714#[inline]
36715#[target_feature(enable = "neon")]
36716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36717#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36718#[cfg_attr(
36719 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36720 assert_instr(umaxp)
36721)]
36722#[cfg_attr(
36723 not(target_arch = "arm"),
36724 stable(feature = "neon_intrinsics", since = "1.59.0")
36725)]
36726#[cfg_attr(
36727 target_arch = "arm",
36728 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36729)]
36730pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36731 unsafe extern "unadjusted" {
36732 #[cfg_attr(
36733 any(target_arch = "aarch64", target_arch = "arm64ec"),
36734 link_name = "llvm.aarch64.neon.umaxp.v2i32"
36735 )]
36736 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")]
36737 fn _vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
36738 }
36739 unsafe { _vpmax_u32(a, b) }
36740}
36741#[doc = "Folding minimum of adjacent pairs"]
36742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"]
36743#[inline]
36744#[target_feature(enable = "neon")]
36745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36746#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36747#[cfg_attr(
36748 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36749 assert_instr(fminp)
36750)]
36751#[cfg_attr(
36752 not(target_arch = "arm"),
36753 stable(feature = "neon_intrinsics", since = "1.59.0")
36754)]
36755#[cfg_attr(
36756 target_arch = "arm",
36757 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36758)]
36759pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
36760 unsafe extern "unadjusted" {
36761 #[cfg_attr(
36762 any(target_arch = "aarch64", target_arch = "arm64ec"),
36763 link_name = "llvm.aarch64.neon.fminp.v2f32"
36764 )]
36765 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")]
36766 fn _vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
36767 }
36768 unsafe { _vpmin_f32(a, b) }
36769}
36770#[doc = "Folding minimum of adjacent pairs"]
36771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"]
36772#[inline]
36773#[target_feature(enable = "neon")]
36774#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36775#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36776#[cfg_attr(
36777 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36778 assert_instr(sminp)
36779)]
36780#[cfg_attr(
36781 not(target_arch = "arm"),
36782 stable(feature = "neon_intrinsics", since = "1.59.0")
36783)]
36784#[cfg_attr(
36785 target_arch = "arm",
36786 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36787)]
36788pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
36789 unsafe extern "unadjusted" {
36790 #[cfg_attr(
36791 any(target_arch = "aarch64", target_arch = "arm64ec"),
36792 link_name = "llvm.aarch64.neon.sminp.v8i8"
36793 )]
36794 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")]
36795 fn _vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
36796 }
36797 unsafe { _vpmin_s8(a, b) }
36798}
36799#[doc = "Folding minimum of adjacent pairs"]
36800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"]
36801#[inline]
36802#[target_feature(enable = "neon")]
36803#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36804#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36805#[cfg_attr(
36806 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36807 assert_instr(sminp)
36808)]
36809#[cfg_attr(
36810 not(target_arch = "arm"),
36811 stable(feature = "neon_intrinsics", since = "1.59.0")
36812)]
36813#[cfg_attr(
36814 target_arch = "arm",
36815 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36816)]
36817pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
36818 unsafe extern "unadjusted" {
36819 #[cfg_attr(
36820 any(target_arch = "aarch64", target_arch = "arm64ec"),
36821 link_name = "llvm.aarch64.neon.sminp.v4i16"
36822 )]
36823 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")]
36824 fn _vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
36825 }
36826 unsafe { _vpmin_s16(a, b) }
36827}
36828#[doc = "Folding minimum of adjacent pairs"]
36829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"]
36830#[inline]
36831#[target_feature(enable = "neon")]
36832#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36833#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36834#[cfg_attr(
36835 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36836 assert_instr(sminp)
36837)]
36838#[cfg_attr(
36839 not(target_arch = "arm"),
36840 stable(feature = "neon_intrinsics", since = "1.59.0")
36841)]
36842#[cfg_attr(
36843 target_arch = "arm",
36844 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36845)]
36846pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
36847 unsafe extern "unadjusted" {
36848 #[cfg_attr(
36849 any(target_arch = "aarch64", target_arch = "arm64ec"),
36850 link_name = "llvm.aarch64.neon.sminp.v2i32"
36851 )]
36852 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")]
36853 fn _vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
36854 }
36855 unsafe { _vpmin_s32(a, b) }
36856}
36857#[doc = "Folding minimum of adjacent pairs"]
36858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"]
36859#[inline]
36860#[target_feature(enable = "neon")]
36861#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36862#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36863#[cfg_attr(
36864 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36865 assert_instr(uminp)
36866)]
36867#[cfg_attr(
36868 not(target_arch = "arm"),
36869 stable(feature = "neon_intrinsics", since = "1.59.0")
36870)]
36871#[cfg_attr(
36872 target_arch = "arm",
36873 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36874)]
36875pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36876 unsafe extern "unadjusted" {
36877 #[cfg_attr(
36878 any(target_arch = "aarch64", target_arch = "arm64ec"),
36879 link_name = "llvm.aarch64.neon.uminp.v8i8"
36880 )]
36881 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")]
36882 fn _vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
36883 }
36884 unsafe { _vpmin_u8(a, b) }
36885}
36886#[doc = "Folding minimum of adjacent pairs"]
36887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"]
36888#[inline]
36889#[target_feature(enable = "neon")]
36890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36892#[cfg_attr(
36893 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36894 assert_instr(uminp)
36895)]
36896#[cfg_attr(
36897 not(target_arch = "arm"),
36898 stable(feature = "neon_intrinsics", since = "1.59.0")
36899)]
36900#[cfg_attr(
36901 target_arch = "arm",
36902 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36903)]
36904pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36905 unsafe extern "unadjusted" {
36906 #[cfg_attr(
36907 any(target_arch = "aarch64", target_arch = "arm64ec"),
36908 link_name = "llvm.aarch64.neon.uminp.v4i16"
36909 )]
36910 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")]
36911 fn _vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
36912 }
36913 unsafe { _vpmin_u16(a, b) }
36914}
36915#[doc = "Folding minimum of adjacent pairs"]
36916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"]
36917#[inline]
36918#[target_feature(enable = "neon")]
36919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36921#[cfg_attr(
36922 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36923 assert_instr(uminp)
36924)]
36925#[cfg_attr(
36926 not(target_arch = "arm"),
36927 stable(feature = "neon_intrinsics", since = "1.59.0")
36928)]
36929#[cfg_attr(
36930 target_arch = "arm",
36931 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36932)]
36933pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36934 unsafe extern "unadjusted" {
36935 #[cfg_attr(
36936 any(target_arch = "aarch64", target_arch = "arm64ec"),
36937 link_name = "llvm.aarch64.neon.uminp.v2i32"
36938 )]
36939 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")]
36940 fn _vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
36941 }
36942 unsafe { _vpmin_u32(a, b) }
36943}
36944#[doc = "Signed saturating Absolute value"]
36945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"]
36946#[inline]
36947#[target_feature(enable = "neon")]
36948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36949#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
36950#[cfg_attr(
36951 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36952 assert_instr(sqabs)
36953)]
36954#[cfg_attr(
36955 not(target_arch = "arm"),
36956 stable(feature = "neon_intrinsics", since = "1.59.0")
36957)]
36958#[cfg_attr(
36959 target_arch = "arm",
36960 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36961)]
36962pub fn vqabs_s8(a: int8x8_t) -> int8x8_t {
36963 unsafe extern "unadjusted" {
36964 #[cfg_attr(
36965 any(target_arch = "aarch64", target_arch = "arm64ec"),
36966 link_name = "llvm.aarch64.neon.sqabs.v8i8"
36967 )]
36968 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i8")]
36969 fn _vqabs_s8(a: int8x8_t) -> int8x8_t;
36970 }
36971 unsafe { _vqabs_s8(a) }
36972}
36973#[doc = "Signed saturating Absolute value"]
36974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"]
36975#[inline]
36976#[target_feature(enable = "neon")]
36977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36978#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
36979#[cfg_attr(
36980 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36981 assert_instr(sqabs)
36982)]
36983#[cfg_attr(
36984 not(target_arch = "arm"),
36985 stable(feature = "neon_intrinsics", since = "1.59.0")
36986)]
36987#[cfg_attr(
36988 target_arch = "arm",
36989 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36990)]
36991pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t {
36992 unsafe extern "unadjusted" {
36993 #[cfg_attr(
36994 any(target_arch = "aarch64", target_arch = "arm64ec"),
36995 link_name = "llvm.aarch64.neon.sqabs.v16i8"
36996 )]
36997 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v16i8")]
36998 fn _vqabsq_s8(a: int8x16_t) -> int8x16_t;
36999 }
37000 unsafe { _vqabsq_s8(a) }
37001}
37002#[doc = "Signed saturating Absolute value"]
37003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"]
37004#[inline]
37005#[target_feature(enable = "neon")]
37006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37007#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
37008#[cfg_attr(
37009 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37010 assert_instr(sqabs)
37011)]
37012#[cfg_attr(
37013 not(target_arch = "arm"),
37014 stable(feature = "neon_intrinsics", since = "1.59.0")
37015)]
37016#[cfg_attr(
37017 target_arch = "arm",
37018 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37019)]
37020pub fn vqabs_s16(a: int16x4_t) -> int16x4_t {
37021 unsafe extern "unadjusted" {
37022 #[cfg_attr(
37023 any(target_arch = "aarch64", target_arch = "arm64ec"),
37024 link_name = "llvm.aarch64.neon.sqabs.v4i16"
37025 )]
37026 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i16")]
37027 fn _vqabs_s16(a: int16x4_t) -> int16x4_t;
37028 }
37029 unsafe { _vqabs_s16(a) }
37030}
37031#[doc = "Signed saturating Absolute value"]
37032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"]
37033#[inline]
37034#[target_feature(enable = "neon")]
37035#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37036#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
37037#[cfg_attr(
37038 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37039 assert_instr(sqabs)
37040)]
37041#[cfg_attr(
37042 not(target_arch = "arm"),
37043 stable(feature = "neon_intrinsics", since = "1.59.0")
37044)]
37045#[cfg_attr(
37046 target_arch = "arm",
37047 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37048)]
37049pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t {
37050 unsafe extern "unadjusted" {
37051 #[cfg_attr(
37052 any(target_arch = "aarch64", target_arch = "arm64ec"),
37053 link_name = "llvm.aarch64.neon.sqabs.v8i16"
37054 )]
37055 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i16")]
37056 fn _vqabsq_s16(a: int16x8_t) -> int16x8_t;
37057 }
37058 unsafe { _vqabsq_s16(a) }
37059}
37060#[doc = "Signed saturating Absolute value"]
37061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"]
37062#[inline]
37063#[target_feature(enable = "neon")]
37064#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37065#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
37066#[cfg_attr(
37067 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37068 assert_instr(sqabs)
37069)]
37070#[cfg_attr(
37071 not(target_arch = "arm"),
37072 stable(feature = "neon_intrinsics", since = "1.59.0")
37073)]
37074#[cfg_attr(
37075 target_arch = "arm",
37076 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37077)]
37078pub fn vqabs_s32(a: int32x2_t) -> int32x2_t {
37079 unsafe extern "unadjusted" {
37080 #[cfg_attr(
37081 any(target_arch = "aarch64", target_arch = "arm64ec"),
37082 link_name = "llvm.aarch64.neon.sqabs.v2i32"
37083 )]
37084 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v2i32")]
37085 fn _vqabs_s32(a: int32x2_t) -> int32x2_t;
37086 }
37087 unsafe { _vqabs_s32(a) }
37088}
37089#[doc = "Signed saturating Absolute value"]
37090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"]
37091#[inline]
37092#[target_feature(enable = "neon")]
37093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37094#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
37095#[cfg_attr(
37096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37097 assert_instr(sqabs)
37098)]
37099#[cfg_attr(
37100 not(target_arch = "arm"),
37101 stable(feature = "neon_intrinsics", since = "1.59.0")
37102)]
37103#[cfg_attr(
37104 target_arch = "arm",
37105 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37106)]
37107pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t {
37108 unsafe extern "unadjusted" {
37109 #[cfg_attr(
37110 any(target_arch = "aarch64", target_arch = "arm64ec"),
37111 link_name = "llvm.aarch64.neon.sqabs.v4i32"
37112 )]
37113 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i32")]
37114 fn _vqabsq_s32(a: int32x4_t) -> int32x4_t;
37115 }
37116 unsafe { _vqabsq_s32(a) }
37117}
37118#[doc = "Saturating add"]
37119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"]
37120#[inline]
37121#[target_feature(enable = "neon")]
37122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37123#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
37124#[cfg_attr(
37125 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37126 assert_instr(sqadd)
37127)]
37128#[cfg_attr(
37129 not(target_arch = "arm"),
37130 stable(feature = "neon_intrinsics", since = "1.59.0")
37131)]
37132#[cfg_attr(
37133 target_arch = "arm",
37134 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37135)]
37136pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
37137 unsafe extern "unadjusted" {
37138 #[cfg_attr(
37139 any(target_arch = "aarch64", target_arch = "arm64ec"),
37140 link_name = "llvm.aarch64.neon.sqadd.v8i8"
37141 )]
37142 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i8")]
37143 fn _vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
37144 }
37145 unsafe { _vqadd_s8(a, b) }
37146}
37147#[doc = "Saturating add"]
37148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"]
37149#[inline]
37150#[target_feature(enable = "neon")]
37151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37152#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
37153#[cfg_attr(
37154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37155 assert_instr(sqadd)
37156)]
37157#[cfg_attr(
37158 not(target_arch = "arm"),
37159 stable(feature = "neon_intrinsics", since = "1.59.0")
37160)]
37161#[cfg_attr(
37162 target_arch = "arm",
37163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37164)]
37165pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
37166 unsafe extern "unadjusted" {
37167 #[cfg_attr(
37168 any(target_arch = "aarch64", target_arch = "arm64ec"),
37169 link_name = "llvm.aarch64.neon.sqadd.v16i8"
37170 )]
37171 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v16i8")]
37172 fn _vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
37173 }
37174 unsafe { _vqaddq_s8(a, b) }
37175}
37176#[doc = "Saturating add"]
37177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"]
37178#[inline]
37179#[target_feature(enable = "neon")]
37180#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37181#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
37182#[cfg_attr(
37183 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37184 assert_instr(sqadd)
37185)]
37186#[cfg_attr(
37187 not(target_arch = "arm"),
37188 stable(feature = "neon_intrinsics", since = "1.59.0")
37189)]
37190#[cfg_attr(
37191 target_arch = "arm",
37192 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37193)]
37194pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
37195 unsafe extern "unadjusted" {
37196 #[cfg_attr(
37197 any(target_arch = "aarch64", target_arch = "arm64ec"),
37198 link_name = "llvm.aarch64.neon.sqadd.v4i16"
37199 )]
37200 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i16")]
37201 fn _vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
37202 }
37203 unsafe { _vqadd_s16(a, b) }
37204}
37205#[doc = "Saturating add"]
37206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"]
37207#[inline]
37208#[target_feature(enable = "neon")]
37209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37210#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
37211#[cfg_attr(
37212 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37213 assert_instr(sqadd)
37214)]
37215#[cfg_attr(
37216 not(target_arch = "arm"),
37217 stable(feature = "neon_intrinsics", since = "1.59.0")
37218)]
37219#[cfg_attr(
37220 target_arch = "arm",
37221 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37222)]
37223pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
37224 unsafe extern "unadjusted" {
37225 #[cfg_attr(
37226 any(target_arch = "aarch64", target_arch = "arm64ec"),
37227 link_name = "llvm.aarch64.neon.sqadd.v8i16"
37228 )]
37229 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i16")]
37230 fn _vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
37231 }
37232 unsafe { _vqaddq_s16(a, b) }
37233}
37234#[doc = "Saturating add"]
37235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"]
37236#[inline]
37237#[target_feature(enable = "neon")]
37238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37239#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
37240#[cfg_attr(
37241 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37242 assert_instr(sqadd)
37243)]
37244#[cfg_attr(
37245 not(target_arch = "arm"),
37246 stable(feature = "neon_intrinsics", since = "1.59.0")
37247)]
37248#[cfg_attr(
37249 target_arch = "arm",
37250 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37251)]
37252pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
37253 unsafe extern "unadjusted" {
37254 #[cfg_attr(
37255 any(target_arch = "aarch64", target_arch = "arm64ec"),
37256 link_name = "llvm.aarch64.neon.sqadd.v2i32"
37257 )]
37258 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i32")]
37259 fn _vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
37260 }
37261 unsafe { _vqadd_s32(a, b) }
37262}
37263#[doc = "Saturating add"]
37264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"]
37265#[inline]
37266#[target_feature(enable = "neon")]
37267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37268#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
37269#[cfg_attr(
37270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37271 assert_instr(sqadd)
37272)]
37273#[cfg_attr(
37274 not(target_arch = "arm"),
37275 stable(feature = "neon_intrinsics", since = "1.59.0")
37276)]
37277#[cfg_attr(
37278 target_arch = "arm",
37279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37280)]
37281pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
37282 unsafe extern "unadjusted" {
37283 #[cfg_attr(
37284 any(target_arch = "aarch64", target_arch = "arm64ec"),
37285 link_name = "llvm.aarch64.neon.sqadd.v4i32"
37286 )]
37287 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i32")]
37288 fn _vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
37289 }
37290 unsafe { _vqaddq_s32(a, b) }
37291}
37292#[doc = "Saturating add"]
37293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"]
37294#[inline]
37295#[target_feature(enable = "neon")]
37296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37297#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
37298#[cfg_attr(
37299 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37300 assert_instr(sqadd)
37301)]
37302#[cfg_attr(
37303 not(target_arch = "arm"),
37304 stable(feature = "neon_intrinsics", since = "1.59.0")
37305)]
37306#[cfg_attr(
37307 target_arch = "arm",
37308 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37309)]
37310pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
37311 unsafe extern "unadjusted" {
37312 #[cfg_attr(
37313 any(target_arch = "aarch64", target_arch = "arm64ec"),
37314 link_name = "llvm.aarch64.neon.sqadd.v1i64"
37315 )]
37316 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v1i64")]
37317 fn _vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
37318 }
37319 unsafe { _vqadd_s64(a, b) }
37320}
37321#[doc = "Saturating add"]
37322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"]
37323#[inline]
37324#[target_feature(enable = "neon")]
37325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37326#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
37327#[cfg_attr(
37328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37329 assert_instr(sqadd)
37330)]
37331#[cfg_attr(
37332 not(target_arch = "arm"),
37333 stable(feature = "neon_intrinsics", since = "1.59.0")
37334)]
37335#[cfg_attr(
37336 target_arch = "arm",
37337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37338)]
37339pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
37340 unsafe extern "unadjusted" {
37341 #[cfg_attr(
37342 any(target_arch = "aarch64", target_arch = "arm64ec"),
37343 link_name = "llvm.aarch64.neon.sqadd.v2i64"
37344 )]
37345 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i64")]
37346 fn _vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
37347 }
37348 unsafe { _vqaddq_s64(a, b) }
37349}
37350#[doc = "Saturating add"]
37351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"]
37352#[inline]
37353#[target_feature(enable = "neon")]
37354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37355#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
37356#[cfg_attr(
37357 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37358 assert_instr(uqadd)
37359)]
37360#[cfg_attr(
37361 not(target_arch = "arm"),
37362 stable(feature = "neon_intrinsics", since = "1.59.0")
37363)]
37364#[cfg_attr(
37365 target_arch = "arm",
37366 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37367)]
37368pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
37369 unsafe extern "unadjusted" {
37370 #[cfg_attr(
37371 any(target_arch = "aarch64", target_arch = "arm64ec"),
37372 link_name = "llvm.aarch64.neon.uqadd.v8i8"
37373 )]
37374 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i8")]
37375 fn _vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
37376 }
37377 unsafe { _vqadd_u8(a, b) }
37378}
37379#[doc = "Saturating add"]
37380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"]
37381#[inline]
37382#[target_feature(enable = "neon")]
37383#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37384#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
37385#[cfg_attr(
37386 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37387 assert_instr(uqadd)
37388)]
37389#[cfg_attr(
37390 not(target_arch = "arm"),
37391 stable(feature = "neon_intrinsics", since = "1.59.0")
37392)]
37393#[cfg_attr(
37394 target_arch = "arm",
37395 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37396)]
37397pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
37398 unsafe extern "unadjusted" {
37399 #[cfg_attr(
37400 any(target_arch = "aarch64", target_arch = "arm64ec"),
37401 link_name = "llvm.aarch64.neon.uqadd.v16i8"
37402 )]
37403 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v16i8")]
37404 fn _vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
37405 }
37406 unsafe { _vqaddq_u8(a, b) }
37407}
37408#[doc = "Saturating add"]
37409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"]
37410#[inline]
37411#[target_feature(enable = "neon")]
37412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37413#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
37414#[cfg_attr(
37415 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37416 assert_instr(uqadd)
37417)]
37418#[cfg_attr(
37419 not(target_arch = "arm"),
37420 stable(feature = "neon_intrinsics", since = "1.59.0")
37421)]
37422#[cfg_attr(
37423 target_arch = "arm",
37424 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37425)]
37426pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
37427 unsafe extern "unadjusted" {
37428 #[cfg_attr(
37429 any(target_arch = "aarch64", target_arch = "arm64ec"),
37430 link_name = "llvm.aarch64.neon.uqadd.v4i16"
37431 )]
37432 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i16")]
37433 fn _vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
37434 }
37435 unsafe { _vqadd_u16(a, b) }
37436}
37437#[doc = "Saturating add"]
37438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"]
37439#[inline]
37440#[target_feature(enable = "neon")]
37441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37442#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
37443#[cfg_attr(
37444 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37445 assert_instr(uqadd)
37446)]
37447#[cfg_attr(
37448 not(target_arch = "arm"),
37449 stable(feature = "neon_intrinsics", since = "1.59.0")
37450)]
37451#[cfg_attr(
37452 target_arch = "arm",
37453 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37454)]
37455pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
37456 unsafe extern "unadjusted" {
37457 #[cfg_attr(
37458 any(target_arch = "aarch64", target_arch = "arm64ec"),
37459 link_name = "llvm.aarch64.neon.uqadd.v8i16"
37460 )]
37461 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i16")]
37462 fn _vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
37463 }
37464 unsafe { _vqaddq_u16(a, b) }
37465}
37466#[doc = "Saturating add"]
37467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"]
37468#[inline]
37469#[target_feature(enable = "neon")]
37470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37471#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
37472#[cfg_attr(
37473 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37474 assert_instr(uqadd)
37475)]
37476#[cfg_attr(
37477 not(target_arch = "arm"),
37478 stable(feature = "neon_intrinsics", since = "1.59.0")
37479)]
37480#[cfg_attr(
37481 target_arch = "arm",
37482 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37483)]
37484pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
37485 unsafe extern "unadjusted" {
37486 #[cfg_attr(
37487 any(target_arch = "aarch64", target_arch = "arm64ec"),
37488 link_name = "llvm.aarch64.neon.uqadd.v2i32"
37489 )]
37490 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i32")]
37491 fn _vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
37492 }
37493 unsafe { _vqadd_u32(a, b) }
37494}
37495#[doc = "Saturating add"]
37496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"]
37497#[inline]
37498#[target_feature(enable = "neon")]
37499#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37500#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
37501#[cfg_attr(
37502 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37503 assert_instr(uqadd)
37504)]
37505#[cfg_attr(
37506 not(target_arch = "arm"),
37507 stable(feature = "neon_intrinsics", since = "1.59.0")
37508)]
37509#[cfg_attr(
37510 target_arch = "arm",
37511 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37512)]
37513pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
37514 unsafe extern "unadjusted" {
37515 #[cfg_attr(
37516 any(target_arch = "aarch64", target_arch = "arm64ec"),
37517 link_name = "llvm.aarch64.neon.uqadd.v4i32"
37518 )]
37519 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i32")]
37520 fn _vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
37521 }
37522 unsafe { _vqaddq_u32(a, b) }
37523}
37524#[doc = "Saturating add"]
37525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"]
37526#[inline]
37527#[target_feature(enable = "neon")]
37528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37529#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
37530#[cfg_attr(
37531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37532 assert_instr(uqadd)
37533)]
37534#[cfg_attr(
37535 not(target_arch = "arm"),
37536 stable(feature = "neon_intrinsics", since = "1.59.0")
37537)]
37538#[cfg_attr(
37539 target_arch = "arm",
37540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37541)]
37542pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
37543 unsafe extern "unadjusted" {
37544 #[cfg_attr(
37545 any(target_arch = "aarch64", target_arch = "arm64ec"),
37546 link_name = "llvm.aarch64.neon.uqadd.v1i64"
37547 )]
37548 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v1i64")]
37549 fn _vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t;
37550 }
37551 unsafe { _vqadd_u64(a, b) }
37552}
37553#[doc = "Saturating add"]
37554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"]
37555#[inline]
37556#[target_feature(enable = "neon")]
37557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37558#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
37559#[cfg_attr(
37560 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37561 assert_instr(uqadd)
37562)]
37563#[cfg_attr(
37564 not(target_arch = "arm"),
37565 stable(feature = "neon_intrinsics", since = "1.59.0")
37566)]
37567#[cfg_attr(
37568 target_arch = "arm",
37569 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37570)]
37571pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
37572 unsafe extern "unadjusted" {
37573 #[cfg_attr(
37574 any(target_arch = "aarch64", target_arch = "arm64ec"),
37575 link_name = "llvm.aarch64.neon.uqadd.v2i64"
37576 )]
37577 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i64")]
37578 fn _vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
37579 }
37580 unsafe { _vqaddq_u64(a, b) }
37581}
37582#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"]
37584#[inline]
37585#[target_feature(enable = "neon")]
37586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))]
37588#[cfg_attr(
37589 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37590 assert_instr(sqdmlal, N = 2)
37591)]
37592#[rustc_legacy_const_generics(3)]
37593#[cfg_attr(
37594 not(target_arch = "arm"),
37595 stable(feature = "neon_intrinsics", since = "1.59.0")
37596)]
37597#[cfg_attr(
37598 target_arch = "arm",
37599 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37600)]
37601pub fn vqdmlal_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37602 static_assert_uimm_bits!(N, 2);
37603 vqaddq_s32(a, vqdmull_lane_s16::<N>(b, c))
37604}
37605#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"]
37607#[inline]
37608#[target_feature(enable = "neon")]
37609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))]
37611#[cfg_attr(
37612 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37613 assert_instr(sqdmlal, N = 1)
37614)]
37615#[rustc_legacy_const_generics(3)]
37616#[cfg_attr(
37617 not(target_arch = "arm"),
37618 stable(feature = "neon_intrinsics", since = "1.59.0")
37619)]
37620#[cfg_attr(
37621 target_arch = "arm",
37622 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37623)]
37624pub fn vqdmlal_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37625 static_assert_uimm_bits!(N, 1);
37626 vqaddq_s64(a, vqdmull_lane_s32::<N>(b, c))
37627}
37628#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"]
37630#[inline]
37631#[target_feature(enable = "neon")]
37632#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37633#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37634#[cfg_attr(
37635 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37636 assert_instr(sqdmlal)
37637)]
37638#[cfg_attr(
37639 not(target_arch = "arm"),
37640 stable(feature = "neon_intrinsics", since = "1.59.0")
37641)]
37642#[cfg_attr(
37643 target_arch = "arm",
37644 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37645)]
37646pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
37647 vqaddq_s32(a, vqdmull_n_s16(b, c))
37648}
37649#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"]
37651#[inline]
37652#[target_feature(enable = "neon")]
37653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37654#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37655#[cfg_attr(
37656 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37657 assert_instr(sqdmlal)
37658)]
37659#[cfg_attr(
37660 not(target_arch = "arm"),
37661 stable(feature = "neon_intrinsics", since = "1.59.0")
37662)]
37663#[cfg_attr(
37664 target_arch = "arm",
37665 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37666)]
37667pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
37668 vqaddq_s64(a, vqdmull_n_s32(b, c))
37669}
37670#[doc = "Signed saturating doubling multiply-add long"]
37671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"]
37672#[inline]
37673#[target_feature(enable = "neon")]
37674#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37675#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37676#[cfg_attr(
37677 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37678 assert_instr(sqdmlal)
37679)]
37680#[cfg_attr(
37681 not(target_arch = "arm"),
37682 stable(feature = "neon_intrinsics", since = "1.59.0")
37683)]
37684#[cfg_attr(
37685 target_arch = "arm",
37686 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37687)]
37688pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37689 vqaddq_s32(a, vqdmull_s16(b, c))
37690}
37691#[doc = "Signed saturating doubling multiply-add long"]
37692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"]
37693#[inline]
37694#[target_feature(enable = "neon")]
37695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37696#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37697#[cfg_attr(
37698 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37699 assert_instr(sqdmlal)
37700)]
37701#[cfg_attr(
37702 not(target_arch = "arm"),
37703 stable(feature = "neon_intrinsics", since = "1.59.0")
37704)]
37705#[cfg_attr(
37706 target_arch = "arm",
37707 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37708)]
37709pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37710 vqaddq_s64(a, vqdmull_s32(b, c))
37711}
37712#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"]
37714#[inline]
37715#[target_feature(enable = "neon")]
37716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37717#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))]
37718#[cfg_attr(
37719 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37720 assert_instr(sqdmlsl, N = 2)
37721)]
37722#[rustc_legacy_const_generics(3)]
37723#[cfg_attr(
37724 not(target_arch = "arm"),
37725 stable(feature = "neon_intrinsics", since = "1.59.0")
37726)]
37727#[cfg_attr(
37728 target_arch = "arm",
37729 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37730)]
37731pub fn vqdmlsl_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37732 static_assert_uimm_bits!(N, 2);
37733 vqsubq_s32(a, vqdmull_lane_s16::<N>(b, c))
37734}
37735#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"]
37737#[inline]
37738#[target_feature(enable = "neon")]
37739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))]
37741#[cfg_attr(
37742 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37743 assert_instr(sqdmlsl, N = 1)
37744)]
37745#[rustc_legacy_const_generics(3)]
37746#[cfg_attr(
37747 not(target_arch = "arm"),
37748 stable(feature = "neon_intrinsics", since = "1.59.0")
37749)]
37750#[cfg_attr(
37751 target_arch = "arm",
37752 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37753)]
37754pub fn vqdmlsl_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37755 static_assert_uimm_bits!(N, 1);
37756 vqsubq_s64(a, vqdmull_lane_s32::<N>(b, c))
37757}
37758#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"]
37760#[inline]
37761#[target_feature(enable = "neon")]
37762#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37763#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37764#[cfg_attr(
37765 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37766 assert_instr(sqdmlsl)
37767)]
37768#[cfg_attr(
37769 not(target_arch = "arm"),
37770 stable(feature = "neon_intrinsics", since = "1.59.0")
37771)]
37772#[cfg_attr(
37773 target_arch = "arm",
37774 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37775)]
37776pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
37777 vqsubq_s32(a, vqdmull_n_s16(b, c))
37778}
37779#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"]
37781#[inline]
37782#[target_feature(enable = "neon")]
37783#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37784#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37785#[cfg_attr(
37786 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37787 assert_instr(sqdmlsl)
37788)]
37789#[cfg_attr(
37790 not(target_arch = "arm"),
37791 stable(feature = "neon_intrinsics", since = "1.59.0")
37792)]
37793#[cfg_attr(
37794 target_arch = "arm",
37795 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37796)]
37797pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
37798 vqsubq_s64(a, vqdmull_n_s32(b, c))
37799}
37800#[doc = "Signed saturating doubling multiply-subtract long"]
37801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"]
37802#[inline]
37803#[target_feature(enable = "neon")]
37804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37805#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37806#[cfg_attr(
37807 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37808 assert_instr(sqdmlsl)
37809)]
37810#[cfg_attr(
37811 not(target_arch = "arm"),
37812 stable(feature = "neon_intrinsics", since = "1.59.0")
37813)]
37814#[cfg_attr(
37815 target_arch = "arm",
37816 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37817)]
37818pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37819 vqsubq_s32(a, vqdmull_s16(b, c))
37820}
37821#[doc = "Signed saturating doubling multiply-subtract long"]
37822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"]
37823#[inline]
37824#[target_feature(enable = "neon")]
37825#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37826#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37827#[cfg_attr(
37828 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37829 assert_instr(sqdmlsl)
37830)]
37831#[cfg_attr(
37832 not(target_arch = "arm"),
37833 stable(feature = "neon_intrinsics", since = "1.59.0")
37834)]
37835#[cfg_attr(
37836 target_arch = "arm",
37837 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37838)]
37839pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37840 vqsubq_s64(a, vqdmull_s32(b, c))
37841}
37842#[doc = "Vector saturating doubling multiply high by scalar"]
37843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"]
37844#[inline]
37845#[target_feature(enable = "neon")]
37846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37847#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37848#[cfg_attr(
37849 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37850 assert_instr(sqdmulh, LANE = 0)
37851)]
37852#[rustc_legacy_const_generics(2)]
37853#[cfg_attr(
37854 not(target_arch = "arm"),
37855 stable(feature = "neon_intrinsics", since = "1.59.0")
37856)]
37857#[cfg_attr(
37858 target_arch = "arm",
37859 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37860)]
37861pub fn vqdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
37862 static_assert_uimm_bits!(LANE, 3);
37863 unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) }
37864}
37865#[doc = "Vector saturating doubling multiply high by scalar"]
37866#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"]
37867#[inline]
37868#[target_feature(enable = "neon")]
37869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37870#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37871#[cfg_attr(
37872 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37873 assert_instr(sqdmulh, LANE = 0)
37874)]
37875#[rustc_legacy_const_generics(2)]
37876#[cfg_attr(
37877 not(target_arch = "arm"),
37878 stable(feature = "neon_intrinsics", since = "1.59.0")
37879)]
37880#[cfg_attr(
37881 target_arch = "arm",
37882 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37883)]
37884pub fn vqdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
37885 static_assert_uimm_bits!(LANE, 3);
37886 unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) }
37887}
37888#[doc = "Vector saturating doubling multiply high by scalar"]
37889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"]
37890#[inline]
37891#[target_feature(enable = "neon")]
37892#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37893#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37894#[cfg_attr(
37895 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37896 assert_instr(sqdmulh, LANE = 0)
37897)]
37898#[rustc_legacy_const_generics(2)]
37899#[cfg_attr(
37900 not(target_arch = "arm"),
37901 stable(feature = "neon_intrinsics", since = "1.59.0")
37902)]
37903#[cfg_attr(
37904 target_arch = "arm",
37905 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37906)]
37907pub fn vqdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
37908 static_assert_uimm_bits!(LANE, 2);
37909 unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) }
37910}
37911#[doc = "Vector saturating doubling multiply high by scalar"]
37912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"]
37913#[inline]
37914#[target_feature(enable = "neon")]
37915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37917#[cfg_attr(
37918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37919 assert_instr(sqdmulh, LANE = 0)
37920)]
37921#[rustc_legacy_const_generics(2)]
37922#[cfg_attr(
37923 not(target_arch = "arm"),
37924 stable(feature = "neon_intrinsics", since = "1.59.0")
37925)]
37926#[cfg_attr(
37927 target_arch = "arm",
37928 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37929)]
37930pub fn vqdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
37931 static_assert_uimm_bits!(LANE, 2);
37932 unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) }
37933}
37934#[doc = "Vector saturating doubling multiply high with scalar"]
37935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"]
37936#[inline]
37937#[target_feature(enable = "neon")]
37938#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37939#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37940#[cfg_attr(
37941 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37942 assert_instr(sqdmulh)
37943)]
37944#[cfg_attr(
37945 not(target_arch = "arm"),
37946 stable(feature = "neon_intrinsics", since = "1.59.0")
37947)]
37948#[cfg_attr(
37949 target_arch = "arm",
37950 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37951)]
37952pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
37953 let b: int16x4_t = vdup_n_s16(b);
37954 vqdmulh_s16(a, b)
37955}
37956#[doc = "Vector saturating doubling multiply high with scalar"]
37957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"]
37958#[inline]
37959#[target_feature(enable = "neon")]
37960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37961#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37962#[cfg_attr(
37963 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37964 assert_instr(sqdmulh)
37965)]
37966#[cfg_attr(
37967 not(target_arch = "arm"),
37968 stable(feature = "neon_intrinsics", since = "1.59.0")
37969)]
37970#[cfg_attr(
37971 target_arch = "arm",
37972 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37973)]
37974pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
37975 let b: int16x8_t = vdupq_n_s16(b);
37976 vqdmulhq_s16(a, b)
37977}
37978#[doc = "Vector saturating doubling multiply high with scalar"]
37979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"]
37980#[inline]
37981#[target_feature(enable = "neon")]
37982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37983#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37984#[cfg_attr(
37985 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37986 assert_instr(sqdmulh)
37987)]
37988#[cfg_attr(
37989 not(target_arch = "arm"),
37990 stable(feature = "neon_intrinsics", since = "1.59.0")
37991)]
37992#[cfg_attr(
37993 target_arch = "arm",
37994 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37995)]
37996pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
37997 let b: int32x2_t = vdup_n_s32(b);
37998 vqdmulh_s32(a, b)
37999}
38000#[doc = "Vector saturating doubling multiply high with scalar"]
38001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"]
38002#[inline]
38003#[target_feature(enable = "neon")]
38004#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38005#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38006#[cfg_attr(
38007 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38008 assert_instr(sqdmulh)
38009)]
38010#[cfg_attr(
38011 not(target_arch = "arm"),
38012 stable(feature = "neon_intrinsics", since = "1.59.0")
38013)]
38014#[cfg_attr(
38015 target_arch = "arm",
38016 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38017)]
38018pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
38019 let b: int32x4_t = vdupq_n_s32(b);
38020 vqdmulhq_s32(a, b)
38021}
38022#[doc = "Signed saturating doubling multiply returning high half"]
38023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"]
38024#[inline]
38025#[target_feature(enable = "neon")]
38026#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38027#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38028#[cfg_attr(
38029 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38030 assert_instr(sqdmulh)
38031)]
38032#[cfg_attr(
38033 not(target_arch = "arm"),
38034 stable(feature = "neon_intrinsics", since = "1.59.0")
38035)]
38036#[cfg_attr(
38037 target_arch = "arm",
38038 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38039)]
38040pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
38041 unsafe extern "unadjusted" {
38042 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i16")]
38043 #[cfg_attr(
38044 any(target_arch = "aarch64", target_arch = "arm64ec"),
38045 link_name = "llvm.aarch64.neon.sqdmulh.v4i16"
38046 )]
38047 fn _vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
38048 }
38049 unsafe { _vqdmulh_s16(a, b) }
38050}
38051#[doc = "Signed saturating doubling multiply returning high half"]
38052#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"]
38053#[inline]
38054#[target_feature(enable = "neon")]
38055#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38056#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38057#[cfg_attr(
38058 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38059 assert_instr(sqdmulh)
38060)]
38061#[cfg_attr(
38062 not(target_arch = "arm"),
38063 stable(feature = "neon_intrinsics", since = "1.59.0")
38064)]
38065#[cfg_attr(
38066 target_arch = "arm",
38067 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38068)]
38069pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
38070 unsafe extern "unadjusted" {
38071 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v8i16")]
38072 #[cfg_attr(
38073 any(target_arch = "aarch64", target_arch = "arm64ec"),
38074 link_name = "llvm.aarch64.neon.sqdmulh.v8i16"
38075 )]
38076 fn _vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
38077 }
38078 unsafe { _vqdmulhq_s16(a, b) }
38079}
38080#[doc = "Signed saturating doubling multiply returning high half"]
38081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"]
38082#[inline]
38083#[target_feature(enable = "neon")]
38084#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38085#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38086#[cfg_attr(
38087 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38088 assert_instr(sqdmulh)
38089)]
38090#[cfg_attr(
38091 not(target_arch = "arm"),
38092 stable(feature = "neon_intrinsics", since = "1.59.0")
38093)]
38094#[cfg_attr(
38095 target_arch = "arm",
38096 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38097)]
38098pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
38099 unsafe extern "unadjusted" {
38100 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v2i32")]
38101 #[cfg_attr(
38102 any(target_arch = "aarch64", target_arch = "arm64ec"),
38103 link_name = "llvm.aarch64.neon.sqdmulh.v2i32"
38104 )]
38105 fn _vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
38106 }
38107 unsafe { _vqdmulh_s32(a, b) }
38108}
38109#[doc = "Signed saturating doubling multiply returning high half"]
38110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"]
38111#[inline]
38112#[target_feature(enable = "neon")]
38113#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38114#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
38115#[cfg_attr(
38116 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38117 assert_instr(sqdmulh)
38118)]
38119#[cfg_attr(
38120 not(target_arch = "arm"),
38121 stable(feature = "neon_intrinsics", since = "1.59.0")
38122)]
38123#[cfg_attr(
38124 target_arch = "arm",
38125 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38126)]
38127pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
38128 unsafe extern "unadjusted" {
38129 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i32")]
38130 #[cfg_attr(
38131 any(target_arch = "aarch64", target_arch = "arm64ec"),
38132 link_name = "llvm.aarch64.neon.sqdmulh.v4i32"
38133 )]
38134 fn _vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
38135 }
38136 unsafe { _vqdmulhq_s32(a, b) }
38137}
38138#[doc = "Vector saturating doubling long multiply by scalar"]
38139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"]
38140#[inline]
38141#[target_feature(enable = "neon")]
38142#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38143#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))]
38144#[cfg_attr(
38145 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38146 assert_instr(sqdmull, N = 2)
38147)]
38148#[rustc_legacy_const_generics(2)]
38149#[cfg_attr(
38150 not(target_arch = "arm"),
38151 stable(feature = "neon_intrinsics", since = "1.59.0")
38152)]
38153#[cfg_attr(
38154 target_arch = "arm",
38155 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38156)]
38157pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
38158 static_assert_uimm_bits!(N, 2);
38159 unsafe {
38160 let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]);
38161 vqdmull_s16(a, b)
38162 }
38163}
38164#[doc = "Vector saturating doubling long multiply by scalar"]
38165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"]
38166#[inline]
38167#[target_feature(enable = "neon")]
38168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38169#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))]
38170#[cfg_attr(
38171 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38172 assert_instr(sqdmull, N = 1)
38173)]
38174#[rustc_legacy_const_generics(2)]
38175#[cfg_attr(
38176 not(target_arch = "arm"),
38177 stable(feature = "neon_intrinsics", since = "1.59.0")
38178)]
38179#[cfg_attr(
38180 target_arch = "arm",
38181 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38182)]
38183pub fn vqdmull_lane_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
38184 static_assert_uimm_bits!(N, 1);
38185 unsafe {
38186 let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]);
38187 vqdmull_s32(a, b)
38188 }
38189}
38190#[doc = "Vector saturating doubling long multiply with scalar"]
38191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"]
38192#[inline]
38193#[target_feature(enable = "neon")]
38194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38195#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38196#[cfg_attr(
38197 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38198 assert_instr(sqdmull)
38199)]
38200#[cfg_attr(
38201 not(target_arch = "arm"),
38202 stable(feature = "neon_intrinsics", since = "1.59.0")
38203)]
38204#[cfg_attr(
38205 target_arch = "arm",
38206 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38207)]
38208pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
38209 vqdmull_s16(a, vdup_n_s16(b))
38210}
38211#[doc = "Vector saturating doubling long multiply with scalar"]
38212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"]
38213#[inline]
38214#[target_feature(enable = "neon")]
38215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38216#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38217#[cfg_attr(
38218 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38219 assert_instr(sqdmull)
38220)]
38221#[cfg_attr(
38222 not(target_arch = "arm"),
38223 stable(feature = "neon_intrinsics", since = "1.59.0")
38224)]
38225#[cfg_attr(
38226 target_arch = "arm",
38227 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38228)]
38229pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
38230 vqdmull_s32(a, vdup_n_s32(b))
38231}
38232#[doc = "Signed saturating doubling multiply long"]
38233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"]
38234#[inline]
38235#[target_feature(enable = "neon")]
38236#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38237#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38238#[cfg_attr(
38239 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38240 assert_instr(sqdmull)
38241)]
38242#[cfg_attr(
38243 not(target_arch = "arm"),
38244 stable(feature = "neon_intrinsics", since = "1.59.0")
38245)]
38246#[cfg_attr(
38247 target_arch = "arm",
38248 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38249)]
38250pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
38251 unsafe extern "unadjusted" {
38252 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v4i32")]
38253 #[cfg_attr(
38254 any(target_arch = "aarch64", target_arch = "arm64ec"),
38255 link_name = "llvm.aarch64.neon.sqdmull.v4i32"
38256 )]
38257 fn _vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t;
38258 }
38259 unsafe { _vqdmull_s16(a, b) }
38260}
38261#[doc = "Signed saturating doubling multiply long"]
38262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"]
38263#[inline]
38264#[target_feature(enable = "neon")]
38265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
38267#[cfg_attr(
38268 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38269 assert_instr(sqdmull)
38270)]
38271#[cfg_attr(
38272 not(target_arch = "arm"),
38273 stable(feature = "neon_intrinsics", since = "1.59.0")
38274)]
38275#[cfg_attr(
38276 target_arch = "arm",
38277 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38278)]
38279pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
38280 unsafe extern "unadjusted" {
38281 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v2i64")]
38282 #[cfg_attr(
38283 any(target_arch = "aarch64", target_arch = "arm64ec"),
38284 link_name = "llvm.aarch64.neon.sqdmull.v2i64"
38285 )]
38286 fn _vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t;
38287 }
38288 unsafe { _vqdmull_s32(a, b) }
38289}
38290#[doc = "Signed saturating extract narrow"]
38291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"]
38292#[inline]
38293#[target_feature(enable = "neon")]
38294#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38295#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38296#[cfg_attr(
38297 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38298 assert_instr(sqxtn)
38299)]
38300#[cfg_attr(
38301 not(target_arch = "arm"),
38302 stable(feature = "neon_intrinsics", since = "1.59.0")
38303)]
38304#[cfg_attr(
38305 target_arch = "arm",
38306 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38307)]
38308pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t {
38309 unsafe extern "unadjusted" {
38310 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v8i8")]
38311 #[cfg_attr(
38312 any(target_arch = "aarch64", target_arch = "arm64ec"),
38313 link_name = "llvm.aarch64.neon.sqxtn.v8i8"
38314 )]
38315 fn _vqmovn_s16(a: int16x8_t) -> int8x8_t;
38316 }
38317 unsafe { _vqmovn_s16(a) }
38318}
38319#[doc = "Signed saturating extract narrow"]
38320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"]
38321#[inline]
38322#[target_feature(enable = "neon")]
38323#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38324#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38325#[cfg_attr(
38326 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38327 assert_instr(sqxtn)
38328)]
38329#[cfg_attr(
38330 not(target_arch = "arm"),
38331 stable(feature = "neon_intrinsics", since = "1.59.0")
38332)]
38333#[cfg_attr(
38334 target_arch = "arm",
38335 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38336)]
38337pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t {
38338 unsafe extern "unadjusted" {
38339 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v4i16")]
38340 #[cfg_attr(
38341 any(target_arch = "aarch64", target_arch = "arm64ec"),
38342 link_name = "llvm.aarch64.neon.sqxtn.v4i16"
38343 )]
38344 fn _vqmovn_s32(a: int32x4_t) -> int16x4_t;
38345 }
38346 unsafe { _vqmovn_s32(a) }
38347}
38348#[doc = "Signed saturating extract narrow"]
38349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"]
38350#[inline]
38351#[target_feature(enable = "neon")]
38352#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38353#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38354#[cfg_attr(
38355 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38356 assert_instr(sqxtn)
38357)]
38358#[cfg_attr(
38359 not(target_arch = "arm"),
38360 stable(feature = "neon_intrinsics", since = "1.59.0")
38361)]
38362#[cfg_attr(
38363 target_arch = "arm",
38364 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38365)]
38366pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t {
38367 unsafe extern "unadjusted" {
38368 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v2i32")]
38369 #[cfg_attr(
38370 any(target_arch = "aarch64", target_arch = "arm64ec"),
38371 link_name = "llvm.aarch64.neon.sqxtn.v2i32"
38372 )]
38373 fn _vqmovn_s64(a: int64x2_t) -> int32x2_t;
38374 }
38375 unsafe { _vqmovn_s64(a) }
38376}
38377#[doc = "Unsigned saturating extract narrow"]
38378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"]
38379#[inline]
38380#[target_feature(enable = "neon")]
38381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38383#[cfg_attr(
38384 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38385 assert_instr(uqxtn)
38386)]
38387#[cfg_attr(
38388 not(target_arch = "arm"),
38389 stable(feature = "neon_intrinsics", since = "1.59.0")
38390)]
38391#[cfg_attr(
38392 target_arch = "arm",
38393 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38394)]
38395pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t {
38396 unsafe extern "unadjusted" {
38397 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v8i8")]
38398 #[cfg_attr(
38399 any(target_arch = "aarch64", target_arch = "arm64ec"),
38400 link_name = "llvm.aarch64.neon.uqxtn.v8i8"
38401 )]
38402 fn _vqmovn_u16(a: uint16x8_t) -> uint8x8_t;
38403 }
38404 unsafe { _vqmovn_u16(a) }
38405}
38406#[doc = "Unsigned saturating extract narrow"]
38407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"]
38408#[inline]
38409#[target_feature(enable = "neon")]
38410#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38411#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38412#[cfg_attr(
38413 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38414 assert_instr(uqxtn)
38415)]
38416#[cfg_attr(
38417 not(target_arch = "arm"),
38418 stable(feature = "neon_intrinsics", since = "1.59.0")
38419)]
38420#[cfg_attr(
38421 target_arch = "arm",
38422 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38423)]
38424pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t {
38425 unsafe extern "unadjusted" {
38426 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v4i16")]
38427 #[cfg_attr(
38428 any(target_arch = "aarch64", target_arch = "arm64ec"),
38429 link_name = "llvm.aarch64.neon.uqxtn.v4i16"
38430 )]
38431 fn _vqmovn_u32(a: uint32x4_t) -> uint16x4_t;
38432 }
38433 unsafe { _vqmovn_u32(a) }
38434}
38435#[doc = "Unsigned saturating extract narrow"]
38436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"]
38437#[inline]
38438#[target_feature(enable = "neon")]
38439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38440#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38441#[cfg_attr(
38442 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38443 assert_instr(uqxtn)
38444)]
38445#[cfg_attr(
38446 not(target_arch = "arm"),
38447 stable(feature = "neon_intrinsics", since = "1.59.0")
38448)]
38449#[cfg_attr(
38450 target_arch = "arm",
38451 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38452)]
38453pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t {
38454 unsafe extern "unadjusted" {
38455 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v2i32")]
38456 #[cfg_attr(
38457 any(target_arch = "aarch64", target_arch = "arm64ec"),
38458 link_name = "llvm.aarch64.neon.uqxtn.v2i32"
38459 )]
38460 fn _vqmovn_u64(a: uint64x2_t) -> uint32x2_t;
38461 }
38462 unsafe { _vqmovn_u64(a) }
38463}
38464#[doc = "Signed saturating extract unsigned narrow"]
38465#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"]
38466#[inline]
38467#[target_feature(enable = "neon")]
38468#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38469#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38470#[cfg_attr(
38471 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38472 assert_instr(sqxtun)
38473)]
38474#[cfg_attr(
38475 not(target_arch = "arm"),
38476 stable(feature = "neon_intrinsics", since = "1.59.0")
38477)]
38478#[cfg_attr(
38479 target_arch = "arm",
38480 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38481)]
38482pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t {
38483 unsafe extern "unadjusted" {
38484 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v8i8")]
38485 #[cfg_attr(
38486 any(target_arch = "aarch64", target_arch = "arm64ec"),
38487 link_name = "llvm.aarch64.neon.sqxtun.v8i8"
38488 )]
38489 fn _vqmovun_s16(a: int16x8_t) -> uint8x8_t;
38490 }
38491 unsafe { _vqmovun_s16(a) }
38492}
38493#[doc = "Signed saturating extract unsigned narrow"]
38494#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"]
38495#[inline]
38496#[target_feature(enable = "neon")]
38497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38498#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38499#[cfg_attr(
38500 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38501 assert_instr(sqxtun)
38502)]
38503#[cfg_attr(
38504 not(target_arch = "arm"),
38505 stable(feature = "neon_intrinsics", since = "1.59.0")
38506)]
38507#[cfg_attr(
38508 target_arch = "arm",
38509 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38510)]
38511pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t {
38512 unsafe extern "unadjusted" {
38513 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v4i16")]
38514 #[cfg_attr(
38515 any(target_arch = "aarch64", target_arch = "arm64ec"),
38516 link_name = "llvm.aarch64.neon.sqxtun.v4i16"
38517 )]
38518 fn _vqmovun_s32(a: int32x4_t) -> uint16x4_t;
38519 }
38520 unsafe { _vqmovun_s32(a) }
38521}
38522#[doc = "Signed saturating extract unsigned narrow"]
38523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"]
38524#[inline]
38525#[target_feature(enable = "neon")]
38526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38527#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38528#[cfg_attr(
38529 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38530 assert_instr(sqxtun)
38531)]
38532#[cfg_attr(
38533 not(target_arch = "arm"),
38534 stable(feature = "neon_intrinsics", since = "1.59.0")
38535)]
38536#[cfg_attr(
38537 target_arch = "arm",
38538 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38539)]
38540pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t {
38541 unsafe extern "unadjusted" {
38542 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v2i32")]
38543 #[cfg_attr(
38544 any(target_arch = "aarch64", target_arch = "arm64ec"),
38545 link_name = "llvm.aarch64.neon.sqxtun.v2i32"
38546 )]
38547 fn _vqmovun_s64(a: int64x2_t) -> uint32x2_t;
38548 }
38549 unsafe { _vqmovun_s64(a) }
38550}
38551#[doc = "Signed saturating negate"]
38552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"]
38553#[inline]
38554#[target_feature(enable = "neon")]
38555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38556#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
38557#[cfg_attr(
38558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38559 assert_instr(sqneg)
38560)]
38561#[cfg_attr(
38562 not(target_arch = "arm"),
38563 stable(feature = "neon_intrinsics", since = "1.59.0")
38564)]
38565#[cfg_attr(
38566 target_arch = "arm",
38567 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38568)]
38569pub fn vqneg_s8(a: int8x8_t) -> int8x8_t {
38570 unsafe extern "unadjusted" {
38571 #[cfg_attr(
38572 any(target_arch = "aarch64", target_arch = "arm64ec"),
38573 link_name = "llvm.aarch64.neon.sqneg.v8i8"
38574 )]
38575 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i8")]
38576 fn _vqneg_s8(a: int8x8_t) -> int8x8_t;
38577 }
38578 unsafe { _vqneg_s8(a) }
38579}
38580#[doc = "Signed saturating negate"]
38581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"]
38582#[inline]
38583#[target_feature(enable = "neon")]
38584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38585#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
38586#[cfg_attr(
38587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38588 assert_instr(sqneg)
38589)]
38590#[cfg_attr(
38591 not(target_arch = "arm"),
38592 stable(feature = "neon_intrinsics", since = "1.59.0")
38593)]
38594#[cfg_attr(
38595 target_arch = "arm",
38596 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38597)]
38598pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t {
38599 unsafe extern "unadjusted" {
38600 #[cfg_attr(
38601 any(target_arch = "aarch64", target_arch = "arm64ec"),
38602 link_name = "llvm.aarch64.neon.sqneg.v16i8"
38603 )]
38604 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v16i8")]
38605 fn _vqnegq_s8(a: int8x16_t) -> int8x16_t;
38606 }
38607 unsafe { _vqnegq_s8(a) }
38608}
38609#[doc = "Signed saturating negate"]
38610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"]
38611#[inline]
38612#[target_feature(enable = "neon")]
38613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38614#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
38615#[cfg_attr(
38616 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38617 assert_instr(sqneg)
38618)]
38619#[cfg_attr(
38620 not(target_arch = "arm"),
38621 stable(feature = "neon_intrinsics", since = "1.59.0")
38622)]
38623#[cfg_attr(
38624 target_arch = "arm",
38625 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38626)]
38627pub fn vqneg_s16(a: int16x4_t) -> int16x4_t {
38628 unsafe extern "unadjusted" {
38629 #[cfg_attr(
38630 any(target_arch = "aarch64", target_arch = "arm64ec"),
38631 link_name = "llvm.aarch64.neon.sqneg.v4i16"
38632 )]
38633 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i16")]
38634 fn _vqneg_s16(a: int16x4_t) -> int16x4_t;
38635 }
38636 unsafe { _vqneg_s16(a) }
38637}
38638#[doc = "Signed saturating negate"]
38639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"]
38640#[inline]
38641#[target_feature(enable = "neon")]
38642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38643#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
38644#[cfg_attr(
38645 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38646 assert_instr(sqneg)
38647)]
38648#[cfg_attr(
38649 not(target_arch = "arm"),
38650 stable(feature = "neon_intrinsics", since = "1.59.0")
38651)]
38652#[cfg_attr(
38653 target_arch = "arm",
38654 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38655)]
38656pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t {
38657 unsafe extern "unadjusted" {
38658 #[cfg_attr(
38659 any(target_arch = "aarch64", target_arch = "arm64ec"),
38660 link_name = "llvm.aarch64.neon.sqneg.v8i16"
38661 )]
38662 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i16")]
38663 fn _vqnegq_s16(a: int16x8_t) -> int16x8_t;
38664 }
38665 unsafe { _vqnegq_s16(a) }
38666}
38667#[doc = "Signed saturating negate"]
38668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"]
38669#[inline]
38670#[target_feature(enable = "neon")]
38671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38672#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
38673#[cfg_attr(
38674 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38675 assert_instr(sqneg)
38676)]
38677#[cfg_attr(
38678 not(target_arch = "arm"),
38679 stable(feature = "neon_intrinsics", since = "1.59.0")
38680)]
38681#[cfg_attr(
38682 target_arch = "arm",
38683 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38684)]
38685pub fn vqneg_s32(a: int32x2_t) -> int32x2_t {
38686 unsafe extern "unadjusted" {
38687 #[cfg_attr(
38688 any(target_arch = "aarch64", target_arch = "arm64ec"),
38689 link_name = "llvm.aarch64.neon.sqneg.v2i32"
38690 )]
38691 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v2i32")]
38692 fn _vqneg_s32(a: int32x2_t) -> int32x2_t;
38693 }
38694 unsafe { _vqneg_s32(a) }
38695}
38696#[doc = "Signed saturating negate"]
38697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"]
38698#[inline]
38699#[target_feature(enable = "neon")]
38700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38701#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
38702#[cfg_attr(
38703 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38704 assert_instr(sqneg)
38705)]
38706#[cfg_attr(
38707 not(target_arch = "arm"),
38708 stable(feature = "neon_intrinsics", since = "1.59.0")
38709)]
38710#[cfg_attr(
38711 target_arch = "arm",
38712 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38713)]
38714pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t {
38715 unsafe extern "unadjusted" {
38716 #[cfg_attr(
38717 any(target_arch = "aarch64", target_arch = "arm64ec"),
38718 link_name = "llvm.aarch64.neon.sqneg.v4i32"
38719 )]
38720 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i32")]
38721 fn _vqnegq_s32(a: int32x4_t) -> int32x4_t;
38722 }
38723 unsafe { _vqnegq_s32(a) }
38724}
38725#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"]
38727#[inline]
38728#[target_feature(enable = "neon")]
38729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38730#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38731#[cfg_attr(
38732 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38733 assert_instr(sqrdmulh, LANE = 1)
38734)]
38735#[rustc_legacy_const_generics(2)]
38736#[cfg_attr(
38737 not(target_arch = "arm"),
38738 stable(feature = "neon_intrinsics", since = "1.59.0")
38739)]
38740#[cfg_attr(
38741 target_arch = "arm",
38742 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38743)]
38744pub fn vqrdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
38745 static_assert_uimm_bits!(LANE, 2);
38746 unsafe {
38747 let b: int16x4_t =
38748 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38749 vqrdmulh_s16(a, b)
38750 }
38751}
38752#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"]
38754#[inline]
38755#[target_feature(enable = "neon")]
38756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38758#[cfg_attr(
38759 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38760 assert_instr(sqrdmulh, LANE = 1)
38761)]
38762#[rustc_legacy_const_generics(2)]
38763#[cfg_attr(
38764 not(target_arch = "arm"),
38765 stable(feature = "neon_intrinsics", since = "1.59.0")
38766)]
38767#[cfg_attr(
38768 target_arch = "arm",
38769 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38770)]
38771pub fn vqrdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
38772 static_assert_uimm_bits!(LANE, 1);
38773 unsafe {
38774 let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
38775 vqrdmulh_s32(a, b)
38776 }
38777}
38778#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"]
38780#[inline]
38781#[target_feature(enable = "neon")]
38782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38783#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38784#[cfg_attr(
38785 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38786 assert_instr(sqrdmulh, LANE = 1)
38787)]
38788#[rustc_legacy_const_generics(2)]
38789#[cfg_attr(
38790 not(target_arch = "arm"),
38791 stable(feature = "neon_intrinsics", since = "1.59.0")
38792)]
38793#[cfg_attr(
38794 target_arch = "arm",
38795 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38796)]
38797pub fn vqrdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
38798 static_assert_uimm_bits!(LANE, 3);
38799 unsafe {
38800 let b: int16x4_t =
38801 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38802 vqrdmulh_s16(a, b)
38803 }
38804}
38805#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"]
38807#[inline]
38808#[target_feature(enable = "neon")]
38809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38811#[cfg_attr(
38812 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38813 assert_instr(sqrdmulh, LANE = 1)
38814)]
38815#[rustc_legacy_const_generics(2)]
38816#[cfg_attr(
38817 not(target_arch = "arm"),
38818 stable(feature = "neon_intrinsics", since = "1.59.0")
38819)]
38820#[cfg_attr(
38821 target_arch = "arm",
38822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38823)]
38824pub fn vqrdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
38825 static_assert_uimm_bits!(LANE, 2);
38826 unsafe {
38827 let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
38828 vqrdmulh_s32(a, b)
38829 }
38830}
38831#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"]
38833#[inline]
38834#[target_feature(enable = "neon")]
38835#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38836#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38837#[cfg_attr(
38838 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38839 assert_instr(sqrdmulh, LANE = 1)
38840)]
38841#[rustc_legacy_const_generics(2)]
38842#[cfg_attr(
38843 not(target_arch = "arm"),
38844 stable(feature = "neon_intrinsics", since = "1.59.0")
38845)]
38846#[cfg_attr(
38847 target_arch = "arm",
38848 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38849)]
38850pub fn vqrdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
38851 static_assert_uimm_bits!(LANE, 2);
38852 unsafe {
38853 let b: int16x8_t = simd_shuffle!(
38854 b,
38855 b,
38856 [
38857 LANE as u32,
38858 LANE as u32,
38859 LANE as u32,
38860 LANE as u32,
38861 LANE as u32,
38862 LANE as u32,
38863 LANE as u32,
38864 LANE as u32
38865 ]
38866 );
38867 vqrdmulhq_s16(a, b)
38868 }
38869}
38870#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"]
38872#[inline]
38873#[target_feature(enable = "neon")]
38874#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38875#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38876#[cfg_attr(
38877 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38878 assert_instr(sqrdmulh, LANE = 1)
38879)]
38880#[rustc_legacy_const_generics(2)]
38881#[cfg_attr(
38882 not(target_arch = "arm"),
38883 stable(feature = "neon_intrinsics", since = "1.59.0")
38884)]
38885#[cfg_attr(
38886 target_arch = "arm",
38887 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38888)]
38889pub fn vqrdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
38890 static_assert_uimm_bits!(LANE, 1);
38891 unsafe {
38892 let b: int32x4_t =
38893 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38894 vqrdmulhq_s32(a, b)
38895 }
38896}
38897#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"]
38899#[inline]
38900#[target_feature(enable = "neon")]
38901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38903#[cfg_attr(
38904 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38905 assert_instr(sqrdmulh, LANE = 1)
38906)]
38907#[rustc_legacy_const_generics(2)]
38908#[cfg_attr(
38909 not(target_arch = "arm"),
38910 stable(feature = "neon_intrinsics", since = "1.59.0")
38911)]
38912#[cfg_attr(
38913 target_arch = "arm",
38914 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38915)]
38916pub fn vqrdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
38917 static_assert_uimm_bits!(LANE, 3);
38918 unsafe {
38919 let b: int16x8_t = simd_shuffle!(
38920 b,
38921 b,
38922 [
38923 LANE as u32,
38924 LANE as u32,
38925 LANE as u32,
38926 LANE as u32,
38927 LANE as u32,
38928 LANE as u32,
38929 LANE as u32,
38930 LANE as u32
38931 ]
38932 );
38933 vqrdmulhq_s16(a, b)
38934 }
38935}
38936#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"]
38938#[inline]
38939#[target_feature(enable = "neon")]
38940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38941#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38942#[cfg_attr(
38943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38944 assert_instr(sqrdmulh, LANE = 1)
38945)]
38946#[rustc_legacy_const_generics(2)]
38947#[cfg_attr(
38948 not(target_arch = "arm"),
38949 stable(feature = "neon_intrinsics", since = "1.59.0")
38950)]
38951#[cfg_attr(
38952 target_arch = "arm",
38953 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38954)]
38955pub fn vqrdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
38956 static_assert_uimm_bits!(LANE, 2);
38957 unsafe {
38958 let b: int32x4_t =
38959 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38960 vqrdmulhq_s32(a, b)
38961 }
38962}
38963#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"]
38965#[inline]
38966#[target_feature(enable = "neon")]
38967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38969#[cfg_attr(
38970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38971 assert_instr(sqrdmulh)
38972)]
38973#[cfg_attr(
38974 not(target_arch = "arm"),
38975 stable(feature = "neon_intrinsics", since = "1.59.0")
38976)]
38977#[cfg_attr(
38978 target_arch = "arm",
38979 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38980)]
38981pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
38982 vqrdmulh_s16(a, vdup_n_s16(b))
38983}
38984#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"]
38986#[inline]
38987#[target_feature(enable = "neon")]
38988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38989#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38990#[cfg_attr(
38991 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38992 assert_instr(sqrdmulh)
38993)]
38994#[cfg_attr(
38995 not(target_arch = "arm"),
38996 stable(feature = "neon_intrinsics", since = "1.59.0")
38997)]
38998#[cfg_attr(
38999 target_arch = "arm",
39000 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39001)]
39002pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
39003 vqrdmulhq_s16(a, vdupq_n_s16(b))
39004}
39005#[doc = "Vector saturating rounding doubling multiply high with scalar"]
39006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"]
39007#[inline]
39008#[target_feature(enable = "neon")]
39009#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39010#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39011#[cfg_attr(
39012 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39013 assert_instr(sqrdmulh)
39014)]
39015#[cfg_attr(
39016 not(target_arch = "arm"),
39017 stable(feature = "neon_intrinsics", since = "1.59.0")
39018)]
39019#[cfg_attr(
39020 target_arch = "arm",
39021 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39022)]
39023pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
39024 vqrdmulh_s32(a, vdup_n_s32(b))
39025}
39026#[doc = "Vector saturating rounding doubling multiply high with scalar"]
39027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"]
39028#[inline]
39029#[target_feature(enable = "neon")]
39030#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39031#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39032#[cfg_attr(
39033 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39034 assert_instr(sqrdmulh)
39035)]
39036#[cfg_attr(
39037 not(target_arch = "arm"),
39038 stable(feature = "neon_intrinsics", since = "1.59.0")
39039)]
39040#[cfg_attr(
39041 target_arch = "arm",
39042 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39043)]
39044pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
39045 vqrdmulhq_s32(a, vdupq_n_s32(b))
39046}
39047#[doc = "Signed saturating rounding doubling multiply returning high half"]
39048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"]
39049#[inline]
39050#[target_feature(enable = "neon")]
39051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39053#[cfg_attr(
39054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39055 assert_instr(sqrdmulh)
39056)]
39057#[cfg_attr(
39058 not(target_arch = "arm"),
39059 stable(feature = "neon_intrinsics", since = "1.59.0")
39060)]
39061#[cfg_attr(
39062 target_arch = "arm",
39063 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39064)]
39065pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
39066 unsafe extern "unadjusted" {
39067 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i16")]
39068 #[cfg_attr(
39069 any(target_arch = "aarch64", target_arch = "arm64ec"),
39070 link_name = "llvm.aarch64.neon.sqrdmulh.v4i16"
39071 )]
39072 fn _vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
39073 }
39074 unsafe { _vqrdmulh_s16(a, b) }
39075}
39076#[doc = "Signed saturating rounding doubling multiply returning high half"]
39077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"]
39078#[inline]
39079#[target_feature(enable = "neon")]
39080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39081#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39082#[cfg_attr(
39083 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39084 assert_instr(sqrdmulh)
39085)]
39086#[cfg_attr(
39087 not(target_arch = "arm"),
39088 stable(feature = "neon_intrinsics", since = "1.59.0")
39089)]
39090#[cfg_attr(
39091 target_arch = "arm",
39092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39093)]
39094pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
39095 unsafe extern "unadjusted" {
39096 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v8i16")]
39097 #[cfg_attr(
39098 any(target_arch = "aarch64", target_arch = "arm64ec"),
39099 link_name = "llvm.aarch64.neon.sqrdmulh.v8i16"
39100 )]
39101 fn _vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
39102 }
39103 unsafe { _vqrdmulhq_s16(a, b) }
39104}
39105#[doc = "Signed saturating rounding doubling multiply returning high half"]
39106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"]
39107#[inline]
39108#[target_feature(enable = "neon")]
39109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39110#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39111#[cfg_attr(
39112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39113 assert_instr(sqrdmulh)
39114)]
39115#[cfg_attr(
39116 not(target_arch = "arm"),
39117 stable(feature = "neon_intrinsics", since = "1.59.0")
39118)]
39119#[cfg_attr(
39120 target_arch = "arm",
39121 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39122)]
39123pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
39124 unsafe extern "unadjusted" {
39125 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v2i32")]
39126 #[cfg_attr(
39127 any(target_arch = "aarch64", target_arch = "arm64ec"),
39128 link_name = "llvm.aarch64.neon.sqrdmulh.v2i32"
39129 )]
39130 fn _vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
39131 }
39132 unsafe { _vqrdmulh_s32(a, b) }
39133}
39134#[doc = "Signed saturating rounding doubling multiply returning high half"]
39135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"]
39136#[inline]
39137#[target_feature(enable = "neon")]
39138#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39139#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
39140#[cfg_attr(
39141 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39142 assert_instr(sqrdmulh)
39143)]
39144#[cfg_attr(
39145 not(target_arch = "arm"),
39146 stable(feature = "neon_intrinsics", since = "1.59.0")
39147)]
39148#[cfg_attr(
39149 target_arch = "arm",
39150 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39151)]
39152pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
39153 unsafe extern "unadjusted" {
39154 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i32")]
39155 #[cfg_attr(
39156 any(target_arch = "aarch64", target_arch = "arm64ec"),
39157 link_name = "llvm.aarch64.neon.sqrdmulh.v4i32"
39158 )]
39159 fn _vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
39160 }
39161 unsafe { _vqrdmulhq_s32(a, b) }
39162}
39163#[doc = "Signed saturating rounding shift left"]
39164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"]
39165#[inline]
39166#[target_feature(enable = "neon")]
39167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39168#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39169#[cfg_attr(
39170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39171 assert_instr(sqrshl)
39172)]
39173#[cfg_attr(
39174 not(target_arch = "arm"),
39175 stable(feature = "neon_intrinsics", since = "1.59.0")
39176)]
39177#[cfg_attr(
39178 target_arch = "arm",
39179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39180)]
39181pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
39182 unsafe extern "unadjusted" {
39183 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i8")]
39184 #[cfg_attr(
39185 any(target_arch = "aarch64", target_arch = "arm64ec"),
39186 link_name = "llvm.aarch64.neon.sqrshl.v8i8"
39187 )]
39188 fn _vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
39189 }
39190 unsafe { _vqrshl_s8(a, b) }
39191}
39192#[doc = "Signed saturating rounding shift left"]
39193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"]
39194#[inline]
39195#[target_feature(enable = "neon")]
39196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39197#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39198#[cfg_attr(
39199 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39200 assert_instr(sqrshl)
39201)]
39202#[cfg_attr(
39203 not(target_arch = "arm"),
39204 stable(feature = "neon_intrinsics", since = "1.59.0")
39205)]
39206#[cfg_attr(
39207 target_arch = "arm",
39208 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39209)]
39210pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
39211 unsafe extern "unadjusted" {
39212 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v16i8")]
39213 #[cfg_attr(
39214 any(target_arch = "aarch64", target_arch = "arm64ec"),
39215 link_name = "llvm.aarch64.neon.sqrshl.v16i8"
39216 )]
39217 fn _vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
39218 }
39219 unsafe { _vqrshlq_s8(a, b) }
39220}
39221#[doc = "Signed saturating rounding shift left"]
39222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"]
39223#[inline]
39224#[target_feature(enable = "neon")]
39225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39226#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39227#[cfg_attr(
39228 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39229 assert_instr(sqrshl)
39230)]
39231#[cfg_attr(
39232 not(target_arch = "arm"),
39233 stable(feature = "neon_intrinsics", since = "1.59.0")
39234)]
39235#[cfg_attr(
39236 target_arch = "arm",
39237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39238)]
39239pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
39240 unsafe extern "unadjusted" {
39241 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i16")]
39242 #[cfg_attr(
39243 any(target_arch = "aarch64", target_arch = "arm64ec"),
39244 link_name = "llvm.aarch64.neon.sqrshl.v4i16"
39245 )]
39246 fn _vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
39247 }
39248 unsafe { _vqrshl_s16(a, b) }
39249}
39250#[doc = "Signed saturating rounding shift left"]
39251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"]
39252#[inline]
39253#[target_feature(enable = "neon")]
39254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39255#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39256#[cfg_attr(
39257 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39258 assert_instr(sqrshl)
39259)]
39260#[cfg_attr(
39261 not(target_arch = "arm"),
39262 stable(feature = "neon_intrinsics", since = "1.59.0")
39263)]
39264#[cfg_attr(
39265 target_arch = "arm",
39266 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39267)]
39268pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
39269 unsafe extern "unadjusted" {
39270 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i16")]
39271 #[cfg_attr(
39272 any(target_arch = "aarch64", target_arch = "arm64ec"),
39273 link_name = "llvm.aarch64.neon.sqrshl.v8i16"
39274 )]
39275 fn _vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
39276 }
39277 unsafe { _vqrshlq_s16(a, b) }
39278}
39279#[doc = "Signed saturating rounding shift left"]
39280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"]
39281#[inline]
39282#[target_feature(enable = "neon")]
39283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39285#[cfg_attr(
39286 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39287 assert_instr(sqrshl)
39288)]
39289#[cfg_attr(
39290 not(target_arch = "arm"),
39291 stable(feature = "neon_intrinsics", since = "1.59.0")
39292)]
39293#[cfg_attr(
39294 target_arch = "arm",
39295 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39296)]
39297pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
39298 unsafe extern "unadjusted" {
39299 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i32")]
39300 #[cfg_attr(
39301 any(target_arch = "aarch64", target_arch = "arm64ec"),
39302 link_name = "llvm.aarch64.neon.sqrshl.v2i32"
39303 )]
39304 fn _vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
39305 }
39306 unsafe { _vqrshl_s32(a, b) }
39307}
39308#[doc = "Signed saturating rounding shift left"]
39309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"]
39310#[inline]
39311#[target_feature(enable = "neon")]
39312#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39313#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39314#[cfg_attr(
39315 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39316 assert_instr(sqrshl)
39317)]
39318#[cfg_attr(
39319 not(target_arch = "arm"),
39320 stable(feature = "neon_intrinsics", since = "1.59.0")
39321)]
39322#[cfg_attr(
39323 target_arch = "arm",
39324 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39325)]
39326pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
39327 unsafe extern "unadjusted" {
39328 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i32")]
39329 #[cfg_attr(
39330 any(target_arch = "aarch64", target_arch = "arm64ec"),
39331 link_name = "llvm.aarch64.neon.sqrshl.v4i32"
39332 )]
39333 fn _vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
39334 }
39335 unsafe { _vqrshlq_s32(a, b) }
39336}
39337#[doc = "Signed saturating rounding shift left"]
39338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"]
39339#[inline]
39340#[target_feature(enable = "neon")]
39341#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39342#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39343#[cfg_attr(
39344 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39345 assert_instr(sqrshl)
39346)]
39347#[cfg_attr(
39348 not(target_arch = "arm"),
39349 stable(feature = "neon_intrinsics", since = "1.59.0")
39350)]
39351#[cfg_attr(
39352 target_arch = "arm",
39353 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39354)]
39355pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
39356 unsafe extern "unadjusted" {
39357 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v1i64")]
39358 #[cfg_attr(
39359 any(target_arch = "aarch64", target_arch = "arm64ec"),
39360 link_name = "llvm.aarch64.neon.sqrshl.v1i64"
39361 )]
39362 fn _vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
39363 }
39364 unsafe { _vqrshl_s64(a, b) }
39365}
39366#[doc = "Signed saturating rounding shift left"]
39367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"]
39368#[inline]
39369#[target_feature(enable = "neon")]
39370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39371#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39372#[cfg_attr(
39373 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39374 assert_instr(sqrshl)
39375)]
39376#[cfg_attr(
39377 not(target_arch = "arm"),
39378 stable(feature = "neon_intrinsics", since = "1.59.0")
39379)]
39380#[cfg_attr(
39381 target_arch = "arm",
39382 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39383)]
39384pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
39385 unsafe extern "unadjusted" {
39386 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i64")]
39387 #[cfg_attr(
39388 any(target_arch = "aarch64", target_arch = "arm64ec"),
39389 link_name = "llvm.aarch64.neon.sqrshl.v2i64"
39390 )]
39391 fn _vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
39392 }
39393 unsafe { _vqrshlq_s64(a, b) }
39394}
39395#[doc = "Unsigned signed saturating rounding shift left"]
39396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"]
39397#[inline]
39398#[target_feature(enable = "neon")]
39399#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39400#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39401#[cfg_attr(
39402 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39403 assert_instr(uqrshl)
39404)]
39405#[cfg_attr(
39406 not(target_arch = "arm"),
39407 stable(feature = "neon_intrinsics", since = "1.59.0")
39408)]
39409#[cfg_attr(
39410 target_arch = "arm",
39411 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39412)]
39413pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
39414 unsafe extern "unadjusted" {
39415 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i8")]
39416 #[cfg_attr(
39417 any(target_arch = "aarch64", target_arch = "arm64ec"),
39418 link_name = "llvm.aarch64.neon.uqrshl.v8i8"
39419 )]
39420 fn _vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
39421 }
39422 unsafe { _vqrshl_u8(a, b) }
39423}
39424#[doc = "Unsigned signed saturating rounding shift left"]
39425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"]
39426#[inline]
39427#[target_feature(enable = "neon")]
39428#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39429#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39430#[cfg_attr(
39431 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39432 assert_instr(uqrshl)
39433)]
39434#[cfg_attr(
39435 not(target_arch = "arm"),
39436 stable(feature = "neon_intrinsics", since = "1.59.0")
39437)]
39438#[cfg_attr(
39439 target_arch = "arm",
39440 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39441)]
39442pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
39443 unsafe extern "unadjusted" {
39444 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v16i8")]
39445 #[cfg_attr(
39446 any(target_arch = "aarch64", target_arch = "arm64ec"),
39447 link_name = "llvm.aarch64.neon.uqrshl.v16i8"
39448 )]
39449 fn _vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
39450 }
39451 unsafe { _vqrshlq_u8(a, b) }
39452}
39453#[doc = "Unsigned signed saturating rounding shift left"]
39454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"]
39455#[inline]
39456#[target_feature(enable = "neon")]
39457#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39458#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39459#[cfg_attr(
39460 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39461 assert_instr(uqrshl)
39462)]
39463#[cfg_attr(
39464 not(target_arch = "arm"),
39465 stable(feature = "neon_intrinsics", since = "1.59.0")
39466)]
39467#[cfg_attr(
39468 target_arch = "arm",
39469 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39470)]
39471pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
39472 unsafe extern "unadjusted" {
39473 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i16")]
39474 #[cfg_attr(
39475 any(target_arch = "aarch64", target_arch = "arm64ec"),
39476 link_name = "llvm.aarch64.neon.uqrshl.v4i16"
39477 )]
39478 fn _vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
39479 }
39480 unsafe { _vqrshl_u16(a, b) }
39481}
39482#[doc = "Unsigned signed saturating rounding shift left"]
39483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"]
39484#[inline]
39485#[target_feature(enable = "neon")]
39486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39488#[cfg_attr(
39489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39490 assert_instr(uqrshl)
39491)]
39492#[cfg_attr(
39493 not(target_arch = "arm"),
39494 stable(feature = "neon_intrinsics", since = "1.59.0")
39495)]
39496#[cfg_attr(
39497 target_arch = "arm",
39498 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39499)]
39500pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
39501 unsafe extern "unadjusted" {
39502 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i16")]
39503 #[cfg_attr(
39504 any(target_arch = "aarch64", target_arch = "arm64ec"),
39505 link_name = "llvm.aarch64.neon.uqrshl.v8i16"
39506 )]
39507 fn _vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
39508 }
39509 unsafe { _vqrshlq_u16(a, b) }
39510}
39511#[doc = "Unsigned signed saturating rounding shift left"]
39512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"]
39513#[inline]
39514#[target_feature(enable = "neon")]
39515#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39516#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39517#[cfg_attr(
39518 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39519 assert_instr(uqrshl)
39520)]
39521#[cfg_attr(
39522 not(target_arch = "arm"),
39523 stable(feature = "neon_intrinsics", since = "1.59.0")
39524)]
39525#[cfg_attr(
39526 target_arch = "arm",
39527 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39528)]
39529pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
39530 unsafe extern "unadjusted" {
39531 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i32")]
39532 #[cfg_attr(
39533 any(target_arch = "aarch64", target_arch = "arm64ec"),
39534 link_name = "llvm.aarch64.neon.uqrshl.v2i32"
39535 )]
39536 fn _vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
39537 }
39538 unsafe { _vqrshl_u32(a, b) }
39539}
39540#[doc = "Unsigned signed saturating rounding shift left"]
39541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"]
39542#[inline]
39543#[target_feature(enable = "neon")]
39544#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39545#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39546#[cfg_attr(
39547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39548 assert_instr(uqrshl)
39549)]
39550#[cfg_attr(
39551 not(target_arch = "arm"),
39552 stable(feature = "neon_intrinsics", since = "1.59.0")
39553)]
39554#[cfg_attr(
39555 target_arch = "arm",
39556 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39557)]
39558pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
39559 unsafe extern "unadjusted" {
39560 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i32")]
39561 #[cfg_attr(
39562 any(target_arch = "aarch64", target_arch = "arm64ec"),
39563 link_name = "llvm.aarch64.neon.uqrshl.v4i32"
39564 )]
39565 fn _vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
39566 }
39567 unsafe { _vqrshlq_u32(a, b) }
39568}
39569#[doc = "Unsigned signed saturating rounding shift left"]
39570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"]
39571#[inline]
39572#[target_feature(enable = "neon")]
39573#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39574#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39575#[cfg_attr(
39576 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39577 assert_instr(uqrshl)
39578)]
39579#[cfg_attr(
39580 not(target_arch = "arm"),
39581 stable(feature = "neon_intrinsics", since = "1.59.0")
39582)]
39583#[cfg_attr(
39584 target_arch = "arm",
39585 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39586)]
39587pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
39588 unsafe extern "unadjusted" {
39589 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v1i64")]
39590 #[cfg_attr(
39591 any(target_arch = "aarch64", target_arch = "arm64ec"),
39592 link_name = "llvm.aarch64.neon.uqrshl.v1i64"
39593 )]
39594 fn _vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
39595 }
39596 unsafe { _vqrshl_u64(a, b) }
39597}
39598#[doc = "Unsigned signed saturating rounding shift left"]
39599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"]
39600#[inline]
39601#[target_feature(enable = "neon")]
39602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39603#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39604#[cfg_attr(
39605 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39606 assert_instr(uqrshl)
39607)]
39608#[cfg_attr(
39609 not(target_arch = "arm"),
39610 stable(feature = "neon_intrinsics", since = "1.59.0")
39611)]
39612#[cfg_attr(
39613 target_arch = "arm",
39614 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39615)]
39616pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
39617 unsafe extern "unadjusted" {
39618 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i64")]
39619 #[cfg_attr(
39620 any(target_arch = "aarch64", target_arch = "arm64ec"),
39621 link_name = "llvm.aarch64.neon.uqrshl.v2i64"
39622 )]
39623 fn _vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
39624 }
39625 unsafe { _vqrshlq_u64(a, b) }
39626}
39627#[doc = "Signed saturating rounded shift right narrow"]
39628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
39629#[inline]
39630#[cfg(target_arch = "arm")]
39631#[target_feature(enable = "neon,v7")]
39632#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39633#[rustc_legacy_const_generics(1)]
39634#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39635pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
39636 static_assert!(N >= 1 && N <= 8);
39637 unsafe extern "unadjusted" {
39638 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v8i8")]
39639 fn _vqrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
39640 }
39641 unsafe {
39642 _vqrshrn_n_s16(
39643 a,
39644 const {
39645 int16x8_t([
39646 -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
39647 -N as i16,
39648 ])
39649 },
39650 )
39651 }
39652}
39653#[doc = "Signed saturating rounded shift right narrow"]
39654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
39655#[inline]
39656#[cfg(target_arch = "arm")]
39657#[target_feature(enable = "neon,v7")]
39658#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39659#[rustc_legacy_const_generics(1)]
39660#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39661pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
39662 static_assert!(N >= 1 && N <= 16);
39663 unsafe extern "unadjusted" {
39664 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v4i16")]
39665 fn _vqrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
39666 }
39667 unsafe {
39668 _vqrshrn_n_s32(
39669 a,
39670 const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
39671 )
39672 }
39673}
39674#[doc = "Signed saturating rounded shift right narrow"]
39675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
39676#[inline]
39677#[cfg(target_arch = "arm")]
39678#[target_feature(enable = "neon,v7")]
39679#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39680#[rustc_legacy_const_generics(1)]
39681#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39682pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
39683 static_assert!(N >= 1 && N <= 32);
39684 unsafe extern "unadjusted" {
39685 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")]
39686 fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
39687 }
39688 unsafe { _vqrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
39689}
39690#[doc = "Signed saturating rounded shift right narrow"]
39691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
39692#[inline]
39693#[target_feature(enable = "neon")]
39694#[cfg(not(target_arch = "arm"))]
39695#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39696#[rustc_legacy_const_generics(1)]
39697#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39698pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
39699 static_assert!(N >= 1 && N <= 8);
39700 unsafe extern "unadjusted" {
39701 #[cfg_attr(
39702 any(target_arch = "aarch64", target_arch = "arm64ec"),
39703 link_name = "llvm.aarch64.neon.sqrshrn.v8i8"
39704 )]
39705 fn _vqrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
39706 }
39707 unsafe { _vqrshrn_n_s16(a, N) }
39708}
39709#[doc = "Signed saturating rounded shift right narrow"]
39710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
39711#[inline]
39712#[target_feature(enable = "neon")]
39713#[cfg(not(target_arch = "arm"))]
39714#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39715#[rustc_legacy_const_generics(1)]
39716#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39717pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
39718 static_assert!(N >= 1 && N <= 16);
39719 unsafe extern "unadjusted" {
39720 #[cfg_attr(
39721 any(target_arch = "aarch64", target_arch = "arm64ec"),
39722 link_name = "llvm.aarch64.neon.sqrshrn.v4i16"
39723 )]
39724 fn _vqrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
39725 }
39726 unsafe { _vqrshrn_n_s32(a, N) }
39727}
39728#[doc = "Signed saturating rounded shift right narrow"]
39729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
39730#[inline]
39731#[target_feature(enable = "neon")]
39732#[cfg(not(target_arch = "arm"))]
39733#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39734#[rustc_legacy_const_generics(1)]
39735#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39736pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
39737 static_assert!(N >= 1 && N <= 32);
39738 unsafe extern "unadjusted" {
39739 #[cfg_attr(
39740 any(target_arch = "aarch64", target_arch = "arm64ec"),
39741 link_name = "llvm.aarch64.neon.sqrshrn.v2i32"
39742 )]
39743 fn _vqrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
39744 }
39745 unsafe { _vqrshrn_n_s64(a, N) }
39746}
39747#[doc = "Unsigned signed saturating rounded shift right narrow"]
39748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
39749#[inline]
39750#[cfg(target_arch = "arm")]
39751#[target_feature(enable = "neon,v7")]
39752#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39753#[rustc_legacy_const_generics(1)]
39754#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39755pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
39756 static_assert!(N >= 1 && N <= 8);
39757 unsafe extern "unadjusted" {
39758 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")]
39759 fn _vqrshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
39760 }
39761 unsafe {
39762 _vqrshrn_n_u16(
39763 a,
39764 const {
39765 uint16x8_t([
39766 -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
39767 -N as u16,
39768 ])
39769 },
39770 )
39771 }
39772}
39773#[doc = "Unsigned signed saturating rounded shift right narrow"]
39774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
39775#[inline]
39776#[cfg(target_arch = "arm")]
39777#[target_feature(enable = "neon,v7")]
39778#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39779#[rustc_legacy_const_generics(1)]
39780#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39781pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
39782 static_assert!(N >= 1 && N <= 16);
39783 unsafe extern "unadjusted" {
39784 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")]
39785 fn _vqrshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
39786 }
39787 unsafe {
39788 _vqrshrn_n_u32(
39789 a,
39790 const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
39791 )
39792 }
39793}
39794#[doc = "Unsigned signed saturating rounded shift right narrow"]
39795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
39796#[inline]
39797#[cfg(target_arch = "arm")]
39798#[target_feature(enable = "neon,v7")]
39799#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39800#[rustc_legacy_const_generics(1)]
39801#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39802pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
39803 static_assert!(N >= 1 && N <= 32);
39804 unsafe extern "unadjusted" {
39805 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")]
39806 fn _vqrshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
39807 }
39808 unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
39809}
39810#[doc = "Unsigned signed saturating rounded shift right narrow"]
39811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
39812#[inline]
39813#[target_feature(enable = "neon")]
39814#[cfg(not(target_arch = "arm"))]
39815#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39816#[rustc_legacy_const_generics(1)]
39817#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39818pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
39819 static_assert!(N >= 1 && N <= 8);
39820 unsafe extern "unadjusted" {
39821 #[cfg_attr(
39822 any(target_arch = "aarch64", target_arch = "arm64ec"),
39823 link_name = "llvm.aarch64.neon.uqrshrn.v8i8"
39824 )]
39825 fn _vqrshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t;
39826 }
39827 unsafe { _vqrshrn_n_u16(a, N) }
39828}
39829#[doc = "Unsigned signed saturating rounded shift right narrow"]
39830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
39831#[inline]
39832#[target_feature(enable = "neon")]
39833#[cfg(not(target_arch = "arm"))]
39834#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39835#[rustc_legacy_const_generics(1)]
39836#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39837pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
39838 static_assert!(N >= 1 && N <= 16);
39839 unsafe extern "unadjusted" {
39840 #[cfg_attr(
39841 any(target_arch = "aarch64", target_arch = "arm64ec"),
39842 link_name = "llvm.aarch64.neon.uqrshrn.v4i16"
39843 )]
39844 fn _vqrshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t;
39845 }
39846 unsafe { _vqrshrn_n_u32(a, N) }
39847}
39848#[doc = "Unsigned signed saturating rounded shift right narrow"]
39849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
39850#[inline]
39851#[target_feature(enable = "neon")]
39852#[cfg(not(target_arch = "arm"))]
39853#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39854#[rustc_legacy_const_generics(1)]
39855#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39856pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
39857 static_assert!(N >= 1 && N <= 32);
39858 unsafe extern "unadjusted" {
39859 #[cfg_attr(
39860 any(target_arch = "aarch64", target_arch = "arm64ec"),
39861 link_name = "llvm.aarch64.neon.uqrshrn.v2i32"
39862 )]
39863 fn _vqrshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t;
39864 }
39865 unsafe { _vqrshrn_n_u64(a, N) }
39866}
39867#[doc = "Signed saturating rounded shift right unsigned narrow"]
39868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
39869#[inline]
39870#[cfg(target_arch = "arm")]
39871#[target_feature(enable = "neon,v7")]
39872#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39873#[rustc_legacy_const_generics(1)]
39874#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39875pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
39876 static_assert!(N >= 1 && N <= 8);
39877 unsafe extern "unadjusted" {
39878 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")]
39879 fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
39880 }
39881 unsafe {
39882 _vqrshrun_n_s16(
39883 a,
39884 const {
39885 int16x8_t([
39886 -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
39887 -N as i16,
39888 ])
39889 },
39890 )
39891 }
39892}
39893#[doc = "Signed saturating rounded shift right unsigned narrow"]
39894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
39895#[inline]
39896#[cfg(target_arch = "arm")]
39897#[target_feature(enable = "neon,v7")]
39898#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39899#[rustc_legacy_const_generics(1)]
39900#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39901pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
39902 static_assert!(N >= 1 && N <= 16);
39903 unsafe extern "unadjusted" {
39904 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")]
39905 fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
39906 }
39907 unsafe {
39908 _vqrshrun_n_s32(
39909 a,
39910 const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
39911 )
39912 }
39913}
39914#[doc = "Signed saturating rounded shift right unsigned narrow"]
39915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
39916#[inline]
39917#[cfg(target_arch = "arm")]
39918#[target_feature(enable = "neon,v7")]
39919#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39920#[rustc_legacy_const_generics(1)]
39921#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39922pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
39923 static_assert!(N >= 1 && N <= 32);
39924 unsafe extern "unadjusted" {
39925 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")]
39926 fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
39927 }
39928 unsafe { _vqrshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
39929}
39930#[doc = "Signed saturating rounded shift right unsigned narrow"]
39931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
39932#[inline]
39933#[target_feature(enable = "neon")]
39934#[cfg(not(target_arch = "arm"))]
39935#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39936#[rustc_legacy_const_generics(1)]
39937#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39938pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
39939 static_assert!(N >= 1 && N <= 8);
39940 unsafe extern "unadjusted" {
39941 #[cfg_attr(
39942 any(target_arch = "aarch64", target_arch = "arm64ec"),
39943 link_name = "llvm.aarch64.neon.sqrshrun.v8i8"
39944 )]
39945 fn _vqrshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t;
39946 }
39947 unsafe { _vqrshrun_n_s16(a, N) }
39948}
39949#[doc = "Signed saturating rounded shift right unsigned narrow"]
39950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
39951#[inline]
39952#[target_feature(enable = "neon")]
39953#[cfg(not(target_arch = "arm"))]
39954#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39955#[rustc_legacy_const_generics(1)]
39956#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39957pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
39958 static_assert!(N >= 1 && N <= 16);
39959 unsafe extern "unadjusted" {
39960 #[cfg_attr(
39961 any(target_arch = "aarch64", target_arch = "arm64ec"),
39962 link_name = "llvm.aarch64.neon.sqrshrun.v4i16"
39963 )]
39964 fn _vqrshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t;
39965 }
39966 unsafe { _vqrshrun_n_s32(a, N) }
39967}
39968#[doc = "Signed saturating rounded shift right unsigned narrow"]
39969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
39970#[inline]
39971#[target_feature(enable = "neon")]
39972#[cfg(not(target_arch = "arm"))]
39973#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39974#[rustc_legacy_const_generics(1)]
39975#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39976pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
39977 static_assert!(N >= 1 && N <= 32);
39978 unsafe extern "unadjusted" {
39979 #[cfg_attr(
39980 any(target_arch = "aarch64", target_arch = "arm64ec"),
39981 link_name = "llvm.aarch64.neon.sqrshrun.v2i32"
39982 )]
39983 fn _vqrshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t;
39984 }
39985 unsafe { _vqrshrun_n_s64(a, N) }
39986}
39987#[doc = "Signed saturating shift left"]
39988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"]
39989#[inline]
39990#[target_feature(enable = "neon")]
39991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39993#[cfg_attr(
39994 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39995 assert_instr(sqshl, N = 2)
39996)]
39997#[rustc_legacy_const_generics(1)]
39998#[cfg_attr(
39999 not(target_arch = "arm"),
40000 stable(feature = "neon_intrinsics", since = "1.59.0")
40001)]
40002#[cfg_attr(
40003 target_arch = "arm",
40004 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40005)]
40006pub fn vqshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
40007 static_assert_uimm_bits!(N, 3);
40008 vqshl_s8(a, vdup_n_s8(N as _))
40009}
40010#[doc = "Signed saturating shift left"]
40011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"]
40012#[inline]
40013#[target_feature(enable = "neon")]
40014#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40015#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40016#[cfg_attr(
40017 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40018 assert_instr(sqshl, N = 2)
40019)]
40020#[rustc_legacy_const_generics(1)]
40021#[cfg_attr(
40022 not(target_arch = "arm"),
40023 stable(feature = "neon_intrinsics", since = "1.59.0")
40024)]
40025#[cfg_attr(
40026 target_arch = "arm",
40027 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40028)]
40029pub fn vqshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
40030 static_assert_uimm_bits!(N, 3);
40031 vqshlq_s8(a, vdupq_n_s8(N as _))
40032}
40033#[doc = "Signed saturating shift left"]
40034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"]
40035#[inline]
40036#[target_feature(enable = "neon")]
40037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40039#[cfg_attr(
40040 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40041 assert_instr(sqshl, N = 2)
40042)]
40043#[rustc_legacy_const_generics(1)]
40044#[cfg_attr(
40045 not(target_arch = "arm"),
40046 stable(feature = "neon_intrinsics", since = "1.59.0")
40047)]
40048#[cfg_attr(
40049 target_arch = "arm",
40050 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40051)]
40052pub fn vqshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
40053 static_assert_uimm_bits!(N, 4);
40054 vqshl_s16(a, vdup_n_s16(N as _))
40055}
40056#[doc = "Signed saturating shift left"]
40057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"]
40058#[inline]
40059#[target_feature(enable = "neon")]
40060#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40061#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40062#[cfg_attr(
40063 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40064 assert_instr(sqshl, N = 2)
40065)]
40066#[rustc_legacy_const_generics(1)]
40067#[cfg_attr(
40068 not(target_arch = "arm"),
40069 stable(feature = "neon_intrinsics", since = "1.59.0")
40070)]
40071#[cfg_attr(
40072 target_arch = "arm",
40073 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40074)]
40075pub fn vqshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
40076 static_assert_uimm_bits!(N, 4);
40077 vqshlq_s16(a, vdupq_n_s16(N as _))
40078}
40079#[doc = "Signed saturating shift left"]
40080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"]
40081#[inline]
40082#[target_feature(enable = "neon")]
40083#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40084#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40085#[cfg_attr(
40086 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40087 assert_instr(sqshl, N = 2)
40088)]
40089#[rustc_legacy_const_generics(1)]
40090#[cfg_attr(
40091 not(target_arch = "arm"),
40092 stable(feature = "neon_intrinsics", since = "1.59.0")
40093)]
40094#[cfg_attr(
40095 target_arch = "arm",
40096 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40097)]
40098pub fn vqshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
40099 static_assert_uimm_bits!(N, 5);
40100 vqshl_s32(a, vdup_n_s32(N as _))
40101}
40102#[doc = "Signed saturating shift left"]
40103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"]
40104#[inline]
40105#[target_feature(enable = "neon")]
40106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40108#[cfg_attr(
40109 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40110 assert_instr(sqshl, N = 2)
40111)]
40112#[rustc_legacy_const_generics(1)]
40113#[cfg_attr(
40114 not(target_arch = "arm"),
40115 stable(feature = "neon_intrinsics", since = "1.59.0")
40116)]
40117#[cfg_attr(
40118 target_arch = "arm",
40119 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40120)]
40121pub fn vqshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
40122 static_assert_uimm_bits!(N, 5);
40123 vqshlq_s32(a, vdupq_n_s32(N as _))
40124}
40125#[doc = "Signed saturating shift left"]
40126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"]
40127#[inline]
40128#[target_feature(enable = "neon")]
40129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40130#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40131#[cfg_attr(
40132 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40133 assert_instr(sqshl, N = 2)
40134)]
40135#[rustc_legacy_const_generics(1)]
40136#[cfg_attr(
40137 not(target_arch = "arm"),
40138 stable(feature = "neon_intrinsics", since = "1.59.0")
40139)]
40140#[cfg_attr(
40141 target_arch = "arm",
40142 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40143)]
40144pub fn vqshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
40145 static_assert_uimm_bits!(N, 6);
40146 vqshl_s64(a, vdup_n_s64(N as _))
40147}
40148#[doc = "Signed saturating shift left"]
40149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"]
40150#[inline]
40151#[target_feature(enable = "neon")]
40152#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40153#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40154#[cfg_attr(
40155 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40156 assert_instr(sqshl, N = 2)
40157)]
40158#[rustc_legacy_const_generics(1)]
40159#[cfg_attr(
40160 not(target_arch = "arm"),
40161 stable(feature = "neon_intrinsics", since = "1.59.0")
40162)]
40163#[cfg_attr(
40164 target_arch = "arm",
40165 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40166)]
40167pub fn vqshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
40168 static_assert_uimm_bits!(N, 6);
40169 vqshlq_s64(a, vdupq_n_s64(N as _))
40170}
40171#[doc = "Unsigned saturating shift left"]
40172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"]
40173#[inline]
40174#[target_feature(enable = "neon")]
40175#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40176#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40177#[cfg_attr(
40178 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40179 assert_instr(uqshl, N = 2)
40180)]
40181#[rustc_legacy_const_generics(1)]
40182#[cfg_attr(
40183 not(target_arch = "arm"),
40184 stable(feature = "neon_intrinsics", since = "1.59.0")
40185)]
40186#[cfg_attr(
40187 target_arch = "arm",
40188 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40189)]
40190pub fn vqshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
40191 static_assert_uimm_bits!(N, 3);
40192 vqshl_u8(a, vdup_n_s8(N as _))
40193}
40194#[doc = "Unsigned saturating shift left"]
40195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"]
40196#[inline]
40197#[target_feature(enable = "neon")]
40198#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40199#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40200#[cfg_attr(
40201 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40202 assert_instr(uqshl, N = 2)
40203)]
40204#[rustc_legacy_const_generics(1)]
40205#[cfg_attr(
40206 not(target_arch = "arm"),
40207 stable(feature = "neon_intrinsics", since = "1.59.0")
40208)]
40209#[cfg_attr(
40210 target_arch = "arm",
40211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40212)]
40213pub fn vqshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
40214 static_assert_uimm_bits!(N, 3);
40215 vqshlq_u8(a, vdupq_n_s8(N as _))
40216}
40217#[doc = "Unsigned saturating shift left"]
40218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"]
40219#[inline]
40220#[target_feature(enable = "neon")]
40221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40223#[cfg_attr(
40224 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40225 assert_instr(uqshl, N = 2)
40226)]
40227#[rustc_legacy_const_generics(1)]
40228#[cfg_attr(
40229 not(target_arch = "arm"),
40230 stable(feature = "neon_intrinsics", since = "1.59.0")
40231)]
40232#[cfg_attr(
40233 target_arch = "arm",
40234 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40235)]
40236pub fn vqshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
40237 static_assert_uimm_bits!(N, 4);
40238 vqshl_u16(a, vdup_n_s16(N as _))
40239}
40240#[doc = "Unsigned saturating shift left"]
40241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"]
40242#[inline]
40243#[target_feature(enable = "neon")]
40244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40245#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40246#[cfg_attr(
40247 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40248 assert_instr(uqshl, N = 2)
40249)]
40250#[rustc_legacy_const_generics(1)]
40251#[cfg_attr(
40252 not(target_arch = "arm"),
40253 stable(feature = "neon_intrinsics", since = "1.59.0")
40254)]
40255#[cfg_attr(
40256 target_arch = "arm",
40257 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40258)]
40259pub fn vqshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
40260 static_assert_uimm_bits!(N, 4);
40261 vqshlq_u16(a, vdupq_n_s16(N as _))
40262}
40263#[doc = "Unsigned saturating shift left"]
40264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"]
40265#[inline]
40266#[target_feature(enable = "neon")]
40267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40268#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40269#[cfg_attr(
40270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40271 assert_instr(uqshl, N = 2)
40272)]
40273#[rustc_legacy_const_generics(1)]
40274#[cfg_attr(
40275 not(target_arch = "arm"),
40276 stable(feature = "neon_intrinsics", since = "1.59.0")
40277)]
40278#[cfg_attr(
40279 target_arch = "arm",
40280 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40281)]
40282pub fn vqshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
40283 static_assert_uimm_bits!(N, 5);
40284 vqshl_u32(a, vdup_n_s32(N as _))
40285}
40286#[doc = "Unsigned saturating shift left"]
40287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"]
40288#[inline]
40289#[target_feature(enable = "neon")]
40290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40292#[cfg_attr(
40293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40294 assert_instr(uqshl, N = 2)
40295)]
40296#[rustc_legacy_const_generics(1)]
40297#[cfg_attr(
40298 not(target_arch = "arm"),
40299 stable(feature = "neon_intrinsics", since = "1.59.0")
40300)]
40301#[cfg_attr(
40302 target_arch = "arm",
40303 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40304)]
40305pub fn vqshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
40306 static_assert_uimm_bits!(N, 5);
40307 vqshlq_u32(a, vdupq_n_s32(N as _))
40308}
40309#[doc = "Unsigned saturating shift left"]
40310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"]
40311#[inline]
40312#[target_feature(enable = "neon")]
40313#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40314#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40315#[cfg_attr(
40316 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40317 assert_instr(uqshl, N = 2)
40318)]
40319#[rustc_legacy_const_generics(1)]
40320#[cfg_attr(
40321 not(target_arch = "arm"),
40322 stable(feature = "neon_intrinsics", since = "1.59.0")
40323)]
40324#[cfg_attr(
40325 target_arch = "arm",
40326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40327)]
40328pub fn vqshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
40329 static_assert_uimm_bits!(N, 6);
40330 vqshl_u64(a, vdup_n_s64(N as _))
40331}
40332#[doc = "Unsigned saturating shift left"]
40333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"]
40334#[inline]
40335#[target_feature(enable = "neon")]
40336#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40338#[cfg_attr(
40339 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40340 assert_instr(uqshl, N = 2)
40341)]
40342#[rustc_legacy_const_generics(1)]
40343#[cfg_attr(
40344 not(target_arch = "arm"),
40345 stable(feature = "neon_intrinsics", since = "1.59.0")
40346)]
40347#[cfg_attr(
40348 target_arch = "arm",
40349 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40350)]
40351pub fn vqshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
40352 static_assert_uimm_bits!(N, 6);
40353 vqshlq_u64(a, vdupq_n_s64(N as _))
40354}
40355#[doc = "Signed saturating shift left"]
40356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"]
40357#[inline]
40358#[target_feature(enable = "neon")]
40359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40360#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40361#[cfg_attr(
40362 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40363 assert_instr(sqshl)
40364)]
40365#[cfg_attr(
40366 not(target_arch = "arm"),
40367 stable(feature = "neon_intrinsics", since = "1.59.0")
40368)]
40369#[cfg_attr(
40370 target_arch = "arm",
40371 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40372)]
40373pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
40374 unsafe extern "unadjusted" {
40375 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i8")]
40376 #[cfg_attr(
40377 any(target_arch = "aarch64", target_arch = "arm64ec"),
40378 link_name = "llvm.aarch64.neon.sqshl.v8i8"
40379 )]
40380 fn _vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
40381 }
40382 unsafe { _vqshl_s8(a, b) }
40383}
40384#[doc = "Signed saturating shift left"]
40385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"]
40386#[inline]
40387#[target_feature(enable = "neon")]
40388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40390#[cfg_attr(
40391 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40392 assert_instr(sqshl)
40393)]
40394#[cfg_attr(
40395 not(target_arch = "arm"),
40396 stable(feature = "neon_intrinsics", since = "1.59.0")
40397)]
40398#[cfg_attr(
40399 target_arch = "arm",
40400 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40401)]
40402pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
40403 unsafe extern "unadjusted" {
40404 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v16i8")]
40405 #[cfg_attr(
40406 any(target_arch = "aarch64", target_arch = "arm64ec"),
40407 link_name = "llvm.aarch64.neon.sqshl.v16i8"
40408 )]
40409 fn _vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
40410 }
40411 unsafe { _vqshlq_s8(a, b) }
40412}
40413#[doc = "Signed saturating shift left"]
40414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"]
40415#[inline]
40416#[target_feature(enable = "neon")]
40417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40419#[cfg_attr(
40420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40421 assert_instr(sqshl)
40422)]
40423#[cfg_attr(
40424 not(target_arch = "arm"),
40425 stable(feature = "neon_intrinsics", since = "1.59.0")
40426)]
40427#[cfg_attr(
40428 target_arch = "arm",
40429 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40430)]
40431pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
40432 unsafe extern "unadjusted" {
40433 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i16")]
40434 #[cfg_attr(
40435 any(target_arch = "aarch64", target_arch = "arm64ec"),
40436 link_name = "llvm.aarch64.neon.sqshl.v4i16"
40437 )]
40438 fn _vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
40439 }
40440 unsafe { _vqshl_s16(a, b) }
40441}
40442#[doc = "Signed saturating shift left"]
40443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"]
40444#[inline]
40445#[target_feature(enable = "neon")]
40446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40447#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40448#[cfg_attr(
40449 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40450 assert_instr(sqshl)
40451)]
40452#[cfg_attr(
40453 not(target_arch = "arm"),
40454 stable(feature = "neon_intrinsics", since = "1.59.0")
40455)]
40456#[cfg_attr(
40457 target_arch = "arm",
40458 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40459)]
40460pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
40461 unsafe extern "unadjusted" {
40462 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i16")]
40463 #[cfg_attr(
40464 any(target_arch = "aarch64", target_arch = "arm64ec"),
40465 link_name = "llvm.aarch64.neon.sqshl.v8i16"
40466 )]
40467 fn _vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
40468 }
40469 unsafe { _vqshlq_s16(a, b) }
40470}
40471#[doc = "Signed saturating shift left"]
40472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"]
40473#[inline]
40474#[target_feature(enable = "neon")]
40475#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40476#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40477#[cfg_attr(
40478 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40479 assert_instr(sqshl)
40480)]
40481#[cfg_attr(
40482 not(target_arch = "arm"),
40483 stable(feature = "neon_intrinsics", since = "1.59.0")
40484)]
40485#[cfg_attr(
40486 target_arch = "arm",
40487 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40488)]
40489pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
40490 unsafe extern "unadjusted" {
40491 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i32")]
40492 #[cfg_attr(
40493 any(target_arch = "aarch64", target_arch = "arm64ec"),
40494 link_name = "llvm.aarch64.neon.sqshl.v2i32"
40495 )]
40496 fn _vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
40497 }
40498 unsafe { _vqshl_s32(a, b) }
40499}
40500#[doc = "Signed saturating shift left"]
40501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"]
40502#[inline]
40503#[target_feature(enable = "neon")]
40504#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40505#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40506#[cfg_attr(
40507 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40508 assert_instr(sqshl)
40509)]
40510#[cfg_attr(
40511 not(target_arch = "arm"),
40512 stable(feature = "neon_intrinsics", since = "1.59.0")
40513)]
40514#[cfg_attr(
40515 target_arch = "arm",
40516 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40517)]
40518pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
40519 unsafe extern "unadjusted" {
40520 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i32")]
40521 #[cfg_attr(
40522 any(target_arch = "aarch64", target_arch = "arm64ec"),
40523 link_name = "llvm.aarch64.neon.sqshl.v4i32"
40524 )]
40525 fn _vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
40526 }
40527 unsafe { _vqshlq_s32(a, b) }
40528}
40529#[doc = "Signed saturating shift left"]
40530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"]
40531#[inline]
40532#[target_feature(enable = "neon")]
40533#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40534#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40535#[cfg_attr(
40536 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40537 assert_instr(sqshl)
40538)]
40539#[cfg_attr(
40540 not(target_arch = "arm"),
40541 stable(feature = "neon_intrinsics", since = "1.59.0")
40542)]
40543#[cfg_attr(
40544 target_arch = "arm",
40545 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40546)]
40547pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
40548 unsafe extern "unadjusted" {
40549 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v1i64")]
40550 #[cfg_attr(
40551 any(target_arch = "aarch64", target_arch = "arm64ec"),
40552 link_name = "llvm.aarch64.neon.sqshl.v1i64"
40553 )]
40554 fn _vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
40555 }
40556 unsafe { _vqshl_s64(a, b) }
40557}
40558#[doc = "Signed saturating shift left"]
40559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"]
40560#[inline]
40561#[target_feature(enable = "neon")]
40562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40564#[cfg_attr(
40565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40566 assert_instr(sqshl)
40567)]
40568#[cfg_attr(
40569 not(target_arch = "arm"),
40570 stable(feature = "neon_intrinsics", since = "1.59.0")
40571)]
40572#[cfg_attr(
40573 target_arch = "arm",
40574 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40575)]
40576pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
40577 unsafe extern "unadjusted" {
40578 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i64")]
40579 #[cfg_attr(
40580 any(target_arch = "aarch64", target_arch = "arm64ec"),
40581 link_name = "llvm.aarch64.neon.sqshl.v2i64"
40582 )]
40583 fn _vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
40584 }
40585 unsafe { _vqshlq_s64(a, b) }
40586}
40587#[doc = "Unsigned saturating shift left"]
40588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"]
40589#[inline]
40590#[target_feature(enable = "neon")]
40591#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40592#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40593#[cfg_attr(
40594 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40595 assert_instr(uqshl)
40596)]
40597#[cfg_attr(
40598 not(target_arch = "arm"),
40599 stable(feature = "neon_intrinsics", since = "1.59.0")
40600)]
40601#[cfg_attr(
40602 target_arch = "arm",
40603 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40604)]
40605pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
40606 unsafe extern "unadjusted" {
40607 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i8")]
40608 #[cfg_attr(
40609 any(target_arch = "aarch64", target_arch = "arm64ec"),
40610 link_name = "llvm.aarch64.neon.uqshl.v8i8"
40611 )]
40612 fn _vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
40613 }
40614 unsafe { _vqshl_u8(a, b) }
40615}
40616#[doc = "Unsigned saturating shift left"]
40617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"]
40618#[inline]
40619#[target_feature(enable = "neon")]
40620#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40622#[cfg_attr(
40623 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40624 assert_instr(uqshl)
40625)]
40626#[cfg_attr(
40627 not(target_arch = "arm"),
40628 stable(feature = "neon_intrinsics", since = "1.59.0")
40629)]
40630#[cfg_attr(
40631 target_arch = "arm",
40632 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40633)]
40634pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
40635 unsafe extern "unadjusted" {
40636 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v16i8")]
40637 #[cfg_attr(
40638 any(target_arch = "aarch64", target_arch = "arm64ec"),
40639 link_name = "llvm.aarch64.neon.uqshl.v16i8"
40640 )]
40641 fn _vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
40642 }
40643 unsafe { _vqshlq_u8(a, b) }
40644}
40645#[doc = "Unsigned saturating shift left"]
40646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"]
40647#[inline]
40648#[target_feature(enable = "neon")]
40649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40650#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40651#[cfg_attr(
40652 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40653 assert_instr(uqshl)
40654)]
40655#[cfg_attr(
40656 not(target_arch = "arm"),
40657 stable(feature = "neon_intrinsics", since = "1.59.0")
40658)]
40659#[cfg_attr(
40660 target_arch = "arm",
40661 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40662)]
40663pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
40664 unsafe extern "unadjusted" {
40665 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i16")]
40666 #[cfg_attr(
40667 any(target_arch = "aarch64", target_arch = "arm64ec"),
40668 link_name = "llvm.aarch64.neon.uqshl.v4i16"
40669 )]
40670 fn _vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
40671 }
40672 unsafe { _vqshl_u16(a, b) }
40673}
40674#[doc = "Unsigned saturating shift left"]
40675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"]
40676#[inline]
40677#[target_feature(enable = "neon")]
40678#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40679#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40680#[cfg_attr(
40681 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40682 assert_instr(uqshl)
40683)]
40684#[cfg_attr(
40685 not(target_arch = "arm"),
40686 stable(feature = "neon_intrinsics", since = "1.59.0")
40687)]
40688#[cfg_attr(
40689 target_arch = "arm",
40690 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40691)]
40692pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
40693 unsafe extern "unadjusted" {
40694 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i16")]
40695 #[cfg_attr(
40696 any(target_arch = "aarch64", target_arch = "arm64ec"),
40697 link_name = "llvm.aarch64.neon.uqshl.v8i16"
40698 )]
40699 fn _vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
40700 }
40701 unsafe { _vqshlq_u16(a, b) }
40702}
40703#[doc = "Unsigned saturating shift left"]
40704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"]
40705#[inline]
40706#[target_feature(enable = "neon")]
40707#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40708#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40709#[cfg_attr(
40710 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40711 assert_instr(uqshl)
40712)]
40713#[cfg_attr(
40714 not(target_arch = "arm"),
40715 stable(feature = "neon_intrinsics", since = "1.59.0")
40716)]
40717#[cfg_attr(
40718 target_arch = "arm",
40719 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40720)]
40721pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
40722 unsafe extern "unadjusted" {
40723 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i32")]
40724 #[cfg_attr(
40725 any(target_arch = "aarch64", target_arch = "arm64ec"),
40726 link_name = "llvm.aarch64.neon.uqshl.v2i32"
40727 )]
40728 fn _vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
40729 }
40730 unsafe { _vqshl_u32(a, b) }
40731}
40732#[doc = "Unsigned saturating shift left"]
40733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"]
40734#[inline]
40735#[target_feature(enable = "neon")]
40736#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40737#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40738#[cfg_attr(
40739 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40740 assert_instr(uqshl)
40741)]
40742#[cfg_attr(
40743 not(target_arch = "arm"),
40744 stable(feature = "neon_intrinsics", since = "1.59.0")
40745)]
40746#[cfg_attr(
40747 target_arch = "arm",
40748 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40749)]
40750pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
40751 unsafe extern "unadjusted" {
40752 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i32")]
40753 #[cfg_attr(
40754 any(target_arch = "aarch64", target_arch = "arm64ec"),
40755 link_name = "llvm.aarch64.neon.uqshl.v4i32"
40756 )]
40757 fn _vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
40758 }
40759 unsafe { _vqshlq_u32(a, b) }
40760}
40761#[doc = "Unsigned saturating shift left"]
40762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"]
40763#[inline]
40764#[target_feature(enable = "neon")]
40765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40766#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40767#[cfg_attr(
40768 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40769 assert_instr(uqshl)
40770)]
40771#[cfg_attr(
40772 not(target_arch = "arm"),
40773 stable(feature = "neon_intrinsics", since = "1.59.0")
40774)]
40775#[cfg_attr(
40776 target_arch = "arm",
40777 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40778)]
40779pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
40780 unsafe extern "unadjusted" {
40781 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v1i64")]
40782 #[cfg_attr(
40783 any(target_arch = "aarch64", target_arch = "arm64ec"),
40784 link_name = "llvm.aarch64.neon.uqshl.v1i64"
40785 )]
40786 fn _vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
40787 }
40788 unsafe { _vqshl_u64(a, b) }
40789}
40790#[doc = "Unsigned saturating shift left"]
40791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"]
40792#[inline]
40793#[target_feature(enable = "neon")]
40794#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40795#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40796#[cfg_attr(
40797 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40798 assert_instr(uqshl)
40799)]
40800#[cfg_attr(
40801 not(target_arch = "arm"),
40802 stable(feature = "neon_intrinsics", since = "1.59.0")
40803)]
40804#[cfg_attr(
40805 target_arch = "arm",
40806 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40807)]
40808pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
40809 unsafe extern "unadjusted" {
40810 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i64")]
40811 #[cfg_attr(
40812 any(target_arch = "aarch64", target_arch = "arm64ec"),
40813 link_name = "llvm.aarch64.neon.uqshl.v2i64"
40814 )]
40815 fn _vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
40816 }
40817 unsafe { _vqshlq_u64(a, b) }
40818}
40819#[doc = "Signed saturating shift left unsigned"]
40820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
40821#[inline]
40822#[cfg(target_arch = "arm")]
40823#[target_feature(enable = "neon,v7")]
40824#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40825#[rustc_legacy_const_generics(1)]
40826#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40827pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
40828 static_assert_uimm_bits!(N, 3);
40829 unsafe extern "unadjusted" {
40830 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")]
40831 fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
40832 }
40833 unsafe {
40834 _vqshlu_n_s8(
40835 a,
40836 const {
40837 int8x8_t([
40838 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40839 ])
40840 },
40841 )
40842 }
40843}
40844#[doc = "Signed saturating shift left unsigned"]
40845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
40846#[inline]
40847#[cfg(target_arch = "arm")]
40848#[target_feature(enable = "neon,v7")]
40849#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40850#[rustc_legacy_const_generics(1)]
40851#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40852pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
40853 static_assert_uimm_bits!(N, 3);
40854 unsafe extern "unadjusted" {
40855 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")]
40856 fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
40857 }
40858 unsafe {
40859 _vqshluq_n_s8(
40860 a,
40861 const {
40862 int8x16_t([
40863 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40864 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40865 ])
40866 },
40867 )
40868 }
40869}
40870#[doc = "Signed saturating shift left unsigned"]
40871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
40872#[inline]
40873#[cfg(target_arch = "arm")]
40874#[target_feature(enable = "neon,v7")]
40875#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40876#[rustc_legacy_const_generics(1)]
40877#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40878pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
40879 static_assert_uimm_bits!(N, 4);
40880 unsafe extern "unadjusted" {
40881 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")]
40882 fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
40883 }
40884 unsafe {
40885 _vqshlu_n_s16(
40886 a,
40887 const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
40888 )
40889 }
40890}
40891#[doc = "Signed saturating shift left unsigned"]
40892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
40893#[inline]
40894#[cfg(target_arch = "arm")]
40895#[target_feature(enable = "neon,v7")]
40896#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40897#[rustc_legacy_const_generics(1)]
40898#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40899pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
40900 static_assert_uimm_bits!(N, 4);
40901 unsafe extern "unadjusted" {
40902 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")]
40903 fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
40904 }
40905 unsafe {
40906 _vqshluq_n_s16(
40907 a,
40908 const {
40909 int16x8_t([
40910 N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
40911 ])
40912 },
40913 )
40914 }
40915}
40916#[doc = "Signed saturating shift left unsigned"]
40917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
40918#[inline]
40919#[cfg(target_arch = "arm")]
40920#[target_feature(enable = "neon,v7")]
40921#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40922#[rustc_legacy_const_generics(1)]
40923#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40924pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
40925 static_assert_uimm_bits!(N, 5);
40926 unsafe extern "unadjusted" {
40927 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")]
40928 fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
40929 }
40930 unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
40931}
40932#[doc = "Signed saturating shift left unsigned"]
40933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
40934#[inline]
40935#[cfg(target_arch = "arm")]
40936#[target_feature(enable = "neon,v7")]
40937#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40938#[rustc_legacy_const_generics(1)]
40939#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40940pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
40941 static_assert_uimm_bits!(N, 5);
40942 unsafe extern "unadjusted" {
40943 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")]
40944 fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
40945 }
40946 unsafe {
40947 _vqshluq_n_s32(
40948 a,
40949 const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
40950 )
40951 }
40952}
40953#[doc = "Signed saturating shift left unsigned"]
40954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
40955#[inline]
40956#[cfg(target_arch = "arm")]
40957#[target_feature(enable = "neon,v7")]
40958#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40959#[rustc_legacy_const_generics(1)]
40960#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40961pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
40962 static_assert_uimm_bits!(N, 6);
40963 unsafe extern "unadjusted" {
40964 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v1i64")]
40965 fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t;
40966 }
40967 unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) }
40968}
40969#[doc = "Signed saturating shift left unsigned"]
40970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
40971#[inline]
40972#[cfg(target_arch = "arm")]
40973#[target_feature(enable = "neon,v7")]
40974#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40975#[rustc_legacy_const_generics(1)]
40976#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40977pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
40978 static_assert_uimm_bits!(N, 6);
40979 unsafe extern "unadjusted" {
40980 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")]
40981 fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
40982 }
40983 unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
40984}
40985#[doc = "Signed saturating shift left unsigned"]
40986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
40987#[inline]
40988#[target_feature(enable = "neon")]
40989#[cfg(not(target_arch = "arm"))]
40990#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40991#[rustc_legacy_const_generics(1)]
40992#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40993pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
40994 static_assert_uimm_bits!(N, 3);
40995 unsafe extern "unadjusted" {
40996 #[cfg_attr(
40997 any(target_arch = "aarch64", target_arch = "arm64ec"),
40998 link_name = "llvm.aarch64.neon.sqshlu.v8i8"
40999 )]
41000 fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
41001 }
41002 unsafe {
41003 _vqshlu_n_s8(
41004 a,
41005 const {
41006 int8x8_t([
41007 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
41008 ])
41009 },
41010 )
41011 }
41012}
41013#[doc = "Signed saturating shift left unsigned"]
41014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
41015#[inline]
41016#[target_feature(enable = "neon")]
41017#[cfg(not(target_arch = "arm"))]
41018#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41019#[rustc_legacy_const_generics(1)]
41020#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41021pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
41022 static_assert_uimm_bits!(N, 3);
41023 unsafe extern "unadjusted" {
41024 #[cfg_attr(
41025 any(target_arch = "aarch64", target_arch = "arm64ec"),
41026 link_name = "llvm.aarch64.neon.sqshlu.v16i8"
41027 )]
41028 fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
41029 }
41030 unsafe {
41031 _vqshluq_n_s8(
41032 a,
41033 const {
41034 int8x16_t([
41035 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
41036 N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
41037 ])
41038 },
41039 )
41040 }
41041}
41042#[doc = "Signed saturating shift left unsigned"]
41043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
41044#[inline]
41045#[target_feature(enable = "neon")]
41046#[cfg(not(target_arch = "arm"))]
41047#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41048#[rustc_legacy_const_generics(1)]
41049#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41050pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
41051 static_assert_uimm_bits!(N, 4);
41052 unsafe extern "unadjusted" {
41053 #[cfg_attr(
41054 any(target_arch = "aarch64", target_arch = "arm64ec"),
41055 link_name = "llvm.aarch64.neon.sqshlu.v4i16"
41056 )]
41057 fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
41058 }
41059 unsafe {
41060 _vqshlu_n_s16(
41061 a,
41062 const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
41063 )
41064 }
41065}
41066#[doc = "Signed saturating shift left unsigned"]
41067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
41068#[inline]
41069#[target_feature(enable = "neon")]
41070#[cfg(not(target_arch = "arm"))]
41071#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41072#[rustc_legacy_const_generics(1)]
41073#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41074pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
41075 static_assert_uimm_bits!(N, 4);
41076 unsafe extern "unadjusted" {
41077 #[cfg_attr(
41078 any(target_arch = "aarch64", target_arch = "arm64ec"),
41079 link_name = "llvm.aarch64.neon.sqshlu.v8i16"
41080 )]
41081 fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
41082 }
41083 unsafe {
41084 _vqshluq_n_s16(
41085 a,
41086 const {
41087 int16x8_t([
41088 N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
41089 ])
41090 },
41091 )
41092 }
41093}
41094#[doc = "Signed saturating shift left unsigned"]
41095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
41096#[inline]
41097#[target_feature(enable = "neon")]
41098#[cfg(not(target_arch = "arm"))]
41099#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41100#[rustc_legacy_const_generics(1)]
41101#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41102pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
41103 static_assert_uimm_bits!(N, 5);
41104 unsafe extern "unadjusted" {
41105 #[cfg_attr(
41106 any(target_arch = "aarch64", target_arch = "arm64ec"),
41107 link_name = "llvm.aarch64.neon.sqshlu.v2i32"
41108 )]
41109 fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
41110 }
41111 unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
41112}
41113#[doc = "Signed saturating shift left unsigned"]
41114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
41115#[inline]
41116#[target_feature(enable = "neon")]
41117#[cfg(not(target_arch = "arm"))]
41118#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41119#[rustc_legacy_const_generics(1)]
41120#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41121pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
41122 static_assert_uimm_bits!(N, 5);
41123 unsafe extern "unadjusted" {
41124 #[cfg_attr(
41125 any(target_arch = "aarch64", target_arch = "arm64ec"),
41126 link_name = "llvm.aarch64.neon.sqshlu.v4i32"
41127 )]
41128 fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
41129 }
41130 unsafe {
41131 _vqshluq_n_s32(
41132 a,
41133 const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
41134 )
41135 }
41136}
41137#[doc = "Signed saturating shift left unsigned"]
41138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
41139#[inline]
41140#[target_feature(enable = "neon")]
41141#[cfg(not(target_arch = "arm"))]
41142#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41143#[rustc_legacy_const_generics(1)]
41144#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41145pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
41146 static_assert_uimm_bits!(N, 6);
41147 unsafe extern "unadjusted" {
41148 #[cfg_attr(
41149 any(target_arch = "aarch64", target_arch = "arm64ec"),
41150 link_name = "llvm.aarch64.neon.sqshlu.v1i64"
41151 )]
41152 fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t;
41153 }
41154 unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) }
41155}
41156#[doc = "Signed saturating shift left unsigned"]
41157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
41158#[inline]
41159#[target_feature(enable = "neon")]
41160#[cfg(not(target_arch = "arm"))]
41161#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
41162#[rustc_legacy_const_generics(1)]
41163#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41164pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
41165 static_assert_uimm_bits!(N, 6);
41166 unsafe extern "unadjusted" {
41167 #[cfg_attr(
41168 any(target_arch = "aarch64", target_arch = "arm64ec"),
41169 link_name = "llvm.aarch64.neon.sqshlu.v2i64"
41170 )]
41171 fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
41172 }
41173 unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
41174}
41175#[doc = "Signed saturating shift right narrow"]
41176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
41177#[inline]
41178#[cfg(target_arch = "arm")]
41179#[target_feature(enable = "neon,v7")]
41180#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41181#[rustc_legacy_const_generics(1)]
41182#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41183pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
41184 static_assert!(N >= 1 && N <= 8);
41185 unsafe extern "unadjusted" {
41186 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v8i8")]
41187 fn _vqshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
41188 }
41189 unsafe {
41190 _vqshrn_n_s16(
41191 a,
41192 const {
41193 int16x8_t([
41194 -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
41195 -N as i16,
41196 ])
41197 },
41198 )
41199 }
41200}
41201#[doc = "Signed saturating shift right narrow"]
41202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
41203#[inline]
41204#[cfg(target_arch = "arm")]
41205#[target_feature(enable = "neon,v7")]
41206#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41207#[rustc_legacy_const_generics(1)]
41208#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41209pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
41210 static_assert!(N >= 1 && N <= 16);
41211 unsafe extern "unadjusted" {
41212 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v4i16")]
41213 fn _vqshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
41214 }
41215 unsafe {
41216 _vqshrn_n_s32(
41217 a,
41218 const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
41219 )
41220 }
41221}
41222#[doc = "Signed saturating shift right narrow"]
41223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
41224#[inline]
41225#[cfg(target_arch = "arm")]
41226#[target_feature(enable = "neon,v7")]
41227#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41228#[rustc_legacy_const_generics(1)]
41229#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41230pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
41231 static_assert!(N >= 1 && N <= 32);
41232 unsafe extern "unadjusted" {
41233 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v2i32")]
41234 fn _vqshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
41235 }
41236 unsafe { _vqshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
41237}
41238#[doc = "Signed saturating shift right narrow"]
41239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
41240#[inline]
41241#[target_feature(enable = "neon")]
41242#[cfg(not(target_arch = "arm"))]
41243#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
41244#[rustc_legacy_const_generics(1)]
41245#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41246pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
41247 static_assert!(N >= 1 && N <= 8);
41248 unsafe extern "unadjusted" {
41249 #[cfg_attr(
41250 any(target_arch = "aarch64", target_arch = "arm64ec"),
41251 link_name = "llvm.aarch64.neon.sqshrn.v8i8"
41252 )]
41253 fn _vqshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
41254 }
41255 unsafe { _vqshrn_n_s16(a, N) }
41256}
41257#[doc = "Signed saturating shift right narrow"]
41258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
41259#[inline]
41260#[target_feature(enable = "neon")]
41261#[cfg(not(target_arch = "arm"))]
41262#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
41263#[rustc_legacy_const_generics(1)]
41264#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41265pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
41266 static_assert!(N >= 1 && N <= 16);
41267 unsafe extern "unadjusted" {
41268 #[cfg_attr(
41269 any(target_arch = "aarch64", target_arch = "arm64ec"),
41270 link_name = "llvm.aarch64.neon.sqshrn.v4i16"
41271 )]
41272 fn _vqshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
41273 }
41274 unsafe { _vqshrn_n_s32(a, N) }
41275}
41276#[doc = "Signed saturating shift right narrow"]
41277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
41278#[inline]
41279#[target_feature(enable = "neon")]
41280#[cfg(not(target_arch = "arm"))]
41281#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
41282#[rustc_legacy_const_generics(1)]
41283#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41284pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
41285 static_assert!(N >= 1 && N <= 32);
41286 unsafe extern "unadjusted" {
41287 #[cfg_attr(
41288 any(target_arch = "aarch64", target_arch = "arm64ec"),
41289 link_name = "llvm.aarch64.neon.sqshrn.v2i32"
41290 )]
41291 fn _vqshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
41292 }
41293 unsafe { _vqshrn_n_s64(a, N) }
41294}
41295#[doc = "Unsigned saturating shift right narrow"]
41296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
41297#[inline]
41298#[cfg(target_arch = "arm")]
41299#[target_feature(enable = "neon,v7")]
41300#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41301#[rustc_legacy_const_generics(1)]
41302#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41303pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
41304 static_assert!(N >= 1 && N <= 8);
41305 unsafe extern "unadjusted" {
41306 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")]
41307 fn _vqshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
41308 }
41309 unsafe {
41310 _vqshrn_n_u16(
41311 a,
41312 const {
41313 uint16x8_t([
41314 -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
41315 -N as u16,
41316 ])
41317 },
41318 )
41319 }
41320}
41321#[doc = "Unsigned saturating shift right narrow"]
41322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
41323#[inline]
41324#[cfg(target_arch = "arm")]
41325#[target_feature(enable = "neon,v7")]
41326#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41327#[rustc_legacy_const_generics(1)]
41328#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41329pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
41330 static_assert!(N >= 1 && N <= 16);
41331 unsafe extern "unadjusted" {
41332 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")]
41333 fn _vqshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
41334 }
41335 unsafe {
41336 _vqshrn_n_u32(
41337 a,
41338 const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
41339 )
41340 }
41341}
41342#[doc = "Unsigned saturating shift right narrow"]
41343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
41344#[inline]
41345#[cfg(target_arch = "arm")]
41346#[target_feature(enable = "neon,v7")]
41347#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
41348#[rustc_legacy_const_generics(1)]
41349#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41350pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
41351 static_assert!(N >= 1 && N <= 32);
41352 unsafe extern "unadjusted" {
41353 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")]
41354 fn _vqshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
41355 }
41356 unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
41357}
41358#[doc = "Unsigned saturating shift right narrow"]
41359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
41360#[inline]
41361#[target_feature(enable = "neon")]
41362#[cfg(not(target_arch = "arm"))]
41363#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
41364#[rustc_legacy_const_generics(1)]
41365#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41366pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
41367 static_assert!(N >= 1 && N <= 8);
41368 unsafe extern "unadjusted" {
41369 #[cfg_attr(
41370 any(target_arch = "aarch64", target_arch = "arm64ec"),
41371 link_name = "llvm.aarch64.neon.uqshrn.v8i8"
41372 )]
41373 fn _vqshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t;
41374 }
41375 unsafe { _vqshrn_n_u16(a, N) }
41376}
41377#[doc = "Unsigned saturating shift right narrow"]
41378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
41379#[inline]
41380#[target_feature(enable = "neon")]
41381#[cfg(not(target_arch = "arm"))]
41382#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
41383#[rustc_legacy_const_generics(1)]
41384#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41385pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
41386 static_assert!(N >= 1 && N <= 16);
41387 unsafe extern "unadjusted" {
41388 #[cfg_attr(
41389 any(target_arch = "aarch64", target_arch = "arm64ec"),
41390 link_name = "llvm.aarch64.neon.uqshrn.v4i16"
41391 )]
41392 fn _vqshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t;
41393 }
41394 unsafe { _vqshrn_n_u32(a, N) }
41395}
41396#[doc = "Unsigned saturating shift right narrow"]
41397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
41398#[inline]
41399#[target_feature(enable = "neon")]
41400#[cfg(not(target_arch = "arm"))]
41401#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
41402#[rustc_legacy_const_generics(1)]
41403#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41404pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
41405 static_assert!(N >= 1 && N <= 32);
41406 unsafe extern "unadjusted" {
41407 #[cfg_attr(
41408 any(target_arch = "aarch64", target_arch = "arm64ec"),
41409 link_name = "llvm.aarch64.neon.uqshrn.v2i32"
41410 )]
41411 fn _vqshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t;
41412 }
41413 unsafe { _vqshrn_n_u64(a, N) }
41414}
41415#[doc = "Signed saturating shift right unsigned narrow"]
41416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
41417#[inline]
41418#[cfg(target_arch = "arm")]
41419#[target_feature(enable = "neon,v7")]
41420#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41421#[rustc_legacy_const_generics(1)]
41422#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41423pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
41424 static_assert!(N >= 1 && N <= 8);
41425 unsafe extern "unadjusted" {
41426 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")]
41427 fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
41428 }
41429 unsafe {
41430 _vqshrun_n_s16(
41431 a,
41432 const {
41433 int16x8_t([
41434 -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
41435 -N as i16,
41436 ])
41437 },
41438 )
41439 }
41440}
41441#[doc = "Signed saturating shift right unsigned narrow"]
41442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
41443#[inline]
41444#[cfg(target_arch = "arm")]
41445#[target_feature(enable = "neon,v7")]
41446#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41447#[rustc_legacy_const_generics(1)]
41448#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41449pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
41450 static_assert!(N >= 1 && N <= 16);
41451 unsafe extern "unadjusted" {
41452 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")]
41453 fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
41454 }
41455 unsafe {
41456 _vqshrun_n_s32(
41457 a,
41458 const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
41459 )
41460 }
41461}
41462#[doc = "Signed saturating shift right unsigned narrow"]
41463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
41464#[inline]
41465#[cfg(target_arch = "arm")]
41466#[target_feature(enable = "neon,v7")]
41467#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41468#[rustc_legacy_const_generics(1)]
41469#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41470pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
41471 static_assert!(N >= 1 && N <= 32);
41472 unsafe extern "unadjusted" {
41473 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")]
41474 fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
41475 }
41476 unsafe { _vqshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
41477}
41478#[doc = "Signed saturating shift right unsigned narrow"]
41479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
41480#[inline]
41481#[target_feature(enable = "neon")]
41482#[cfg(not(target_arch = "arm"))]
41483#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41484#[rustc_legacy_const_generics(1)]
41485#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41486pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
41487 static_assert!(N >= 1 && N <= 8);
41488 unsafe extern "unadjusted" {
41489 #[cfg_attr(
41490 any(target_arch = "aarch64", target_arch = "arm64ec"),
41491 link_name = "llvm.aarch64.neon.sqshrun.v8i8"
41492 )]
41493 fn _vqshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t;
41494 }
41495 unsafe { _vqshrun_n_s16(a, N) }
41496}
41497#[doc = "Signed saturating shift right unsigned narrow"]
41498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
41499#[inline]
41500#[target_feature(enable = "neon")]
41501#[cfg(not(target_arch = "arm"))]
41502#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41503#[rustc_legacy_const_generics(1)]
41504#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41505pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
41506 static_assert!(N >= 1 && N <= 16);
41507 unsafe extern "unadjusted" {
41508 #[cfg_attr(
41509 any(target_arch = "aarch64", target_arch = "arm64ec"),
41510 link_name = "llvm.aarch64.neon.sqshrun.v4i16"
41511 )]
41512 fn _vqshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t;
41513 }
41514 unsafe { _vqshrun_n_s32(a, N) }
41515}
41516#[doc = "Signed saturating shift right unsigned narrow"]
41517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
41518#[inline]
41519#[target_feature(enable = "neon")]
41520#[cfg(not(target_arch = "arm"))]
41521#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41522#[rustc_legacy_const_generics(1)]
41523#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41524pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
41525 static_assert!(N >= 1 && N <= 32);
41526 unsafe extern "unadjusted" {
41527 #[cfg_attr(
41528 any(target_arch = "aarch64", target_arch = "arm64ec"),
41529 link_name = "llvm.aarch64.neon.sqshrun.v2i32"
41530 )]
41531 fn _vqshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t;
41532 }
41533 unsafe { _vqshrun_n_s64(a, N) }
41534}
41535#[doc = "Saturating subtract"]
41536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"]
41537#[inline]
41538#[target_feature(enable = "neon")]
41539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41540#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
41541#[cfg_attr(
41542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41543 assert_instr(sqsub)
41544)]
41545#[cfg_attr(
41546 not(target_arch = "arm"),
41547 stable(feature = "neon_intrinsics", since = "1.59.0")
41548)]
41549#[cfg_attr(
41550 target_arch = "arm",
41551 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41552)]
41553pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
41554 unsafe extern "unadjusted" {
41555 #[cfg_attr(
41556 any(target_arch = "aarch64", target_arch = "arm64ec"),
41557 link_name = "llvm.aarch64.neon.sqsub.v8i8"
41558 )]
41559 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i8")]
41560 fn _vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
41561 }
41562 unsafe { _vqsub_s8(a, b) }
41563}
41564#[doc = "Saturating subtract"]
41565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"]
41566#[inline]
41567#[target_feature(enable = "neon")]
41568#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41569#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
41570#[cfg_attr(
41571 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41572 assert_instr(sqsub)
41573)]
41574#[cfg_attr(
41575 not(target_arch = "arm"),
41576 stable(feature = "neon_intrinsics", since = "1.59.0")
41577)]
41578#[cfg_attr(
41579 target_arch = "arm",
41580 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41581)]
41582pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
41583 unsafe extern "unadjusted" {
41584 #[cfg_attr(
41585 any(target_arch = "aarch64", target_arch = "arm64ec"),
41586 link_name = "llvm.aarch64.neon.sqsub.v16i8"
41587 )]
41588 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v16i8")]
41589 fn _vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
41590 }
41591 unsafe { _vqsubq_s8(a, b) }
41592}
41593#[doc = "Saturating subtract"]
41594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"]
41595#[inline]
41596#[target_feature(enable = "neon")]
41597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41598#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
41599#[cfg_attr(
41600 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41601 assert_instr(sqsub)
41602)]
41603#[cfg_attr(
41604 not(target_arch = "arm"),
41605 stable(feature = "neon_intrinsics", since = "1.59.0")
41606)]
41607#[cfg_attr(
41608 target_arch = "arm",
41609 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41610)]
41611pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
41612 unsafe extern "unadjusted" {
41613 #[cfg_attr(
41614 any(target_arch = "aarch64", target_arch = "arm64ec"),
41615 link_name = "llvm.aarch64.neon.sqsub.v4i16"
41616 )]
41617 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i16")]
41618 fn _vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
41619 }
41620 unsafe { _vqsub_s16(a, b) }
41621}
41622#[doc = "Saturating subtract"]
41623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"]
41624#[inline]
41625#[target_feature(enable = "neon")]
41626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41627#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
41628#[cfg_attr(
41629 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41630 assert_instr(sqsub)
41631)]
41632#[cfg_attr(
41633 not(target_arch = "arm"),
41634 stable(feature = "neon_intrinsics", since = "1.59.0")
41635)]
41636#[cfg_attr(
41637 target_arch = "arm",
41638 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41639)]
41640pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
41641 unsafe extern "unadjusted" {
41642 #[cfg_attr(
41643 any(target_arch = "aarch64", target_arch = "arm64ec"),
41644 link_name = "llvm.aarch64.neon.sqsub.v8i16"
41645 )]
41646 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i16")]
41647 fn _vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
41648 }
41649 unsafe { _vqsubq_s16(a, b) }
41650}
41651#[doc = "Saturating subtract"]
41652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"]
41653#[inline]
41654#[target_feature(enable = "neon")]
41655#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41656#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
41657#[cfg_attr(
41658 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41659 assert_instr(sqsub)
41660)]
41661#[cfg_attr(
41662 not(target_arch = "arm"),
41663 stable(feature = "neon_intrinsics", since = "1.59.0")
41664)]
41665#[cfg_attr(
41666 target_arch = "arm",
41667 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41668)]
41669pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
41670 unsafe extern "unadjusted" {
41671 #[cfg_attr(
41672 any(target_arch = "aarch64", target_arch = "arm64ec"),
41673 link_name = "llvm.aarch64.neon.sqsub.v2i32"
41674 )]
41675 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i32")]
41676 fn _vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
41677 }
41678 unsafe { _vqsub_s32(a, b) }
41679}
41680#[doc = "Saturating subtract"]
41681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"]
41682#[inline]
41683#[target_feature(enable = "neon")]
41684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41685#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
41686#[cfg_attr(
41687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41688 assert_instr(sqsub)
41689)]
41690#[cfg_attr(
41691 not(target_arch = "arm"),
41692 stable(feature = "neon_intrinsics", since = "1.59.0")
41693)]
41694#[cfg_attr(
41695 target_arch = "arm",
41696 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41697)]
41698pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
41699 unsafe extern "unadjusted" {
41700 #[cfg_attr(
41701 any(target_arch = "aarch64", target_arch = "arm64ec"),
41702 link_name = "llvm.aarch64.neon.sqsub.v4i32"
41703 )]
41704 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i32")]
41705 fn _vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
41706 }
41707 unsafe { _vqsubq_s32(a, b) }
41708}
41709#[doc = "Saturating subtract"]
41710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"]
41711#[inline]
41712#[target_feature(enable = "neon")]
41713#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41714#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
41715#[cfg_attr(
41716 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41717 assert_instr(sqsub)
41718)]
41719#[cfg_attr(
41720 not(target_arch = "arm"),
41721 stable(feature = "neon_intrinsics", since = "1.59.0")
41722)]
41723#[cfg_attr(
41724 target_arch = "arm",
41725 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41726)]
41727pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
41728 unsafe extern "unadjusted" {
41729 #[cfg_attr(
41730 any(target_arch = "aarch64", target_arch = "arm64ec"),
41731 link_name = "llvm.aarch64.neon.sqsub.v1i64"
41732 )]
41733 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v1i64")]
41734 fn _vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
41735 }
41736 unsafe { _vqsub_s64(a, b) }
41737}
41738#[doc = "Saturating subtract"]
41739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"]
41740#[inline]
41741#[target_feature(enable = "neon")]
41742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41743#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
41744#[cfg_attr(
41745 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41746 assert_instr(sqsub)
41747)]
41748#[cfg_attr(
41749 not(target_arch = "arm"),
41750 stable(feature = "neon_intrinsics", since = "1.59.0")
41751)]
41752#[cfg_attr(
41753 target_arch = "arm",
41754 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41755)]
41756pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
41757 unsafe extern "unadjusted" {
41758 #[cfg_attr(
41759 any(target_arch = "aarch64", target_arch = "arm64ec"),
41760 link_name = "llvm.aarch64.neon.sqsub.v2i64"
41761 )]
41762 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i64")]
41763 fn _vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
41764 }
41765 unsafe { _vqsubq_s64(a, b) }
41766}
41767#[doc = "Saturating subtract"]
41768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"]
41769#[inline]
41770#[target_feature(enable = "neon")]
41771#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41772#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
41773#[cfg_attr(
41774 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41775 assert_instr(uqsub)
41776)]
41777#[cfg_attr(
41778 not(target_arch = "arm"),
41779 stable(feature = "neon_intrinsics", since = "1.59.0")
41780)]
41781#[cfg_attr(
41782 target_arch = "arm",
41783 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41784)]
41785pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
41786 unsafe extern "unadjusted" {
41787 #[cfg_attr(
41788 any(target_arch = "aarch64", target_arch = "arm64ec"),
41789 link_name = "llvm.aarch64.neon.uqsub.v8i8"
41790 )]
41791 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i8")]
41792 fn _vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
41793 }
41794 unsafe { _vqsub_u8(a, b) }
41795}
41796#[doc = "Saturating subtract"]
41797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"]
41798#[inline]
41799#[target_feature(enable = "neon")]
41800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41801#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
41802#[cfg_attr(
41803 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41804 assert_instr(uqsub)
41805)]
41806#[cfg_attr(
41807 not(target_arch = "arm"),
41808 stable(feature = "neon_intrinsics", since = "1.59.0")
41809)]
41810#[cfg_attr(
41811 target_arch = "arm",
41812 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41813)]
41814pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
41815 unsafe extern "unadjusted" {
41816 #[cfg_attr(
41817 any(target_arch = "aarch64", target_arch = "arm64ec"),
41818 link_name = "llvm.aarch64.neon.uqsub.v16i8"
41819 )]
41820 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v16i8")]
41821 fn _vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
41822 }
41823 unsafe { _vqsubq_u8(a, b) }
41824}
41825#[doc = "Saturating subtract"]
41826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"]
41827#[inline]
41828#[target_feature(enable = "neon")]
41829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41830#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
41831#[cfg_attr(
41832 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41833 assert_instr(uqsub)
41834)]
41835#[cfg_attr(
41836 not(target_arch = "arm"),
41837 stable(feature = "neon_intrinsics", since = "1.59.0")
41838)]
41839#[cfg_attr(
41840 target_arch = "arm",
41841 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41842)]
41843pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
41844 unsafe extern "unadjusted" {
41845 #[cfg_attr(
41846 any(target_arch = "aarch64", target_arch = "arm64ec"),
41847 link_name = "llvm.aarch64.neon.uqsub.v4i16"
41848 )]
41849 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i16")]
41850 fn _vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
41851 }
41852 unsafe { _vqsub_u16(a, b) }
41853}
41854#[doc = "Saturating subtract"]
41855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"]
41856#[inline]
41857#[target_feature(enable = "neon")]
41858#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41859#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
41860#[cfg_attr(
41861 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41862 assert_instr(uqsub)
41863)]
41864#[cfg_attr(
41865 not(target_arch = "arm"),
41866 stable(feature = "neon_intrinsics", since = "1.59.0")
41867)]
41868#[cfg_attr(
41869 target_arch = "arm",
41870 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41871)]
41872pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
41873 unsafe extern "unadjusted" {
41874 #[cfg_attr(
41875 any(target_arch = "aarch64", target_arch = "arm64ec"),
41876 link_name = "llvm.aarch64.neon.uqsub.v8i16"
41877 )]
41878 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i16")]
41879 fn _vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
41880 }
41881 unsafe { _vqsubq_u16(a, b) }
41882}
41883#[doc = "Saturating subtract"]
41884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"]
41885#[inline]
41886#[target_feature(enable = "neon")]
41887#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41888#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
41889#[cfg_attr(
41890 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41891 assert_instr(uqsub)
41892)]
41893#[cfg_attr(
41894 not(target_arch = "arm"),
41895 stable(feature = "neon_intrinsics", since = "1.59.0")
41896)]
41897#[cfg_attr(
41898 target_arch = "arm",
41899 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41900)]
41901pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
41902 unsafe extern "unadjusted" {
41903 #[cfg_attr(
41904 any(target_arch = "aarch64", target_arch = "arm64ec"),
41905 link_name = "llvm.aarch64.neon.uqsub.v2i32"
41906 )]
41907 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i32")]
41908 fn _vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
41909 }
41910 unsafe { _vqsub_u32(a, b) }
41911}
41912#[doc = "Saturating subtract"]
41913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"]
41914#[inline]
41915#[target_feature(enable = "neon")]
41916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41917#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
41918#[cfg_attr(
41919 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41920 assert_instr(uqsub)
41921)]
41922#[cfg_attr(
41923 not(target_arch = "arm"),
41924 stable(feature = "neon_intrinsics", since = "1.59.0")
41925)]
41926#[cfg_attr(
41927 target_arch = "arm",
41928 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41929)]
41930pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
41931 unsafe extern "unadjusted" {
41932 #[cfg_attr(
41933 any(target_arch = "aarch64", target_arch = "arm64ec"),
41934 link_name = "llvm.aarch64.neon.uqsub.v4i32"
41935 )]
41936 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i32")]
41937 fn _vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
41938 }
41939 unsafe { _vqsubq_u32(a, b) }
41940}
41941#[doc = "Saturating subtract"]
41942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"]
41943#[inline]
41944#[target_feature(enable = "neon")]
41945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41946#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
41947#[cfg_attr(
41948 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41949 assert_instr(uqsub)
41950)]
41951#[cfg_attr(
41952 not(target_arch = "arm"),
41953 stable(feature = "neon_intrinsics", since = "1.59.0")
41954)]
41955#[cfg_attr(
41956 target_arch = "arm",
41957 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41958)]
41959pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
41960 unsafe extern "unadjusted" {
41961 #[cfg_attr(
41962 any(target_arch = "aarch64", target_arch = "arm64ec"),
41963 link_name = "llvm.aarch64.neon.uqsub.v1i64"
41964 )]
41965 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v1i64")]
41966 fn _vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t;
41967 }
41968 unsafe { _vqsub_u64(a, b) }
41969}
41970#[doc = "Saturating subtract"]
41971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"]
41972#[inline]
41973#[target_feature(enable = "neon")]
41974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41975#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
41976#[cfg_attr(
41977 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41978 assert_instr(uqsub)
41979)]
41980#[cfg_attr(
41981 not(target_arch = "arm"),
41982 stable(feature = "neon_intrinsics", since = "1.59.0")
41983)]
41984#[cfg_attr(
41985 target_arch = "arm",
41986 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41987)]
41988pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
41989 unsafe extern "unadjusted" {
41990 #[cfg_attr(
41991 any(target_arch = "aarch64", target_arch = "arm64ec"),
41992 link_name = "llvm.aarch64.neon.uqsub.v2i64"
41993 )]
41994 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i64")]
41995 fn _vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
41996 }
41997 unsafe { _vqsubq_u64(a, b) }
41998}
41999#[doc = "Rounding Add returning High Narrow (high half)."]
42000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"]
42001#[inline]
42002#[target_feature(enable = "neon")]
42003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42004#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42005#[cfg_attr(
42006 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42007 assert_instr(raddhn2)
42008)]
42009#[cfg_attr(
42010 not(target_arch = "arm"),
42011 stable(feature = "neon_intrinsics", since = "1.59.0")
42012)]
42013#[cfg_attr(
42014 target_arch = "arm",
42015 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42016)]
42017pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
42018 let x = vraddhn_s16(b, c);
42019 unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
42020}
42021#[doc = "Rounding Add returning High Narrow (high half)."]
42022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"]
42023#[inline]
42024#[target_feature(enable = "neon")]
42025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42026#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42027#[cfg_attr(
42028 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42029 assert_instr(raddhn2)
42030)]
42031#[cfg_attr(
42032 not(target_arch = "arm"),
42033 stable(feature = "neon_intrinsics", since = "1.59.0")
42034)]
42035#[cfg_attr(
42036 target_arch = "arm",
42037 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42038)]
42039pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
42040 let x = vraddhn_s32(b, c);
42041 unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) }
42042}
42043#[doc = "Rounding Add returning High Narrow (high half)."]
42044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"]
42045#[inline]
42046#[target_feature(enable = "neon")]
42047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42048#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42049#[cfg_attr(
42050 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42051 assert_instr(raddhn2)
42052)]
42053#[cfg_attr(
42054 not(target_arch = "arm"),
42055 stable(feature = "neon_intrinsics", since = "1.59.0")
42056)]
42057#[cfg_attr(
42058 target_arch = "arm",
42059 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42060)]
42061pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
42062 let x = vraddhn_s64(b, c);
42063 unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
42064}
42065#[doc = "Rounding Add returning High Narrow (high half)."]
42066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"]
42067#[inline]
42068#[target_feature(enable = "neon")]
42069#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42070#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42071#[cfg_attr(
42072 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42073 assert_instr(raddhn2)
42074)]
42075#[cfg_attr(
42076 not(target_arch = "arm"),
42077 stable(feature = "neon_intrinsics", since = "1.59.0")
42078)]
42079#[cfg_attr(
42080 target_arch = "arm",
42081 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42082)]
42083pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
42084 unsafe {
42085 let x: uint8x8_t = transmute(vraddhn_s16(transmute(b), transmute(c)));
42086 simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
42087 }
42088}
42089#[doc = "Rounding Add returning High Narrow (high half)."]
42090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"]
42091#[inline]
42092#[target_feature(enable = "neon")]
42093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42094#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42095#[cfg_attr(
42096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42097 assert_instr(raddhn2)
42098)]
42099#[cfg_attr(
42100 not(target_arch = "arm"),
42101 stable(feature = "neon_intrinsics", since = "1.59.0")
42102)]
42103#[cfg_attr(
42104 target_arch = "arm",
42105 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42106)]
42107pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
42108 unsafe {
42109 let x: uint16x4_t = transmute(vraddhn_s32(transmute(b), transmute(c)));
42110 simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7])
42111 }
42112}
42113#[doc = "Rounding Add returning High Narrow (high half)."]
42114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"]
42115#[inline]
42116#[target_feature(enable = "neon")]
42117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42118#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42119#[cfg_attr(
42120 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42121 assert_instr(raddhn2)
42122)]
42123#[cfg_attr(
42124 not(target_arch = "arm"),
42125 stable(feature = "neon_intrinsics", since = "1.59.0")
42126)]
42127#[cfg_attr(
42128 target_arch = "arm",
42129 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42130)]
42131pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
42132 unsafe {
42133 let x: uint32x2_t = transmute(vraddhn_s64(transmute(b), transmute(c)));
42134 simd_shuffle!(a, x, [0, 1, 2, 3])
42135 }
42136}
42137#[doc = "Rounding Add returning High Narrow."]
42138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"]
42139#[inline]
42140#[target_feature(enable = "neon")]
42141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42142#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42143#[cfg_attr(
42144 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42145 assert_instr(raddhn)
42146)]
42147#[cfg_attr(
42148 not(target_arch = "arm"),
42149 stable(feature = "neon_intrinsics", since = "1.59.0")
42150)]
42151#[cfg_attr(
42152 target_arch = "arm",
42153 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42154)]
42155pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
42156 unsafe extern "unadjusted" {
42157 #[cfg_attr(
42158 any(target_arch = "aarch64", target_arch = "arm64ec"),
42159 link_name = "llvm.aarch64.neon.raddhn.v8i8"
42160 )]
42161 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v8i8")]
42162 fn _vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t;
42163 }
42164 unsafe { _vraddhn_s16(a, b) }
42165}
42166#[doc = "Rounding Add returning High Narrow."]
42167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"]
42168#[inline]
42169#[target_feature(enable = "neon")]
42170#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42171#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42172#[cfg_attr(
42173 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42174 assert_instr(raddhn)
42175)]
42176#[cfg_attr(
42177 not(target_arch = "arm"),
42178 stable(feature = "neon_intrinsics", since = "1.59.0")
42179)]
42180#[cfg_attr(
42181 target_arch = "arm",
42182 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42183)]
42184pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
42185 unsafe extern "unadjusted" {
42186 #[cfg_attr(
42187 any(target_arch = "aarch64", target_arch = "arm64ec"),
42188 link_name = "llvm.aarch64.neon.raddhn.v4i16"
42189 )]
42190 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v4i16")]
42191 fn _vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t;
42192 }
42193 unsafe { _vraddhn_s32(a, b) }
42194}
42195#[doc = "Rounding Add returning High Narrow."]
42196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"]
42197#[inline]
42198#[target_feature(enable = "neon")]
42199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42200#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42201#[cfg_attr(
42202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42203 assert_instr(raddhn)
42204)]
42205#[cfg_attr(
42206 not(target_arch = "arm"),
42207 stable(feature = "neon_intrinsics", since = "1.59.0")
42208)]
42209#[cfg_attr(
42210 target_arch = "arm",
42211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42212)]
42213pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
42214 unsafe extern "unadjusted" {
42215 #[cfg_attr(
42216 any(target_arch = "aarch64", target_arch = "arm64ec"),
42217 link_name = "llvm.aarch64.neon.raddhn.v2i32"
42218 )]
42219 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v2i32")]
42220 fn _vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t;
42221 }
42222 unsafe { _vraddhn_s64(a, b) }
42223}
42224#[doc = "Rounding Add returning High Narrow."]
42225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
42226#[inline]
42227#[cfg(target_endian = "little")]
42228#[target_feature(enable = "neon")]
42229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42230#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42231#[cfg_attr(
42232 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42233 assert_instr(raddhn)
42234)]
42235#[cfg_attr(
42236 not(target_arch = "arm"),
42237 stable(feature = "neon_intrinsics", since = "1.59.0")
42238)]
42239#[cfg_attr(
42240 target_arch = "arm",
42241 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42242)]
42243pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
42244 unsafe { transmute(vraddhn_s16(transmute(a), transmute(b))) }
42245}
42246#[doc = "Rounding Add returning High Narrow."]
42247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
42248#[inline]
42249#[cfg(target_endian = "big")]
42250#[target_feature(enable = "neon")]
42251#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42252#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
42253#[cfg_attr(
42254 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42255 assert_instr(raddhn)
42256)]
42257#[cfg_attr(
42258 not(target_arch = "arm"),
42259 stable(feature = "neon_intrinsics", since = "1.59.0")
42260)]
42261#[cfg_attr(
42262 target_arch = "arm",
42263 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42264)]
42265pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
42266 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42267 let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
42268 unsafe {
42269 let ret_val: uint8x8_t = transmute(vraddhn_s16(transmute(a), transmute(b)));
42270 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42271 }
42272}
42273#[doc = "Rounding Add returning High Narrow."]
42274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
42275#[inline]
42276#[cfg(target_endian = "little")]
42277#[target_feature(enable = "neon")]
42278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42279#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42280#[cfg_attr(
42281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42282 assert_instr(raddhn)
42283)]
42284#[cfg_attr(
42285 not(target_arch = "arm"),
42286 stable(feature = "neon_intrinsics", since = "1.59.0")
42287)]
42288#[cfg_attr(
42289 target_arch = "arm",
42290 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42291)]
42292pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
42293 unsafe { transmute(vraddhn_s32(transmute(a), transmute(b))) }
42294}
42295#[doc = "Rounding Add returning High Narrow."]
42296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
42297#[inline]
42298#[cfg(target_endian = "big")]
42299#[target_feature(enable = "neon")]
42300#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42301#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
42302#[cfg_attr(
42303 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42304 assert_instr(raddhn)
42305)]
42306#[cfg_attr(
42307 not(target_arch = "arm"),
42308 stable(feature = "neon_intrinsics", since = "1.59.0")
42309)]
42310#[cfg_attr(
42311 target_arch = "arm",
42312 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42313)]
42314pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
42315 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42316 let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
42317 unsafe {
42318 let ret_val: uint16x4_t = transmute(vraddhn_s32(transmute(a), transmute(b)));
42319 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42320 }
42321}
42322#[doc = "Rounding Add returning High Narrow."]
42323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
42324#[inline]
42325#[cfg(target_endian = "little")]
42326#[target_feature(enable = "neon")]
42327#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42328#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42329#[cfg_attr(
42330 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42331 assert_instr(raddhn)
42332)]
42333#[cfg_attr(
42334 not(target_arch = "arm"),
42335 stable(feature = "neon_intrinsics", since = "1.59.0")
42336)]
42337#[cfg_attr(
42338 target_arch = "arm",
42339 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42340)]
42341pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
42342 unsafe { transmute(vraddhn_s64(transmute(a), transmute(b))) }
42343}
42344#[doc = "Rounding Add returning High Narrow."]
42345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
42346#[inline]
42347#[cfg(target_endian = "big")]
42348#[target_feature(enable = "neon")]
42349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42350#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
42351#[cfg_attr(
42352 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42353 assert_instr(raddhn)
42354)]
42355#[cfg_attr(
42356 not(target_arch = "arm"),
42357 stable(feature = "neon_intrinsics", since = "1.59.0")
42358)]
42359#[cfg_attr(
42360 target_arch = "arm",
42361 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42362)]
42363pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
42364 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42365 let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
42366 unsafe {
42367 let ret_val: uint32x2_t = transmute(vraddhn_s64(transmute(a), transmute(b)));
42368 simd_shuffle!(ret_val, ret_val, [1, 0])
42369 }
42370}
42371#[doc = "Reciprocal estimate."]
42372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"]
42373#[inline]
42374#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42376#[cfg_attr(
42377 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42378 assert_instr(frecpe)
42379)]
42380#[target_feature(enable = "neon,fp16")]
42381#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42382pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t {
42383 unsafe extern "unadjusted" {
42384 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f16")]
42385 #[cfg_attr(
42386 any(target_arch = "aarch64", target_arch = "arm64ec"),
42387 link_name = "llvm.aarch64.neon.frecpe.v4f16"
42388 )]
42389 fn _vrecpe_f16(a: float16x4_t) -> float16x4_t;
42390 }
42391 unsafe { _vrecpe_f16(a) }
42392}
42393#[doc = "Reciprocal estimate."]
42394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"]
42395#[inline]
42396#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42398#[cfg_attr(
42399 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42400 assert_instr(frecpe)
42401)]
42402#[target_feature(enable = "neon,fp16")]
42403#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42404pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t {
42405 unsafe extern "unadjusted" {
42406 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v8f16")]
42407 #[cfg_attr(
42408 any(target_arch = "aarch64", target_arch = "arm64ec"),
42409 link_name = "llvm.aarch64.neon.frecpe.v8f16"
42410 )]
42411 fn _vrecpeq_f16(a: float16x8_t) -> float16x8_t;
42412 }
42413 unsafe { _vrecpeq_f16(a) }
42414}
42415#[doc = "Reciprocal estimate."]
42416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"]
42417#[inline]
42418#[target_feature(enable = "neon")]
42419#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42420#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42421#[cfg_attr(
42422 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42423 assert_instr(frecpe)
42424)]
42425#[cfg_attr(
42426 not(target_arch = "arm"),
42427 stable(feature = "neon_intrinsics", since = "1.59.0")
42428)]
42429#[cfg_attr(
42430 target_arch = "arm",
42431 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42432)]
42433pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t {
42434 unsafe extern "unadjusted" {
42435 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2f32")]
42436 #[cfg_attr(
42437 any(target_arch = "aarch64", target_arch = "arm64ec"),
42438 link_name = "llvm.aarch64.neon.frecpe.v2f32"
42439 )]
42440 fn _vrecpe_f32(a: float32x2_t) -> float32x2_t;
42441 }
42442 unsafe { _vrecpe_f32(a) }
42443}
42444#[doc = "Reciprocal estimate."]
42445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"]
42446#[inline]
42447#[target_feature(enable = "neon")]
42448#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42449#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42450#[cfg_attr(
42451 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42452 assert_instr(frecpe)
42453)]
42454#[cfg_attr(
42455 not(target_arch = "arm"),
42456 stable(feature = "neon_intrinsics", since = "1.59.0")
42457)]
42458#[cfg_attr(
42459 target_arch = "arm",
42460 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42461)]
42462pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t {
42463 unsafe extern "unadjusted" {
42464 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f32")]
42465 #[cfg_attr(
42466 any(target_arch = "aarch64", target_arch = "arm64ec"),
42467 link_name = "llvm.aarch64.neon.frecpe.v4f32"
42468 )]
42469 fn _vrecpeq_f32(a: float32x4_t) -> float32x4_t;
42470 }
42471 unsafe { _vrecpeq_f32(a) }
42472}
42473#[doc = "Unsigned reciprocal estimate"]
42474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"]
42475#[inline]
42476#[target_feature(enable = "neon")]
42477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42479#[cfg_attr(
42480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42481 assert_instr(urecpe)
42482)]
42483#[cfg_attr(
42484 not(target_arch = "arm"),
42485 stable(feature = "neon_intrinsics", since = "1.59.0")
42486)]
42487#[cfg_attr(
42488 target_arch = "arm",
42489 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42490)]
42491pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t {
42492 unsafe extern "unadjusted" {
42493 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2i32")]
42494 #[cfg_attr(
42495 any(target_arch = "aarch64", target_arch = "arm64ec"),
42496 link_name = "llvm.aarch64.neon.urecpe.v2i32"
42497 )]
42498 fn _vrecpe_u32(a: uint32x2_t) -> uint32x2_t;
42499 }
42500 unsafe { _vrecpe_u32(a) }
42501}
42502#[doc = "Unsigned reciprocal estimate"]
42503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"]
42504#[inline]
42505#[target_feature(enable = "neon")]
42506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42508#[cfg_attr(
42509 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42510 assert_instr(urecpe)
42511)]
42512#[cfg_attr(
42513 not(target_arch = "arm"),
42514 stable(feature = "neon_intrinsics", since = "1.59.0")
42515)]
42516#[cfg_attr(
42517 target_arch = "arm",
42518 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42519)]
42520pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t {
42521 unsafe extern "unadjusted" {
42522 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4i32")]
42523 #[cfg_attr(
42524 any(target_arch = "aarch64", target_arch = "arm64ec"),
42525 link_name = "llvm.aarch64.neon.urecpe.v4i32"
42526 )]
42527 fn _vrecpeq_u32(a: uint32x4_t) -> uint32x4_t;
42528 }
42529 unsafe { _vrecpeq_u32(a) }
42530}
42531#[doc = "Floating-point reciprocal step"]
42532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"]
42533#[inline]
42534#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42536#[cfg_attr(
42537 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42538 assert_instr(frecps)
42539)]
42540#[target_feature(enable = "neon,fp16")]
42541#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42542pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
42543 unsafe extern "unadjusted" {
42544 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f16")]
42545 #[cfg_attr(
42546 any(target_arch = "aarch64", target_arch = "arm64ec"),
42547 link_name = "llvm.aarch64.neon.frecps.v4f16"
42548 )]
42549 fn _vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
42550 }
42551 unsafe { _vrecps_f16(a, b) }
42552}
42553#[doc = "Floating-point reciprocal step"]
42554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"]
42555#[inline]
42556#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42558#[cfg_attr(
42559 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42560 assert_instr(frecps)
42561)]
42562#[target_feature(enable = "neon,fp16")]
42563#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42564pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
42565 unsafe extern "unadjusted" {
42566 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v8f16")]
42567 #[cfg_attr(
42568 any(target_arch = "aarch64", target_arch = "arm64ec"),
42569 link_name = "llvm.aarch64.neon.frecps.v8f16"
42570 )]
42571 fn _vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
42572 }
42573 unsafe { _vrecpsq_f16(a, b) }
42574}
42575#[doc = "Floating-point reciprocal step"]
42576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"]
42577#[inline]
42578#[target_feature(enable = "neon")]
42579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42580#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42581#[cfg_attr(
42582 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42583 assert_instr(frecps)
42584)]
42585#[cfg_attr(
42586 not(target_arch = "arm"),
42587 stable(feature = "neon_intrinsics", since = "1.59.0")
42588)]
42589#[cfg_attr(
42590 target_arch = "arm",
42591 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42592)]
42593pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
42594 unsafe extern "unadjusted" {
42595 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v2f32")]
42596 #[cfg_attr(
42597 any(target_arch = "aarch64", target_arch = "arm64ec"),
42598 link_name = "llvm.aarch64.neon.frecps.v2f32"
42599 )]
42600 fn _vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
42601 }
42602 unsafe { _vrecps_f32(a, b) }
42603}
42604#[doc = "Floating-point reciprocal step"]
42605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"]
42606#[inline]
42607#[target_feature(enable = "neon")]
42608#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42609#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42610#[cfg_attr(
42611 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42612 assert_instr(frecps)
42613)]
42614#[cfg_attr(
42615 not(target_arch = "arm"),
42616 stable(feature = "neon_intrinsics", since = "1.59.0")
42617)]
42618#[cfg_attr(
42619 target_arch = "arm",
42620 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42621)]
42622pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
42623 unsafe extern "unadjusted" {
42624 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f32")]
42625 #[cfg_attr(
42626 any(target_arch = "aarch64", target_arch = "arm64ec"),
42627 link_name = "llvm.aarch64.neon.frecps.v4f32"
42628 )]
42629 fn _vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
42630 }
42631 unsafe { _vrecpsq_f32(a, b) }
42632}
42633#[doc = "Vector reinterpret cast operation"]
42634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
42635#[inline]
42636#[cfg(target_endian = "little")]
42637#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42638#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42639#[cfg_attr(
42640 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42641 assert_instr(nop)
42642)]
42643#[target_feature(enable = "neon,fp16")]
42644#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42645pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
42646 unsafe { transmute(a) }
42647}
42648#[doc = "Vector reinterpret cast operation"]
42649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
42650#[inline]
42651#[cfg(target_endian = "big")]
42652#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42653#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42654#[cfg_attr(
42655 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42656 assert_instr(nop)
42657)]
42658#[target_feature(enable = "neon,fp16")]
42659#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42660pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
42661 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42662 unsafe {
42663 let ret_val: float32x2_t = transmute(a);
42664 simd_shuffle!(ret_val, ret_val, [1, 0])
42665 }
42666}
42667#[doc = "Vector reinterpret cast operation"]
42668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
42669#[inline]
42670#[cfg(target_endian = "little")]
42671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42673#[cfg_attr(
42674 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42675 assert_instr(nop)
42676)]
42677#[target_feature(enable = "neon,fp16")]
42678#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42679pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
42680 unsafe { transmute(a) }
42681}
42682#[doc = "Vector reinterpret cast operation"]
42683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
42684#[inline]
42685#[cfg(target_endian = "big")]
42686#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42687#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42688#[cfg_attr(
42689 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42690 assert_instr(nop)
42691)]
42692#[target_feature(enable = "neon,fp16")]
42693#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42694pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
42695 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42696 unsafe {
42697 let ret_val: int8x8_t = transmute(a);
42698 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42699 }
42700}
42701#[doc = "Vector reinterpret cast operation"]
42702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
42703#[inline]
42704#[cfg(target_endian = "little")]
42705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42707#[cfg_attr(
42708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42709 assert_instr(nop)
42710)]
42711#[target_feature(enable = "neon,fp16")]
42712#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42713pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
42714 unsafe { transmute(a) }
42715}
42716#[doc = "Vector reinterpret cast operation"]
42717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
42718#[inline]
42719#[cfg(target_endian = "big")]
42720#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42721#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42722#[cfg_attr(
42723 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42724 assert_instr(nop)
42725)]
42726#[target_feature(enable = "neon,fp16")]
42727#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42728pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
42729 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42730 unsafe {
42731 let ret_val: int16x4_t = transmute(a);
42732 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42733 }
42734}
42735#[doc = "Vector reinterpret cast operation"]
42736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
42737#[inline]
42738#[cfg(target_endian = "little")]
42739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42741#[cfg_attr(
42742 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42743 assert_instr(nop)
42744)]
42745#[target_feature(enable = "neon,fp16")]
42746#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42747pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
42748 unsafe { transmute(a) }
42749}
42750#[doc = "Vector reinterpret cast operation"]
42751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
42752#[inline]
42753#[cfg(target_endian = "big")]
42754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42755#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42756#[cfg_attr(
42757 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42758 assert_instr(nop)
42759)]
42760#[target_feature(enable = "neon,fp16")]
42761#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42762pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
42763 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42764 unsafe {
42765 let ret_val: int32x2_t = transmute(a);
42766 simd_shuffle!(ret_val, ret_val, [1, 0])
42767 }
42768}
42769#[doc = "Vector reinterpret cast operation"]
42770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
42771#[inline]
42772#[cfg(target_endian = "little")]
42773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42774#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42775#[cfg_attr(
42776 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42777 assert_instr(nop)
42778)]
42779#[target_feature(enable = "neon,fp16")]
42780#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42781pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
42782 unsafe { transmute(a) }
42783}
42784#[doc = "Vector reinterpret cast operation"]
42785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
42786#[inline]
42787#[cfg(target_endian = "big")]
42788#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42789#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42790#[cfg_attr(
42791 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42792 assert_instr(nop)
42793)]
42794#[target_feature(enable = "neon,fp16")]
42795#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42796pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
42797 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42798 unsafe { transmute(a) }
42799}
42800#[doc = "Vector reinterpret cast operation"]
42801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
42802#[inline]
42803#[cfg(target_endian = "little")]
42804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42805#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42806#[cfg_attr(
42807 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42808 assert_instr(nop)
42809)]
42810#[target_feature(enable = "neon,fp16")]
42811#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42812pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
42813 unsafe { transmute(a) }
42814}
42815#[doc = "Vector reinterpret cast operation"]
42816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
42817#[inline]
42818#[cfg(target_endian = "big")]
42819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42821#[cfg_attr(
42822 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42823 assert_instr(nop)
42824)]
42825#[target_feature(enable = "neon,fp16")]
42826#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42827pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
42828 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42829 unsafe {
42830 let ret_val: uint8x8_t = transmute(a);
42831 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42832 }
42833}
42834#[doc = "Vector reinterpret cast operation"]
42835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
42836#[inline]
42837#[cfg(target_endian = "little")]
42838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42839#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42840#[cfg_attr(
42841 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42842 assert_instr(nop)
42843)]
42844#[target_feature(enable = "neon,fp16")]
42845#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42846pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
42847 unsafe { transmute(a) }
42848}
42849#[doc = "Vector reinterpret cast operation"]
42850#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
42851#[inline]
42852#[cfg(target_endian = "big")]
42853#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42854#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42855#[cfg_attr(
42856 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42857 assert_instr(nop)
42858)]
42859#[target_feature(enable = "neon,fp16")]
42860#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42861pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
42862 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42863 unsafe {
42864 let ret_val: uint16x4_t = transmute(a);
42865 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42866 }
42867}
42868#[doc = "Vector reinterpret cast operation"]
42869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
42870#[inline]
42871#[cfg(target_endian = "little")]
42872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42873#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42874#[cfg_attr(
42875 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42876 assert_instr(nop)
42877)]
42878#[target_feature(enable = "neon,fp16")]
42879#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42880pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
42881 unsafe { transmute(a) }
42882}
42883#[doc = "Vector reinterpret cast operation"]
42884#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
42885#[inline]
42886#[cfg(target_endian = "big")]
42887#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42888#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42889#[cfg_attr(
42890 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42891 assert_instr(nop)
42892)]
42893#[target_feature(enable = "neon,fp16")]
42894#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42895pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
42896 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42897 unsafe {
42898 let ret_val: uint32x2_t = transmute(a);
42899 simd_shuffle!(ret_val, ret_val, [1, 0])
42900 }
42901}
42902#[doc = "Vector reinterpret cast operation"]
42903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
42904#[inline]
42905#[cfg(target_endian = "little")]
42906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42907#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42908#[cfg_attr(
42909 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42910 assert_instr(nop)
42911)]
42912#[target_feature(enable = "neon,fp16")]
42913#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42914pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
42915 unsafe { transmute(a) }
42916}
42917#[doc = "Vector reinterpret cast operation"]
42918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
42919#[inline]
42920#[cfg(target_endian = "big")]
42921#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42922#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42923#[cfg_attr(
42924 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42925 assert_instr(nop)
42926)]
42927#[target_feature(enable = "neon,fp16")]
42928#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42929pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
42930 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42931 unsafe { transmute(a) }
42932}
42933#[doc = "Vector reinterpret cast operation"]
42934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
42935#[inline]
42936#[cfg(target_endian = "little")]
42937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42938#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42939#[cfg_attr(
42940 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42941 assert_instr(nop)
42942)]
42943#[target_feature(enable = "neon,fp16")]
42944#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42945pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
42946 unsafe { transmute(a) }
42947}
42948#[doc = "Vector reinterpret cast operation"]
42949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
42950#[inline]
42951#[cfg(target_endian = "big")]
42952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42953#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42954#[cfg_attr(
42955 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42956 assert_instr(nop)
42957)]
42958#[target_feature(enable = "neon,fp16")]
42959#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42960pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
42961 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42962 unsafe {
42963 let ret_val: poly8x8_t = transmute(a);
42964 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42965 }
42966}
42967#[doc = "Vector reinterpret cast operation"]
42968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
42969#[inline]
42970#[cfg(target_endian = "little")]
42971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42972#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42973#[cfg_attr(
42974 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42975 assert_instr(nop)
42976)]
42977#[target_feature(enable = "neon,fp16")]
42978#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42979pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
42980 unsafe { transmute(a) }
42981}
42982#[doc = "Vector reinterpret cast operation"]
42983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
42984#[inline]
42985#[cfg(target_endian = "big")]
42986#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42987#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42988#[cfg_attr(
42989 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42990 assert_instr(nop)
42991)]
42992#[target_feature(enable = "neon,fp16")]
42993#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42994pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
42995 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42996 unsafe {
42997 let ret_val: poly16x4_t = transmute(a);
42998 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42999 }
43000}
43001#[doc = "Vector reinterpret cast operation"]
43002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
43003#[inline]
43004#[cfg(target_endian = "little")]
43005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43007#[cfg_attr(
43008 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43009 assert_instr(nop)
43010)]
43011#[target_feature(enable = "neon,fp16")]
43012#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43013pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
43014 unsafe { transmute(a) }
43015}
43016#[doc = "Vector reinterpret cast operation"]
43017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
43018#[inline]
43019#[cfg(target_endian = "big")]
43020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43021#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43022#[cfg_attr(
43023 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43024 assert_instr(nop)
43025)]
43026#[target_feature(enable = "neon,fp16")]
43027#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43028pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
43029 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43030 unsafe {
43031 let ret_val: float32x4_t = transmute(a);
43032 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43033 }
43034}
43035#[doc = "Vector reinterpret cast operation"]
43036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
43037#[inline]
43038#[cfg(target_endian = "little")]
43039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43041#[cfg_attr(
43042 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43043 assert_instr(nop)
43044)]
43045#[target_feature(enable = "neon,fp16")]
43046#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43047pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
43048 unsafe { transmute(a) }
43049}
43050#[doc = "Vector reinterpret cast operation"]
43051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
43052#[inline]
43053#[cfg(target_endian = "big")]
43054#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43055#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43056#[cfg_attr(
43057 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43058 assert_instr(nop)
43059)]
43060#[target_feature(enable = "neon,fp16")]
43061#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43062pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
43063 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43064 unsafe {
43065 let ret_val: int8x16_t = transmute(a);
43066 simd_shuffle!(
43067 ret_val,
43068 ret_val,
43069 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
43070 )
43071 }
43072}
43073#[doc = "Vector reinterpret cast operation"]
43074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
43075#[inline]
43076#[cfg(target_endian = "little")]
43077#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43078#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43079#[cfg_attr(
43080 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43081 assert_instr(nop)
43082)]
43083#[target_feature(enable = "neon,fp16")]
43084#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43085pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
43086 unsafe { transmute(a) }
43087}
43088#[doc = "Vector reinterpret cast operation"]
43089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
43090#[inline]
43091#[cfg(target_endian = "big")]
43092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43093#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43094#[cfg_attr(
43095 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43096 assert_instr(nop)
43097)]
43098#[target_feature(enable = "neon,fp16")]
43099#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43100pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
43101 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43102 unsafe {
43103 let ret_val: int16x8_t = transmute(a);
43104 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43105 }
43106}
43107#[doc = "Vector reinterpret cast operation"]
43108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
43109#[inline]
43110#[cfg(target_endian = "little")]
43111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43113#[cfg_attr(
43114 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43115 assert_instr(nop)
43116)]
43117#[target_feature(enable = "neon,fp16")]
43118#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43119pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
43120 unsafe { transmute(a) }
43121}
43122#[doc = "Vector reinterpret cast operation"]
43123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
43124#[inline]
43125#[cfg(target_endian = "big")]
43126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43127#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43128#[cfg_attr(
43129 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43130 assert_instr(nop)
43131)]
43132#[target_feature(enable = "neon,fp16")]
43133#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43134pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
43135 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43136 unsafe {
43137 let ret_val: int32x4_t = transmute(a);
43138 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43139 }
43140}
43141#[doc = "Vector reinterpret cast operation"]
43142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
43143#[inline]
43144#[cfg(target_endian = "little")]
43145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43146#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43147#[cfg_attr(
43148 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43149 assert_instr(nop)
43150)]
43151#[target_feature(enable = "neon,fp16")]
43152#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43153pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
43154 unsafe { transmute(a) }
43155}
43156#[doc = "Vector reinterpret cast operation"]
43157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
43158#[inline]
43159#[cfg(target_endian = "big")]
43160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43162#[cfg_attr(
43163 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43164 assert_instr(nop)
43165)]
43166#[target_feature(enable = "neon,fp16")]
43167#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43168pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
43169 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43170 unsafe {
43171 let ret_val: int64x2_t = transmute(a);
43172 simd_shuffle!(ret_val, ret_val, [1, 0])
43173 }
43174}
43175#[doc = "Vector reinterpret cast operation"]
43176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
43177#[inline]
43178#[cfg(target_endian = "little")]
43179#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43180#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43181#[cfg_attr(
43182 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43183 assert_instr(nop)
43184)]
43185#[target_feature(enable = "neon,fp16")]
43186#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43187pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
43188 unsafe { transmute(a) }
43189}
43190#[doc = "Vector reinterpret cast operation"]
43191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
43192#[inline]
43193#[cfg(target_endian = "big")]
43194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43195#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43196#[cfg_attr(
43197 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43198 assert_instr(nop)
43199)]
43200#[target_feature(enable = "neon,fp16")]
43201#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43202pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
43203 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43204 unsafe {
43205 let ret_val: uint8x16_t = transmute(a);
43206 simd_shuffle!(
43207 ret_val,
43208 ret_val,
43209 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
43210 )
43211 }
43212}
43213#[doc = "Vector reinterpret cast operation"]
43214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
43215#[inline]
43216#[cfg(target_endian = "little")]
43217#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43218#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43219#[cfg_attr(
43220 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43221 assert_instr(nop)
43222)]
43223#[target_feature(enable = "neon,fp16")]
43224#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43225pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
43226 unsafe { transmute(a) }
43227}
43228#[doc = "Vector reinterpret cast operation"]
43229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
43230#[inline]
43231#[cfg(target_endian = "big")]
43232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43233#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43234#[cfg_attr(
43235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43236 assert_instr(nop)
43237)]
43238#[target_feature(enable = "neon,fp16")]
43239#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43240pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
43241 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43242 unsafe {
43243 let ret_val: uint16x8_t = transmute(a);
43244 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43245 }
43246}
43247#[doc = "Vector reinterpret cast operation"]
43248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
43249#[inline]
43250#[cfg(target_endian = "little")]
43251#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43252#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43253#[cfg_attr(
43254 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43255 assert_instr(nop)
43256)]
43257#[target_feature(enable = "neon,fp16")]
43258#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43259pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
43260 unsafe { transmute(a) }
43261}
43262#[doc = "Vector reinterpret cast operation"]
43263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
43264#[inline]
43265#[cfg(target_endian = "big")]
43266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43267#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43268#[cfg_attr(
43269 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43270 assert_instr(nop)
43271)]
43272#[target_feature(enable = "neon,fp16")]
43273#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43274pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
43275 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43276 unsafe {
43277 let ret_val: uint32x4_t = transmute(a);
43278 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43279 }
43280}
43281#[doc = "Vector reinterpret cast operation"]
43282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
43283#[inline]
43284#[cfg(target_endian = "little")]
43285#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43286#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43287#[cfg_attr(
43288 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43289 assert_instr(nop)
43290)]
43291#[target_feature(enable = "neon,fp16")]
43292#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43293pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
43294 unsafe { transmute(a) }
43295}
43296#[doc = "Vector reinterpret cast operation"]
43297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
43298#[inline]
43299#[cfg(target_endian = "big")]
43300#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43301#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43302#[cfg_attr(
43303 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43304 assert_instr(nop)
43305)]
43306#[target_feature(enable = "neon,fp16")]
43307#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43308pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
43309 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43310 unsafe {
43311 let ret_val: uint64x2_t = transmute(a);
43312 simd_shuffle!(ret_val, ret_val, [1, 0])
43313 }
43314}
43315#[doc = "Vector reinterpret cast operation"]
43316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
43317#[inline]
43318#[cfg(target_endian = "little")]
43319#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43320#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43321#[cfg_attr(
43322 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43323 assert_instr(nop)
43324)]
43325#[target_feature(enable = "neon,fp16")]
43326#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43327pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
43328 unsafe { transmute(a) }
43329}
43330#[doc = "Vector reinterpret cast operation"]
43331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
43332#[inline]
43333#[cfg(target_endian = "big")]
43334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43335#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43336#[cfg_attr(
43337 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43338 assert_instr(nop)
43339)]
43340#[target_feature(enable = "neon,fp16")]
43341#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43342pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
43343 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43344 unsafe {
43345 let ret_val: poly8x16_t = transmute(a);
43346 simd_shuffle!(
43347 ret_val,
43348 ret_val,
43349 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
43350 )
43351 }
43352}
43353#[doc = "Vector reinterpret cast operation"]
43354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
43355#[inline]
43356#[cfg(target_endian = "little")]
43357#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43358#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43359#[cfg_attr(
43360 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43361 assert_instr(nop)
43362)]
43363#[target_feature(enable = "neon,fp16")]
43364#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43365pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
43366 unsafe { transmute(a) }
43367}
43368#[doc = "Vector reinterpret cast operation"]
43369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
43370#[inline]
43371#[cfg(target_endian = "big")]
43372#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43373#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43374#[cfg_attr(
43375 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43376 assert_instr(nop)
43377)]
43378#[target_feature(enable = "neon,fp16")]
43379#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43380pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
43381 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43382 unsafe {
43383 let ret_val: poly16x8_t = transmute(a);
43384 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43385 }
43386}
43387#[doc = "Vector reinterpret cast operation"]
43388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
43389#[inline]
43390#[cfg(target_endian = "little")]
43391#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43392#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43393#[cfg_attr(
43394 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43395 assert_instr(nop)
43396)]
43397#[target_feature(enable = "neon,fp16")]
43398#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43399pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
43400 unsafe { transmute(a) }
43401}
43402#[doc = "Vector reinterpret cast operation"]
43403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
43404#[inline]
43405#[cfg(target_endian = "big")]
43406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43408#[cfg_attr(
43409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43410 assert_instr(nop)
43411)]
43412#[target_feature(enable = "neon,fp16")]
43413#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43414pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
43415 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43416 unsafe {
43417 let ret_val: float16x4_t = transmute(a);
43418 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43419 }
43420}
43421#[doc = "Vector reinterpret cast operation"]
43422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
43423#[inline]
43424#[cfg(target_endian = "little")]
43425#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43426#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43427#[cfg_attr(
43428 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43429 assert_instr(nop)
43430)]
43431#[target_feature(enable = "neon,fp16")]
43432#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43433pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
43434 unsafe { transmute(a) }
43435}
43436#[doc = "Vector reinterpret cast operation"]
43437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
43438#[inline]
43439#[cfg(target_endian = "big")]
43440#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43441#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43442#[cfg_attr(
43443 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43444 assert_instr(nop)
43445)]
43446#[target_feature(enable = "neon,fp16")]
43447#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43448pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
43449 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43450 unsafe {
43451 let ret_val: float16x8_t = transmute(a);
43452 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43453 }
43454}
43455#[doc = "Vector reinterpret cast operation"]
43456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
43457#[inline]
43458#[cfg(target_endian = "little")]
43459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43461#[cfg_attr(
43462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43463 assert_instr(nop)
43464)]
43465#[target_feature(enable = "neon,fp16")]
43466#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43467pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
43468 unsafe { transmute(a) }
43469}
43470#[doc = "Vector reinterpret cast operation"]
43471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
43472#[inline]
43473#[cfg(target_endian = "big")]
43474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43475#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43476#[cfg_attr(
43477 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43478 assert_instr(nop)
43479)]
43480#[target_feature(enable = "neon,fp16")]
43481#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43482pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
43483 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43484 unsafe {
43485 let ret_val: float16x4_t = transmute(a);
43486 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43487 }
43488}
43489#[doc = "Vector reinterpret cast operation"]
43490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
43491#[inline]
43492#[cfg(target_endian = "little")]
43493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43494#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43495#[cfg_attr(
43496 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43497 assert_instr(nop)
43498)]
43499#[target_feature(enable = "neon,fp16")]
43500#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43501pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
43502 unsafe { transmute(a) }
43503}
43504#[doc = "Vector reinterpret cast operation"]
43505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
43506#[inline]
43507#[cfg(target_endian = "big")]
43508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43509#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43510#[cfg_attr(
43511 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43512 assert_instr(nop)
43513)]
43514#[target_feature(enable = "neon,fp16")]
43515#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43516pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
43517 let a: int8x16_t =
43518 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43519 unsafe {
43520 let ret_val: float16x8_t = transmute(a);
43521 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43522 }
43523}
43524#[doc = "Vector reinterpret cast operation"]
43525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
43526#[inline]
43527#[cfg(target_endian = "little")]
43528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43530#[cfg_attr(
43531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43532 assert_instr(nop)
43533)]
43534#[target_feature(enable = "neon,fp16")]
43535#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43536pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
43537 unsafe { transmute(a) }
43538}
43539#[doc = "Vector reinterpret cast operation"]
43540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
43541#[inline]
43542#[cfg(target_endian = "big")]
43543#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43544#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43545#[cfg_attr(
43546 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43547 assert_instr(nop)
43548)]
43549#[target_feature(enable = "neon,fp16")]
43550#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43551pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
43552 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43553 unsafe {
43554 let ret_val: float16x4_t = transmute(a);
43555 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43556 }
43557}
43558#[doc = "Vector reinterpret cast operation"]
43559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
43560#[inline]
43561#[cfg(target_endian = "little")]
43562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43564#[cfg_attr(
43565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43566 assert_instr(nop)
43567)]
43568#[target_feature(enable = "neon,fp16")]
43569#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43570pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
43571 unsafe { transmute(a) }
43572}
43573#[doc = "Vector reinterpret cast operation"]
43574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
43575#[inline]
43576#[cfg(target_endian = "big")]
43577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43579#[cfg_attr(
43580 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43581 assert_instr(nop)
43582)]
43583#[target_feature(enable = "neon,fp16")]
43584#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43585pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
43586 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43587 unsafe {
43588 let ret_val: float16x8_t = transmute(a);
43589 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43590 }
43591}
43592#[doc = "Vector reinterpret cast operation"]
43593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
43594#[inline]
43595#[cfg(target_endian = "little")]
43596#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43597#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43598#[cfg_attr(
43599 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43600 assert_instr(nop)
43601)]
43602#[target_feature(enable = "neon,fp16")]
43603#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43604pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
43605 unsafe { transmute(a) }
43606}
43607#[doc = "Vector reinterpret cast operation"]
43608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
43609#[inline]
43610#[cfg(target_endian = "big")]
43611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43612#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43613#[cfg_attr(
43614 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43615 assert_instr(nop)
43616)]
43617#[target_feature(enable = "neon,fp16")]
43618#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43619pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
43620 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43621 unsafe {
43622 let ret_val: float16x4_t = transmute(a);
43623 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43624 }
43625}
43626#[doc = "Vector reinterpret cast operation"]
43627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
43628#[inline]
43629#[cfg(target_endian = "little")]
43630#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43631#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43632#[cfg_attr(
43633 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43634 assert_instr(nop)
43635)]
43636#[target_feature(enable = "neon,fp16")]
43637#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43638pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
43639 unsafe { transmute(a) }
43640}
43641#[doc = "Vector reinterpret cast operation"]
43642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
43643#[inline]
43644#[cfg(target_endian = "big")]
43645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43646#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43647#[cfg_attr(
43648 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43649 assert_instr(nop)
43650)]
43651#[target_feature(enable = "neon,fp16")]
43652#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43653pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
43654 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43655 unsafe {
43656 let ret_val: float16x8_t = transmute(a);
43657 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43658 }
43659}
43660#[doc = "Vector reinterpret cast operation"]
43661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
43662#[inline]
43663#[cfg(target_endian = "little")]
43664#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43665#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43666#[cfg_attr(
43667 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43668 assert_instr(nop)
43669)]
43670#[target_feature(enable = "neon,fp16")]
43671#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43672pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
43673 unsafe { transmute(a) }
43674}
43675#[doc = "Vector reinterpret cast operation"]
43676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
43677#[inline]
43678#[cfg(target_endian = "big")]
43679#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43680#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43681#[cfg_attr(
43682 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43683 assert_instr(nop)
43684)]
43685#[target_feature(enable = "neon,fp16")]
43686#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43687pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
43688 unsafe {
43689 let ret_val: float16x4_t = transmute(a);
43690 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43691 }
43692}
43693#[doc = "Vector reinterpret cast operation"]
43694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
43695#[inline]
43696#[cfg(target_endian = "little")]
43697#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43698#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43699#[cfg_attr(
43700 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43701 assert_instr(nop)
43702)]
43703#[target_feature(enable = "neon,fp16")]
43704#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43705pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
43706 unsafe { transmute(a) }
43707}
43708#[doc = "Vector reinterpret cast operation"]
43709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
43710#[inline]
43711#[cfg(target_endian = "big")]
43712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43713#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43714#[cfg_attr(
43715 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43716 assert_instr(nop)
43717)]
43718#[target_feature(enable = "neon,fp16")]
43719#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43720pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
43721 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43722 unsafe {
43723 let ret_val: float16x8_t = transmute(a);
43724 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43725 }
43726}
43727#[doc = "Vector reinterpret cast operation"]
43728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
43729#[inline]
43730#[cfg(target_endian = "little")]
43731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43733#[cfg_attr(
43734 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43735 assert_instr(nop)
43736)]
43737#[target_feature(enable = "neon,fp16")]
43738#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43739pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
43740 unsafe { transmute(a) }
43741}
43742#[doc = "Vector reinterpret cast operation"]
43743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
43744#[inline]
43745#[cfg(target_endian = "big")]
43746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43747#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43748#[cfg_attr(
43749 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43750 assert_instr(nop)
43751)]
43752#[target_feature(enable = "neon,fp16")]
43753#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43754pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
43755 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43756 unsafe {
43757 let ret_val: float16x4_t = transmute(a);
43758 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43759 }
43760}
43761#[doc = "Vector reinterpret cast operation"]
43762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
43763#[inline]
43764#[cfg(target_endian = "little")]
43765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43766#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43767#[cfg_attr(
43768 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43769 assert_instr(nop)
43770)]
43771#[target_feature(enable = "neon,fp16")]
43772#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43773pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
43774 unsafe { transmute(a) }
43775}
43776#[doc = "Vector reinterpret cast operation"]
43777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
43778#[inline]
43779#[cfg(target_endian = "big")]
43780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43782#[cfg_attr(
43783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43784 assert_instr(nop)
43785)]
43786#[target_feature(enable = "neon,fp16")]
43787#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43788pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
43789 let a: uint8x16_t =
43790 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43791 unsafe {
43792 let ret_val: float16x8_t = transmute(a);
43793 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43794 }
43795}
43796#[doc = "Vector reinterpret cast operation"]
43797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
43798#[inline]
43799#[cfg(target_endian = "little")]
43800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43801#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43802#[cfg_attr(
43803 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43804 assert_instr(nop)
43805)]
43806#[target_feature(enable = "neon,fp16")]
43807#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43808pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
43809 unsafe { transmute(a) }
43810}
43811#[doc = "Vector reinterpret cast operation"]
43812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
43813#[inline]
43814#[cfg(target_endian = "big")]
43815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43817#[cfg_attr(
43818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43819 assert_instr(nop)
43820)]
43821#[target_feature(enable = "neon,fp16")]
43822#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43823pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
43824 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43825 unsafe {
43826 let ret_val: float16x4_t = transmute(a);
43827 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43828 }
43829}
43830#[doc = "Vector reinterpret cast operation"]
43831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
43832#[inline]
43833#[cfg(target_endian = "little")]
43834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43835#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43836#[cfg_attr(
43837 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43838 assert_instr(nop)
43839)]
43840#[target_feature(enable = "neon,fp16")]
43841#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43842pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
43843 unsafe { transmute(a) }
43844}
43845#[doc = "Vector reinterpret cast operation"]
43846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
43847#[inline]
43848#[cfg(target_endian = "big")]
43849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43850#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43851#[cfg_attr(
43852 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43853 assert_instr(nop)
43854)]
43855#[target_feature(enable = "neon,fp16")]
43856#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43857pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
43858 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43859 unsafe {
43860 let ret_val: float16x8_t = transmute(a);
43861 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43862 }
43863}
43864#[doc = "Vector reinterpret cast operation"]
43865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
43866#[inline]
43867#[cfg(target_endian = "little")]
43868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43869#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43870#[cfg_attr(
43871 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43872 assert_instr(nop)
43873)]
43874#[target_feature(enable = "neon,fp16")]
43875#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43876pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
43877 unsafe { transmute(a) }
43878}
43879#[doc = "Vector reinterpret cast operation"]
43880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
43881#[inline]
43882#[cfg(target_endian = "big")]
43883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43885#[cfg_attr(
43886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43887 assert_instr(nop)
43888)]
43889#[target_feature(enable = "neon,fp16")]
43890#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43891pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
43892 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43893 unsafe {
43894 let ret_val: float16x4_t = transmute(a);
43895 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43896 }
43897}
43898#[doc = "Vector reinterpret cast operation"]
43899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
43900#[inline]
43901#[cfg(target_endian = "little")]
43902#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43903#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43904#[cfg_attr(
43905 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43906 assert_instr(nop)
43907)]
43908#[target_feature(enable = "neon,fp16")]
43909#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43910pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
43911 unsafe { transmute(a) }
43912}
43913#[doc = "Vector reinterpret cast operation"]
43914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
43915#[inline]
43916#[cfg(target_endian = "big")]
43917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43918#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43919#[cfg_attr(
43920 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43921 assert_instr(nop)
43922)]
43923#[target_feature(enable = "neon,fp16")]
43924#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43925pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
43926 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43927 unsafe {
43928 let ret_val: float16x8_t = transmute(a);
43929 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43930 }
43931}
43932#[doc = "Vector reinterpret cast operation"]
43933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
43934#[inline]
43935#[cfg(target_endian = "little")]
43936#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43938#[cfg_attr(
43939 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43940 assert_instr(nop)
43941)]
43942#[target_feature(enable = "neon,fp16")]
43943#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43944pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
43945 unsafe { transmute(a) }
43946}
43947#[doc = "Vector reinterpret cast operation"]
43948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
43949#[inline]
43950#[cfg(target_endian = "big")]
43951#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43952#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43953#[cfg_attr(
43954 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43955 assert_instr(nop)
43956)]
43957#[target_feature(enable = "neon,fp16")]
43958#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43959pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
43960 unsafe {
43961 let ret_val: float16x4_t = transmute(a);
43962 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43963 }
43964}
43965#[doc = "Vector reinterpret cast operation"]
43966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
43967#[inline]
43968#[cfg(target_endian = "little")]
43969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43971#[cfg_attr(
43972 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43973 assert_instr(nop)
43974)]
43975#[target_feature(enable = "neon,fp16")]
43976#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43977pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
43978 unsafe { transmute(a) }
43979}
43980#[doc = "Vector reinterpret cast operation"]
43981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
43982#[inline]
43983#[cfg(target_endian = "big")]
43984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43986#[cfg_attr(
43987 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43988 assert_instr(nop)
43989)]
43990#[target_feature(enable = "neon,fp16")]
43991#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43992pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
43993 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43994 unsafe {
43995 let ret_val: float16x8_t = transmute(a);
43996 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43997 }
43998}
43999#[doc = "Vector reinterpret cast operation"]
44000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
44001#[inline]
44002#[cfg(target_endian = "little")]
44003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44005#[cfg_attr(
44006 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44007 assert_instr(nop)
44008)]
44009#[target_feature(enable = "neon,fp16")]
44010#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44011pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
44012 unsafe { transmute(a) }
44013}
44014#[doc = "Vector reinterpret cast operation"]
44015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
44016#[inline]
44017#[cfg(target_endian = "big")]
44018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44019#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44020#[cfg_attr(
44021 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44022 assert_instr(nop)
44023)]
44024#[target_feature(enable = "neon,fp16")]
44025#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44026pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
44027 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44028 unsafe {
44029 let ret_val: float16x4_t = transmute(a);
44030 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44031 }
44032}
44033#[doc = "Vector reinterpret cast operation"]
44034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
44035#[inline]
44036#[cfg(target_endian = "little")]
44037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44039#[cfg_attr(
44040 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44041 assert_instr(nop)
44042)]
44043#[target_feature(enable = "neon,fp16")]
44044#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44045pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
44046 unsafe { transmute(a) }
44047}
44048#[doc = "Vector reinterpret cast operation"]
44049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
44050#[inline]
44051#[cfg(target_endian = "big")]
44052#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44053#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44054#[cfg_attr(
44055 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44056 assert_instr(nop)
44057)]
44058#[target_feature(enable = "neon,fp16")]
44059#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44060pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
44061 let a: poly8x16_t =
44062 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
44063 unsafe {
44064 let ret_val: float16x8_t = transmute(a);
44065 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44066 }
44067}
44068#[doc = "Vector reinterpret cast operation"]
44069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
44070#[inline]
44071#[cfg(target_endian = "little")]
44072#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44073#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44074#[cfg_attr(
44075 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44076 assert_instr(nop)
44077)]
44078#[target_feature(enable = "neon,fp16")]
44079#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44080pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
44081 unsafe { transmute(a) }
44082}
44083#[doc = "Vector reinterpret cast operation"]
44084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
44085#[inline]
44086#[cfg(target_endian = "big")]
44087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44089#[cfg_attr(
44090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44091 assert_instr(nop)
44092)]
44093#[target_feature(enable = "neon,fp16")]
44094#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44095pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
44096 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44097 unsafe {
44098 let ret_val: float16x4_t = transmute(a);
44099 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44100 }
44101}
44102#[doc = "Vector reinterpret cast operation"]
44103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
44104#[inline]
44105#[cfg(target_endian = "little")]
44106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44108#[cfg_attr(
44109 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44110 assert_instr(nop)
44111)]
44112#[target_feature(enable = "neon,fp16")]
44113#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44114pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
44115 unsafe { transmute(a) }
44116}
44117#[doc = "Vector reinterpret cast operation"]
44118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
44119#[inline]
44120#[cfg(target_endian = "big")]
44121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44122#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44123#[cfg_attr(
44124 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44125 assert_instr(nop)
44126)]
44127#[target_feature(enable = "neon,fp16")]
44128#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44129pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
44130 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44131 unsafe {
44132 let ret_val: float16x8_t = transmute(a);
44133 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44134 }
44135}
44136#[doc = "Vector reinterpret cast operation"]
44137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
44138#[inline]
44139#[cfg(target_endian = "little")]
44140#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44142#[cfg_attr(
44143 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44144 assert_instr(nop)
44145)]
44146#[target_feature(enable = "neon,fp16")]
44147#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44148pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
44149 unsafe { transmute(a) }
44150}
44151#[doc = "Vector reinterpret cast operation"]
44152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
44153#[inline]
44154#[cfg(target_endian = "big")]
44155#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44156#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44157#[cfg_attr(
44158 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44159 assert_instr(nop)
44160)]
44161#[target_feature(enable = "neon,fp16")]
44162#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44163pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
44164 unsafe {
44165 let ret_val: float16x8_t = transmute(a);
44166 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44167 }
44168}
44169#[doc = "Vector reinterpret cast operation"]
44170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
44171#[inline]
44172#[cfg(target_endian = "little")]
44173#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44174#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44175#[cfg_attr(
44176 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44177 assert_instr(nop)
44178)]
44179#[target_feature(enable = "neon,fp16")]
44180#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44181pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
44182 unsafe { transmute(a) }
44183}
44184#[doc = "Vector reinterpret cast operation"]
44185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
44186#[inline]
44187#[cfg(target_endian = "big")]
44188#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44189#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44190#[cfg_attr(
44191 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44192 assert_instr(nop)
44193)]
44194#[target_feature(enable = "neon,fp16")]
44195#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44196pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
44197 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44198 unsafe { transmute(a) }
44199}
44200#[doc = "Vector reinterpret cast operation"]
44201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
44202#[inline]
44203#[cfg(target_endian = "little")]
44204#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44205#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44206#[cfg_attr(
44207 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44208 assert_instr(nop)
44209)]
44210#[target_feature(enable = "neon,fp16")]
44211#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44212pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
44213 unsafe { transmute(a) }
44214}
44215#[doc = "Vector reinterpret cast operation"]
44216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
44217#[inline]
44218#[cfg(target_endian = "big")]
44219#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44220#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44221#[cfg_attr(
44222 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44223 assert_instr(nop)
44224)]
44225#[target_feature(enable = "neon,fp16")]
44226#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44227pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
44228 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44229 unsafe { transmute(a) }
44230}
44231#[doc = "Vector reinterpret cast operation"]
44232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
44233#[inline]
44234#[cfg(target_endian = "little")]
44235#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44237#[cfg_attr(
44238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44239 assert_instr(nop)
44240)]
44241#[target_feature(enable = "neon,fp16")]
44242#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44243pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
44244 unsafe { transmute(a) }
44245}
44246#[doc = "Vector reinterpret cast operation"]
44247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
44248#[inline]
44249#[cfg(target_endian = "big")]
44250#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44251#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44252#[cfg_attr(
44253 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44254 assert_instr(nop)
44255)]
44256#[target_feature(enable = "neon,fp16")]
44257#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44258pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
44259 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44260 unsafe {
44261 let ret_val: poly64x2_t = transmute(a);
44262 simd_shuffle!(ret_val, ret_val, [1, 0])
44263 }
44264}
44265#[doc = "Vector reinterpret cast operation"]
44266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
44267#[inline]
44268#[cfg(target_endian = "little")]
44269#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44271#[cfg_attr(
44272 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44273 assert_instr(nop)
44274)]
44275#[target_feature(enable = "neon,fp16")]
44276#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44277pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
44278 unsafe { transmute(a) }
44279}
44280#[doc = "Vector reinterpret cast operation"]
44281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
44282#[inline]
44283#[cfg(target_endian = "big")]
44284#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44285#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44286#[cfg_attr(
44287 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44288 assert_instr(nop)
44289)]
44290#[target_feature(enable = "neon,fp16")]
44291#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44292pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
44293 unsafe {
44294 let ret_val: float16x4_t = transmute(a);
44295 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44296 }
44297}
44298#[doc = "Vector reinterpret cast operation"]
44299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
44300#[inline]
44301#[cfg(target_endian = "little")]
44302#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44303#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44304#[cfg_attr(
44305 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44306 assert_instr(nop)
44307)]
44308#[target_feature(enable = "neon,fp16")]
44309#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44310pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
44311 unsafe { transmute(a) }
44312}
44313#[doc = "Vector reinterpret cast operation"]
44314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
44315#[inline]
44316#[cfg(target_endian = "big")]
44317#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
44318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44319#[cfg_attr(
44320 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44321 assert_instr(nop)
44322)]
44323#[target_feature(enable = "neon,fp16")]
44324#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
44325pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
44326 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44327 unsafe {
44328 let ret_val: float16x8_t = transmute(a);
44329 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44330 }
44331}
44332#[doc = "Vector reinterpret cast operation"]
44333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
44334#[inline]
44335#[cfg(target_endian = "little")]
44336#[target_feature(enable = "neon")]
44337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44339#[cfg_attr(
44340 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44341 assert_instr(nop)
44342)]
44343#[cfg_attr(
44344 not(target_arch = "arm"),
44345 stable(feature = "neon_intrinsics", since = "1.59.0")
44346)]
44347#[cfg_attr(
44348 target_arch = "arm",
44349 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44350)]
44351pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
44352 unsafe { transmute(a) }
44353}
44354#[doc = "Vector reinterpret cast operation"]
44355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
44356#[inline]
44357#[cfg(target_endian = "big")]
44358#[target_feature(enable = "neon")]
44359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44360#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44361#[cfg_attr(
44362 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44363 assert_instr(nop)
44364)]
44365#[cfg_attr(
44366 not(target_arch = "arm"),
44367 stable(feature = "neon_intrinsics", since = "1.59.0")
44368)]
44369#[cfg_attr(
44370 target_arch = "arm",
44371 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44372)]
44373pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
44374 unsafe {
44375 let ret_val: float32x4_t = transmute(a);
44376 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44377 }
44378}
44379#[doc = "Vector reinterpret cast operation"]
44380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
44381#[inline]
44382#[cfg(target_endian = "little")]
44383#[target_feature(enable = "neon")]
44384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44386#[cfg_attr(
44387 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44388 assert_instr(nop)
44389)]
44390#[cfg_attr(
44391 not(target_arch = "arm"),
44392 stable(feature = "neon_intrinsics", since = "1.59.0")
44393)]
44394#[cfg_attr(
44395 target_arch = "arm",
44396 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44397)]
44398pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
44399 unsafe { transmute(a) }
44400}
44401#[doc = "Vector reinterpret cast operation"]
44402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
44403#[inline]
44404#[cfg(target_endian = "big")]
44405#[target_feature(enable = "neon")]
44406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44408#[cfg_attr(
44409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44410 assert_instr(nop)
44411)]
44412#[cfg_attr(
44413 not(target_arch = "arm"),
44414 stable(feature = "neon_intrinsics", since = "1.59.0")
44415)]
44416#[cfg_attr(
44417 target_arch = "arm",
44418 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44419)]
44420pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
44421 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44422 unsafe {
44423 let ret_val: int8x8_t = transmute(a);
44424 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44425 }
44426}
44427#[doc = "Vector reinterpret cast operation"]
44428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
44429#[inline]
44430#[cfg(target_endian = "little")]
44431#[target_feature(enable = "neon")]
44432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44433#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44434#[cfg_attr(
44435 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44436 assert_instr(nop)
44437)]
44438#[cfg_attr(
44439 not(target_arch = "arm"),
44440 stable(feature = "neon_intrinsics", since = "1.59.0")
44441)]
44442#[cfg_attr(
44443 target_arch = "arm",
44444 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44445)]
44446pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
44447 unsafe { transmute(a) }
44448}
44449#[doc = "Vector reinterpret cast operation"]
44450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
44451#[inline]
44452#[cfg(target_endian = "big")]
44453#[target_feature(enable = "neon")]
44454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44455#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44456#[cfg_attr(
44457 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44458 assert_instr(nop)
44459)]
44460#[cfg_attr(
44461 not(target_arch = "arm"),
44462 stable(feature = "neon_intrinsics", since = "1.59.0")
44463)]
44464#[cfg_attr(
44465 target_arch = "arm",
44466 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44467)]
44468pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
44469 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44470 unsafe {
44471 let ret_val: int16x4_t = transmute(a);
44472 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44473 }
44474}
44475#[doc = "Vector reinterpret cast operation"]
44476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
44477#[inline]
44478#[cfg(target_endian = "little")]
44479#[target_feature(enable = "neon")]
44480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44482#[cfg_attr(
44483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44484 assert_instr(nop)
44485)]
44486#[cfg_attr(
44487 not(target_arch = "arm"),
44488 stable(feature = "neon_intrinsics", since = "1.59.0")
44489)]
44490#[cfg_attr(
44491 target_arch = "arm",
44492 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44493)]
44494pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
44495 unsafe { transmute(a) }
44496}
44497#[doc = "Vector reinterpret cast operation"]
44498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
44499#[inline]
44500#[cfg(target_endian = "big")]
44501#[target_feature(enable = "neon")]
44502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44504#[cfg_attr(
44505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44506 assert_instr(nop)
44507)]
44508#[cfg_attr(
44509 not(target_arch = "arm"),
44510 stable(feature = "neon_intrinsics", since = "1.59.0")
44511)]
44512#[cfg_attr(
44513 target_arch = "arm",
44514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44515)]
44516pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
44517 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44518 unsafe {
44519 let ret_val: int32x2_t = transmute(a);
44520 simd_shuffle!(ret_val, ret_val, [1, 0])
44521 }
44522}
44523#[doc = "Vector reinterpret cast operation"]
44524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
44525#[inline]
44526#[cfg(target_endian = "little")]
44527#[target_feature(enable = "neon")]
44528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44530#[cfg_attr(
44531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44532 assert_instr(nop)
44533)]
44534#[cfg_attr(
44535 not(target_arch = "arm"),
44536 stable(feature = "neon_intrinsics", since = "1.59.0")
44537)]
44538#[cfg_attr(
44539 target_arch = "arm",
44540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44541)]
44542pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
44543 unsafe { transmute(a) }
44544}
44545#[doc = "Vector reinterpret cast operation"]
44546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
44547#[inline]
44548#[cfg(target_endian = "big")]
44549#[target_feature(enable = "neon")]
44550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44552#[cfg_attr(
44553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44554 assert_instr(nop)
44555)]
44556#[cfg_attr(
44557 not(target_arch = "arm"),
44558 stable(feature = "neon_intrinsics", since = "1.59.0")
44559)]
44560#[cfg_attr(
44561 target_arch = "arm",
44562 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44563)]
44564pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
44565 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44566 unsafe { transmute(a) }
44567}
44568#[doc = "Vector reinterpret cast operation"]
44569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
44570#[inline]
44571#[cfg(target_endian = "little")]
44572#[target_feature(enable = "neon")]
44573#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44574#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44575#[cfg_attr(
44576 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44577 assert_instr(nop)
44578)]
44579#[cfg_attr(
44580 not(target_arch = "arm"),
44581 stable(feature = "neon_intrinsics", since = "1.59.0")
44582)]
44583#[cfg_attr(
44584 target_arch = "arm",
44585 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44586)]
44587pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
44588 unsafe { transmute(a) }
44589}
44590#[doc = "Vector reinterpret cast operation"]
44591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
44592#[inline]
44593#[cfg(target_endian = "big")]
44594#[target_feature(enable = "neon")]
44595#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44596#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44597#[cfg_attr(
44598 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44599 assert_instr(nop)
44600)]
44601#[cfg_attr(
44602 not(target_arch = "arm"),
44603 stable(feature = "neon_intrinsics", since = "1.59.0")
44604)]
44605#[cfg_attr(
44606 target_arch = "arm",
44607 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44608)]
44609pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
44610 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44611 unsafe {
44612 let ret_val: uint8x8_t = transmute(a);
44613 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44614 }
44615}
44616#[doc = "Vector reinterpret cast operation"]
44617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
44618#[inline]
44619#[cfg(target_endian = "little")]
44620#[target_feature(enable = "neon")]
44621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44622#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44623#[cfg_attr(
44624 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44625 assert_instr(nop)
44626)]
44627#[cfg_attr(
44628 not(target_arch = "arm"),
44629 stable(feature = "neon_intrinsics", since = "1.59.0")
44630)]
44631#[cfg_attr(
44632 target_arch = "arm",
44633 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44634)]
44635pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
44636 unsafe { transmute(a) }
44637}
44638#[doc = "Vector reinterpret cast operation"]
44639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
44640#[inline]
44641#[cfg(target_endian = "big")]
44642#[target_feature(enable = "neon")]
44643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44645#[cfg_attr(
44646 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44647 assert_instr(nop)
44648)]
44649#[cfg_attr(
44650 not(target_arch = "arm"),
44651 stable(feature = "neon_intrinsics", since = "1.59.0")
44652)]
44653#[cfg_attr(
44654 target_arch = "arm",
44655 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44656)]
44657pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
44658 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44659 unsafe {
44660 let ret_val: uint16x4_t = transmute(a);
44661 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44662 }
44663}
44664#[doc = "Vector reinterpret cast operation"]
44665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
44666#[inline]
44667#[cfg(target_endian = "little")]
44668#[target_feature(enable = "neon")]
44669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44671#[cfg_attr(
44672 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44673 assert_instr(nop)
44674)]
44675#[cfg_attr(
44676 not(target_arch = "arm"),
44677 stable(feature = "neon_intrinsics", since = "1.59.0")
44678)]
44679#[cfg_attr(
44680 target_arch = "arm",
44681 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44682)]
44683pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
44684 unsafe { transmute(a) }
44685}
44686#[doc = "Vector reinterpret cast operation"]
44687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
44688#[inline]
44689#[cfg(target_endian = "big")]
44690#[target_feature(enable = "neon")]
44691#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44692#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44693#[cfg_attr(
44694 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44695 assert_instr(nop)
44696)]
44697#[cfg_attr(
44698 not(target_arch = "arm"),
44699 stable(feature = "neon_intrinsics", since = "1.59.0")
44700)]
44701#[cfg_attr(
44702 target_arch = "arm",
44703 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44704)]
44705pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
44706 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44707 unsafe {
44708 let ret_val: uint32x2_t = transmute(a);
44709 simd_shuffle!(ret_val, ret_val, [1, 0])
44710 }
44711}
44712#[doc = "Vector reinterpret cast operation"]
44713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
44714#[inline]
44715#[cfg(target_endian = "little")]
44716#[target_feature(enable = "neon")]
44717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44718#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44719#[cfg_attr(
44720 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44721 assert_instr(nop)
44722)]
44723#[cfg_attr(
44724 not(target_arch = "arm"),
44725 stable(feature = "neon_intrinsics", since = "1.59.0")
44726)]
44727#[cfg_attr(
44728 target_arch = "arm",
44729 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44730)]
44731pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
44732 unsafe { transmute(a) }
44733}
44734#[doc = "Vector reinterpret cast operation"]
44735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
44736#[inline]
44737#[cfg(target_endian = "big")]
44738#[target_feature(enable = "neon")]
44739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44741#[cfg_attr(
44742 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44743 assert_instr(nop)
44744)]
44745#[cfg_attr(
44746 not(target_arch = "arm"),
44747 stable(feature = "neon_intrinsics", since = "1.59.0")
44748)]
44749#[cfg_attr(
44750 target_arch = "arm",
44751 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44752)]
44753pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
44754 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44755 unsafe { transmute(a) }
44756}
44757#[doc = "Vector reinterpret cast operation"]
44758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
44759#[inline]
44760#[cfg(target_endian = "little")]
44761#[target_feature(enable = "neon")]
44762#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44763#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44764#[cfg_attr(
44765 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44766 assert_instr(nop)
44767)]
44768#[cfg_attr(
44769 not(target_arch = "arm"),
44770 stable(feature = "neon_intrinsics", since = "1.59.0")
44771)]
44772#[cfg_attr(
44773 target_arch = "arm",
44774 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44775)]
44776pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
44777 unsafe { transmute(a) }
44778}
44779#[doc = "Vector reinterpret cast operation"]
44780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
44781#[inline]
44782#[cfg(target_endian = "big")]
44783#[target_feature(enable = "neon")]
44784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44785#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44786#[cfg_attr(
44787 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44788 assert_instr(nop)
44789)]
44790#[cfg_attr(
44791 not(target_arch = "arm"),
44792 stable(feature = "neon_intrinsics", since = "1.59.0")
44793)]
44794#[cfg_attr(
44795 target_arch = "arm",
44796 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44797)]
44798pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
44799 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44800 unsafe {
44801 let ret_val: poly8x8_t = transmute(a);
44802 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44803 }
44804}
44805#[doc = "Vector reinterpret cast operation"]
44806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
44807#[inline]
44808#[cfg(target_endian = "little")]
44809#[target_feature(enable = "neon")]
44810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44812#[cfg_attr(
44813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44814 assert_instr(nop)
44815)]
44816#[cfg_attr(
44817 not(target_arch = "arm"),
44818 stable(feature = "neon_intrinsics", since = "1.59.0")
44819)]
44820#[cfg_attr(
44821 target_arch = "arm",
44822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44823)]
44824pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
44825 unsafe { transmute(a) }
44826}
44827#[doc = "Vector reinterpret cast operation"]
44828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
44829#[inline]
44830#[cfg(target_endian = "big")]
44831#[target_feature(enable = "neon")]
44832#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44833#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44834#[cfg_attr(
44835 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44836 assert_instr(nop)
44837)]
44838#[cfg_attr(
44839 not(target_arch = "arm"),
44840 stable(feature = "neon_intrinsics", since = "1.59.0")
44841)]
44842#[cfg_attr(
44843 target_arch = "arm",
44844 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44845)]
44846pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
44847 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44848 unsafe {
44849 let ret_val: poly16x4_t = transmute(a);
44850 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44851 }
44852}
44853#[doc = "Vector reinterpret cast operation"]
44854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
44855#[inline]
44856#[cfg(target_endian = "little")]
44857#[target_feature(enable = "neon")]
44858#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44859#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44860#[cfg_attr(
44861 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44862 assert_instr(nop)
44863)]
44864#[cfg_attr(
44865 not(target_arch = "arm"),
44866 stable(feature = "neon_intrinsics", since = "1.59.0")
44867)]
44868#[cfg_attr(
44869 target_arch = "arm",
44870 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44871)]
44872pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
44873 unsafe { transmute(a) }
44874}
44875#[doc = "Vector reinterpret cast operation"]
44876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
44877#[inline]
44878#[cfg(target_endian = "big")]
44879#[target_feature(enable = "neon")]
44880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44881#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44882#[cfg_attr(
44883 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44884 assert_instr(nop)
44885)]
44886#[cfg_attr(
44887 not(target_arch = "arm"),
44888 stable(feature = "neon_intrinsics", since = "1.59.0")
44889)]
44890#[cfg_attr(
44891 target_arch = "arm",
44892 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44893)]
44894pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
44895 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44896 unsafe { transmute(a) }
44897}
44898#[doc = "Vector reinterpret cast operation"]
44899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
44900#[inline]
44901#[cfg(target_endian = "little")]
44902#[target_feature(enable = "neon")]
44903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44904#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44905#[cfg_attr(
44906 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44907 assert_instr(nop)
44908)]
44909#[cfg_attr(
44910 not(target_arch = "arm"),
44911 stable(feature = "neon_intrinsics", since = "1.59.0")
44912)]
44913#[cfg_attr(
44914 target_arch = "arm",
44915 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44916)]
44917pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
44918 unsafe { transmute(a) }
44919}
44920#[doc = "Vector reinterpret cast operation"]
44921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
44922#[inline]
44923#[cfg(target_endian = "big")]
44924#[target_feature(enable = "neon")]
44925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44926#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44927#[cfg_attr(
44928 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44929 assert_instr(nop)
44930)]
44931#[cfg_attr(
44932 not(target_arch = "arm"),
44933 stable(feature = "neon_intrinsics", since = "1.59.0")
44934)]
44935#[cfg_attr(
44936 target_arch = "arm",
44937 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44938)]
44939pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
44940 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44941 unsafe {
44942 let ret_val: int8x16_t = transmute(a);
44943 simd_shuffle!(
44944 ret_val,
44945 ret_val,
44946 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
44947 )
44948 }
44949}
44950#[doc = "Vector reinterpret cast operation"]
44951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
44952#[inline]
44953#[cfg(target_endian = "little")]
44954#[target_feature(enable = "neon")]
44955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44957#[cfg_attr(
44958 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44959 assert_instr(nop)
44960)]
44961#[cfg_attr(
44962 not(target_arch = "arm"),
44963 stable(feature = "neon_intrinsics", since = "1.59.0")
44964)]
44965#[cfg_attr(
44966 target_arch = "arm",
44967 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44968)]
44969pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
44970 unsafe { transmute(a) }
44971}
44972#[doc = "Vector reinterpret cast operation"]
44973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
44974#[inline]
44975#[cfg(target_endian = "big")]
44976#[target_feature(enable = "neon")]
44977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44978#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44979#[cfg_attr(
44980 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44981 assert_instr(nop)
44982)]
44983#[cfg_attr(
44984 not(target_arch = "arm"),
44985 stable(feature = "neon_intrinsics", since = "1.59.0")
44986)]
44987#[cfg_attr(
44988 target_arch = "arm",
44989 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44990)]
44991pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
44992 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44993 unsafe {
44994 let ret_val: int16x8_t = transmute(a);
44995 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44996 }
44997}
44998#[doc = "Vector reinterpret cast operation"]
44999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
45000#[inline]
45001#[cfg(target_endian = "little")]
45002#[target_feature(enable = "neon")]
45003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45005#[cfg_attr(
45006 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45007 assert_instr(nop)
45008)]
45009#[cfg_attr(
45010 not(target_arch = "arm"),
45011 stable(feature = "neon_intrinsics", since = "1.59.0")
45012)]
45013#[cfg_attr(
45014 target_arch = "arm",
45015 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45016)]
45017pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
45018 unsafe { transmute(a) }
45019}
45020#[doc = "Vector reinterpret cast operation"]
45021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
45022#[inline]
45023#[cfg(target_endian = "big")]
45024#[target_feature(enable = "neon")]
45025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45027#[cfg_attr(
45028 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45029 assert_instr(nop)
45030)]
45031#[cfg_attr(
45032 not(target_arch = "arm"),
45033 stable(feature = "neon_intrinsics", since = "1.59.0")
45034)]
45035#[cfg_attr(
45036 target_arch = "arm",
45037 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45038)]
45039pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
45040 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45041 unsafe {
45042 let ret_val: int32x4_t = transmute(a);
45043 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45044 }
45045}
45046#[doc = "Vector reinterpret cast operation"]
45047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
45048#[inline]
45049#[cfg(target_endian = "little")]
45050#[target_feature(enable = "neon")]
45051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45053#[cfg_attr(
45054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45055 assert_instr(nop)
45056)]
45057#[cfg_attr(
45058 not(target_arch = "arm"),
45059 stable(feature = "neon_intrinsics", since = "1.59.0")
45060)]
45061#[cfg_attr(
45062 target_arch = "arm",
45063 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45064)]
45065pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
45066 unsafe { transmute(a) }
45067}
45068#[doc = "Vector reinterpret cast operation"]
45069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
45070#[inline]
45071#[cfg(target_endian = "big")]
45072#[target_feature(enable = "neon")]
45073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45074#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45075#[cfg_attr(
45076 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45077 assert_instr(nop)
45078)]
45079#[cfg_attr(
45080 not(target_arch = "arm"),
45081 stable(feature = "neon_intrinsics", since = "1.59.0")
45082)]
45083#[cfg_attr(
45084 target_arch = "arm",
45085 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45086)]
45087pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
45088 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45089 unsafe {
45090 let ret_val: int64x2_t = transmute(a);
45091 simd_shuffle!(ret_val, ret_val, [1, 0])
45092 }
45093}
45094#[doc = "Vector reinterpret cast operation"]
45095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
45096#[inline]
45097#[cfg(target_endian = "little")]
45098#[target_feature(enable = "neon")]
45099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45100#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45101#[cfg_attr(
45102 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45103 assert_instr(nop)
45104)]
45105#[cfg_attr(
45106 not(target_arch = "arm"),
45107 stable(feature = "neon_intrinsics", since = "1.59.0")
45108)]
45109#[cfg_attr(
45110 target_arch = "arm",
45111 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45112)]
45113pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
45114 unsafe { transmute(a) }
45115}
45116#[doc = "Vector reinterpret cast operation"]
45117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
45118#[inline]
45119#[cfg(target_endian = "big")]
45120#[target_feature(enable = "neon")]
45121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45122#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45123#[cfg_attr(
45124 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45125 assert_instr(nop)
45126)]
45127#[cfg_attr(
45128 not(target_arch = "arm"),
45129 stable(feature = "neon_intrinsics", since = "1.59.0")
45130)]
45131#[cfg_attr(
45132 target_arch = "arm",
45133 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45134)]
45135pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
45136 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45137 unsafe {
45138 let ret_val: uint8x16_t = transmute(a);
45139 simd_shuffle!(
45140 ret_val,
45141 ret_val,
45142 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
45143 )
45144 }
45145}
45146#[doc = "Vector reinterpret cast operation"]
45147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
45148#[inline]
45149#[cfg(target_endian = "little")]
45150#[target_feature(enable = "neon")]
45151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45153#[cfg_attr(
45154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45155 assert_instr(nop)
45156)]
45157#[cfg_attr(
45158 not(target_arch = "arm"),
45159 stable(feature = "neon_intrinsics", since = "1.59.0")
45160)]
45161#[cfg_attr(
45162 target_arch = "arm",
45163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45164)]
45165pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
45166 unsafe { transmute(a) }
45167}
45168#[doc = "Vector reinterpret cast operation"]
45169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
45170#[inline]
45171#[cfg(target_endian = "big")]
45172#[target_feature(enable = "neon")]
45173#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45174#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45175#[cfg_attr(
45176 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45177 assert_instr(nop)
45178)]
45179#[cfg_attr(
45180 not(target_arch = "arm"),
45181 stable(feature = "neon_intrinsics", since = "1.59.0")
45182)]
45183#[cfg_attr(
45184 target_arch = "arm",
45185 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45186)]
45187pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
45188 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45189 unsafe {
45190 let ret_val: uint16x8_t = transmute(a);
45191 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45192 }
45193}
45194#[doc = "Vector reinterpret cast operation"]
45195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
45196#[inline]
45197#[cfg(target_endian = "little")]
45198#[target_feature(enable = "neon")]
45199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45201#[cfg_attr(
45202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45203 assert_instr(nop)
45204)]
45205#[cfg_attr(
45206 not(target_arch = "arm"),
45207 stable(feature = "neon_intrinsics", since = "1.59.0")
45208)]
45209#[cfg_attr(
45210 target_arch = "arm",
45211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45212)]
45213pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
45214 unsafe { transmute(a) }
45215}
45216#[doc = "Vector reinterpret cast operation"]
45217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
45218#[inline]
45219#[cfg(target_endian = "big")]
45220#[target_feature(enable = "neon")]
45221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45223#[cfg_attr(
45224 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45225 assert_instr(nop)
45226)]
45227#[cfg_attr(
45228 not(target_arch = "arm"),
45229 stable(feature = "neon_intrinsics", since = "1.59.0")
45230)]
45231#[cfg_attr(
45232 target_arch = "arm",
45233 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45234)]
45235pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
45236 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45237 unsafe {
45238 let ret_val: uint32x4_t = transmute(a);
45239 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45240 }
45241}
45242#[doc = "Vector reinterpret cast operation"]
45243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
45244#[inline]
45245#[cfg(target_endian = "little")]
45246#[target_feature(enable = "neon")]
45247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45249#[cfg_attr(
45250 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45251 assert_instr(nop)
45252)]
45253#[cfg_attr(
45254 not(target_arch = "arm"),
45255 stable(feature = "neon_intrinsics", since = "1.59.0")
45256)]
45257#[cfg_attr(
45258 target_arch = "arm",
45259 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45260)]
45261pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
45262 unsafe { transmute(a) }
45263}
45264#[doc = "Vector reinterpret cast operation"]
45265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
45266#[inline]
45267#[cfg(target_endian = "big")]
45268#[target_feature(enable = "neon")]
45269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45271#[cfg_attr(
45272 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45273 assert_instr(nop)
45274)]
45275#[cfg_attr(
45276 not(target_arch = "arm"),
45277 stable(feature = "neon_intrinsics", since = "1.59.0")
45278)]
45279#[cfg_attr(
45280 target_arch = "arm",
45281 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45282)]
45283pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
45284 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45285 unsafe {
45286 let ret_val: uint64x2_t = transmute(a);
45287 simd_shuffle!(ret_val, ret_val, [1, 0])
45288 }
45289}
45290#[doc = "Vector reinterpret cast operation"]
45291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
45292#[inline]
45293#[cfg(target_endian = "little")]
45294#[target_feature(enable = "neon")]
45295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45297#[cfg_attr(
45298 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45299 assert_instr(nop)
45300)]
45301#[cfg_attr(
45302 not(target_arch = "arm"),
45303 stable(feature = "neon_intrinsics", since = "1.59.0")
45304)]
45305#[cfg_attr(
45306 target_arch = "arm",
45307 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45308)]
45309pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
45310 unsafe { transmute(a) }
45311}
45312#[doc = "Vector reinterpret cast operation"]
45313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
45314#[inline]
45315#[cfg(target_endian = "big")]
45316#[target_feature(enable = "neon")]
45317#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45319#[cfg_attr(
45320 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45321 assert_instr(nop)
45322)]
45323#[cfg_attr(
45324 not(target_arch = "arm"),
45325 stable(feature = "neon_intrinsics", since = "1.59.0")
45326)]
45327#[cfg_attr(
45328 target_arch = "arm",
45329 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45330)]
45331pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
45332 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45333 unsafe {
45334 let ret_val: poly8x16_t = transmute(a);
45335 simd_shuffle!(
45336 ret_val,
45337 ret_val,
45338 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
45339 )
45340 }
45341}
45342#[doc = "Vector reinterpret cast operation"]
45343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
45344#[inline]
45345#[cfg(target_endian = "little")]
45346#[target_feature(enable = "neon")]
45347#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45348#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45349#[cfg_attr(
45350 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45351 assert_instr(nop)
45352)]
45353#[cfg_attr(
45354 not(target_arch = "arm"),
45355 stable(feature = "neon_intrinsics", since = "1.59.0")
45356)]
45357#[cfg_attr(
45358 target_arch = "arm",
45359 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45360)]
45361pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
45362 unsafe { transmute(a) }
45363}
45364#[doc = "Vector reinterpret cast operation"]
45365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
45366#[inline]
45367#[cfg(target_endian = "big")]
45368#[target_feature(enable = "neon")]
45369#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45370#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45371#[cfg_attr(
45372 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45373 assert_instr(nop)
45374)]
45375#[cfg_attr(
45376 not(target_arch = "arm"),
45377 stable(feature = "neon_intrinsics", since = "1.59.0")
45378)]
45379#[cfg_attr(
45380 target_arch = "arm",
45381 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45382)]
45383pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
45384 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45385 unsafe {
45386 let ret_val: poly16x8_t = transmute(a);
45387 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45388 }
45389}
45390#[doc = "Vector reinterpret cast operation"]
45391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
45392#[inline]
45393#[cfg(target_endian = "little")]
45394#[target_feature(enable = "neon")]
45395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45396#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45397#[cfg_attr(
45398 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45399 assert_instr(nop)
45400)]
45401#[cfg_attr(
45402 not(target_arch = "arm"),
45403 stable(feature = "neon_intrinsics", since = "1.59.0")
45404)]
45405#[cfg_attr(
45406 target_arch = "arm",
45407 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45408)]
45409pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
45410 unsafe { transmute(a) }
45411}
45412#[doc = "Vector reinterpret cast operation"]
45413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
45414#[inline]
45415#[cfg(target_endian = "big")]
45416#[target_feature(enable = "neon")]
45417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45419#[cfg_attr(
45420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45421 assert_instr(nop)
45422)]
45423#[cfg_attr(
45424 not(target_arch = "arm"),
45425 stable(feature = "neon_intrinsics", since = "1.59.0")
45426)]
45427#[cfg_attr(
45428 target_arch = "arm",
45429 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45430)]
45431pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
45432 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45433 unsafe {
45434 let ret_val: float32x2_t = transmute(a);
45435 simd_shuffle!(ret_val, ret_val, [1, 0])
45436 }
45437}
45438#[doc = "Vector reinterpret cast operation"]
45439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
45440#[inline]
45441#[cfg(target_endian = "little")]
45442#[target_feature(enable = "neon")]
45443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45445#[cfg_attr(
45446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45447 assert_instr(nop)
45448)]
45449#[cfg_attr(
45450 not(target_arch = "arm"),
45451 stable(feature = "neon_intrinsics", since = "1.59.0")
45452)]
45453#[cfg_attr(
45454 target_arch = "arm",
45455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45456)]
45457pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
45458 unsafe { transmute(a) }
45459}
45460#[doc = "Vector reinterpret cast operation"]
45461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
45462#[inline]
45463#[cfg(target_endian = "big")]
45464#[target_feature(enable = "neon")]
45465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45467#[cfg_attr(
45468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45469 assert_instr(nop)
45470)]
45471#[cfg_attr(
45472 not(target_arch = "arm"),
45473 stable(feature = "neon_intrinsics", since = "1.59.0")
45474)]
45475#[cfg_attr(
45476 target_arch = "arm",
45477 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45478)]
45479pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
45480 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45481 unsafe {
45482 let ret_val: int16x4_t = transmute(a);
45483 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45484 }
45485}
45486#[doc = "Vector reinterpret cast operation"]
45487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
45488#[inline]
45489#[cfg(target_endian = "little")]
45490#[target_feature(enable = "neon")]
45491#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45492#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45493#[cfg_attr(
45494 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45495 assert_instr(nop)
45496)]
45497#[cfg_attr(
45498 not(target_arch = "arm"),
45499 stable(feature = "neon_intrinsics", since = "1.59.0")
45500)]
45501#[cfg_attr(
45502 target_arch = "arm",
45503 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45504)]
45505pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
45506 unsafe { transmute(a) }
45507}
45508#[doc = "Vector reinterpret cast operation"]
45509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
45510#[inline]
45511#[cfg(target_endian = "big")]
45512#[target_feature(enable = "neon")]
45513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45515#[cfg_attr(
45516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45517 assert_instr(nop)
45518)]
45519#[cfg_attr(
45520 not(target_arch = "arm"),
45521 stable(feature = "neon_intrinsics", since = "1.59.0")
45522)]
45523#[cfg_attr(
45524 target_arch = "arm",
45525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45526)]
45527pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
45528 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45529 unsafe {
45530 let ret_val: int32x2_t = transmute(a);
45531 simd_shuffle!(ret_val, ret_val, [1, 0])
45532 }
45533}
45534#[doc = "Vector reinterpret cast operation"]
45535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
45536#[inline]
45537#[cfg(target_endian = "little")]
45538#[target_feature(enable = "neon")]
45539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45540#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45541#[cfg_attr(
45542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45543 assert_instr(nop)
45544)]
45545#[cfg_attr(
45546 not(target_arch = "arm"),
45547 stable(feature = "neon_intrinsics", since = "1.59.0")
45548)]
45549#[cfg_attr(
45550 target_arch = "arm",
45551 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45552)]
45553pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
45554 unsafe { transmute(a) }
45555}
45556#[doc = "Vector reinterpret cast operation"]
45557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
45558#[inline]
45559#[cfg(target_endian = "big")]
45560#[target_feature(enable = "neon")]
45561#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45562#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45563#[cfg_attr(
45564 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45565 assert_instr(nop)
45566)]
45567#[cfg_attr(
45568 not(target_arch = "arm"),
45569 stable(feature = "neon_intrinsics", since = "1.59.0")
45570)]
45571#[cfg_attr(
45572 target_arch = "arm",
45573 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45574)]
45575pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
45576 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45577 unsafe { transmute(a) }
45578}
45579#[doc = "Vector reinterpret cast operation"]
45580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
45581#[inline]
45582#[cfg(target_endian = "little")]
45583#[target_feature(enable = "neon")]
45584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45585#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45586#[cfg_attr(
45587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45588 assert_instr(nop)
45589)]
45590#[cfg_attr(
45591 not(target_arch = "arm"),
45592 stable(feature = "neon_intrinsics", since = "1.59.0")
45593)]
45594#[cfg_attr(
45595 target_arch = "arm",
45596 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45597)]
45598pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
45599 unsafe { transmute(a) }
45600}
45601#[doc = "Vector reinterpret cast operation"]
45602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
45603#[inline]
45604#[cfg(target_endian = "big")]
45605#[target_feature(enable = "neon")]
45606#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45607#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45608#[cfg_attr(
45609 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45610 assert_instr(nop)
45611)]
45612#[cfg_attr(
45613 not(target_arch = "arm"),
45614 stable(feature = "neon_intrinsics", since = "1.59.0")
45615)]
45616#[cfg_attr(
45617 target_arch = "arm",
45618 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45619)]
45620pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
45621 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45622 unsafe {
45623 let ret_val: uint8x8_t = transmute(a);
45624 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45625 }
45626}
45627#[doc = "Vector reinterpret cast operation"]
45628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
45629#[inline]
45630#[cfg(target_endian = "little")]
45631#[target_feature(enable = "neon")]
45632#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45633#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45634#[cfg_attr(
45635 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45636 assert_instr(nop)
45637)]
45638#[cfg_attr(
45639 not(target_arch = "arm"),
45640 stable(feature = "neon_intrinsics", since = "1.59.0")
45641)]
45642#[cfg_attr(
45643 target_arch = "arm",
45644 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45645)]
45646pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
45647 unsafe { transmute(a) }
45648}
45649#[doc = "Vector reinterpret cast operation"]
45650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
45651#[inline]
45652#[cfg(target_endian = "big")]
45653#[target_feature(enable = "neon")]
45654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45655#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45656#[cfg_attr(
45657 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45658 assert_instr(nop)
45659)]
45660#[cfg_attr(
45661 not(target_arch = "arm"),
45662 stable(feature = "neon_intrinsics", since = "1.59.0")
45663)]
45664#[cfg_attr(
45665 target_arch = "arm",
45666 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45667)]
45668pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
45669 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45670 unsafe {
45671 let ret_val: uint16x4_t = transmute(a);
45672 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45673 }
45674}
45675#[doc = "Vector reinterpret cast operation"]
45676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
45677#[inline]
45678#[cfg(target_endian = "little")]
45679#[target_feature(enable = "neon")]
45680#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45681#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45682#[cfg_attr(
45683 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45684 assert_instr(nop)
45685)]
45686#[cfg_attr(
45687 not(target_arch = "arm"),
45688 stable(feature = "neon_intrinsics", since = "1.59.0")
45689)]
45690#[cfg_attr(
45691 target_arch = "arm",
45692 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45693)]
45694pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
45695 unsafe { transmute(a) }
45696}
45697#[doc = "Vector reinterpret cast operation"]
45698#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
45699#[inline]
45700#[cfg(target_endian = "big")]
45701#[target_feature(enable = "neon")]
45702#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45703#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45704#[cfg_attr(
45705 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45706 assert_instr(nop)
45707)]
45708#[cfg_attr(
45709 not(target_arch = "arm"),
45710 stable(feature = "neon_intrinsics", since = "1.59.0")
45711)]
45712#[cfg_attr(
45713 target_arch = "arm",
45714 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45715)]
45716pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
45717 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45718 unsafe {
45719 let ret_val: uint32x2_t = transmute(a);
45720 simd_shuffle!(ret_val, ret_val, [1, 0])
45721 }
45722}
45723#[doc = "Vector reinterpret cast operation"]
45724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
45725#[inline]
45726#[cfg(target_endian = "little")]
45727#[target_feature(enable = "neon")]
45728#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45729#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45730#[cfg_attr(
45731 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45732 assert_instr(nop)
45733)]
45734#[cfg_attr(
45735 not(target_arch = "arm"),
45736 stable(feature = "neon_intrinsics", since = "1.59.0")
45737)]
45738#[cfg_attr(
45739 target_arch = "arm",
45740 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45741)]
45742pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
45743 unsafe { transmute(a) }
45744}
45745#[doc = "Vector reinterpret cast operation"]
45746#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
45747#[inline]
45748#[cfg(target_endian = "big")]
45749#[target_feature(enable = "neon")]
45750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45751#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45752#[cfg_attr(
45753 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45754 assert_instr(nop)
45755)]
45756#[cfg_attr(
45757 not(target_arch = "arm"),
45758 stable(feature = "neon_intrinsics", since = "1.59.0")
45759)]
45760#[cfg_attr(
45761 target_arch = "arm",
45762 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45763)]
45764pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
45765 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45766 unsafe { transmute(a) }
45767}
45768#[doc = "Vector reinterpret cast operation"]
45769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
45770#[inline]
45771#[cfg(target_endian = "little")]
45772#[target_feature(enable = "neon")]
45773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45774#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45775#[cfg_attr(
45776 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45777 assert_instr(nop)
45778)]
45779#[cfg_attr(
45780 not(target_arch = "arm"),
45781 stable(feature = "neon_intrinsics", since = "1.59.0")
45782)]
45783#[cfg_attr(
45784 target_arch = "arm",
45785 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45786)]
45787pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
45788 unsafe { transmute(a) }
45789}
45790#[doc = "Vector reinterpret cast operation"]
45791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
45792#[inline]
45793#[cfg(target_endian = "big")]
45794#[target_feature(enable = "neon")]
45795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45796#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45797#[cfg_attr(
45798 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45799 assert_instr(nop)
45800)]
45801#[cfg_attr(
45802 not(target_arch = "arm"),
45803 stable(feature = "neon_intrinsics", since = "1.59.0")
45804)]
45805#[cfg_attr(
45806 target_arch = "arm",
45807 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45808)]
45809pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
45810 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45811 unsafe {
45812 let ret_val: poly8x8_t = transmute(a);
45813 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45814 }
45815}
45816#[doc = "Vector reinterpret cast operation"]
45817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
45818#[inline]
45819#[cfg(target_endian = "little")]
45820#[target_feature(enable = "neon")]
45821#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45822#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45823#[cfg_attr(
45824 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45825 assert_instr(nop)
45826)]
45827#[cfg_attr(
45828 not(target_arch = "arm"),
45829 stable(feature = "neon_intrinsics", since = "1.59.0")
45830)]
45831#[cfg_attr(
45832 target_arch = "arm",
45833 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45834)]
45835pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
45836 unsafe { transmute(a) }
45837}
45838#[doc = "Vector reinterpret cast operation"]
45839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
45840#[inline]
45841#[cfg(target_endian = "big")]
45842#[target_feature(enable = "neon")]
45843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45845#[cfg_attr(
45846 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45847 assert_instr(nop)
45848)]
45849#[cfg_attr(
45850 not(target_arch = "arm"),
45851 stable(feature = "neon_intrinsics", since = "1.59.0")
45852)]
45853#[cfg_attr(
45854 target_arch = "arm",
45855 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45856)]
45857pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
45858 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45859 unsafe {
45860 let ret_val: poly16x4_t = transmute(a);
45861 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45862 }
45863}
45864#[doc = "Vector reinterpret cast operation"]
45865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
45866#[inline]
45867#[cfg(target_endian = "little")]
45868#[target_feature(enable = "neon")]
45869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45870#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45871#[cfg_attr(
45872 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45873 assert_instr(nop)
45874)]
45875#[cfg_attr(
45876 not(target_arch = "arm"),
45877 stable(feature = "neon_intrinsics", since = "1.59.0")
45878)]
45879#[cfg_attr(
45880 target_arch = "arm",
45881 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45882)]
45883pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
45884 unsafe { transmute(a) }
45885}
45886#[doc = "Vector reinterpret cast operation"]
45887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
45888#[inline]
45889#[cfg(target_endian = "big")]
45890#[target_feature(enable = "neon")]
45891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45893#[cfg_attr(
45894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45895 assert_instr(nop)
45896)]
45897#[cfg_attr(
45898 not(target_arch = "arm"),
45899 stable(feature = "neon_intrinsics", since = "1.59.0")
45900)]
45901#[cfg_attr(
45902 target_arch = "arm",
45903 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45904)]
45905pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
45906 let a: int8x16_t =
45907 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45908 unsafe {
45909 let ret_val: float32x4_t = transmute(a);
45910 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45911 }
45912}
45913#[doc = "Vector reinterpret cast operation"]
45914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
45915#[inline]
45916#[cfg(target_endian = "little")]
45917#[target_feature(enable = "neon")]
45918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45919#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45920#[cfg_attr(
45921 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45922 assert_instr(nop)
45923)]
45924#[cfg_attr(
45925 not(target_arch = "arm"),
45926 stable(feature = "neon_intrinsics", since = "1.59.0")
45927)]
45928#[cfg_attr(
45929 target_arch = "arm",
45930 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45931)]
45932pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
45933 unsafe { transmute(a) }
45934}
45935#[doc = "Vector reinterpret cast operation"]
45936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
45937#[inline]
45938#[cfg(target_endian = "big")]
45939#[target_feature(enable = "neon")]
45940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45941#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45942#[cfg_attr(
45943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45944 assert_instr(nop)
45945)]
45946#[cfg_attr(
45947 not(target_arch = "arm"),
45948 stable(feature = "neon_intrinsics", since = "1.59.0")
45949)]
45950#[cfg_attr(
45951 target_arch = "arm",
45952 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45953)]
45954pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
45955 let a: int8x16_t =
45956 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45957 unsafe {
45958 let ret_val: int16x8_t = transmute(a);
45959 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45960 }
45961}
45962#[doc = "Vector reinterpret cast operation"]
45963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
45964#[inline]
45965#[cfg(target_endian = "little")]
45966#[target_feature(enable = "neon")]
45967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45969#[cfg_attr(
45970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45971 assert_instr(nop)
45972)]
45973#[cfg_attr(
45974 not(target_arch = "arm"),
45975 stable(feature = "neon_intrinsics", since = "1.59.0")
45976)]
45977#[cfg_attr(
45978 target_arch = "arm",
45979 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45980)]
45981pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
45982 unsafe { transmute(a) }
45983}
45984#[doc = "Vector reinterpret cast operation"]
45985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
45986#[inline]
45987#[cfg(target_endian = "big")]
45988#[target_feature(enable = "neon")]
45989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45991#[cfg_attr(
45992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45993 assert_instr(nop)
45994)]
45995#[cfg_attr(
45996 not(target_arch = "arm"),
45997 stable(feature = "neon_intrinsics", since = "1.59.0")
45998)]
45999#[cfg_attr(
46000 target_arch = "arm",
46001 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46002)]
46003pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
46004 let a: int8x16_t =
46005 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46006 unsafe {
46007 let ret_val: int32x4_t = transmute(a);
46008 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46009 }
46010}
46011#[doc = "Vector reinterpret cast operation"]
46012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
46013#[inline]
46014#[cfg(target_endian = "little")]
46015#[target_feature(enable = "neon")]
46016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46017#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46018#[cfg_attr(
46019 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46020 assert_instr(nop)
46021)]
46022#[cfg_attr(
46023 not(target_arch = "arm"),
46024 stable(feature = "neon_intrinsics", since = "1.59.0")
46025)]
46026#[cfg_attr(
46027 target_arch = "arm",
46028 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46029)]
46030pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
46031 unsafe { transmute(a) }
46032}
46033#[doc = "Vector reinterpret cast operation"]
46034#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
46035#[inline]
46036#[cfg(target_endian = "big")]
46037#[target_feature(enable = "neon")]
46038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46040#[cfg_attr(
46041 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46042 assert_instr(nop)
46043)]
46044#[cfg_attr(
46045 not(target_arch = "arm"),
46046 stable(feature = "neon_intrinsics", since = "1.59.0")
46047)]
46048#[cfg_attr(
46049 target_arch = "arm",
46050 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46051)]
46052pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
46053 let a: int8x16_t =
46054 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46055 unsafe {
46056 let ret_val: int64x2_t = transmute(a);
46057 simd_shuffle!(ret_val, ret_val, [1, 0])
46058 }
46059}
46060#[doc = "Vector reinterpret cast operation"]
46061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
46062#[inline]
46063#[cfg(target_endian = "little")]
46064#[target_feature(enable = "neon")]
46065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46067#[cfg_attr(
46068 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46069 assert_instr(nop)
46070)]
46071#[cfg_attr(
46072 not(target_arch = "arm"),
46073 stable(feature = "neon_intrinsics", since = "1.59.0")
46074)]
46075#[cfg_attr(
46076 target_arch = "arm",
46077 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46078)]
46079pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
46080 unsafe { transmute(a) }
46081}
46082#[doc = "Vector reinterpret cast operation"]
46083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
46084#[inline]
46085#[cfg(target_endian = "big")]
46086#[target_feature(enable = "neon")]
46087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46089#[cfg_attr(
46090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46091 assert_instr(nop)
46092)]
46093#[cfg_attr(
46094 not(target_arch = "arm"),
46095 stable(feature = "neon_intrinsics", since = "1.59.0")
46096)]
46097#[cfg_attr(
46098 target_arch = "arm",
46099 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46100)]
46101pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
46102 let a: int8x16_t =
46103 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46104 unsafe {
46105 let ret_val: uint8x16_t = transmute(a);
46106 simd_shuffle!(
46107 ret_val,
46108 ret_val,
46109 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46110 )
46111 }
46112}
46113#[doc = "Vector reinterpret cast operation"]
46114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
46115#[inline]
46116#[cfg(target_endian = "little")]
46117#[target_feature(enable = "neon")]
46118#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46119#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46120#[cfg_attr(
46121 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46122 assert_instr(nop)
46123)]
46124#[cfg_attr(
46125 not(target_arch = "arm"),
46126 stable(feature = "neon_intrinsics", since = "1.59.0")
46127)]
46128#[cfg_attr(
46129 target_arch = "arm",
46130 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46131)]
46132pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
46133 unsafe { transmute(a) }
46134}
46135#[doc = "Vector reinterpret cast operation"]
46136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
46137#[inline]
46138#[cfg(target_endian = "big")]
46139#[target_feature(enable = "neon")]
46140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46142#[cfg_attr(
46143 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46144 assert_instr(nop)
46145)]
46146#[cfg_attr(
46147 not(target_arch = "arm"),
46148 stable(feature = "neon_intrinsics", since = "1.59.0")
46149)]
46150#[cfg_attr(
46151 target_arch = "arm",
46152 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46153)]
46154pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
46155 let a: int8x16_t =
46156 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46157 unsafe {
46158 let ret_val: uint16x8_t = transmute(a);
46159 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46160 }
46161}
46162#[doc = "Vector reinterpret cast operation"]
46163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
46164#[inline]
46165#[cfg(target_endian = "little")]
46166#[target_feature(enable = "neon")]
46167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46168#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46169#[cfg_attr(
46170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46171 assert_instr(nop)
46172)]
46173#[cfg_attr(
46174 not(target_arch = "arm"),
46175 stable(feature = "neon_intrinsics", since = "1.59.0")
46176)]
46177#[cfg_attr(
46178 target_arch = "arm",
46179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46180)]
46181pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
46182 unsafe { transmute(a) }
46183}
46184#[doc = "Vector reinterpret cast operation"]
46185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
46186#[inline]
46187#[cfg(target_endian = "big")]
46188#[target_feature(enable = "neon")]
46189#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46190#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46191#[cfg_attr(
46192 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46193 assert_instr(nop)
46194)]
46195#[cfg_attr(
46196 not(target_arch = "arm"),
46197 stable(feature = "neon_intrinsics", since = "1.59.0")
46198)]
46199#[cfg_attr(
46200 target_arch = "arm",
46201 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46202)]
46203pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
46204 let a: int8x16_t =
46205 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46206 unsafe {
46207 let ret_val: uint32x4_t = transmute(a);
46208 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46209 }
46210}
46211#[doc = "Vector reinterpret cast operation"]
46212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
46213#[inline]
46214#[cfg(target_endian = "little")]
46215#[target_feature(enable = "neon")]
46216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46217#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46218#[cfg_attr(
46219 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46220 assert_instr(nop)
46221)]
46222#[cfg_attr(
46223 not(target_arch = "arm"),
46224 stable(feature = "neon_intrinsics", since = "1.59.0")
46225)]
46226#[cfg_attr(
46227 target_arch = "arm",
46228 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46229)]
46230pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
46231 unsafe { transmute(a) }
46232}
46233#[doc = "Vector reinterpret cast operation"]
46234#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
46235#[inline]
46236#[cfg(target_endian = "big")]
46237#[target_feature(enable = "neon")]
46238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46239#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46240#[cfg_attr(
46241 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46242 assert_instr(nop)
46243)]
46244#[cfg_attr(
46245 not(target_arch = "arm"),
46246 stable(feature = "neon_intrinsics", since = "1.59.0")
46247)]
46248#[cfg_attr(
46249 target_arch = "arm",
46250 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46251)]
46252pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
46253 let a: int8x16_t =
46254 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46255 unsafe {
46256 let ret_val: uint64x2_t = transmute(a);
46257 simd_shuffle!(ret_val, ret_val, [1, 0])
46258 }
46259}
46260#[doc = "Vector reinterpret cast operation"]
46261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
46262#[inline]
46263#[cfg(target_endian = "little")]
46264#[target_feature(enable = "neon")]
46265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46267#[cfg_attr(
46268 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46269 assert_instr(nop)
46270)]
46271#[cfg_attr(
46272 not(target_arch = "arm"),
46273 stable(feature = "neon_intrinsics", since = "1.59.0")
46274)]
46275#[cfg_attr(
46276 target_arch = "arm",
46277 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46278)]
46279pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
46280 unsafe { transmute(a) }
46281}
46282#[doc = "Vector reinterpret cast operation"]
46283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
46284#[inline]
46285#[cfg(target_endian = "big")]
46286#[target_feature(enable = "neon")]
46287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46288#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46289#[cfg_attr(
46290 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46291 assert_instr(nop)
46292)]
46293#[cfg_attr(
46294 not(target_arch = "arm"),
46295 stable(feature = "neon_intrinsics", since = "1.59.0")
46296)]
46297#[cfg_attr(
46298 target_arch = "arm",
46299 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46300)]
46301pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
46302 let a: int8x16_t =
46303 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46304 unsafe {
46305 let ret_val: poly8x16_t = transmute(a);
46306 simd_shuffle!(
46307 ret_val,
46308 ret_val,
46309 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46310 )
46311 }
46312}
46313#[doc = "Vector reinterpret cast operation"]
46314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
46315#[inline]
46316#[cfg(target_endian = "little")]
46317#[target_feature(enable = "neon")]
46318#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46319#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46320#[cfg_attr(
46321 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46322 assert_instr(nop)
46323)]
46324#[cfg_attr(
46325 not(target_arch = "arm"),
46326 stable(feature = "neon_intrinsics", since = "1.59.0")
46327)]
46328#[cfg_attr(
46329 target_arch = "arm",
46330 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46331)]
46332pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
46333 unsafe { transmute(a) }
46334}
46335#[doc = "Vector reinterpret cast operation"]
46336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
46337#[inline]
46338#[cfg(target_endian = "big")]
46339#[target_feature(enable = "neon")]
46340#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46341#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46342#[cfg_attr(
46343 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46344 assert_instr(nop)
46345)]
46346#[cfg_attr(
46347 not(target_arch = "arm"),
46348 stable(feature = "neon_intrinsics", since = "1.59.0")
46349)]
46350#[cfg_attr(
46351 target_arch = "arm",
46352 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46353)]
46354pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
46355 let a: int8x16_t =
46356 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
46357 unsafe {
46358 let ret_val: poly16x8_t = transmute(a);
46359 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46360 }
46361}
46362#[doc = "Vector reinterpret cast operation"]
46363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
46364#[inline]
46365#[cfg(target_endian = "little")]
46366#[target_feature(enable = "neon")]
46367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46369#[cfg_attr(
46370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46371 assert_instr(nop)
46372)]
46373#[cfg_attr(
46374 not(target_arch = "arm"),
46375 stable(feature = "neon_intrinsics", since = "1.59.0")
46376)]
46377#[cfg_attr(
46378 target_arch = "arm",
46379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46380)]
46381pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
46382 unsafe { transmute(a) }
46383}
46384#[doc = "Vector reinterpret cast operation"]
46385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
46386#[inline]
46387#[cfg(target_endian = "big")]
46388#[target_feature(enable = "neon")]
46389#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46390#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46391#[cfg_attr(
46392 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46393 assert_instr(nop)
46394)]
46395#[cfg_attr(
46396 not(target_arch = "arm"),
46397 stable(feature = "neon_intrinsics", since = "1.59.0")
46398)]
46399#[cfg_attr(
46400 target_arch = "arm",
46401 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46402)]
46403pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
46404 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46405 unsafe {
46406 let ret_val: float32x2_t = transmute(a);
46407 simd_shuffle!(ret_val, ret_val, [1, 0])
46408 }
46409}
46410#[doc = "Vector reinterpret cast operation"]
46411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
46412#[inline]
46413#[cfg(target_endian = "little")]
46414#[target_feature(enable = "neon")]
46415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46417#[cfg_attr(
46418 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46419 assert_instr(nop)
46420)]
46421#[cfg_attr(
46422 not(target_arch = "arm"),
46423 stable(feature = "neon_intrinsics", since = "1.59.0")
46424)]
46425#[cfg_attr(
46426 target_arch = "arm",
46427 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46428)]
46429pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
46430 unsafe { transmute(a) }
46431}
46432#[doc = "Vector reinterpret cast operation"]
46433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
46434#[inline]
46435#[cfg(target_endian = "big")]
46436#[target_feature(enable = "neon")]
46437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46438#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46439#[cfg_attr(
46440 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46441 assert_instr(nop)
46442)]
46443#[cfg_attr(
46444 not(target_arch = "arm"),
46445 stable(feature = "neon_intrinsics", since = "1.59.0")
46446)]
46447#[cfg_attr(
46448 target_arch = "arm",
46449 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46450)]
46451pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
46452 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46453 unsafe {
46454 let ret_val: int8x8_t = transmute(a);
46455 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46456 }
46457}
46458#[doc = "Vector reinterpret cast operation"]
46459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
46460#[inline]
46461#[cfg(target_endian = "little")]
46462#[target_feature(enable = "neon")]
46463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46465#[cfg_attr(
46466 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46467 assert_instr(nop)
46468)]
46469#[cfg_attr(
46470 not(target_arch = "arm"),
46471 stable(feature = "neon_intrinsics", since = "1.59.0")
46472)]
46473#[cfg_attr(
46474 target_arch = "arm",
46475 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46476)]
46477pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
46478 unsafe { transmute(a) }
46479}
46480#[doc = "Vector reinterpret cast operation"]
46481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
46482#[inline]
46483#[cfg(target_endian = "big")]
46484#[target_feature(enable = "neon")]
46485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46486#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46487#[cfg_attr(
46488 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46489 assert_instr(nop)
46490)]
46491#[cfg_attr(
46492 not(target_arch = "arm"),
46493 stable(feature = "neon_intrinsics", since = "1.59.0")
46494)]
46495#[cfg_attr(
46496 target_arch = "arm",
46497 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46498)]
46499pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
46500 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46501 unsafe {
46502 let ret_val: int32x2_t = transmute(a);
46503 simd_shuffle!(ret_val, ret_val, [1, 0])
46504 }
46505}
46506#[doc = "Vector reinterpret cast operation"]
46507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
46508#[inline]
46509#[cfg(target_endian = "little")]
46510#[target_feature(enable = "neon")]
46511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46513#[cfg_attr(
46514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46515 assert_instr(nop)
46516)]
46517#[cfg_attr(
46518 not(target_arch = "arm"),
46519 stable(feature = "neon_intrinsics", since = "1.59.0")
46520)]
46521#[cfg_attr(
46522 target_arch = "arm",
46523 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46524)]
46525pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
46526 unsafe { transmute(a) }
46527}
46528#[doc = "Vector reinterpret cast operation"]
46529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
46530#[inline]
46531#[cfg(target_endian = "big")]
46532#[target_feature(enable = "neon")]
46533#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46534#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46535#[cfg_attr(
46536 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46537 assert_instr(nop)
46538)]
46539#[cfg_attr(
46540 not(target_arch = "arm"),
46541 stable(feature = "neon_intrinsics", since = "1.59.0")
46542)]
46543#[cfg_attr(
46544 target_arch = "arm",
46545 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46546)]
46547pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
46548 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46549 unsafe { transmute(a) }
46550}
46551#[doc = "Vector reinterpret cast operation"]
46552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
46553#[inline]
46554#[cfg(target_endian = "little")]
46555#[target_feature(enable = "neon")]
46556#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46558#[cfg_attr(
46559 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46560 assert_instr(nop)
46561)]
46562#[cfg_attr(
46563 not(target_arch = "arm"),
46564 stable(feature = "neon_intrinsics", since = "1.59.0")
46565)]
46566#[cfg_attr(
46567 target_arch = "arm",
46568 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46569)]
46570pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
46571 unsafe { transmute(a) }
46572}
46573#[doc = "Vector reinterpret cast operation"]
46574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
46575#[inline]
46576#[cfg(target_endian = "big")]
46577#[target_feature(enable = "neon")]
46578#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46579#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46580#[cfg_attr(
46581 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46582 assert_instr(nop)
46583)]
46584#[cfg_attr(
46585 not(target_arch = "arm"),
46586 stable(feature = "neon_intrinsics", since = "1.59.0")
46587)]
46588#[cfg_attr(
46589 target_arch = "arm",
46590 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46591)]
46592pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
46593 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46594 unsafe {
46595 let ret_val: uint8x8_t = transmute(a);
46596 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46597 }
46598}
46599#[doc = "Vector reinterpret cast operation"]
46600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
46601#[inline]
46602#[cfg(target_endian = "little")]
46603#[target_feature(enable = "neon")]
46604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46606#[cfg_attr(
46607 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46608 assert_instr(nop)
46609)]
46610#[cfg_attr(
46611 not(target_arch = "arm"),
46612 stable(feature = "neon_intrinsics", since = "1.59.0")
46613)]
46614#[cfg_attr(
46615 target_arch = "arm",
46616 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46617)]
46618pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
46619 unsafe { transmute(a) }
46620}
46621#[doc = "Vector reinterpret cast operation"]
46622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
46623#[inline]
46624#[cfg(target_endian = "big")]
46625#[target_feature(enable = "neon")]
46626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46627#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46628#[cfg_attr(
46629 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46630 assert_instr(nop)
46631)]
46632#[cfg_attr(
46633 not(target_arch = "arm"),
46634 stable(feature = "neon_intrinsics", since = "1.59.0")
46635)]
46636#[cfg_attr(
46637 target_arch = "arm",
46638 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46639)]
46640pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
46641 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46642 unsafe {
46643 let ret_val: uint16x4_t = transmute(a);
46644 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46645 }
46646}
46647#[doc = "Vector reinterpret cast operation"]
46648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
46649#[inline]
46650#[cfg(target_endian = "little")]
46651#[target_feature(enable = "neon")]
46652#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46653#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46654#[cfg_attr(
46655 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46656 assert_instr(nop)
46657)]
46658#[cfg_attr(
46659 not(target_arch = "arm"),
46660 stable(feature = "neon_intrinsics", since = "1.59.0")
46661)]
46662#[cfg_attr(
46663 target_arch = "arm",
46664 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46665)]
46666pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
46667 unsafe { transmute(a) }
46668}
46669#[doc = "Vector reinterpret cast operation"]
46670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
46671#[inline]
46672#[cfg(target_endian = "big")]
46673#[target_feature(enable = "neon")]
46674#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46675#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46676#[cfg_attr(
46677 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46678 assert_instr(nop)
46679)]
46680#[cfg_attr(
46681 not(target_arch = "arm"),
46682 stable(feature = "neon_intrinsics", since = "1.59.0")
46683)]
46684#[cfg_attr(
46685 target_arch = "arm",
46686 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46687)]
46688pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
46689 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46690 unsafe {
46691 let ret_val: uint32x2_t = transmute(a);
46692 simd_shuffle!(ret_val, ret_val, [1, 0])
46693 }
46694}
46695#[doc = "Vector reinterpret cast operation"]
46696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
46697#[inline]
46698#[cfg(target_endian = "little")]
46699#[target_feature(enable = "neon")]
46700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46701#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46702#[cfg_attr(
46703 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46704 assert_instr(nop)
46705)]
46706#[cfg_attr(
46707 not(target_arch = "arm"),
46708 stable(feature = "neon_intrinsics", since = "1.59.0")
46709)]
46710#[cfg_attr(
46711 target_arch = "arm",
46712 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46713)]
46714pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
46715 unsafe { transmute(a) }
46716}
46717#[doc = "Vector reinterpret cast operation"]
46718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
46719#[inline]
46720#[cfg(target_endian = "big")]
46721#[target_feature(enable = "neon")]
46722#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46723#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46724#[cfg_attr(
46725 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46726 assert_instr(nop)
46727)]
46728#[cfg_attr(
46729 not(target_arch = "arm"),
46730 stable(feature = "neon_intrinsics", since = "1.59.0")
46731)]
46732#[cfg_attr(
46733 target_arch = "arm",
46734 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46735)]
46736pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
46737 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46738 unsafe { transmute(a) }
46739}
46740#[doc = "Vector reinterpret cast operation"]
46741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
46742#[inline]
46743#[cfg(target_endian = "little")]
46744#[target_feature(enable = "neon")]
46745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46746#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46747#[cfg_attr(
46748 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46749 assert_instr(nop)
46750)]
46751#[cfg_attr(
46752 not(target_arch = "arm"),
46753 stable(feature = "neon_intrinsics", since = "1.59.0")
46754)]
46755#[cfg_attr(
46756 target_arch = "arm",
46757 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46758)]
46759pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
46760 unsafe { transmute(a) }
46761}
46762#[doc = "Vector reinterpret cast operation"]
46763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
46764#[inline]
46765#[cfg(target_endian = "big")]
46766#[target_feature(enable = "neon")]
46767#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46768#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46769#[cfg_attr(
46770 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46771 assert_instr(nop)
46772)]
46773#[cfg_attr(
46774 not(target_arch = "arm"),
46775 stable(feature = "neon_intrinsics", since = "1.59.0")
46776)]
46777#[cfg_attr(
46778 target_arch = "arm",
46779 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46780)]
46781pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
46782 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46783 unsafe {
46784 let ret_val: poly8x8_t = transmute(a);
46785 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46786 }
46787}
46788#[doc = "Vector reinterpret cast operation"]
46789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
46790#[inline]
46791#[cfg(target_endian = "little")]
46792#[target_feature(enable = "neon")]
46793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46795#[cfg_attr(
46796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46797 assert_instr(nop)
46798)]
46799#[cfg_attr(
46800 not(target_arch = "arm"),
46801 stable(feature = "neon_intrinsics", since = "1.59.0")
46802)]
46803#[cfg_attr(
46804 target_arch = "arm",
46805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46806)]
46807pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
46808 unsafe { transmute(a) }
46809}
46810#[doc = "Vector reinterpret cast operation"]
46811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
46812#[inline]
46813#[cfg(target_endian = "big")]
46814#[target_feature(enable = "neon")]
46815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46817#[cfg_attr(
46818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46819 assert_instr(nop)
46820)]
46821#[cfg_attr(
46822 not(target_arch = "arm"),
46823 stable(feature = "neon_intrinsics", since = "1.59.0")
46824)]
46825#[cfg_attr(
46826 target_arch = "arm",
46827 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46828)]
46829pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
46830 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46831 unsafe {
46832 let ret_val: poly16x4_t = transmute(a);
46833 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46834 }
46835}
46836#[doc = "Vector reinterpret cast operation"]
46837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
46838#[inline]
46839#[cfg(target_endian = "little")]
46840#[target_feature(enable = "neon")]
46841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46842#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46843#[cfg_attr(
46844 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46845 assert_instr(nop)
46846)]
46847#[cfg_attr(
46848 not(target_arch = "arm"),
46849 stable(feature = "neon_intrinsics", since = "1.59.0")
46850)]
46851#[cfg_attr(
46852 target_arch = "arm",
46853 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46854)]
46855pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
46856 unsafe { transmute(a) }
46857}
46858#[doc = "Vector reinterpret cast operation"]
46859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
46860#[inline]
46861#[cfg(target_endian = "big")]
46862#[target_feature(enable = "neon")]
46863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46864#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46865#[cfg_attr(
46866 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46867 assert_instr(nop)
46868)]
46869#[cfg_attr(
46870 not(target_arch = "arm"),
46871 stable(feature = "neon_intrinsics", since = "1.59.0")
46872)]
46873#[cfg_attr(
46874 target_arch = "arm",
46875 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46876)]
46877pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
46878 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46879 unsafe {
46880 let ret_val: float32x4_t = transmute(a);
46881 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46882 }
46883}
46884#[doc = "Vector reinterpret cast operation"]
46885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
46886#[inline]
46887#[cfg(target_endian = "little")]
46888#[target_feature(enable = "neon")]
46889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46890#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46891#[cfg_attr(
46892 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46893 assert_instr(nop)
46894)]
46895#[cfg_attr(
46896 not(target_arch = "arm"),
46897 stable(feature = "neon_intrinsics", since = "1.59.0")
46898)]
46899#[cfg_attr(
46900 target_arch = "arm",
46901 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46902)]
46903pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
46904 unsafe { transmute(a) }
46905}
46906#[doc = "Vector reinterpret cast operation"]
46907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
46908#[inline]
46909#[cfg(target_endian = "big")]
46910#[target_feature(enable = "neon")]
46911#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46912#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46913#[cfg_attr(
46914 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46915 assert_instr(nop)
46916)]
46917#[cfg_attr(
46918 not(target_arch = "arm"),
46919 stable(feature = "neon_intrinsics", since = "1.59.0")
46920)]
46921#[cfg_attr(
46922 target_arch = "arm",
46923 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46924)]
46925pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
46926 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46927 unsafe {
46928 let ret_val: int8x16_t = transmute(a);
46929 simd_shuffle!(
46930 ret_val,
46931 ret_val,
46932 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46933 )
46934 }
46935}
46936#[doc = "Vector reinterpret cast operation"]
46937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
46938#[inline]
46939#[cfg(target_endian = "little")]
46940#[target_feature(enable = "neon")]
46941#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46942#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46943#[cfg_attr(
46944 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46945 assert_instr(nop)
46946)]
46947#[cfg_attr(
46948 not(target_arch = "arm"),
46949 stable(feature = "neon_intrinsics", since = "1.59.0")
46950)]
46951#[cfg_attr(
46952 target_arch = "arm",
46953 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46954)]
46955pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
46956 unsafe { transmute(a) }
46957}
46958#[doc = "Vector reinterpret cast operation"]
46959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
46960#[inline]
46961#[cfg(target_endian = "big")]
46962#[target_feature(enable = "neon")]
46963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46964#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46965#[cfg_attr(
46966 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46967 assert_instr(nop)
46968)]
46969#[cfg_attr(
46970 not(target_arch = "arm"),
46971 stable(feature = "neon_intrinsics", since = "1.59.0")
46972)]
46973#[cfg_attr(
46974 target_arch = "arm",
46975 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46976)]
46977pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
46978 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46979 unsafe {
46980 let ret_val: int32x4_t = transmute(a);
46981 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46982 }
46983}
46984#[doc = "Vector reinterpret cast operation"]
46985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
46986#[inline]
46987#[cfg(target_endian = "little")]
46988#[target_feature(enable = "neon")]
46989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46991#[cfg_attr(
46992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46993 assert_instr(nop)
46994)]
46995#[cfg_attr(
46996 not(target_arch = "arm"),
46997 stable(feature = "neon_intrinsics", since = "1.59.0")
46998)]
46999#[cfg_attr(
47000 target_arch = "arm",
47001 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47002)]
47003pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
47004 unsafe { transmute(a) }
47005}
47006#[doc = "Vector reinterpret cast operation"]
47007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
47008#[inline]
47009#[cfg(target_endian = "big")]
47010#[target_feature(enable = "neon")]
47011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47013#[cfg_attr(
47014 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47015 assert_instr(nop)
47016)]
47017#[cfg_attr(
47018 not(target_arch = "arm"),
47019 stable(feature = "neon_intrinsics", since = "1.59.0")
47020)]
47021#[cfg_attr(
47022 target_arch = "arm",
47023 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47024)]
47025pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
47026 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47027 unsafe {
47028 let ret_val: int64x2_t = transmute(a);
47029 simd_shuffle!(ret_val, ret_val, [1, 0])
47030 }
47031}
47032#[doc = "Vector reinterpret cast operation"]
47033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
47034#[inline]
47035#[cfg(target_endian = "little")]
47036#[target_feature(enable = "neon")]
47037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47039#[cfg_attr(
47040 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47041 assert_instr(nop)
47042)]
47043#[cfg_attr(
47044 not(target_arch = "arm"),
47045 stable(feature = "neon_intrinsics", since = "1.59.0")
47046)]
47047#[cfg_attr(
47048 target_arch = "arm",
47049 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47050)]
47051pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
47052 unsafe { transmute(a) }
47053}
47054#[doc = "Vector reinterpret cast operation"]
47055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
47056#[inline]
47057#[cfg(target_endian = "big")]
47058#[target_feature(enable = "neon")]
47059#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47060#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47061#[cfg_attr(
47062 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47063 assert_instr(nop)
47064)]
47065#[cfg_attr(
47066 not(target_arch = "arm"),
47067 stable(feature = "neon_intrinsics", since = "1.59.0")
47068)]
47069#[cfg_attr(
47070 target_arch = "arm",
47071 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47072)]
47073pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
47074 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47075 unsafe {
47076 let ret_val: uint8x16_t = transmute(a);
47077 simd_shuffle!(
47078 ret_val,
47079 ret_val,
47080 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47081 )
47082 }
47083}
47084#[doc = "Vector reinterpret cast operation"]
47085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
47086#[inline]
47087#[cfg(target_endian = "little")]
47088#[target_feature(enable = "neon")]
47089#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47090#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47091#[cfg_attr(
47092 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47093 assert_instr(nop)
47094)]
47095#[cfg_attr(
47096 not(target_arch = "arm"),
47097 stable(feature = "neon_intrinsics", since = "1.59.0")
47098)]
47099#[cfg_attr(
47100 target_arch = "arm",
47101 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47102)]
47103pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
47104 unsafe { transmute(a) }
47105}
47106#[doc = "Vector reinterpret cast operation"]
47107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
47108#[inline]
47109#[cfg(target_endian = "big")]
47110#[target_feature(enable = "neon")]
47111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47113#[cfg_attr(
47114 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47115 assert_instr(nop)
47116)]
47117#[cfg_attr(
47118 not(target_arch = "arm"),
47119 stable(feature = "neon_intrinsics", since = "1.59.0")
47120)]
47121#[cfg_attr(
47122 target_arch = "arm",
47123 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47124)]
47125pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
47126 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47127 unsafe {
47128 let ret_val: uint16x8_t = transmute(a);
47129 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47130 }
47131}
47132#[doc = "Vector reinterpret cast operation"]
47133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
47134#[inline]
47135#[cfg(target_endian = "little")]
47136#[target_feature(enable = "neon")]
47137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47138#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47139#[cfg_attr(
47140 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47141 assert_instr(nop)
47142)]
47143#[cfg_attr(
47144 not(target_arch = "arm"),
47145 stable(feature = "neon_intrinsics", since = "1.59.0")
47146)]
47147#[cfg_attr(
47148 target_arch = "arm",
47149 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47150)]
47151pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
47152 unsafe { transmute(a) }
47153}
47154#[doc = "Vector reinterpret cast operation"]
47155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
47156#[inline]
47157#[cfg(target_endian = "big")]
47158#[target_feature(enable = "neon")]
47159#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47160#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47161#[cfg_attr(
47162 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47163 assert_instr(nop)
47164)]
47165#[cfg_attr(
47166 not(target_arch = "arm"),
47167 stable(feature = "neon_intrinsics", since = "1.59.0")
47168)]
47169#[cfg_attr(
47170 target_arch = "arm",
47171 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47172)]
47173pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
47174 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47175 unsafe {
47176 let ret_val: uint32x4_t = transmute(a);
47177 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47178 }
47179}
47180#[doc = "Vector reinterpret cast operation"]
47181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
47182#[inline]
47183#[cfg(target_endian = "little")]
47184#[target_feature(enable = "neon")]
47185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47187#[cfg_attr(
47188 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47189 assert_instr(nop)
47190)]
47191#[cfg_attr(
47192 not(target_arch = "arm"),
47193 stable(feature = "neon_intrinsics", since = "1.59.0")
47194)]
47195#[cfg_attr(
47196 target_arch = "arm",
47197 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47198)]
47199pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
47200 unsafe { transmute(a) }
47201}
47202#[doc = "Vector reinterpret cast operation"]
47203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
47204#[inline]
47205#[cfg(target_endian = "big")]
47206#[target_feature(enable = "neon")]
47207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47208#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47209#[cfg_attr(
47210 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47211 assert_instr(nop)
47212)]
47213#[cfg_attr(
47214 not(target_arch = "arm"),
47215 stable(feature = "neon_intrinsics", since = "1.59.0")
47216)]
47217#[cfg_attr(
47218 target_arch = "arm",
47219 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47220)]
47221pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
47222 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47223 unsafe {
47224 let ret_val: uint64x2_t = transmute(a);
47225 simd_shuffle!(ret_val, ret_val, [1, 0])
47226 }
47227}
47228#[doc = "Vector reinterpret cast operation"]
47229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
47230#[inline]
47231#[cfg(target_endian = "little")]
47232#[target_feature(enable = "neon")]
47233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47235#[cfg_attr(
47236 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47237 assert_instr(nop)
47238)]
47239#[cfg_attr(
47240 not(target_arch = "arm"),
47241 stable(feature = "neon_intrinsics", since = "1.59.0")
47242)]
47243#[cfg_attr(
47244 target_arch = "arm",
47245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47246)]
47247pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
47248 unsafe { transmute(a) }
47249}
47250#[doc = "Vector reinterpret cast operation"]
47251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
47252#[inline]
47253#[cfg(target_endian = "big")]
47254#[target_feature(enable = "neon")]
47255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47257#[cfg_attr(
47258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47259 assert_instr(nop)
47260)]
47261#[cfg_attr(
47262 not(target_arch = "arm"),
47263 stable(feature = "neon_intrinsics", since = "1.59.0")
47264)]
47265#[cfg_attr(
47266 target_arch = "arm",
47267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47268)]
47269pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
47270 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47271 unsafe {
47272 let ret_val: poly8x16_t = transmute(a);
47273 simd_shuffle!(
47274 ret_val,
47275 ret_val,
47276 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47277 )
47278 }
47279}
47280#[doc = "Vector reinterpret cast operation"]
47281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
47282#[inline]
47283#[cfg(target_endian = "little")]
47284#[target_feature(enable = "neon")]
47285#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47286#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47287#[cfg_attr(
47288 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47289 assert_instr(nop)
47290)]
47291#[cfg_attr(
47292 not(target_arch = "arm"),
47293 stable(feature = "neon_intrinsics", since = "1.59.0")
47294)]
47295#[cfg_attr(
47296 target_arch = "arm",
47297 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47298)]
47299pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
47300 unsafe { transmute(a) }
47301}
47302#[doc = "Vector reinterpret cast operation"]
47303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
47304#[inline]
47305#[cfg(target_endian = "big")]
47306#[target_feature(enable = "neon")]
47307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47308#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47309#[cfg_attr(
47310 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47311 assert_instr(nop)
47312)]
47313#[cfg_attr(
47314 not(target_arch = "arm"),
47315 stable(feature = "neon_intrinsics", since = "1.59.0")
47316)]
47317#[cfg_attr(
47318 target_arch = "arm",
47319 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47320)]
47321pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
47322 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
47323 unsafe {
47324 let ret_val: poly16x8_t = transmute(a);
47325 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47326 }
47327}
47328#[doc = "Vector reinterpret cast operation"]
47329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
47330#[inline]
47331#[cfg(target_endian = "little")]
47332#[target_feature(enable = "neon")]
47333#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47334#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47335#[cfg_attr(
47336 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47337 assert_instr(nop)
47338)]
47339#[cfg_attr(
47340 not(target_arch = "arm"),
47341 stable(feature = "neon_intrinsics", since = "1.59.0")
47342)]
47343#[cfg_attr(
47344 target_arch = "arm",
47345 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47346)]
47347pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
47348 unsafe { transmute(a) }
47349}
47350#[doc = "Vector reinterpret cast operation"]
47351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
47352#[inline]
47353#[cfg(target_endian = "big")]
47354#[target_feature(enable = "neon")]
47355#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47356#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47357#[cfg_attr(
47358 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47359 assert_instr(nop)
47360)]
47361#[cfg_attr(
47362 not(target_arch = "arm"),
47363 stable(feature = "neon_intrinsics", since = "1.59.0")
47364)]
47365#[cfg_attr(
47366 target_arch = "arm",
47367 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47368)]
47369pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
47370 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47371 unsafe {
47372 let ret_val: float32x2_t = transmute(a);
47373 simd_shuffle!(ret_val, ret_val, [1, 0])
47374 }
47375}
47376#[doc = "Vector reinterpret cast operation"]
47377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
47378#[inline]
47379#[cfg(target_endian = "little")]
47380#[target_feature(enable = "neon")]
47381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47383#[cfg_attr(
47384 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47385 assert_instr(nop)
47386)]
47387#[cfg_attr(
47388 not(target_arch = "arm"),
47389 stable(feature = "neon_intrinsics", since = "1.59.0")
47390)]
47391#[cfg_attr(
47392 target_arch = "arm",
47393 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47394)]
47395pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
47396 unsafe { transmute(a) }
47397}
47398#[doc = "Vector reinterpret cast operation"]
47399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
47400#[inline]
47401#[cfg(target_endian = "big")]
47402#[target_feature(enable = "neon")]
47403#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47404#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47405#[cfg_attr(
47406 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47407 assert_instr(nop)
47408)]
47409#[cfg_attr(
47410 not(target_arch = "arm"),
47411 stable(feature = "neon_intrinsics", since = "1.59.0")
47412)]
47413#[cfg_attr(
47414 target_arch = "arm",
47415 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47416)]
47417pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
47418 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47419 unsafe {
47420 let ret_val: int8x8_t = transmute(a);
47421 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47422 }
47423}
47424#[doc = "Vector reinterpret cast operation"]
47425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
47426#[inline]
47427#[cfg(target_endian = "little")]
47428#[target_feature(enable = "neon")]
47429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47431#[cfg_attr(
47432 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47433 assert_instr(nop)
47434)]
47435#[cfg_attr(
47436 not(target_arch = "arm"),
47437 stable(feature = "neon_intrinsics", since = "1.59.0")
47438)]
47439#[cfg_attr(
47440 target_arch = "arm",
47441 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47442)]
47443pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
47444 unsafe { transmute(a) }
47445}
47446#[doc = "Vector reinterpret cast operation"]
47447#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
47448#[inline]
47449#[cfg(target_endian = "big")]
47450#[target_feature(enable = "neon")]
47451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47453#[cfg_attr(
47454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47455 assert_instr(nop)
47456)]
47457#[cfg_attr(
47458 not(target_arch = "arm"),
47459 stable(feature = "neon_intrinsics", since = "1.59.0")
47460)]
47461#[cfg_attr(
47462 target_arch = "arm",
47463 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47464)]
47465pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
47466 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47467 unsafe {
47468 let ret_val: int16x4_t = transmute(a);
47469 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47470 }
47471}
47472#[doc = "Vector reinterpret cast operation"]
47473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
47474#[inline]
47475#[cfg(target_endian = "little")]
47476#[target_feature(enable = "neon")]
47477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47479#[cfg_attr(
47480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47481 assert_instr(nop)
47482)]
47483#[cfg_attr(
47484 not(target_arch = "arm"),
47485 stable(feature = "neon_intrinsics", since = "1.59.0")
47486)]
47487#[cfg_attr(
47488 target_arch = "arm",
47489 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47490)]
47491pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
47492 unsafe { transmute(a) }
47493}
47494#[doc = "Vector reinterpret cast operation"]
47495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
47496#[inline]
47497#[cfg(target_endian = "big")]
47498#[target_feature(enable = "neon")]
47499#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47500#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47501#[cfg_attr(
47502 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47503 assert_instr(nop)
47504)]
47505#[cfg_attr(
47506 not(target_arch = "arm"),
47507 stable(feature = "neon_intrinsics", since = "1.59.0")
47508)]
47509#[cfg_attr(
47510 target_arch = "arm",
47511 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47512)]
47513pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
47514 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47515 unsafe { transmute(a) }
47516}
47517#[doc = "Vector reinterpret cast operation"]
47518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
47519#[inline]
47520#[cfg(target_endian = "little")]
47521#[target_feature(enable = "neon")]
47522#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47523#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47524#[cfg_attr(
47525 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47526 assert_instr(nop)
47527)]
47528#[cfg_attr(
47529 not(target_arch = "arm"),
47530 stable(feature = "neon_intrinsics", since = "1.59.0")
47531)]
47532#[cfg_attr(
47533 target_arch = "arm",
47534 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47535)]
47536pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
47537 unsafe { transmute(a) }
47538}
47539#[doc = "Vector reinterpret cast operation"]
47540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
47541#[inline]
47542#[cfg(target_endian = "big")]
47543#[target_feature(enable = "neon")]
47544#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47545#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47546#[cfg_attr(
47547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47548 assert_instr(nop)
47549)]
47550#[cfg_attr(
47551 not(target_arch = "arm"),
47552 stable(feature = "neon_intrinsics", since = "1.59.0")
47553)]
47554#[cfg_attr(
47555 target_arch = "arm",
47556 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47557)]
47558pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
47559 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47560 unsafe {
47561 let ret_val: uint8x8_t = transmute(a);
47562 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47563 }
47564}
47565#[doc = "Vector reinterpret cast operation"]
47566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
47567#[inline]
47568#[cfg(target_endian = "little")]
47569#[target_feature(enable = "neon")]
47570#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47571#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47572#[cfg_attr(
47573 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47574 assert_instr(nop)
47575)]
47576#[cfg_attr(
47577 not(target_arch = "arm"),
47578 stable(feature = "neon_intrinsics", since = "1.59.0")
47579)]
47580#[cfg_attr(
47581 target_arch = "arm",
47582 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47583)]
47584pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
47585 unsafe { transmute(a) }
47586}
47587#[doc = "Vector reinterpret cast operation"]
47588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
47589#[inline]
47590#[cfg(target_endian = "big")]
47591#[target_feature(enable = "neon")]
47592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47594#[cfg_attr(
47595 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47596 assert_instr(nop)
47597)]
47598#[cfg_attr(
47599 not(target_arch = "arm"),
47600 stable(feature = "neon_intrinsics", since = "1.59.0")
47601)]
47602#[cfg_attr(
47603 target_arch = "arm",
47604 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47605)]
47606pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
47607 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47608 unsafe {
47609 let ret_val: uint16x4_t = transmute(a);
47610 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47611 }
47612}
47613#[doc = "Vector reinterpret cast operation"]
47614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
47615#[inline]
47616#[cfg(target_endian = "little")]
47617#[target_feature(enable = "neon")]
47618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47619#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47620#[cfg_attr(
47621 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47622 assert_instr(nop)
47623)]
47624#[cfg_attr(
47625 not(target_arch = "arm"),
47626 stable(feature = "neon_intrinsics", since = "1.59.0")
47627)]
47628#[cfg_attr(
47629 target_arch = "arm",
47630 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47631)]
47632pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
47633 unsafe { transmute(a) }
47634}
47635#[doc = "Vector reinterpret cast operation"]
47636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
47637#[inline]
47638#[cfg(target_endian = "big")]
47639#[target_feature(enable = "neon")]
47640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47642#[cfg_attr(
47643 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47644 assert_instr(nop)
47645)]
47646#[cfg_attr(
47647 not(target_arch = "arm"),
47648 stable(feature = "neon_intrinsics", since = "1.59.0")
47649)]
47650#[cfg_attr(
47651 target_arch = "arm",
47652 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47653)]
47654pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
47655 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47656 unsafe {
47657 let ret_val: uint32x2_t = transmute(a);
47658 simd_shuffle!(ret_val, ret_val, [1, 0])
47659 }
47660}
47661#[doc = "Vector reinterpret cast operation"]
47662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
47663#[inline]
47664#[cfg(target_endian = "little")]
47665#[target_feature(enable = "neon")]
47666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47667#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47668#[cfg_attr(
47669 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47670 assert_instr(nop)
47671)]
47672#[cfg_attr(
47673 not(target_arch = "arm"),
47674 stable(feature = "neon_intrinsics", since = "1.59.0")
47675)]
47676#[cfg_attr(
47677 target_arch = "arm",
47678 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47679)]
47680pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
47681 unsafe { transmute(a) }
47682}
47683#[doc = "Vector reinterpret cast operation"]
47684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
47685#[inline]
47686#[cfg(target_endian = "big")]
47687#[target_feature(enable = "neon")]
47688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47689#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47690#[cfg_attr(
47691 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47692 assert_instr(nop)
47693)]
47694#[cfg_attr(
47695 not(target_arch = "arm"),
47696 stable(feature = "neon_intrinsics", since = "1.59.0")
47697)]
47698#[cfg_attr(
47699 target_arch = "arm",
47700 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47701)]
47702pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
47703 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47704 unsafe { transmute(a) }
47705}
47706#[doc = "Vector reinterpret cast operation"]
47707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
47708#[inline]
47709#[cfg(target_endian = "little")]
47710#[target_feature(enable = "neon")]
47711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47712#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47713#[cfg_attr(
47714 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47715 assert_instr(nop)
47716)]
47717#[cfg_attr(
47718 not(target_arch = "arm"),
47719 stable(feature = "neon_intrinsics", since = "1.59.0")
47720)]
47721#[cfg_attr(
47722 target_arch = "arm",
47723 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47724)]
47725pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
47726 unsafe { transmute(a) }
47727}
47728#[doc = "Vector reinterpret cast operation"]
47729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
47730#[inline]
47731#[cfg(target_endian = "big")]
47732#[target_feature(enable = "neon")]
47733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47734#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47735#[cfg_attr(
47736 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47737 assert_instr(nop)
47738)]
47739#[cfg_attr(
47740 not(target_arch = "arm"),
47741 stable(feature = "neon_intrinsics", since = "1.59.0")
47742)]
47743#[cfg_attr(
47744 target_arch = "arm",
47745 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47746)]
47747pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
47748 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47749 unsafe {
47750 let ret_val: poly8x8_t = transmute(a);
47751 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47752 }
47753}
47754#[doc = "Vector reinterpret cast operation"]
47755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
47756#[inline]
47757#[cfg(target_endian = "little")]
47758#[target_feature(enable = "neon")]
47759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47761#[cfg_attr(
47762 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47763 assert_instr(nop)
47764)]
47765#[cfg_attr(
47766 not(target_arch = "arm"),
47767 stable(feature = "neon_intrinsics", since = "1.59.0")
47768)]
47769#[cfg_attr(
47770 target_arch = "arm",
47771 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47772)]
47773pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
47774 unsafe { transmute(a) }
47775}
47776#[doc = "Vector reinterpret cast operation"]
47777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
47778#[inline]
47779#[cfg(target_endian = "big")]
47780#[target_feature(enable = "neon")]
47781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47783#[cfg_attr(
47784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47785 assert_instr(nop)
47786)]
47787#[cfg_attr(
47788 not(target_arch = "arm"),
47789 stable(feature = "neon_intrinsics", since = "1.59.0")
47790)]
47791#[cfg_attr(
47792 target_arch = "arm",
47793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47794)]
47795pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
47796 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47797 unsafe {
47798 let ret_val: poly16x4_t = transmute(a);
47799 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47800 }
47801}
47802#[doc = "Vector reinterpret cast operation"]
47803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
47804#[inline]
47805#[cfg(target_endian = "little")]
47806#[target_feature(enable = "neon")]
47807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47808#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47809#[cfg_attr(
47810 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47811 assert_instr(nop)
47812)]
47813#[cfg_attr(
47814 not(target_arch = "arm"),
47815 stable(feature = "neon_intrinsics", since = "1.59.0")
47816)]
47817#[cfg_attr(
47818 target_arch = "arm",
47819 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47820)]
47821pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
47822 unsafe { transmute(a) }
47823}
47824#[doc = "Vector reinterpret cast operation"]
47825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
47826#[inline]
47827#[cfg(target_endian = "big")]
47828#[target_feature(enable = "neon")]
47829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47831#[cfg_attr(
47832 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47833 assert_instr(nop)
47834)]
47835#[cfg_attr(
47836 not(target_arch = "arm"),
47837 stable(feature = "neon_intrinsics", since = "1.59.0")
47838)]
47839#[cfg_attr(
47840 target_arch = "arm",
47841 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47842)]
47843pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
47844 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47845 unsafe {
47846 let ret_val: float32x4_t = transmute(a);
47847 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47848 }
47849}
47850#[doc = "Vector reinterpret cast operation"]
47851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
47852#[inline]
47853#[cfg(target_endian = "little")]
47854#[target_feature(enable = "neon")]
47855#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47856#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47857#[cfg_attr(
47858 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47859 assert_instr(nop)
47860)]
47861#[cfg_attr(
47862 not(target_arch = "arm"),
47863 stable(feature = "neon_intrinsics", since = "1.59.0")
47864)]
47865#[cfg_attr(
47866 target_arch = "arm",
47867 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47868)]
47869pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
47870 unsafe { transmute(a) }
47871}
47872#[doc = "Vector reinterpret cast operation"]
47873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
47874#[inline]
47875#[cfg(target_endian = "big")]
47876#[target_feature(enable = "neon")]
47877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47878#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47879#[cfg_attr(
47880 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47881 assert_instr(nop)
47882)]
47883#[cfg_attr(
47884 not(target_arch = "arm"),
47885 stable(feature = "neon_intrinsics", since = "1.59.0")
47886)]
47887#[cfg_attr(
47888 target_arch = "arm",
47889 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47890)]
47891pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
47892 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47893 unsafe {
47894 let ret_val: int8x16_t = transmute(a);
47895 simd_shuffle!(
47896 ret_val,
47897 ret_val,
47898 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47899 )
47900 }
47901}
47902#[doc = "Vector reinterpret cast operation"]
47903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
47904#[inline]
47905#[cfg(target_endian = "little")]
47906#[target_feature(enable = "neon")]
47907#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47908#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47909#[cfg_attr(
47910 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47911 assert_instr(nop)
47912)]
47913#[cfg_attr(
47914 not(target_arch = "arm"),
47915 stable(feature = "neon_intrinsics", since = "1.59.0")
47916)]
47917#[cfg_attr(
47918 target_arch = "arm",
47919 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47920)]
47921pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
47922 unsafe { transmute(a) }
47923}
47924#[doc = "Vector reinterpret cast operation"]
47925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
47926#[inline]
47927#[cfg(target_endian = "big")]
47928#[target_feature(enable = "neon")]
47929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47930#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47931#[cfg_attr(
47932 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47933 assert_instr(nop)
47934)]
47935#[cfg_attr(
47936 not(target_arch = "arm"),
47937 stable(feature = "neon_intrinsics", since = "1.59.0")
47938)]
47939#[cfg_attr(
47940 target_arch = "arm",
47941 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47942)]
47943pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
47944 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47945 unsafe {
47946 let ret_val: int16x8_t = transmute(a);
47947 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47948 }
47949}
47950#[doc = "Vector reinterpret cast operation"]
47951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
47952#[inline]
47953#[cfg(target_endian = "little")]
47954#[target_feature(enable = "neon")]
47955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47957#[cfg_attr(
47958 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47959 assert_instr(nop)
47960)]
47961#[cfg_attr(
47962 not(target_arch = "arm"),
47963 stable(feature = "neon_intrinsics", since = "1.59.0")
47964)]
47965#[cfg_attr(
47966 target_arch = "arm",
47967 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47968)]
47969pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
47970 unsafe { transmute(a) }
47971}
47972#[doc = "Vector reinterpret cast operation"]
47973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
47974#[inline]
47975#[cfg(target_endian = "big")]
47976#[target_feature(enable = "neon")]
47977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47978#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47979#[cfg_attr(
47980 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47981 assert_instr(nop)
47982)]
47983#[cfg_attr(
47984 not(target_arch = "arm"),
47985 stable(feature = "neon_intrinsics", since = "1.59.0")
47986)]
47987#[cfg_attr(
47988 target_arch = "arm",
47989 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47990)]
47991pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
47992 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47993 unsafe {
47994 let ret_val: int64x2_t = transmute(a);
47995 simd_shuffle!(ret_val, ret_val, [1, 0])
47996 }
47997}
47998#[doc = "Vector reinterpret cast operation"]
47999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
48000#[inline]
48001#[cfg(target_endian = "little")]
48002#[target_feature(enable = "neon")]
48003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48005#[cfg_attr(
48006 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48007 assert_instr(nop)
48008)]
48009#[cfg_attr(
48010 not(target_arch = "arm"),
48011 stable(feature = "neon_intrinsics", since = "1.59.0")
48012)]
48013#[cfg_attr(
48014 target_arch = "arm",
48015 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48016)]
48017pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
48018 unsafe { transmute(a) }
48019}
48020#[doc = "Vector reinterpret cast operation"]
48021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
48022#[inline]
48023#[cfg(target_endian = "big")]
48024#[target_feature(enable = "neon")]
48025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48027#[cfg_attr(
48028 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48029 assert_instr(nop)
48030)]
48031#[cfg_attr(
48032 not(target_arch = "arm"),
48033 stable(feature = "neon_intrinsics", since = "1.59.0")
48034)]
48035#[cfg_attr(
48036 target_arch = "arm",
48037 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48038)]
48039pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
48040 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48041 unsafe {
48042 let ret_val: uint8x16_t = transmute(a);
48043 simd_shuffle!(
48044 ret_val,
48045 ret_val,
48046 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48047 )
48048 }
48049}
48050#[doc = "Vector reinterpret cast operation"]
48051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
48052#[inline]
48053#[cfg(target_endian = "little")]
48054#[target_feature(enable = "neon")]
48055#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48056#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48057#[cfg_attr(
48058 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48059 assert_instr(nop)
48060)]
48061#[cfg_attr(
48062 not(target_arch = "arm"),
48063 stable(feature = "neon_intrinsics", since = "1.59.0")
48064)]
48065#[cfg_attr(
48066 target_arch = "arm",
48067 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48068)]
48069pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
48070 unsafe { transmute(a) }
48071}
48072#[doc = "Vector reinterpret cast operation"]
48073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
48074#[inline]
48075#[cfg(target_endian = "big")]
48076#[target_feature(enable = "neon")]
48077#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48078#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48079#[cfg_attr(
48080 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48081 assert_instr(nop)
48082)]
48083#[cfg_attr(
48084 not(target_arch = "arm"),
48085 stable(feature = "neon_intrinsics", since = "1.59.0")
48086)]
48087#[cfg_attr(
48088 target_arch = "arm",
48089 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48090)]
48091pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
48092 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48093 unsafe {
48094 let ret_val: uint16x8_t = transmute(a);
48095 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48096 }
48097}
48098#[doc = "Vector reinterpret cast operation"]
48099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
48100#[inline]
48101#[cfg(target_endian = "little")]
48102#[target_feature(enable = "neon")]
48103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48105#[cfg_attr(
48106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48107 assert_instr(nop)
48108)]
48109#[cfg_attr(
48110 not(target_arch = "arm"),
48111 stable(feature = "neon_intrinsics", since = "1.59.0")
48112)]
48113#[cfg_attr(
48114 target_arch = "arm",
48115 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48116)]
48117pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
48118 unsafe { transmute(a) }
48119}
48120#[doc = "Vector reinterpret cast operation"]
48121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
48122#[inline]
48123#[cfg(target_endian = "big")]
48124#[target_feature(enable = "neon")]
48125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48127#[cfg_attr(
48128 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48129 assert_instr(nop)
48130)]
48131#[cfg_attr(
48132 not(target_arch = "arm"),
48133 stable(feature = "neon_intrinsics", since = "1.59.0")
48134)]
48135#[cfg_attr(
48136 target_arch = "arm",
48137 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48138)]
48139pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
48140 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48141 unsafe {
48142 let ret_val: uint32x4_t = transmute(a);
48143 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48144 }
48145}
48146#[doc = "Vector reinterpret cast operation"]
48147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
48148#[inline]
48149#[cfg(target_endian = "little")]
48150#[target_feature(enable = "neon")]
48151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48153#[cfg_attr(
48154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48155 assert_instr(nop)
48156)]
48157#[cfg_attr(
48158 not(target_arch = "arm"),
48159 stable(feature = "neon_intrinsics", since = "1.59.0")
48160)]
48161#[cfg_attr(
48162 target_arch = "arm",
48163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48164)]
48165pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
48166 unsafe { transmute(a) }
48167}
48168#[doc = "Vector reinterpret cast operation"]
48169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
48170#[inline]
48171#[cfg(target_endian = "big")]
48172#[target_feature(enable = "neon")]
48173#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48174#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48175#[cfg_attr(
48176 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48177 assert_instr(nop)
48178)]
48179#[cfg_attr(
48180 not(target_arch = "arm"),
48181 stable(feature = "neon_intrinsics", since = "1.59.0")
48182)]
48183#[cfg_attr(
48184 target_arch = "arm",
48185 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48186)]
48187pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
48188 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48189 unsafe {
48190 let ret_val: uint64x2_t = transmute(a);
48191 simd_shuffle!(ret_val, ret_val, [1, 0])
48192 }
48193}
48194#[doc = "Vector reinterpret cast operation"]
48195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
48196#[inline]
48197#[cfg(target_endian = "little")]
48198#[target_feature(enable = "neon")]
48199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48201#[cfg_attr(
48202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48203 assert_instr(nop)
48204)]
48205#[cfg_attr(
48206 not(target_arch = "arm"),
48207 stable(feature = "neon_intrinsics", since = "1.59.0")
48208)]
48209#[cfg_attr(
48210 target_arch = "arm",
48211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48212)]
48213pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
48214 unsafe { transmute(a) }
48215}
48216#[doc = "Vector reinterpret cast operation"]
48217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
48218#[inline]
48219#[cfg(target_endian = "big")]
48220#[target_feature(enable = "neon")]
48221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48223#[cfg_attr(
48224 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48225 assert_instr(nop)
48226)]
48227#[cfg_attr(
48228 not(target_arch = "arm"),
48229 stable(feature = "neon_intrinsics", since = "1.59.0")
48230)]
48231#[cfg_attr(
48232 target_arch = "arm",
48233 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48234)]
48235pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
48236 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48237 unsafe {
48238 let ret_val: poly8x16_t = transmute(a);
48239 simd_shuffle!(
48240 ret_val,
48241 ret_val,
48242 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48243 )
48244 }
48245}
48246#[doc = "Vector reinterpret cast operation"]
48247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
48248#[inline]
48249#[cfg(target_endian = "little")]
48250#[target_feature(enable = "neon")]
48251#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48252#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48253#[cfg_attr(
48254 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48255 assert_instr(nop)
48256)]
48257#[cfg_attr(
48258 not(target_arch = "arm"),
48259 stable(feature = "neon_intrinsics", since = "1.59.0")
48260)]
48261#[cfg_attr(
48262 target_arch = "arm",
48263 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48264)]
48265pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
48266 unsafe { transmute(a) }
48267}
48268#[doc = "Vector reinterpret cast operation"]
48269#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
48270#[inline]
48271#[cfg(target_endian = "big")]
48272#[target_feature(enable = "neon")]
48273#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48274#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48275#[cfg_attr(
48276 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48277 assert_instr(nop)
48278)]
48279#[cfg_attr(
48280 not(target_arch = "arm"),
48281 stable(feature = "neon_intrinsics", since = "1.59.0")
48282)]
48283#[cfg_attr(
48284 target_arch = "arm",
48285 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48286)]
48287pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
48288 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
48289 unsafe {
48290 let ret_val: poly16x8_t = transmute(a);
48291 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48292 }
48293}
48294#[doc = "Vector reinterpret cast operation"]
48295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
48296#[inline]
48297#[cfg(target_endian = "little")]
48298#[target_feature(enable = "neon")]
48299#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48300#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48301#[cfg_attr(
48302 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48303 assert_instr(nop)
48304)]
48305#[cfg_attr(
48306 not(target_arch = "arm"),
48307 stable(feature = "neon_intrinsics", since = "1.59.0")
48308)]
48309#[cfg_attr(
48310 target_arch = "arm",
48311 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48312)]
48313pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
48314 unsafe { transmute(a) }
48315}
48316#[doc = "Vector reinterpret cast operation"]
48317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
48318#[inline]
48319#[cfg(target_endian = "big")]
48320#[target_feature(enable = "neon")]
48321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48322#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48323#[cfg_attr(
48324 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48325 assert_instr(nop)
48326)]
48327#[cfg_attr(
48328 not(target_arch = "arm"),
48329 stable(feature = "neon_intrinsics", since = "1.59.0")
48330)]
48331#[cfg_attr(
48332 target_arch = "arm",
48333 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48334)]
48335pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
48336 unsafe {
48337 let ret_val: float32x2_t = transmute(a);
48338 simd_shuffle!(ret_val, ret_val, [1, 0])
48339 }
48340}
48341#[doc = "Vector reinterpret cast operation"]
48342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
48343#[inline]
48344#[cfg(target_endian = "little")]
48345#[target_feature(enable = "neon")]
48346#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48347#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48348#[cfg_attr(
48349 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48350 assert_instr(nop)
48351)]
48352#[cfg_attr(
48353 not(target_arch = "arm"),
48354 stable(feature = "neon_intrinsics", since = "1.59.0")
48355)]
48356#[cfg_attr(
48357 target_arch = "arm",
48358 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48359)]
48360pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
48361 unsafe { transmute(a) }
48362}
48363#[doc = "Vector reinterpret cast operation"]
48364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
48365#[inline]
48366#[cfg(target_endian = "big")]
48367#[target_feature(enable = "neon")]
48368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48370#[cfg_attr(
48371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48372 assert_instr(nop)
48373)]
48374#[cfg_attr(
48375 not(target_arch = "arm"),
48376 stable(feature = "neon_intrinsics", since = "1.59.0")
48377)]
48378#[cfg_attr(
48379 target_arch = "arm",
48380 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48381)]
48382pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
48383 unsafe {
48384 let ret_val: int8x8_t = transmute(a);
48385 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48386 }
48387}
48388#[doc = "Vector reinterpret cast operation"]
48389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
48390#[inline]
48391#[cfg(target_endian = "little")]
48392#[target_feature(enable = "neon")]
48393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48395#[cfg_attr(
48396 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48397 assert_instr(nop)
48398)]
48399#[cfg_attr(
48400 not(target_arch = "arm"),
48401 stable(feature = "neon_intrinsics", since = "1.59.0")
48402)]
48403#[cfg_attr(
48404 target_arch = "arm",
48405 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48406)]
48407pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
48408 unsafe { transmute(a) }
48409}
48410#[doc = "Vector reinterpret cast operation"]
48411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
48412#[inline]
48413#[cfg(target_endian = "big")]
48414#[target_feature(enable = "neon")]
48415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48417#[cfg_attr(
48418 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48419 assert_instr(nop)
48420)]
48421#[cfg_attr(
48422 not(target_arch = "arm"),
48423 stable(feature = "neon_intrinsics", since = "1.59.0")
48424)]
48425#[cfg_attr(
48426 target_arch = "arm",
48427 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48428)]
48429pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
48430 unsafe {
48431 let ret_val: int16x4_t = transmute(a);
48432 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48433 }
48434}
48435#[doc = "Vector reinterpret cast operation"]
48436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
48437#[inline]
48438#[cfg(target_endian = "little")]
48439#[target_feature(enable = "neon")]
48440#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48441#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48442#[cfg_attr(
48443 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48444 assert_instr(nop)
48445)]
48446#[cfg_attr(
48447 not(target_arch = "arm"),
48448 stable(feature = "neon_intrinsics", since = "1.59.0")
48449)]
48450#[cfg_attr(
48451 target_arch = "arm",
48452 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48453)]
48454pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
48455 unsafe { transmute(a) }
48456}
48457#[doc = "Vector reinterpret cast operation"]
48458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
48459#[inline]
48460#[cfg(target_endian = "big")]
48461#[target_feature(enable = "neon")]
48462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48464#[cfg_attr(
48465 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48466 assert_instr(nop)
48467)]
48468#[cfg_attr(
48469 not(target_arch = "arm"),
48470 stable(feature = "neon_intrinsics", since = "1.59.0")
48471)]
48472#[cfg_attr(
48473 target_arch = "arm",
48474 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48475)]
48476pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
48477 unsafe {
48478 let ret_val: int32x2_t = transmute(a);
48479 simd_shuffle!(ret_val, ret_val, [1, 0])
48480 }
48481}
48482#[doc = "Vector reinterpret cast operation"]
48483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
48484#[inline]
48485#[cfg(target_endian = "little")]
48486#[target_feature(enable = "neon")]
48487#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48488#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48489#[cfg_attr(
48490 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48491 assert_instr(nop)
48492)]
48493#[cfg_attr(
48494 not(target_arch = "arm"),
48495 stable(feature = "neon_intrinsics", since = "1.59.0")
48496)]
48497#[cfg_attr(
48498 target_arch = "arm",
48499 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48500)]
48501pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
48502 unsafe { transmute(a) }
48503}
48504#[doc = "Vector reinterpret cast operation"]
48505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
48506#[inline]
48507#[cfg(target_endian = "big")]
48508#[target_feature(enable = "neon")]
48509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48511#[cfg_attr(
48512 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48513 assert_instr(nop)
48514)]
48515#[cfg_attr(
48516 not(target_arch = "arm"),
48517 stable(feature = "neon_intrinsics", since = "1.59.0")
48518)]
48519#[cfg_attr(
48520 target_arch = "arm",
48521 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48522)]
48523pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
48524 unsafe {
48525 let ret_val: uint8x8_t = transmute(a);
48526 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48527 }
48528}
48529#[doc = "Vector reinterpret cast operation"]
48530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
48531#[inline]
48532#[cfg(target_endian = "little")]
48533#[target_feature(enable = "neon")]
48534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48536#[cfg_attr(
48537 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48538 assert_instr(nop)
48539)]
48540#[cfg_attr(
48541 not(target_arch = "arm"),
48542 stable(feature = "neon_intrinsics", since = "1.59.0")
48543)]
48544#[cfg_attr(
48545 target_arch = "arm",
48546 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48547)]
48548pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
48549 unsafe { transmute(a) }
48550}
48551#[doc = "Vector reinterpret cast operation"]
48552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
48553#[inline]
48554#[cfg(target_endian = "big")]
48555#[target_feature(enable = "neon")]
48556#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48558#[cfg_attr(
48559 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48560 assert_instr(nop)
48561)]
48562#[cfg_attr(
48563 not(target_arch = "arm"),
48564 stable(feature = "neon_intrinsics", since = "1.59.0")
48565)]
48566#[cfg_attr(
48567 target_arch = "arm",
48568 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48569)]
48570pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
48571 unsafe {
48572 let ret_val: uint16x4_t = transmute(a);
48573 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48574 }
48575}
48576#[doc = "Vector reinterpret cast operation"]
48577#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
48578#[inline]
48579#[cfg(target_endian = "little")]
48580#[target_feature(enable = "neon")]
48581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48582#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48583#[cfg_attr(
48584 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48585 assert_instr(nop)
48586)]
48587#[cfg_attr(
48588 not(target_arch = "arm"),
48589 stable(feature = "neon_intrinsics", since = "1.59.0")
48590)]
48591#[cfg_attr(
48592 target_arch = "arm",
48593 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48594)]
48595pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
48596 unsafe { transmute(a) }
48597}
48598#[doc = "Vector reinterpret cast operation"]
48599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
48600#[inline]
48601#[cfg(target_endian = "big")]
48602#[target_feature(enable = "neon")]
48603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48605#[cfg_attr(
48606 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48607 assert_instr(nop)
48608)]
48609#[cfg_attr(
48610 not(target_arch = "arm"),
48611 stable(feature = "neon_intrinsics", since = "1.59.0")
48612)]
48613#[cfg_attr(
48614 target_arch = "arm",
48615 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48616)]
48617pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
48618 unsafe {
48619 let ret_val: uint32x2_t = transmute(a);
48620 simd_shuffle!(ret_val, ret_val, [1, 0])
48621 }
48622}
48623#[doc = "Vector reinterpret cast operation"]
48624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"]
48625#[inline]
48626#[target_feature(enable = "neon")]
48627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48628#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48629#[cfg_attr(
48630 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48631 assert_instr(nop)
48632)]
48633#[cfg_attr(
48634 not(target_arch = "arm"),
48635 stable(feature = "neon_intrinsics", since = "1.59.0")
48636)]
48637#[cfg_attr(
48638 target_arch = "arm",
48639 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48640)]
48641pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
48642 unsafe { transmute(a) }
48643}
48644#[doc = "Vector reinterpret cast operation"]
48645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
48646#[inline]
48647#[cfg(target_endian = "little")]
48648#[target_feature(enable = "neon")]
48649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48650#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48651#[cfg_attr(
48652 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48653 assert_instr(nop)
48654)]
48655#[cfg_attr(
48656 not(target_arch = "arm"),
48657 stable(feature = "neon_intrinsics", since = "1.59.0")
48658)]
48659#[cfg_attr(
48660 target_arch = "arm",
48661 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48662)]
48663pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
48664 unsafe { transmute(a) }
48665}
48666#[doc = "Vector reinterpret cast operation"]
48667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
48668#[inline]
48669#[cfg(target_endian = "big")]
48670#[target_feature(enable = "neon")]
48671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48673#[cfg_attr(
48674 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48675 assert_instr(nop)
48676)]
48677#[cfg_attr(
48678 not(target_arch = "arm"),
48679 stable(feature = "neon_intrinsics", since = "1.59.0")
48680)]
48681#[cfg_attr(
48682 target_arch = "arm",
48683 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48684)]
48685pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
48686 unsafe {
48687 let ret_val: poly8x8_t = transmute(a);
48688 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48689 }
48690}
48691#[doc = "Vector reinterpret cast operation"]
48692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
48693#[inline]
48694#[cfg(target_endian = "little")]
48695#[target_feature(enable = "neon")]
48696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48697#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48698#[cfg_attr(
48699 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48700 assert_instr(nop)
48701)]
48702#[cfg_attr(
48703 not(target_arch = "arm"),
48704 stable(feature = "neon_intrinsics", since = "1.59.0")
48705)]
48706#[cfg_attr(
48707 target_arch = "arm",
48708 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48709)]
48710pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
48711 unsafe { transmute(a) }
48712}
48713#[doc = "Vector reinterpret cast operation"]
48714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
48715#[inline]
48716#[cfg(target_endian = "big")]
48717#[target_feature(enable = "neon")]
48718#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48719#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48720#[cfg_attr(
48721 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48722 assert_instr(nop)
48723)]
48724#[cfg_attr(
48725 not(target_arch = "arm"),
48726 stable(feature = "neon_intrinsics", since = "1.59.0")
48727)]
48728#[cfg_attr(
48729 target_arch = "arm",
48730 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48731)]
48732pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
48733 unsafe {
48734 let ret_val: poly16x4_t = transmute(a);
48735 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48736 }
48737}
48738#[doc = "Vector reinterpret cast operation"]
48739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
48740#[inline]
48741#[cfg(target_endian = "little")]
48742#[target_feature(enable = "neon")]
48743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48744#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48745#[cfg_attr(
48746 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48747 assert_instr(nop)
48748)]
48749#[cfg_attr(
48750 not(target_arch = "arm"),
48751 stable(feature = "neon_intrinsics", since = "1.59.0")
48752)]
48753#[cfg_attr(
48754 target_arch = "arm",
48755 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48756)]
48757pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
48758 unsafe { transmute(a) }
48759}
48760#[doc = "Vector reinterpret cast operation"]
48761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
48762#[inline]
48763#[cfg(target_endian = "big")]
48764#[target_feature(enable = "neon")]
48765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48766#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48767#[cfg_attr(
48768 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48769 assert_instr(nop)
48770)]
48771#[cfg_attr(
48772 not(target_arch = "arm"),
48773 stable(feature = "neon_intrinsics", since = "1.59.0")
48774)]
48775#[cfg_attr(
48776 target_arch = "arm",
48777 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48778)]
48779pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
48780 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48781 unsafe {
48782 let ret_val: float32x4_t = transmute(a);
48783 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48784 }
48785}
48786#[doc = "Vector reinterpret cast operation"]
48787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
48788#[inline]
48789#[cfg(target_endian = "little")]
48790#[target_feature(enable = "neon")]
48791#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48793#[cfg_attr(
48794 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48795 assert_instr(nop)
48796)]
48797#[cfg_attr(
48798 not(target_arch = "arm"),
48799 stable(feature = "neon_intrinsics", since = "1.59.0")
48800)]
48801#[cfg_attr(
48802 target_arch = "arm",
48803 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48804)]
48805pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
48806 unsafe { transmute(a) }
48807}
48808#[doc = "Vector reinterpret cast operation"]
48809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
48810#[inline]
48811#[cfg(target_endian = "big")]
48812#[target_feature(enable = "neon")]
48813#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48814#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48815#[cfg_attr(
48816 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48817 assert_instr(nop)
48818)]
48819#[cfg_attr(
48820 not(target_arch = "arm"),
48821 stable(feature = "neon_intrinsics", since = "1.59.0")
48822)]
48823#[cfg_attr(
48824 target_arch = "arm",
48825 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48826)]
48827pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
48828 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48829 unsafe {
48830 let ret_val: int8x16_t = transmute(a);
48831 simd_shuffle!(
48832 ret_val,
48833 ret_val,
48834 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48835 )
48836 }
48837}
48838#[doc = "Vector reinterpret cast operation"]
48839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
48840#[inline]
48841#[cfg(target_endian = "little")]
48842#[target_feature(enable = "neon")]
48843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48845#[cfg_attr(
48846 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48847 assert_instr(nop)
48848)]
48849#[cfg_attr(
48850 not(target_arch = "arm"),
48851 stable(feature = "neon_intrinsics", since = "1.59.0")
48852)]
48853#[cfg_attr(
48854 target_arch = "arm",
48855 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48856)]
48857pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
48858 unsafe { transmute(a) }
48859}
48860#[doc = "Vector reinterpret cast operation"]
48861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
48862#[inline]
48863#[cfg(target_endian = "big")]
48864#[target_feature(enable = "neon")]
48865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48867#[cfg_attr(
48868 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48869 assert_instr(nop)
48870)]
48871#[cfg_attr(
48872 not(target_arch = "arm"),
48873 stable(feature = "neon_intrinsics", since = "1.59.0")
48874)]
48875#[cfg_attr(
48876 target_arch = "arm",
48877 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48878)]
48879pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
48880 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48881 unsafe {
48882 let ret_val: int16x8_t = transmute(a);
48883 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48884 }
48885}
48886#[doc = "Vector reinterpret cast operation"]
48887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
48888#[inline]
48889#[cfg(target_endian = "little")]
48890#[target_feature(enable = "neon")]
48891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48893#[cfg_attr(
48894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48895 assert_instr(nop)
48896)]
48897#[cfg_attr(
48898 not(target_arch = "arm"),
48899 stable(feature = "neon_intrinsics", since = "1.59.0")
48900)]
48901#[cfg_attr(
48902 target_arch = "arm",
48903 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48904)]
48905pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
48906 unsafe { transmute(a) }
48907}
48908#[doc = "Vector reinterpret cast operation"]
48909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
48910#[inline]
48911#[cfg(target_endian = "big")]
48912#[target_feature(enable = "neon")]
48913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48914#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48915#[cfg_attr(
48916 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48917 assert_instr(nop)
48918)]
48919#[cfg_attr(
48920 not(target_arch = "arm"),
48921 stable(feature = "neon_intrinsics", since = "1.59.0")
48922)]
48923#[cfg_attr(
48924 target_arch = "arm",
48925 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48926)]
48927pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
48928 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48929 unsafe {
48930 let ret_val: int32x4_t = transmute(a);
48931 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48932 }
48933}
48934#[doc = "Vector reinterpret cast operation"]
48935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
48936#[inline]
48937#[cfg(target_endian = "little")]
48938#[target_feature(enable = "neon")]
48939#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48940#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48941#[cfg_attr(
48942 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48943 assert_instr(nop)
48944)]
48945#[cfg_attr(
48946 not(target_arch = "arm"),
48947 stable(feature = "neon_intrinsics", since = "1.59.0")
48948)]
48949#[cfg_attr(
48950 target_arch = "arm",
48951 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48952)]
48953pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
48954 unsafe { transmute(a) }
48955}
48956#[doc = "Vector reinterpret cast operation"]
48957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
48958#[inline]
48959#[cfg(target_endian = "big")]
48960#[target_feature(enable = "neon")]
48961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48962#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48963#[cfg_attr(
48964 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48965 assert_instr(nop)
48966)]
48967#[cfg_attr(
48968 not(target_arch = "arm"),
48969 stable(feature = "neon_intrinsics", since = "1.59.0")
48970)]
48971#[cfg_attr(
48972 target_arch = "arm",
48973 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48974)]
48975pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
48976 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48977 unsafe {
48978 let ret_val: uint8x16_t = transmute(a);
48979 simd_shuffle!(
48980 ret_val,
48981 ret_val,
48982 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48983 )
48984 }
48985}
48986#[doc = "Vector reinterpret cast operation"]
48987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
48988#[inline]
48989#[cfg(target_endian = "little")]
48990#[target_feature(enable = "neon")]
48991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48993#[cfg_attr(
48994 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48995 assert_instr(nop)
48996)]
48997#[cfg_attr(
48998 not(target_arch = "arm"),
48999 stable(feature = "neon_intrinsics", since = "1.59.0")
49000)]
49001#[cfg_attr(
49002 target_arch = "arm",
49003 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49004)]
49005pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
49006 unsafe { transmute(a) }
49007}
49008#[doc = "Vector reinterpret cast operation"]
49009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
49010#[inline]
49011#[cfg(target_endian = "big")]
49012#[target_feature(enable = "neon")]
49013#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49014#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49015#[cfg_attr(
49016 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49017 assert_instr(nop)
49018)]
49019#[cfg_attr(
49020 not(target_arch = "arm"),
49021 stable(feature = "neon_intrinsics", since = "1.59.0")
49022)]
49023#[cfg_attr(
49024 target_arch = "arm",
49025 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49026)]
49027pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
49028 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49029 unsafe {
49030 let ret_val: uint16x8_t = transmute(a);
49031 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49032 }
49033}
49034#[doc = "Vector reinterpret cast operation"]
49035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
49036#[inline]
49037#[cfg(target_endian = "little")]
49038#[target_feature(enable = "neon")]
49039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49041#[cfg_attr(
49042 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49043 assert_instr(nop)
49044)]
49045#[cfg_attr(
49046 not(target_arch = "arm"),
49047 stable(feature = "neon_intrinsics", since = "1.59.0")
49048)]
49049#[cfg_attr(
49050 target_arch = "arm",
49051 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49052)]
49053pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
49054 unsafe { transmute(a) }
49055}
49056#[doc = "Vector reinterpret cast operation"]
49057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
49058#[inline]
49059#[cfg(target_endian = "big")]
49060#[target_feature(enable = "neon")]
49061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49063#[cfg_attr(
49064 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49065 assert_instr(nop)
49066)]
49067#[cfg_attr(
49068 not(target_arch = "arm"),
49069 stable(feature = "neon_intrinsics", since = "1.59.0")
49070)]
49071#[cfg_attr(
49072 target_arch = "arm",
49073 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49074)]
49075pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
49076 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49077 unsafe {
49078 let ret_val: uint32x4_t = transmute(a);
49079 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49080 }
49081}
49082#[doc = "Vector reinterpret cast operation"]
49083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
49084#[inline]
49085#[cfg(target_endian = "little")]
49086#[target_feature(enable = "neon")]
49087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49089#[cfg_attr(
49090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49091 assert_instr(nop)
49092)]
49093#[cfg_attr(
49094 not(target_arch = "arm"),
49095 stable(feature = "neon_intrinsics", since = "1.59.0")
49096)]
49097#[cfg_attr(
49098 target_arch = "arm",
49099 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49100)]
49101pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
49102 unsafe { transmute(a) }
49103}
49104#[doc = "Vector reinterpret cast operation"]
49105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
49106#[inline]
49107#[cfg(target_endian = "big")]
49108#[target_feature(enable = "neon")]
49109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49110#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49111#[cfg_attr(
49112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49113 assert_instr(nop)
49114)]
49115#[cfg_attr(
49116 not(target_arch = "arm"),
49117 stable(feature = "neon_intrinsics", since = "1.59.0")
49118)]
49119#[cfg_attr(
49120 target_arch = "arm",
49121 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49122)]
49123pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
49124 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49125 unsafe {
49126 let ret_val: uint64x2_t = transmute(a);
49127 simd_shuffle!(ret_val, ret_val, [1, 0])
49128 }
49129}
49130#[doc = "Vector reinterpret cast operation"]
49131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
49132#[inline]
49133#[cfg(target_endian = "little")]
49134#[target_feature(enable = "neon")]
49135#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49136#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49137#[cfg_attr(
49138 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49139 assert_instr(nop)
49140)]
49141#[cfg_attr(
49142 not(target_arch = "arm"),
49143 stable(feature = "neon_intrinsics", since = "1.59.0")
49144)]
49145#[cfg_attr(
49146 target_arch = "arm",
49147 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49148)]
49149pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
49150 unsafe { transmute(a) }
49151}
49152#[doc = "Vector reinterpret cast operation"]
49153#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
49154#[inline]
49155#[cfg(target_endian = "big")]
49156#[target_feature(enable = "neon")]
49157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49158#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49159#[cfg_attr(
49160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49161 assert_instr(nop)
49162)]
49163#[cfg_attr(
49164 not(target_arch = "arm"),
49165 stable(feature = "neon_intrinsics", since = "1.59.0")
49166)]
49167#[cfg_attr(
49168 target_arch = "arm",
49169 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49170)]
49171pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
49172 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49173 unsafe {
49174 let ret_val: poly8x16_t = transmute(a);
49175 simd_shuffle!(
49176 ret_val,
49177 ret_val,
49178 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
49179 )
49180 }
49181}
49182#[doc = "Vector reinterpret cast operation"]
49183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
49184#[inline]
49185#[cfg(target_endian = "little")]
49186#[target_feature(enable = "neon")]
49187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49189#[cfg_attr(
49190 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49191 assert_instr(nop)
49192)]
49193#[cfg_attr(
49194 not(target_arch = "arm"),
49195 stable(feature = "neon_intrinsics", since = "1.59.0")
49196)]
49197#[cfg_attr(
49198 target_arch = "arm",
49199 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49200)]
49201pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
49202 unsafe { transmute(a) }
49203}
49204#[doc = "Vector reinterpret cast operation"]
49205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
49206#[inline]
49207#[cfg(target_endian = "big")]
49208#[target_feature(enable = "neon")]
49209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49210#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49211#[cfg_attr(
49212 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49213 assert_instr(nop)
49214)]
49215#[cfg_attr(
49216 not(target_arch = "arm"),
49217 stable(feature = "neon_intrinsics", since = "1.59.0")
49218)]
49219#[cfg_attr(
49220 target_arch = "arm",
49221 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49222)]
49223pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
49224 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
49225 unsafe {
49226 let ret_val: poly16x8_t = transmute(a);
49227 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49228 }
49229}
49230#[doc = "Vector reinterpret cast operation"]
49231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
49232#[inline]
49233#[cfg(target_endian = "little")]
49234#[target_feature(enable = "neon")]
49235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49237#[cfg_attr(
49238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49239 assert_instr(nop)
49240)]
49241#[cfg_attr(
49242 not(target_arch = "arm"),
49243 stable(feature = "neon_intrinsics", since = "1.59.0")
49244)]
49245#[cfg_attr(
49246 target_arch = "arm",
49247 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49248)]
49249pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
49250 unsafe { transmute(a) }
49251}
49252#[doc = "Vector reinterpret cast operation"]
49253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
49254#[inline]
49255#[cfg(target_endian = "big")]
49256#[target_feature(enable = "neon")]
49257#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49258#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49259#[cfg_attr(
49260 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49261 assert_instr(nop)
49262)]
49263#[cfg_attr(
49264 not(target_arch = "arm"),
49265 stable(feature = "neon_intrinsics", since = "1.59.0")
49266)]
49267#[cfg_attr(
49268 target_arch = "arm",
49269 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49270)]
49271pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
49272 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49273 unsafe {
49274 let ret_val: float32x2_t = transmute(a);
49275 simd_shuffle!(ret_val, ret_val, [1, 0])
49276 }
49277}
49278#[doc = "Vector reinterpret cast operation"]
49279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
49280#[inline]
49281#[cfg(target_endian = "little")]
49282#[target_feature(enable = "neon")]
49283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49285#[cfg_attr(
49286 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49287 assert_instr(nop)
49288)]
49289#[cfg_attr(
49290 not(target_arch = "arm"),
49291 stable(feature = "neon_intrinsics", since = "1.59.0")
49292)]
49293#[cfg_attr(
49294 target_arch = "arm",
49295 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49296)]
49297pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
49298 unsafe { transmute(a) }
49299}
49300#[doc = "Vector reinterpret cast operation"]
49301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
49302#[inline]
49303#[cfg(target_endian = "big")]
49304#[target_feature(enable = "neon")]
49305#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49306#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49307#[cfg_attr(
49308 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49309 assert_instr(nop)
49310)]
49311#[cfg_attr(
49312 not(target_arch = "arm"),
49313 stable(feature = "neon_intrinsics", since = "1.59.0")
49314)]
49315#[cfg_attr(
49316 target_arch = "arm",
49317 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49318)]
49319pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
49320 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49321 unsafe {
49322 let ret_val: int8x8_t = transmute(a);
49323 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49324 }
49325}
49326#[doc = "Vector reinterpret cast operation"]
49327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
49328#[inline]
49329#[cfg(target_endian = "little")]
49330#[target_feature(enable = "neon")]
49331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49333#[cfg_attr(
49334 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49335 assert_instr(nop)
49336)]
49337#[cfg_attr(
49338 not(target_arch = "arm"),
49339 stable(feature = "neon_intrinsics", since = "1.59.0")
49340)]
49341#[cfg_attr(
49342 target_arch = "arm",
49343 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49344)]
49345pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
49346 unsafe { transmute(a) }
49347}
49348#[doc = "Vector reinterpret cast operation"]
49349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
49350#[inline]
49351#[cfg(target_endian = "big")]
49352#[target_feature(enable = "neon")]
49353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49354#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49355#[cfg_attr(
49356 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49357 assert_instr(nop)
49358)]
49359#[cfg_attr(
49360 not(target_arch = "arm"),
49361 stable(feature = "neon_intrinsics", since = "1.59.0")
49362)]
49363#[cfg_attr(
49364 target_arch = "arm",
49365 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49366)]
49367pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
49368 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49369 unsafe {
49370 let ret_val: int16x4_t = transmute(a);
49371 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49372 }
49373}
49374#[doc = "Vector reinterpret cast operation"]
49375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
49376#[inline]
49377#[cfg(target_endian = "little")]
49378#[target_feature(enable = "neon")]
49379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49380#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49381#[cfg_attr(
49382 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49383 assert_instr(nop)
49384)]
49385#[cfg_attr(
49386 not(target_arch = "arm"),
49387 stable(feature = "neon_intrinsics", since = "1.59.0")
49388)]
49389#[cfg_attr(
49390 target_arch = "arm",
49391 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49392)]
49393pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
49394 unsafe { transmute(a) }
49395}
49396#[doc = "Vector reinterpret cast operation"]
49397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
49398#[inline]
49399#[cfg(target_endian = "big")]
49400#[target_feature(enable = "neon")]
49401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49403#[cfg_attr(
49404 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49405 assert_instr(nop)
49406)]
49407#[cfg_attr(
49408 not(target_arch = "arm"),
49409 stable(feature = "neon_intrinsics", since = "1.59.0")
49410)]
49411#[cfg_attr(
49412 target_arch = "arm",
49413 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49414)]
49415pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
49416 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49417 unsafe {
49418 let ret_val: int32x2_t = transmute(a);
49419 simd_shuffle!(ret_val, ret_val, [1, 0])
49420 }
49421}
49422#[doc = "Vector reinterpret cast operation"]
49423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
49424#[inline]
49425#[cfg(target_endian = "little")]
49426#[target_feature(enable = "neon")]
49427#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49428#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49429#[cfg_attr(
49430 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49431 assert_instr(nop)
49432)]
49433#[cfg_attr(
49434 not(target_arch = "arm"),
49435 stable(feature = "neon_intrinsics", since = "1.59.0")
49436)]
49437#[cfg_attr(
49438 target_arch = "arm",
49439 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49440)]
49441pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
49442 unsafe { transmute(a) }
49443}
49444#[doc = "Vector reinterpret cast operation"]
49445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
49446#[inline]
49447#[cfg(target_endian = "big")]
49448#[target_feature(enable = "neon")]
49449#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49450#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49451#[cfg_attr(
49452 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49453 assert_instr(nop)
49454)]
49455#[cfg_attr(
49456 not(target_arch = "arm"),
49457 stable(feature = "neon_intrinsics", since = "1.59.0")
49458)]
49459#[cfg_attr(
49460 target_arch = "arm",
49461 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49462)]
49463pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
49464 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49465 unsafe { transmute(a) }
49466}
49467#[doc = "Vector reinterpret cast operation"]
49468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
49469#[inline]
49470#[cfg(target_endian = "little")]
49471#[target_feature(enable = "neon")]
49472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49474#[cfg_attr(
49475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49476 assert_instr(nop)
49477)]
49478#[cfg_attr(
49479 not(target_arch = "arm"),
49480 stable(feature = "neon_intrinsics", since = "1.59.0")
49481)]
49482#[cfg_attr(
49483 target_arch = "arm",
49484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49485)]
49486pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
49487 unsafe { transmute(a) }
49488}
49489#[doc = "Vector reinterpret cast operation"]
49490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
49491#[inline]
49492#[cfg(target_endian = "big")]
49493#[target_feature(enable = "neon")]
49494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49496#[cfg_attr(
49497 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49498 assert_instr(nop)
49499)]
49500#[cfg_attr(
49501 not(target_arch = "arm"),
49502 stable(feature = "neon_intrinsics", since = "1.59.0")
49503)]
49504#[cfg_attr(
49505 target_arch = "arm",
49506 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49507)]
49508pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
49509 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49510 unsafe {
49511 let ret_val: uint16x4_t = transmute(a);
49512 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49513 }
49514}
49515#[doc = "Vector reinterpret cast operation"]
49516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
49517#[inline]
49518#[cfg(target_endian = "little")]
49519#[target_feature(enable = "neon")]
49520#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49521#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49522#[cfg_attr(
49523 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49524 assert_instr(nop)
49525)]
49526#[cfg_attr(
49527 not(target_arch = "arm"),
49528 stable(feature = "neon_intrinsics", since = "1.59.0")
49529)]
49530#[cfg_attr(
49531 target_arch = "arm",
49532 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49533)]
49534pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
49535 unsafe { transmute(a) }
49536}
49537#[doc = "Vector reinterpret cast operation"]
49538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
49539#[inline]
49540#[cfg(target_endian = "big")]
49541#[target_feature(enable = "neon")]
49542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49544#[cfg_attr(
49545 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49546 assert_instr(nop)
49547)]
49548#[cfg_attr(
49549 not(target_arch = "arm"),
49550 stable(feature = "neon_intrinsics", since = "1.59.0")
49551)]
49552#[cfg_attr(
49553 target_arch = "arm",
49554 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49555)]
49556pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
49557 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49558 unsafe {
49559 let ret_val: uint32x2_t = transmute(a);
49560 simd_shuffle!(ret_val, ret_val, [1, 0])
49561 }
49562}
49563#[doc = "Vector reinterpret cast operation"]
49564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
49565#[inline]
49566#[cfg(target_endian = "little")]
49567#[target_feature(enable = "neon")]
49568#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49569#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49570#[cfg_attr(
49571 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49572 assert_instr(nop)
49573)]
49574#[cfg_attr(
49575 not(target_arch = "arm"),
49576 stable(feature = "neon_intrinsics", since = "1.59.0")
49577)]
49578#[cfg_attr(
49579 target_arch = "arm",
49580 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49581)]
49582pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
49583 unsafe { transmute(a) }
49584}
49585#[doc = "Vector reinterpret cast operation"]
49586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
49587#[inline]
49588#[cfg(target_endian = "big")]
49589#[target_feature(enable = "neon")]
49590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49591#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49592#[cfg_attr(
49593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49594 assert_instr(nop)
49595)]
49596#[cfg_attr(
49597 not(target_arch = "arm"),
49598 stable(feature = "neon_intrinsics", since = "1.59.0")
49599)]
49600#[cfg_attr(
49601 target_arch = "arm",
49602 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49603)]
49604pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
49605 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49606 unsafe { transmute(a) }
49607}
49608#[doc = "Vector reinterpret cast operation"]
49609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
49610#[inline]
49611#[cfg(target_endian = "little")]
49612#[target_feature(enable = "neon")]
49613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49614#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49615#[cfg_attr(
49616 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49617 assert_instr(nop)
49618)]
49619#[cfg_attr(
49620 not(target_arch = "arm"),
49621 stable(feature = "neon_intrinsics", since = "1.59.0")
49622)]
49623#[cfg_attr(
49624 target_arch = "arm",
49625 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49626)]
49627pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
49628 unsafe { transmute(a) }
49629}
49630#[doc = "Vector reinterpret cast operation"]
49631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
49632#[inline]
49633#[cfg(target_endian = "big")]
49634#[target_feature(enable = "neon")]
49635#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49636#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49637#[cfg_attr(
49638 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49639 assert_instr(nop)
49640)]
49641#[cfg_attr(
49642 not(target_arch = "arm"),
49643 stable(feature = "neon_intrinsics", since = "1.59.0")
49644)]
49645#[cfg_attr(
49646 target_arch = "arm",
49647 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49648)]
49649pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
49650 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49651 unsafe {
49652 let ret_val: poly8x8_t = transmute(a);
49653 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49654 }
49655}
49656#[doc = "Vector reinterpret cast operation"]
49657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
49658#[inline]
49659#[cfg(target_endian = "little")]
49660#[target_feature(enable = "neon")]
49661#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49662#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49663#[cfg_attr(
49664 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49665 assert_instr(nop)
49666)]
49667#[cfg_attr(
49668 not(target_arch = "arm"),
49669 stable(feature = "neon_intrinsics", since = "1.59.0")
49670)]
49671#[cfg_attr(
49672 target_arch = "arm",
49673 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49674)]
49675pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
49676 unsafe { transmute(a) }
49677}
49678#[doc = "Vector reinterpret cast operation"]
49679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
49680#[inline]
49681#[cfg(target_endian = "big")]
49682#[target_feature(enable = "neon")]
49683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49685#[cfg_attr(
49686 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49687 assert_instr(nop)
49688)]
49689#[cfg_attr(
49690 not(target_arch = "arm"),
49691 stable(feature = "neon_intrinsics", since = "1.59.0")
49692)]
49693#[cfg_attr(
49694 target_arch = "arm",
49695 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49696)]
49697pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
49698 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49699 unsafe {
49700 let ret_val: poly16x4_t = transmute(a);
49701 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49702 }
49703}
49704#[doc = "Vector reinterpret cast operation"]
49705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
49706#[inline]
49707#[cfg(target_endian = "little")]
49708#[target_feature(enable = "neon")]
49709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49711#[cfg_attr(
49712 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49713 assert_instr(nop)
49714)]
49715#[cfg_attr(
49716 not(target_arch = "arm"),
49717 stable(feature = "neon_intrinsics", since = "1.59.0")
49718)]
49719#[cfg_attr(
49720 target_arch = "arm",
49721 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49722)]
49723pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
49724 unsafe { transmute(a) }
49725}
49726#[doc = "Vector reinterpret cast operation"]
49727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
49728#[inline]
49729#[cfg(target_endian = "big")]
49730#[target_feature(enable = "neon")]
49731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49733#[cfg_attr(
49734 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49735 assert_instr(nop)
49736)]
49737#[cfg_attr(
49738 not(target_arch = "arm"),
49739 stable(feature = "neon_intrinsics", since = "1.59.0")
49740)]
49741#[cfg_attr(
49742 target_arch = "arm",
49743 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49744)]
49745pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
49746 let a: uint8x16_t =
49747 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49748 unsafe {
49749 let ret_val: float32x4_t = transmute(a);
49750 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49751 }
49752}
49753#[doc = "Vector reinterpret cast operation"]
49754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
49755#[inline]
49756#[cfg(target_endian = "little")]
49757#[target_feature(enable = "neon")]
49758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49759#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49760#[cfg_attr(
49761 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49762 assert_instr(nop)
49763)]
49764#[cfg_attr(
49765 not(target_arch = "arm"),
49766 stable(feature = "neon_intrinsics", since = "1.59.0")
49767)]
49768#[cfg_attr(
49769 target_arch = "arm",
49770 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49771)]
49772pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
49773 unsafe { transmute(a) }
49774}
49775#[doc = "Vector reinterpret cast operation"]
49776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
49777#[inline]
49778#[cfg(target_endian = "big")]
49779#[target_feature(enable = "neon")]
49780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49782#[cfg_attr(
49783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49784 assert_instr(nop)
49785)]
49786#[cfg_attr(
49787 not(target_arch = "arm"),
49788 stable(feature = "neon_intrinsics", since = "1.59.0")
49789)]
49790#[cfg_attr(
49791 target_arch = "arm",
49792 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49793)]
49794pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
49795 let a: uint8x16_t =
49796 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49797 unsafe {
49798 let ret_val: int8x16_t = transmute(a);
49799 simd_shuffle!(
49800 ret_val,
49801 ret_val,
49802 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
49803 )
49804 }
49805}
49806#[doc = "Vector reinterpret cast operation"]
49807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
49808#[inline]
49809#[cfg(target_endian = "little")]
49810#[target_feature(enable = "neon")]
49811#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49812#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49813#[cfg_attr(
49814 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49815 assert_instr(nop)
49816)]
49817#[cfg_attr(
49818 not(target_arch = "arm"),
49819 stable(feature = "neon_intrinsics", since = "1.59.0")
49820)]
49821#[cfg_attr(
49822 target_arch = "arm",
49823 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49824)]
49825pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
49826 unsafe { transmute(a) }
49827}
49828#[doc = "Vector reinterpret cast operation"]
49829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
49830#[inline]
49831#[cfg(target_endian = "big")]
49832#[target_feature(enable = "neon")]
49833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49834#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49835#[cfg_attr(
49836 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49837 assert_instr(nop)
49838)]
49839#[cfg_attr(
49840 not(target_arch = "arm"),
49841 stable(feature = "neon_intrinsics", since = "1.59.0")
49842)]
49843#[cfg_attr(
49844 target_arch = "arm",
49845 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49846)]
49847pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
49848 let a: uint8x16_t =
49849 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49850 unsafe {
49851 let ret_val: int16x8_t = transmute(a);
49852 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49853 }
49854}
49855#[doc = "Vector reinterpret cast operation"]
49856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
49857#[inline]
49858#[cfg(target_endian = "little")]
49859#[target_feature(enable = "neon")]
49860#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49861#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49862#[cfg_attr(
49863 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49864 assert_instr(nop)
49865)]
49866#[cfg_attr(
49867 not(target_arch = "arm"),
49868 stable(feature = "neon_intrinsics", since = "1.59.0")
49869)]
49870#[cfg_attr(
49871 target_arch = "arm",
49872 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49873)]
49874pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
49875 unsafe { transmute(a) }
49876}
49877#[doc = "Vector reinterpret cast operation"]
49878#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
49879#[inline]
49880#[cfg(target_endian = "big")]
49881#[target_feature(enable = "neon")]
49882#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49883#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49884#[cfg_attr(
49885 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49886 assert_instr(nop)
49887)]
49888#[cfg_attr(
49889 not(target_arch = "arm"),
49890 stable(feature = "neon_intrinsics", since = "1.59.0")
49891)]
49892#[cfg_attr(
49893 target_arch = "arm",
49894 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49895)]
49896pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
49897 let a: uint8x16_t =
49898 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49899 unsafe {
49900 let ret_val: int32x4_t = transmute(a);
49901 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49902 }
49903}
49904#[doc = "Vector reinterpret cast operation"]
49905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
49906#[inline]
49907#[cfg(target_endian = "little")]
49908#[target_feature(enable = "neon")]
49909#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49910#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49911#[cfg_attr(
49912 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49913 assert_instr(nop)
49914)]
49915#[cfg_attr(
49916 not(target_arch = "arm"),
49917 stable(feature = "neon_intrinsics", since = "1.59.0")
49918)]
49919#[cfg_attr(
49920 target_arch = "arm",
49921 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49922)]
49923pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
49924 unsafe { transmute(a) }
49925}
49926#[doc = "Vector reinterpret cast operation"]
49927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
49928#[inline]
49929#[cfg(target_endian = "big")]
49930#[target_feature(enable = "neon")]
49931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49933#[cfg_attr(
49934 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49935 assert_instr(nop)
49936)]
49937#[cfg_attr(
49938 not(target_arch = "arm"),
49939 stable(feature = "neon_intrinsics", since = "1.59.0")
49940)]
49941#[cfg_attr(
49942 target_arch = "arm",
49943 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49944)]
49945pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
49946 let a: uint8x16_t =
49947 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49948 unsafe {
49949 let ret_val: int64x2_t = transmute(a);
49950 simd_shuffle!(ret_val, ret_val, [1, 0])
49951 }
49952}
49953#[doc = "Vector reinterpret cast operation"]
49954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
49955#[inline]
49956#[cfg(target_endian = "little")]
49957#[target_feature(enable = "neon")]
49958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49960#[cfg_attr(
49961 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49962 assert_instr(nop)
49963)]
49964#[cfg_attr(
49965 not(target_arch = "arm"),
49966 stable(feature = "neon_intrinsics", since = "1.59.0")
49967)]
49968#[cfg_attr(
49969 target_arch = "arm",
49970 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49971)]
49972pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
49973 unsafe { transmute(a) }
49974}
49975#[doc = "Vector reinterpret cast operation"]
49976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
49977#[inline]
49978#[cfg(target_endian = "big")]
49979#[target_feature(enable = "neon")]
49980#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49981#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49982#[cfg_attr(
49983 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49984 assert_instr(nop)
49985)]
49986#[cfg_attr(
49987 not(target_arch = "arm"),
49988 stable(feature = "neon_intrinsics", since = "1.59.0")
49989)]
49990#[cfg_attr(
49991 target_arch = "arm",
49992 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49993)]
49994pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
49995 let a: uint8x16_t =
49996 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49997 unsafe {
49998 let ret_val: uint16x8_t = transmute(a);
49999 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50000 }
50001}
50002#[doc = "Vector reinterpret cast operation"]
50003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
50004#[inline]
50005#[cfg(target_endian = "little")]
50006#[target_feature(enable = "neon")]
50007#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50008#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50009#[cfg_attr(
50010 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50011 assert_instr(nop)
50012)]
50013#[cfg_attr(
50014 not(target_arch = "arm"),
50015 stable(feature = "neon_intrinsics", since = "1.59.0")
50016)]
50017#[cfg_attr(
50018 target_arch = "arm",
50019 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50020)]
50021pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
50022 unsafe { transmute(a) }
50023}
50024#[doc = "Vector reinterpret cast operation"]
50025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
50026#[inline]
50027#[cfg(target_endian = "big")]
50028#[target_feature(enable = "neon")]
50029#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50030#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50031#[cfg_attr(
50032 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50033 assert_instr(nop)
50034)]
50035#[cfg_attr(
50036 not(target_arch = "arm"),
50037 stable(feature = "neon_intrinsics", since = "1.59.0")
50038)]
50039#[cfg_attr(
50040 target_arch = "arm",
50041 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50042)]
50043pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
50044 let a: uint8x16_t =
50045 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50046 unsafe {
50047 let ret_val: uint32x4_t = transmute(a);
50048 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50049 }
50050}
50051#[doc = "Vector reinterpret cast operation"]
50052#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
50053#[inline]
50054#[cfg(target_endian = "little")]
50055#[target_feature(enable = "neon")]
50056#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50057#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50058#[cfg_attr(
50059 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50060 assert_instr(nop)
50061)]
50062#[cfg_attr(
50063 not(target_arch = "arm"),
50064 stable(feature = "neon_intrinsics", since = "1.59.0")
50065)]
50066#[cfg_attr(
50067 target_arch = "arm",
50068 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50069)]
50070pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
50071 unsafe { transmute(a) }
50072}
50073#[doc = "Vector reinterpret cast operation"]
50074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
50075#[inline]
50076#[cfg(target_endian = "big")]
50077#[target_feature(enable = "neon")]
50078#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50079#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50080#[cfg_attr(
50081 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50082 assert_instr(nop)
50083)]
50084#[cfg_attr(
50085 not(target_arch = "arm"),
50086 stable(feature = "neon_intrinsics", since = "1.59.0")
50087)]
50088#[cfg_attr(
50089 target_arch = "arm",
50090 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50091)]
50092pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
50093 let a: uint8x16_t =
50094 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50095 unsafe {
50096 let ret_val: uint64x2_t = transmute(a);
50097 simd_shuffle!(ret_val, ret_val, [1, 0])
50098 }
50099}
50100#[doc = "Vector reinterpret cast operation"]
50101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
50102#[inline]
50103#[cfg(target_endian = "little")]
50104#[target_feature(enable = "neon")]
50105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50106#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50107#[cfg_attr(
50108 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50109 assert_instr(nop)
50110)]
50111#[cfg_attr(
50112 not(target_arch = "arm"),
50113 stable(feature = "neon_intrinsics", since = "1.59.0")
50114)]
50115#[cfg_attr(
50116 target_arch = "arm",
50117 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50118)]
50119pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
50120 unsafe { transmute(a) }
50121}
50122#[doc = "Vector reinterpret cast operation"]
50123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
50124#[inline]
50125#[cfg(target_endian = "big")]
50126#[target_feature(enable = "neon")]
50127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50128#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50129#[cfg_attr(
50130 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50131 assert_instr(nop)
50132)]
50133#[cfg_attr(
50134 not(target_arch = "arm"),
50135 stable(feature = "neon_intrinsics", since = "1.59.0")
50136)]
50137#[cfg_attr(
50138 target_arch = "arm",
50139 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50140)]
50141pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
50142 let a: uint8x16_t =
50143 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50144 unsafe {
50145 let ret_val: poly8x16_t = transmute(a);
50146 simd_shuffle!(
50147 ret_val,
50148 ret_val,
50149 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50150 )
50151 }
50152}
50153#[doc = "Vector reinterpret cast operation"]
50154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
50155#[inline]
50156#[cfg(target_endian = "little")]
50157#[target_feature(enable = "neon")]
50158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50160#[cfg_attr(
50161 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50162 assert_instr(nop)
50163)]
50164#[cfg_attr(
50165 not(target_arch = "arm"),
50166 stable(feature = "neon_intrinsics", since = "1.59.0")
50167)]
50168#[cfg_attr(
50169 target_arch = "arm",
50170 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50171)]
50172pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
50173 unsafe { transmute(a) }
50174}
50175#[doc = "Vector reinterpret cast operation"]
50176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
50177#[inline]
50178#[cfg(target_endian = "big")]
50179#[target_feature(enable = "neon")]
50180#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50181#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50182#[cfg_attr(
50183 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50184 assert_instr(nop)
50185)]
50186#[cfg_attr(
50187 not(target_arch = "arm"),
50188 stable(feature = "neon_intrinsics", since = "1.59.0")
50189)]
50190#[cfg_attr(
50191 target_arch = "arm",
50192 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50193)]
50194pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
50195 let a: uint8x16_t =
50196 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
50197 unsafe {
50198 let ret_val: poly16x8_t = transmute(a);
50199 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50200 }
50201}
50202#[doc = "Vector reinterpret cast operation"]
50203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
50204#[inline]
50205#[cfg(target_endian = "little")]
50206#[target_feature(enable = "neon")]
50207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50208#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50209#[cfg_attr(
50210 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50211 assert_instr(nop)
50212)]
50213#[cfg_attr(
50214 not(target_arch = "arm"),
50215 stable(feature = "neon_intrinsics", since = "1.59.0")
50216)]
50217#[cfg_attr(
50218 target_arch = "arm",
50219 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50220)]
50221pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
50222 unsafe { transmute(a) }
50223}
50224#[doc = "Vector reinterpret cast operation"]
50225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
50226#[inline]
50227#[cfg(target_endian = "big")]
50228#[target_feature(enable = "neon")]
50229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50230#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50231#[cfg_attr(
50232 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50233 assert_instr(nop)
50234)]
50235#[cfg_attr(
50236 not(target_arch = "arm"),
50237 stable(feature = "neon_intrinsics", since = "1.59.0")
50238)]
50239#[cfg_attr(
50240 target_arch = "arm",
50241 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50242)]
50243pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
50244 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50245 unsafe {
50246 let ret_val: float32x2_t = transmute(a);
50247 simd_shuffle!(ret_val, ret_val, [1, 0])
50248 }
50249}
50250#[doc = "Vector reinterpret cast operation"]
50251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
50252#[inline]
50253#[cfg(target_endian = "little")]
50254#[target_feature(enable = "neon")]
50255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50257#[cfg_attr(
50258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50259 assert_instr(nop)
50260)]
50261#[cfg_attr(
50262 not(target_arch = "arm"),
50263 stable(feature = "neon_intrinsics", since = "1.59.0")
50264)]
50265#[cfg_attr(
50266 target_arch = "arm",
50267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50268)]
50269pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
50270 unsafe { transmute(a) }
50271}
50272#[doc = "Vector reinterpret cast operation"]
50273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
50274#[inline]
50275#[cfg(target_endian = "big")]
50276#[target_feature(enable = "neon")]
50277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50278#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50279#[cfg_attr(
50280 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50281 assert_instr(nop)
50282)]
50283#[cfg_attr(
50284 not(target_arch = "arm"),
50285 stable(feature = "neon_intrinsics", since = "1.59.0")
50286)]
50287#[cfg_attr(
50288 target_arch = "arm",
50289 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50290)]
50291pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
50292 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50293 unsafe {
50294 let ret_val: int8x8_t = transmute(a);
50295 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50296 }
50297}
50298#[doc = "Vector reinterpret cast operation"]
50299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
50300#[inline]
50301#[cfg(target_endian = "little")]
50302#[target_feature(enable = "neon")]
50303#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50304#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50305#[cfg_attr(
50306 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50307 assert_instr(nop)
50308)]
50309#[cfg_attr(
50310 not(target_arch = "arm"),
50311 stable(feature = "neon_intrinsics", since = "1.59.0")
50312)]
50313#[cfg_attr(
50314 target_arch = "arm",
50315 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50316)]
50317pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
50318 unsafe { transmute(a) }
50319}
50320#[doc = "Vector reinterpret cast operation"]
50321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
50322#[inline]
50323#[cfg(target_endian = "big")]
50324#[target_feature(enable = "neon")]
50325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50327#[cfg_attr(
50328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50329 assert_instr(nop)
50330)]
50331#[cfg_attr(
50332 not(target_arch = "arm"),
50333 stable(feature = "neon_intrinsics", since = "1.59.0")
50334)]
50335#[cfg_attr(
50336 target_arch = "arm",
50337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50338)]
50339pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
50340 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50341 unsafe {
50342 let ret_val: int16x4_t = transmute(a);
50343 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50344 }
50345}
50346#[doc = "Vector reinterpret cast operation"]
50347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
50348#[inline]
50349#[cfg(target_endian = "little")]
50350#[target_feature(enable = "neon")]
50351#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50352#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50353#[cfg_attr(
50354 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50355 assert_instr(nop)
50356)]
50357#[cfg_attr(
50358 not(target_arch = "arm"),
50359 stable(feature = "neon_intrinsics", since = "1.59.0")
50360)]
50361#[cfg_attr(
50362 target_arch = "arm",
50363 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50364)]
50365pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
50366 unsafe { transmute(a) }
50367}
50368#[doc = "Vector reinterpret cast operation"]
50369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
50370#[inline]
50371#[cfg(target_endian = "big")]
50372#[target_feature(enable = "neon")]
50373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50375#[cfg_attr(
50376 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50377 assert_instr(nop)
50378)]
50379#[cfg_attr(
50380 not(target_arch = "arm"),
50381 stable(feature = "neon_intrinsics", since = "1.59.0")
50382)]
50383#[cfg_attr(
50384 target_arch = "arm",
50385 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50386)]
50387pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
50388 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50389 unsafe {
50390 let ret_val: int32x2_t = transmute(a);
50391 simd_shuffle!(ret_val, ret_val, [1, 0])
50392 }
50393}
50394#[doc = "Vector reinterpret cast operation"]
50395#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
50396#[inline]
50397#[cfg(target_endian = "little")]
50398#[target_feature(enable = "neon")]
50399#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50400#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50401#[cfg_attr(
50402 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50403 assert_instr(nop)
50404)]
50405#[cfg_attr(
50406 not(target_arch = "arm"),
50407 stable(feature = "neon_intrinsics", since = "1.59.0")
50408)]
50409#[cfg_attr(
50410 target_arch = "arm",
50411 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50412)]
50413pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
50414 unsafe { transmute(a) }
50415}
50416#[doc = "Vector reinterpret cast operation"]
50417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
50418#[inline]
50419#[cfg(target_endian = "big")]
50420#[target_feature(enable = "neon")]
50421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50423#[cfg_attr(
50424 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50425 assert_instr(nop)
50426)]
50427#[cfg_attr(
50428 not(target_arch = "arm"),
50429 stable(feature = "neon_intrinsics", since = "1.59.0")
50430)]
50431#[cfg_attr(
50432 target_arch = "arm",
50433 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50434)]
50435pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
50436 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50437 unsafe { transmute(a) }
50438}
50439#[doc = "Vector reinterpret cast operation"]
50440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
50441#[inline]
50442#[cfg(target_endian = "little")]
50443#[target_feature(enable = "neon")]
50444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50446#[cfg_attr(
50447 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50448 assert_instr(nop)
50449)]
50450#[cfg_attr(
50451 not(target_arch = "arm"),
50452 stable(feature = "neon_intrinsics", since = "1.59.0")
50453)]
50454#[cfg_attr(
50455 target_arch = "arm",
50456 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50457)]
50458pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
50459 unsafe { transmute(a) }
50460}
50461#[doc = "Vector reinterpret cast operation"]
50462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
50463#[inline]
50464#[cfg(target_endian = "big")]
50465#[target_feature(enable = "neon")]
50466#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50467#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50468#[cfg_attr(
50469 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50470 assert_instr(nop)
50471)]
50472#[cfg_attr(
50473 not(target_arch = "arm"),
50474 stable(feature = "neon_intrinsics", since = "1.59.0")
50475)]
50476#[cfg_attr(
50477 target_arch = "arm",
50478 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50479)]
50480pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
50481 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50482 unsafe {
50483 let ret_val: uint8x8_t = transmute(a);
50484 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50485 }
50486}
50487#[doc = "Vector reinterpret cast operation"]
50488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
50489#[inline]
50490#[cfg(target_endian = "little")]
50491#[target_feature(enable = "neon")]
50492#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50493#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50494#[cfg_attr(
50495 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50496 assert_instr(nop)
50497)]
50498#[cfg_attr(
50499 not(target_arch = "arm"),
50500 stable(feature = "neon_intrinsics", since = "1.59.0")
50501)]
50502#[cfg_attr(
50503 target_arch = "arm",
50504 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50505)]
50506pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
50507 unsafe { transmute(a) }
50508}
50509#[doc = "Vector reinterpret cast operation"]
50510#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
50511#[inline]
50512#[cfg(target_endian = "big")]
50513#[target_feature(enable = "neon")]
50514#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50515#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50516#[cfg_attr(
50517 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50518 assert_instr(nop)
50519)]
50520#[cfg_attr(
50521 not(target_arch = "arm"),
50522 stable(feature = "neon_intrinsics", since = "1.59.0")
50523)]
50524#[cfg_attr(
50525 target_arch = "arm",
50526 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50527)]
50528pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
50529 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50530 unsafe {
50531 let ret_val: uint32x2_t = transmute(a);
50532 simd_shuffle!(ret_val, ret_val, [1, 0])
50533 }
50534}
50535#[doc = "Vector reinterpret cast operation"]
50536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
50537#[inline]
50538#[cfg(target_endian = "little")]
50539#[target_feature(enable = "neon")]
50540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50541#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50542#[cfg_attr(
50543 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50544 assert_instr(nop)
50545)]
50546#[cfg_attr(
50547 not(target_arch = "arm"),
50548 stable(feature = "neon_intrinsics", since = "1.59.0")
50549)]
50550#[cfg_attr(
50551 target_arch = "arm",
50552 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50553)]
50554pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
50555 unsafe { transmute(a) }
50556}
50557#[doc = "Vector reinterpret cast operation"]
50558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
50559#[inline]
50560#[cfg(target_endian = "big")]
50561#[target_feature(enable = "neon")]
50562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50564#[cfg_attr(
50565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50566 assert_instr(nop)
50567)]
50568#[cfg_attr(
50569 not(target_arch = "arm"),
50570 stable(feature = "neon_intrinsics", since = "1.59.0")
50571)]
50572#[cfg_attr(
50573 target_arch = "arm",
50574 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50575)]
50576pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
50577 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50578 unsafe { transmute(a) }
50579}
50580#[doc = "Vector reinterpret cast operation"]
50581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
50582#[inline]
50583#[cfg(target_endian = "little")]
50584#[target_feature(enable = "neon")]
50585#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50586#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50587#[cfg_attr(
50588 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50589 assert_instr(nop)
50590)]
50591#[cfg_attr(
50592 not(target_arch = "arm"),
50593 stable(feature = "neon_intrinsics", since = "1.59.0")
50594)]
50595#[cfg_attr(
50596 target_arch = "arm",
50597 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50598)]
50599pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
50600 unsafe { transmute(a) }
50601}
50602#[doc = "Vector reinterpret cast operation"]
50603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
50604#[inline]
50605#[cfg(target_endian = "big")]
50606#[target_feature(enable = "neon")]
50607#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50608#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50609#[cfg_attr(
50610 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50611 assert_instr(nop)
50612)]
50613#[cfg_attr(
50614 not(target_arch = "arm"),
50615 stable(feature = "neon_intrinsics", since = "1.59.0")
50616)]
50617#[cfg_attr(
50618 target_arch = "arm",
50619 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50620)]
50621pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
50622 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50623 unsafe {
50624 let ret_val: poly8x8_t = transmute(a);
50625 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50626 }
50627}
50628#[doc = "Vector reinterpret cast operation"]
50629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
50630#[inline]
50631#[cfg(target_endian = "little")]
50632#[target_feature(enable = "neon")]
50633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50634#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50635#[cfg_attr(
50636 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50637 assert_instr(nop)
50638)]
50639#[cfg_attr(
50640 not(target_arch = "arm"),
50641 stable(feature = "neon_intrinsics", since = "1.59.0")
50642)]
50643#[cfg_attr(
50644 target_arch = "arm",
50645 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50646)]
50647pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
50648 unsafe { transmute(a) }
50649}
50650#[doc = "Vector reinterpret cast operation"]
50651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
50652#[inline]
50653#[cfg(target_endian = "big")]
50654#[target_feature(enable = "neon")]
50655#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50656#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50657#[cfg_attr(
50658 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50659 assert_instr(nop)
50660)]
50661#[cfg_attr(
50662 not(target_arch = "arm"),
50663 stable(feature = "neon_intrinsics", since = "1.59.0")
50664)]
50665#[cfg_attr(
50666 target_arch = "arm",
50667 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50668)]
50669pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
50670 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50671 unsafe {
50672 let ret_val: poly16x4_t = transmute(a);
50673 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50674 }
50675}
50676#[doc = "Vector reinterpret cast operation"]
50677#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
50678#[inline]
50679#[cfg(target_endian = "little")]
50680#[target_feature(enable = "neon")]
50681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50682#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50683#[cfg_attr(
50684 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50685 assert_instr(nop)
50686)]
50687#[cfg_attr(
50688 not(target_arch = "arm"),
50689 stable(feature = "neon_intrinsics", since = "1.59.0")
50690)]
50691#[cfg_attr(
50692 target_arch = "arm",
50693 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50694)]
50695pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
50696 unsafe { transmute(a) }
50697}
50698#[doc = "Vector reinterpret cast operation"]
50699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
50700#[inline]
50701#[cfg(target_endian = "big")]
50702#[target_feature(enable = "neon")]
50703#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50704#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50705#[cfg_attr(
50706 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50707 assert_instr(nop)
50708)]
50709#[cfg_attr(
50710 not(target_arch = "arm"),
50711 stable(feature = "neon_intrinsics", since = "1.59.0")
50712)]
50713#[cfg_attr(
50714 target_arch = "arm",
50715 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50716)]
50717pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
50718 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50719 unsafe {
50720 let ret_val: float32x4_t = transmute(a);
50721 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50722 }
50723}
50724#[doc = "Vector reinterpret cast operation"]
50725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
50726#[inline]
50727#[cfg(target_endian = "little")]
50728#[target_feature(enable = "neon")]
50729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50730#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50731#[cfg_attr(
50732 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50733 assert_instr(nop)
50734)]
50735#[cfg_attr(
50736 not(target_arch = "arm"),
50737 stable(feature = "neon_intrinsics", since = "1.59.0")
50738)]
50739#[cfg_attr(
50740 target_arch = "arm",
50741 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50742)]
50743pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
50744 unsafe { transmute(a) }
50745}
50746#[doc = "Vector reinterpret cast operation"]
50747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
50748#[inline]
50749#[cfg(target_endian = "big")]
50750#[target_feature(enable = "neon")]
50751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50752#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50753#[cfg_attr(
50754 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50755 assert_instr(nop)
50756)]
50757#[cfg_attr(
50758 not(target_arch = "arm"),
50759 stable(feature = "neon_intrinsics", since = "1.59.0")
50760)]
50761#[cfg_attr(
50762 target_arch = "arm",
50763 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50764)]
50765pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
50766 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50767 unsafe {
50768 let ret_val: int8x16_t = transmute(a);
50769 simd_shuffle!(
50770 ret_val,
50771 ret_val,
50772 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50773 )
50774 }
50775}
50776#[doc = "Vector reinterpret cast operation"]
50777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
50778#[inline]
50779#[cfg(target_endian = "little")]
50780#[target_feature(enable = "neon")]
50781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50783#[cfg_attr(
50784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50785 assert_instr(nop)
50786)]
50787#[cfg_attr(
50788 not(target_arch = "arm"),
50789 stable(feature = "neon_intrinsics", since = "1.59.0")
50790)]
50791#[cfg_attr(
50792 target_arch = "arm",
50793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50794)]
50795pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
50796 unsafe { transmute(a) }
50797}
50798#[doc = "Vector reinterpret cast operation"]
50799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
50800#[inline]
50801#[cfg(target_endian = "big")]
50802#[target_feature(enable = "neon")]
50803#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50804#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50805#[cfg_attr(
50806 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50807 assert_instr(nop)
50808)]
50809#[cfg_attr(
50810 not(target_arch = "arm"),
50811 stable(feature = "neon_intrinsics", since = "1.59.0")
50812)]
50813#[cfg_attr(
50814 target_arch = "arm",
50815 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50816)]
50817pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
50818 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50819 unsafe {
50820 let ret_val: int16x8_t = transmute(a);
50821 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50822 }
50823}
50824#[doc = "Vector reinterpret cast operation"]
50825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
50826#[inline]
50827#[cfg(target_endian = "little")]
50828#[target_feature(enable = "neon")]
50829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50831#[cfg_attr(
50832 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50833 assert_instr(nop)
50834)]
50835#[cfg_attr(
50836 not(target_arch = "arm"),
50837 stable(feature = "neon_intrinsics", since = "1.59.0")
50838)]
50839#[cfg_attr(
50840 target_arch = "arm",
50841 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50842)]
50843pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
50844 unsafe { transmute(a) }
50845}
50846#[doc = "Vector reinterpret cast operation"]
50847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
50848#[inline]
50849#[cfg(target_endian = "big")]
50850#[target_feature(enable = "neon")]
50851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50852#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50853#[cfg_attr(
50854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50855 assert_instr(nop)
50856)]
50857#[cfg_attr(
50858 not(target_arch = "arm"),
50859 stable(feature = "neon_intrinsics", since = "1.59.0")
50860)]
50861#[cfg_attr(
50862 target_arch = "arm",
50863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50864)]
50865pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
50866 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50867 unsafe {
50868 let ret_val: int32x4_t = transmute(a);
50869 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50870 }
50871}
50872#[doc = "Vector reinterpret cast operation"]
50873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
50874#[inline]
50875#[cfg(target_endian = "little")]
50876#[target_feature(enable = "neon")]
50877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50878#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50879#[cfg_attr(
50880 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50881 assert_instr(nop)
50882)]
50883#[cfg_attr(
50884 not(target_arch = "arm"),
50885 stable(feature = "neon_intrinsics", since = "1.59.0")
50886)]
50887#[cfg_attr(
50888 target_arch = "arm",
50889 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50890)]
50891pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
50892 unsafe { transmute(a) }
50893}
50894#[doc = "Vector reinterpret cast operation"]
50895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
50896#[inline]
50897#[cfg(target_endian = "big")]
50898#[target_feature(enable = "neon")]
50899#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50900#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50901#[cfg_attr(
50902 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50903 assert_instr(nop)
50904)]
50905#[cfg_attr(
50906 not(target_arch = "arm"),
50907 stable(feature = "neon_intrinsics", since = "1.59.0")
50908)]
50909#[cfg_attr(
50910 target_arch = "arm",
50911 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50912)]
50913pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
50914 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50915 unsafe {
50916 let ret_val: int64x2_t = transmute(a);
50917 simd_shuffle!(ret_val, ret_val, [1, 0])
50918 }
50919}
50920#[doc = "Vector reinterpret cast operation"]
50921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
50922#[inline]
50923#[cfg(target_endian = "little")]
50924#[target_feature(enable = "neon")]
50925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50926#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50927#[cfg_attr(
50928 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50929 assert_instr(nop)
50930)]
50931#[cfg_attr(
50932 not(target_arch = "arm"),
50933 stable(feature = "neon_intrinsics", since = "1.59.0")
50934)]
50935#[cfg_attr(
50936 target_arch = "arm",
50937 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50938)]
50939pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
50940 unsafe { transmute(a) }
50941}
50942#[doc = "Vector reinterpret cast operation"]
50943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
50944#[inline]
50945#[cfg(target_endian = "big")]
50946#[target_feature(enable = "neon")]
50947#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50948#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50949#[cfg_attr(
50950 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50951 assert_instr(nop)
50952)]
50953#[cfg_attr(
50954 not(target_arch = "arm"),
50955 stable(feature = "neon_intrinsics", since = "1.59.0")
50956)]
50957#[cfg_attr(
50958 target_arch = "arm",
50959 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50960)]
50961pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
50962 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50963 unsafe {
50964 let ret_val: uint8x16_t = transmute(a);
50965 simd_shuffle!(
50966 ret_val,
50967 ret_val,
50968 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50969 )
50970 }
50971}
50972#[doc = "Vector reinterpret cast operation"]
50973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
50974#[inline]
50975#[cfg(target_endian = "little")]
50976#[target_feature(enable = "neon")]
50977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50978#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50979#[cfg_attr(
50980 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50981 assert_instr(nop)
50982)]
50983#[cfg_attr(
50984 not(target_arch = "arm"),
50985 stable(feature = "neon_intrinsics", since = "1.59.0")
50986)]
50987#[cfg_attr(
50988 target_arch = "arm",
50989 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50990)]
50991pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
50992 unsafe { transmute(a) }
50993}
50994#[doc = "Vector reinterpret cast operation"]
50995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
50996#[inline]
50997#[cfg(target_endian = "big")]
50998#[target_feature(enable = "neon")]
50999#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51000#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51001#[cfg_attr(
51002 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51003 assert_instr(nop)
51004)]
51005#[cfg_attr(
51006 not(target_arch = "arm"),
51007 stable(feature = "neon_intrinsics", since = "1.59.0")
51008)]
51009#[cfg_attr(
51010 target_arch = "arm",
51011 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51012)]
51013pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
51014 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
51015 unsafe {
51016 let ret_val: uint32x4_t = transmute(a);
51017 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51018 }
51019}
51020#[doc = "Vector reinterpret cast operation"]
51021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
51022#[inline]
51023#[cfg(target_endian = "little")]
51024#[target_feature(enable = "neon")]
51025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51027#[cfg_attr(
51028 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51029 assert_instr(nop)
51030)]
51031#[cfg_attr(
51032 not(target_arch = "arm"),
51033 stable(feature = "neon_intrinsics", since = "1.59.0")
51034)]
51035#[cfg_attr(
51036 target_arch = "arm",
51037 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51038)]
51039pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
51040 unsafe { transmute(a) }
51041}
51042#[doc = "Vector reinterpret cast operation"]
51043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
51044#[inline]
51045#[cfg(target_endian = "big")]
51046#[target_feature(enable = "neon")]
51047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51048#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51049#[cfg_attr(
51050 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51051 assert_instr(nop)
51052)]
51053#[cfg_attr(
51054 not(target_arch = "arm"),
51055 stable(feature = "neon_intrinsics", since = "1.59.0")
51056)]
51057#[cfg_attr(
51058 target_arch = "arm",
51059 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51060)]
51061pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
51062 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
51063 unsafe {
51064 let ret_val: uint64x2_t = transmute(a);
51065 simd_shuffle!(ret_val, ret_val, [1, 0])
51066 }
51067}
51068#[doc = "Vector reinterpret cast operation"]
51069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
51070#[inline]
51071#[cfg(target_endian = "little")]
51072#[target_feature(enable = "neon")]
51073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51074#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51075#[cfg_attr(
51076 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51077 assert_instr(nop)
51078)]
51079#[cfg_attr(
51080 not(target_arch = "arm"),
51081 stable(feature = "neon_intrinsics", since = "1.59.0")
51082)]
51083#[cfg_attr(
51084 target_arch = "arm",
51085 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51086)]
51087pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
51088 unsafe { transmute(a) }
51089}
51090#[doc = "Vector reinterpret cast operation"]
51091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
51092#[inline]
51093#[cfg(target_endian = "big")]
51094#[target_feature(enable = "neon")]
51095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51097#[cfg_attr(
51098 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51099 assert_instr(nop)
51100)]
51101#[cfg_attr(
51102 not(target_arch = "arm"),
51103 stable(feature = "neon_intrinsics", since = "1.59.0")
51104)]
51105#[cfg_attr(
51106 target_arch = "arm",
51107 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51108)]
51109pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
51110 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
51111 unsafe {
51112 let ret_val: poly8x16_t = transmute(a);
51113 simd_shuffle!(
51114 ret_val,
51115 ret_val,
51116 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51117 )
51118 }
51119}
51120#[doc = "Vector reinterpret cast operation"]
51121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
51122#[inline]
51123#[cfg(target_endian = "little")]
51124#[target_feature(enable = "neon")]
51125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51127#[cfg_attr(
51128 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51129 assert_instr(nop)
51130)]
51131#[cfg_attr(
51132 not(target_arch = "arm"),
51133 stable(feature = "neon_intrinsics", since = "1.59.0")
51134)]
51135#[cfg_attr(
51136 target_arch = "arm",
51137 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51138)]
51139pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
51140 unsafe { transmute(a) }
51141}
51142#[doc = "Vector reinterpret cast operation"]
51143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
51144#[inline]
51145#[cfg(target_endian = "big")]
51146#[target_feature(enable = "neon")]
51147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51149#[cfg_attr(
51150 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51151 assert_instr(nop)
51152)]
51153#[cfg_attr(
51154 not(target_arch = "arm"),
51155 stable(feature = "neon_intrinsics", since = "1.59.0")
51156)]
51157#[cfg_attr(
51158 target_arch = "arm",
51159 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51160)]
51161pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
51162 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
51163 unsafe {
51164 let ret_val: poly16x8_t = transmute(a);
51165 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51166 }
51167}
51168#[doc = "Vector reinterpret cast operation"]
51169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
51170#[inline]
51171#[cfg(target_endian = "little")]
51172#[target_feature(enable = "neon")]
51173#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51174#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51175#[cfg_attr(
51176 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51177 assert_instr(nop)
51178)]
51179#[cfg_attr(
51180 not(target_arch = "arm"),
51181 stable(feature = "neon_intrinsics", since = "1.59.0")
51182)]
51183#[cfg_attr(
51184 target_arch = "arm",
51185 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51186)]
51187pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
51188 unsafe { transmute(a) }
51189}
51190#[doc = "Vector reinterpret cast operation"]
51191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
51192#[inline]
51193#[cfg(target_endian = "big")]
51194#[target_feature(enable = "neon")]
51195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51196#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51197#[cfg_attr(
51198 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51199 assert_instr(nop)
51200)]
51201#[cfg_attr(
51202 not(target_arch = "arm"),
51203 stable(feature = "neon_intrinsics", since = "1.59.0")
51204)]
51205#[cfg_attr(
51206 target_arch = "arm",
51207 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51208)]
51209pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
51210 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51211 unsafe {
51212 let ret_val: float32x2_t = transmute(a);
51213 simd_shuffle!(ret_val, ret_val, [1, 0])
51214 }
51215}
51216#[doc = "Vector reinterpret cast operation"]
51217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
51218#[inline]
51219#[cfg(target_endian = "little")]
51220#[target_feature(enable = "neon")]
51221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51223#[cfg_attr(
51224 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51225 assert_instr(nop)
51226)]
51227#[cfg_attr(
51228 not(target_arch = "arm"),
51229 stable(feature = "neon_intrinsics", since = "1.59.0")
51230)]
51231#[cfg_attr(
51232 target_arch = "arm",
51233 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51234)]
51235pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
51236 unsafe { transmute(a) }
51237}
51238#[doc = "Vector reinterpret cast operation"]
51239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
51240#[inline]
51241#[cfg(target_endian = "big")]
51242#[target_feature(enable = "neon")]
51243#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51244#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51245#[cfg_attr(
51246 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51247 assert_instr(nop)
51248)]
51249#[cfg_attr(
51250 not(target_arch = "arm"),
51251 stable(feature = "neon_intrinsics", since = "1.59.0")
51252)]
51253#[cfg_attr(
51254 target_arch = "arm",
51255 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51256)]
51257pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
51258 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51259 unsafe {
51260 let ret_val: int8x8_t = transmute(a);
51261 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51262 }
51263}
51264#[doc = "Vector reinterpret cast operation"]
51265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
51266#[inline]
51267#[cfg(target_endian = "little")]
51268#[target_feature(enable = "neon")]
51269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51271#[cfg_attr(
51272 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51273 assert_instr(nop)
51274)]
51275#[cfg_attr(
51276 not(target_arch = "arm"),
51277 stable(feature = "neon_intrinsics", since = "1.59.0")
51278)]
51279#[cfg_attr(
51280 target_arch = "arm",
51281 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51282)]
51283pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
51284 unsafe { transmute(a) }
51285}
51286#[doc = "Vector reinterpret cast operation"]
51287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
51288#[inline]
51289#[cfg(target_endian = "big")]
51290#[target_feature(enable = "neon")]
51291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51293#[cfg_attr(
51294 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51295 assert_instr(nop)
51296)]
51297#[cfg_attr(
51298 not(target_arch = "arm"),
51299 stable(feature = "neon_intrinsics", since = "1.59.0")
51300)]
51301#[cfg_attr(
51302 target_arch = "arm",
51303 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51304)]
51305pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
51306 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51307 unsafe {
51308 let ret_val: int16x4_t = transmute(a);
51309 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51310 }
51311}
51312#[doc = "Vector reinterpret cast operation"]
51313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
51314#[inline]
51315#[cfg(target_endian = "little")]
51316#[target_feature(enable = "neon")]
51317#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51319#[cfg_attr(
51320 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51321 assert_instr(nop)
51322)]
51323#[cfg_attr(
51324 not(target_arch = "arm"),
51325 stable(feature = "neon_intrinsics", since = "1.59.0")
51326)]
51327#[cfg_attr(
51328 target_arch = "arm",
51329 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51330)]
51331pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
51332 unsafe { transmute(a) }
51333}
51334#[doc = "Vector reinterpret cast operation"]
51335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
51336#[inline]
51337#[cfg(target_endian = "big")]
51338#[target_feature(enable = "neon")]
51339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51341#[cfg_attr(
51342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51343 assert_instr(nop)
51344)]
51345#[cfg_attr(
51346 not(target_arch = "arm"),
51347 stable(feature = "neon_intrinsics", since = "1.59.0")
51348)]
51349#[cfg_attr(
51350 target_arch = "arm",
51351 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51352)]
51353pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
51354 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51355 unsafe {
51356 let ret_val: int32x2_t = transmute(a);
51357 simd_shuffle!(ret_val, ret_val, [1, 0])
51358 }
51359}
51360#[doc = "Vector reinterpret cast operation"]
51361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
51362#[inline]
51363#[cfg(target_endian = "little")]
51364#[target_feature(enable = "neon")]
51365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51366#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51367#[cfg_attr(
51368 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51369 assert_instr(nop)
51370)]
51371#[cfg_attr(
51372 not(target_arch = "arm"),
51373 stable(feature = "neon_intrinsics", since = "1.59.0")
51374)]
51375#[cfg_attr(
51376 target_arch = "arm",
51377 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51378)]
51379pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
51380 unsafe { transmute(a) }
51381}
51382#[doc = "Vector reinterpret cast operation"]
51383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
51384#[inline]
51385#[cfg(target_endian = "big")]
51386#[target_feature(enable = "neon")]
51387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51389#[cfg_attr(
51390 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51391 assert_instr(nop)
51392)]
51393#[cfg_attr(
51394 not(target_arch = "arm"),
51395 stable(feature = "neon_intrinsics", since = "1.59.0")
51396)]
51397#[cfg_attr(
51398 target_arch = "arm",
51399 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51400)]
51401pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
51402 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51403 unsafe { transmute(a) }
51404}
51405#[doc = "Vector reinterpret cast operation"]
51406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
51407#[inline]
51408#[cfg(target_endian = "little")]
51409#[target_feature(enable = "neon")]
51410#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51411#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51412#[cfg_attr(
51413 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51414 assert_instr(nop)
51415)]
51416#[cfg_attr(
51417 not(target_arch = "arm"),
51418 stable(feature = "neon_intrinsics", since = "1.59.0")
51419)]
51420#[cfg_attr(
51421 target_arch = "arm",
51422 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51423)]
51424pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
51425 unsafe { transmute(a) }
51426}
51427#[doc = "Vector reinterpret cast operation"]
51428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
51429#[inline]
51430#[cfg(target_endian = "big")]
51431#[target_feature(enable = "neon")]
51432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51433#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51434#[cfg_attr(
51435 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51436 assert_instr(nop)
51437)]
51438#[cfg_attr(
51439 not(target_arch = "arm"),
51440 stable(feature = "neon_intrinsics", since = "1.59.0")
51441)]
51442#[cfg_attr(
51443 target_arch = "arm",
51444 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51445)]
51446pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
51447 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51448 unsafe {
51449 let ret_val: uint8x8_t = transmute(a);
51450 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51451 }
51452}
51453#[doc = "Vector reinterpret cast operation"]
51454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
51455#[inline]
51456#[cfg(target_endian = "little")]
51457#[target_feature(enable = "neon")]
51458#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51459#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51460#[cfg_attr(
51461 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51462 assert_instr(nop)
51463)]
51464#[cfg_attr(
51465 not(target_arch = "arm"),
51466 stable(feature = "neon_intrinsics", since = "1.59.0")
51467)]
51468#[cfg_attr(
51469 target_arch = "arm",
51470 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51471)]
51472pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
51473 unsafe { transmute(a) }
51474}
51475#[doc = "Vector reinterpret cast operation"]
51476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
51477#[inline]
51478#[cfg(target_endian = "big")]
51479#[target_feature(enable = "neon")]
51480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51482#[cfg_attr(
51483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51484 assert_instr(nop)
51485)]
51486#[cfg_attr(
51487 not(target_arch = "arm"),
51488 stable(feature = "neon_intrinsics", since = "1.59.0")
51489)]
51490#[cfg_attr(
51491 target_arch = "arm",
51492 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51493)]
51494pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
51495 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51496 unsafe {
51497 let ret_val: uint16x4_t = transmute(a);
51498 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51499 }
51500}
51501#[doc = "Vector reinterpret cast operation"]
51502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
51503#[inline]
51504#[cfg(target_endian = "little")]
51505#[target_feature(enable = "neon")]
51506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51508#[cfg_attr(
51509 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51510 assert_instr(nop)
51511)]
51512#[cfg_attr(
51513 not(target_arch = "arm"),
51514 stable(feature = "neon_intrinsics", since = "1.59.0")
51515)]
51516#[cfg_attr(
51517 target_arch = "arm",
51518 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51519)]
51520pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
51521 unsafe { transmute(a) }
51522}
51523#[doc = "Vector reinterpret cast operation"]
51524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
51525#[inline]
51526#[cfg(target_endian = "big")]
51527#[target_feature(enable = "neon")]
51528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51530#[cfg_attr(
51531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51532 assert_instr(nop)
51533)]
51534#[cfg_attr(
51535 not(target_arch = "arm"),
51536 stable(feature = "neon_intrinsics", since = "1.59.0")
51537)]
51538#[cfg_attr(
51539 target_arch = "arm",
51540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51541)]
51542pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
51543 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51544 unsafe { transmute(a) }
51545}
51546#[doc = "Vector reinterpret cast operation"]
51547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
51548#[inline]
51549#[cfg(target_endian = "little")]
51550#[target_feature(enable = "neon")]
51551#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51552#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51553#[cfg_attr(
51554 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51555 assert_instr(nop)
51556)]
51557#[cfg_attr(
51558 not(target_arch = "arm"),
51559 stable(feature = "neon_intrinsics", since = "1.59.0")
51560)]
51561#[cfg_attr(
51562 target_arch = "arm",
51563 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51564)]
51565pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
51566 unsafe { transmute(a) }
51567}
51568#[doc = "Vector reinterpret cast operation"]
51569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
51570#[inline]
51571#[cfg(target_endian = "big")]
51572#[target_feature(enable = "neon")]
51573#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51574#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51575#[cfg_attr(
51576 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51577 assert_instr(nop)
51578)]
51579#[cfg_attr(
51580 not(target_arch = "arm"),
51581 stable(feature = "neon_intrinsics", since = "1.59.0")
51582)]
51583#[cfg_attr(
51584 target_arch = "arm",
51585 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51586)]
51587pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
51588 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51589 unsafe {
51590 let ret_val: poly8x8_t = transmute(a);
51591 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51592 }
51593}
51594#[doc = "Vector reinterpret cast operation"]
51595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
51596#[inline]
51597#[cfg(target_endian = "little")]
51598#[target_feature(enable = "neon")]
51599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51600#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51601#[cfg_attr(
51602 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51603 assert_instr(nop)
51604)]
51605#[cfg_attr(
51606 not(target_arch = "arm"),
51607 stable(feature = "neon_intrinsics", since = "1.59.0")
51608)]
51609#[cfg_attr(
51610 target_arch = "arm",
51611 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51612)]
51613pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
51614 unsafe { transmute(a) }
51615}
51616#[doc = "Vector reinterpret cast operation"]
51617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
51618#[inline]
51619#[cfg(target_endian = "big")]
51620#[target_feature(enable = "neon")]
51621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51622#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51623#[cfg_attr(
51624 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51625 assert_instr(nop)
51626)]
51627#[cfg_attr(
51628 not(target_arch = "arm"),
51629 stable(feature = "neon_intrinsics", since = "1.59.0")
51630)]
51631#[cfg_attr(
51632 target_arch = "arm",
51633 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51634)]
51635pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
51636 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51637 unsafe {
51638 let ret_val: poly16x4_t = transmute(a);
51639 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51640 }
51641}
51642#[doc = "Vector reinterpret cast operation"]
51643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
51644#[inline]
51645#[cfg(target_endian = "little")]
51646#[target_feature(enable = "neon")]
51647#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51648#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51649#[cfg_attr(
51650 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51651 assert_instr(nop)
51652)]
51653#[cfg_attr(
51654 not(target_arch = "arm"),
51655 stable(feature = "neon_intrinsics", since = "1.59.0")
51656)]
51657#[cfg_attr(
51658 target_arch = "arm",
51659 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51660)]
51661pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
51662 unsafe { transmute(a) }
51663}
51664#[doc = "Vector reinterpret cast operation"]
51665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
51666#[inline]
51667#[cfg(target_endian = "big")]
51668#[target_feature(enable = "neon")]
51669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51671#[cfg_attr(
51672 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51673 assert_instr(nop)
51674)]
51675#[cfg_attr(
51676 not(target_arch = "arm"),
51677 stable(feature = "neon_intrinsics", since = "1.59.0")
51678)]
51679#[cfg_attr(
51680 target_arch = "arm",
51681 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51682)]
51683pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
51684 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51685 unsafe {
51686 let ret_val: float32x4_t = transmute(a);
51687 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51688 }
51689}
51690#[doc = "Vector reinterpret cast operation"]
51691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
51692#[inline]
51693#[cfg(target_endian = "little")]
51694#[target_feature(enable = "neon")]
51695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51696#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51697#[cfg_attr(
51698 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51699 assert_instr(nop)
51700)]
51701#[cfg_attr(
51702 not(target_arch = "arm"),
51703 stable(feature = "neon_intrinsics", since = "1.59.0")
51704)]
51705#[cfg_attr(
51706 target_arch = "arm",
51707 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51708)]
51709pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
51710 unsafe { transmute(a) }
51711}
51712#[doc = "Vector reinterpret cast operation"]
51713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
51714#[inline]
51715#[cfg(target_endian = "big")]
51716#[target_feature(enable = "neon")]
51717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51718#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51719#[cfg_attr(
51720 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51721 assert_instr(nop)
51722)]
51723#[cfg_attr(
51724 not(target_arch = "arm"),
51725 stable(feature = "neon_intrinsics", since = "1.59.0")
51726)]
51727#[cfg_attr(
51728 target_arch = "arm",
51729 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51730)]
51731pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
51732 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51733 unsafe {
51734 let ret_val: int8x16_t = transmute(a);
51735 simd_shuffle!(
51736 ret_val,
51737 ret_val,
51738 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51739 )
51740 }
51741}
51742#[doc = "Vector reinterpret cast operation"]
51743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
51744#[inline]
51745#[cfg(target_endian = "little")]
51746#[target_feature(enable = "neon")]
51747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51748#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51749#[cfg_attr(
51750 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51751 assert_instr(nop)
51752)]
51753#[cfg_attr(
51754 not(target_arch = "arm"),
51755 stable(feature = "neon_intrinsics", since = "1.59.0")
51756)]
51757#[cfg_attr(
51758 target_arch = "arm",
51759 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51760)]
51761pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
51762 unsafe { transmute(a) }
51763}
51764#[doc = "Vector reinterpret cast operation"]
51765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
51766#[inline]
51767#[cfg(target_endian = "big")]
51768#[target_feature(enable = "neon")]
51769#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51770#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51771#[cfg_attr(
51772 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51773 assert_instr(nop)
51774)]
51775#[cfg_attr(
51776 not(target_arch = "arm"),
51777 stable(feature = "neon_intrinsics", since = "1.59.0")
51778)]
51779#[cfg_attr(
51780 target_arch = "arm",
51781 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51782)]
51783pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
51784 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51785 unsafe {
51786 let ret_val: int16x8_t = transmute(a);
51787 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51788 }
51789}
51790#[doc = "Vector reinterpret cast operation"]
51791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
51792#[inline]
51793#[cfg(target_endian = "little")]
51794#[target_feature(enable = "neon")]
51795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51796#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51797#[cfg_attr(
51798 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51799 assert_instr(nop)
51800)]
51801#[cfg_attr(
51802 not(target_arch = "arm"),
51803 stable(feature = "neon_intrinsics", since = "1.59.0")
51804)]
51805#[cfg_attr(
51806 target_arch = "arm",
51807 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51808)]
51809pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
51810 unsafe { transmute(a) }
51811}
51812#[doc = "Vector reinterpret cast operation"]
51813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
51814#[inline]
51815#[cfg(target_endian = "big")]
51816#[target_feature(enable = "neon")]
51817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51818#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51819#[cfg_attr(
51820 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51821 assert_instr(nop)
51822)]
51823#[cfg_attr(
51824 not(target_arch = "arm"),
51825 stable(feature = "neon_intrinsics", since = "1.59.0")
51826)]
51827#[cfg_attr(
51828 target_arch = "arm",
51829 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51830)]
51831pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
51832 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51833 unsafe {
51834 let ret_val: int32x4_t = transmute(a);
51835 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51836 }
51837}
51838#[doc = "Vector reinterpret cast operation"]
51839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
51840#[inline]
51841#[cfg(target_endian = "little")]
51842#[target_feature(enable = "neon")]
51843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51845#[cfg_attr(
51846 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51847 assert_instr(nop)
51848)]
51849#[cfg_attr(
51850 not(target_arch = "arm"),
51851 stable(feature = "neon_intrinsics", since = "1.59.0")
51852)]
51853#[cfg_attr(
51854 target_arch = "arm",
51855 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51856)]
51857pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
51858 unsafe { transmute(a) }
51859}
51860#[doc = "Vector reinterpret cast operation"]
51861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
51862#[inline]
51863#[cfg(target_endian = "big")]
51864#[target_feature(enable = "neon")]
51865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51867#[cfg_attr(
51868 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51869 assert_instr(nop)
51870)]
51871#[cfg_attr(
51872 not(target_arch = "arm"),
51873 stable(feature = "neon_intrinsics", since = "1.59.0")
51874)]
51875#[cfg_attr(
51876 target_arch = "arm",
51877 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51878)]
51879pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
51880 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51881 unsafe {
51882 let ret_val: int64x2_t = transmute(a);
51883 simd_shuffle!(ret_val, ret_val, [1, 0])
51884 }
51885}
51886#[doc = "Vector reinterpret cast operation"]
51887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
51888#[inline]
51889#[cfg(target_endian = "little")]
51890#[target_feature(enable = "neon")]
51891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51893#[cfg_attr(
51894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51895 assert_instr(nop)
51896)]
51897#[cfg_attr(
51898 not(target_arch = "arm"),
51899 stable(feature = "neon_intrinsics", since = "1.59.0")
51900)]
51901#[cfg_attr(
51902 target_arch = "arm",
51903 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51904)]
51905pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
51906 unsafe { transmute(a) }
51907}
51908#[doc = "Vector reinterpret cast operation"]
51909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
51910#[inline]
51911#[cfg(target_endian = "big")]
51912#[target_feature(enable = "neon")]
51913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51914#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51915#[cfg_attr(
51916 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51917 assert_instr(nop)
51918)]
51919#[cfg_attr(
51920 not(target_arch = "arm"),
51921 stable(feature = "neon_intrinsics", since = "1.59.0")
51922)]
51923#[cfg_attr(
51924 target_arch = "arm",
51925 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51926)]
51927pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
51928 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51929 unsafe {
51930 let ret_val: uint8x16_t = transmute(a);
51931 simd_shuffle!(
51932 ret_val,
51933 ret_val,
51934 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51935 )
51936 }
51937}
51938#[doc = "Vector reinterpret cast operation"]
51939#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
51940#[inline]
51941#[cfg(target_endian = "little")]
51942#[target_feature(enable = "neon")]
51943#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51944#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51945#[cfg_attr(
51946 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51947 assert_instr(nop)
51948)]
51949#[cfg_attr(
51950 not(target_arch = "arm"),
51951 stable(feature = "neon_intrinsics", since = "1.59.0")
51952)]
51953#[cfg_attr(
51954 target_arch = "arm",
51955 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51956)]
51957pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
51958 unsafe { transmute(a) }
51959}
51960#[doc = "Vector reinterpret cast operation"]
51961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
51962#[inline]
51963#[cfg(target_endian = "big")]
51964#[target_feature(enable = "neon")]
51965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51967#[cfg_attr(
51968 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51969 assert_instr(nop)
51970)]
51971#[cfg_attr(
51972 not(target_arch = "arm"),
51973 stable(feature = "neon_intrinsics", since = "1.59.0")
51974)]
51975#[cfg_attr(
51976 target_arch = "arm",
51977 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51978)]
51979pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
51980 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51981 unsafe {
51982 let ret_val: uint16x8_t = transmute(a);
51983 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51984 }
51985}
51986#[doc = "Vector reinterpret cast operation"]
51987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
51988#[inline]
51989#[cfg(target_endian = "little")]
51990#[target_feature(enable = "neon")]
51991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51993#[cfg_attr(
51994 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51995 assert_instr(nop)
51996)]
51997#[cfg_attr(
51998 not(target_arch = "arm"),
51999 stable(feature = "neon_intrinsics", since = "1.59.0")
52000)]
52001#[cfg_attr(
52002 target_arch = "arm",
52003 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52004)]
52005pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
52006 unsafe { transmute(a) }
52007}
52008#[doc = "Vector reinterpret cast operation"]
52009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
52010#[inline]
52011#[cfg(target_endian = "big")]
52012#[target_feature(enable = "neon")]
52013#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52014#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52015#[cfg_attr(
52016 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52017 assert_instr(nop)
52018)]
52019#[cfg_attr(
52020 not(target_arch = "arm"),
52021 stable(feature = "neon_intrinsics", since = "1.59.0")
52022)]
52023#[cfg_attr(
52024 target_arch = "arm",
52025 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52026)]
52027pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
52028 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
52029 unsafe {
52030 let ret_val: uint64x2_t = transmute(a);
52031 simd_shuffle!(ret_val, ret_val, [1, 0])
52032 }
52033}
52034#[doc = "Vector reinterpret cast operation"]
52035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
52036#[inline]
52037#[cfg(target_endian = "little")]
52038#[target_feature(enable = "neon")]
52039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52041#[cfg_attr(
52042 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52043 assert_instr(nop)
52044)]
52045#[cfg_attr(
52046 not(target_arch = "arm"),
52047 stable(feature = "neon_intrinsics", since = "1.59.0")
52048)]
52049#[cfg_attr(
52050 target_arch = "arm",
52051 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52052)]
52053pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
52054 unsafe { transmute(a) }
52055}
52056#[doc = "Vector reinterpret cast operation"]
52057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
52058#[inline]
52059#[cfg(target_endian = "big")]
52060#[target_feature(enable = "neon")]
52061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52062#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52063#[cfg_attr(
52064 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52065 assert_instr(nop)
52066)]
52067#[cfg_attr(
52068 not(target_arch = "arm"),
52069 stable(feature = "neon_intrinsics", since = "1.59.0")
52070)]
52071#[cfg_attr(
52072 target_arch = "arm",
52073 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52074)]
52075pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
52076 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
52077 unsafe {
52078 let ret_val: poly8x16_t = transmute(a);
52079 simd_shuffle!(
52080 ret_val,
52081 ret_val,
52082 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52083 )
52084 }
52085}
52086#[doc = "Vector reinterpret cast operation"]
52087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
52088#[inline]
52089#[cfg(target_endian = "little")]
52090#[target_feature(enable = "neon")]
52091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52093#[cfg_attr(
52094 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52095 assert_instr(nop)
52096)]
52097#[cfg_attr(
52098 not(target_arch = "arm"),
52099 stable(feature = "neon_intrinsics", since = "1.59.0")
52100)]
52101#[cfg_attr(
52102 target_arch = "arm",
52103 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52104)]
52105pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
52106 unsafe { transmute(a) }
52107}
52108#[doc = "Vector reinterpret cast operation"]
52109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
52110#[inline]
52111#[cfg(target_endian = "big")]
52112#[target_feature(enable = "neon")]
52113#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52114#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52115#[cfg_attr(
52116 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52117 assert_instr(nop)
52118)]
52119#[cfg_attr(
52120 not(target_arch = "arm"),
52121 stable(feature = "neon_intrinsics", since = "1.59.0")
52122)]
52123#[cfg_attr(
52124 target_arch = "arm",
52125 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52126)]
52127pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
52128 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
52129 unsafe {
52130 let ret_val: poly16x8_t = transmute(a);
52131 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52132 }
52133}
52134#[doc = "Vector reinterpret cast operation"]
52135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
52136#[inline]
52137#[cfg(target_endian = "little")]
52138#[target_feature(enable = "neon")]
52139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52140#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52141#[cfg_attr(
52142 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52143 assert_instr(nop)
52144)]
52145#[cfg_attr(
52146 not(target_arch = "arm"),
52147 stable(feature = "neon_intrinsics", since = "1.59.0")
52148)]
52149#[cfg_attr(
52150 target_arch = "arm",
52151 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52152)]
52153pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
52154 unsafe { transmute(a) }
52155}
52156#[doc = "Vector reinterpret cast operation"]
52157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
52158#[inline]
52159#[cfg(target_endian = "big")]
52160#[target_feature(enable = "neon")]
52161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52163#[cfg_attr(
52164 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52165 assert_instr(nop)
52166)]
52167#[cfg_attr(
52168 not(target_arch = "arm"),
52169 stable(feature = "neon_intrinsics", since = "1.59.0")
52170)]
52171#[cfg_attr(
52172 target_arch = "arm",
52173 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52174)]
52175pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
52176 unsafe {
52177 let ret_val: float32x2_t = transmute(a);
52178 simd_shuffle!(ret_val, ret_val, [1, 0])
52179 }
52180}
52181#[doc = "Vector reinterpret cast operation"]
52182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
52183#[inline]
52184#[cfg(target_endian = "little")]
52185#[target_feature(enable = "neon")]
52186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52187#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52188#[cfg_attr(
52189 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52190 assert_instr(nop)
52191)]
52192#[cfg_attr(
52193 not(target_arch = "arm"),
52194 stable(feature = "neon_intrinsics", since = "1.59.0")
52195)]
52196#[cfg_attr(
52197 target_arch = "arm",
52198 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52199)]
52200pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
52201 unsafe { transmute(a) }
52202}
52203#[doc = "Vector reinterpret cast operation"]
52204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
52205#[inline]
52206#[cfg(target_endian = "big")]
52207#[target_feature(enable = "neon")]
52208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52209#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52210#[cfg_attr(
52211 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52212 assert_instr(nop)
52213)]
52214#[cfg_attr(
52215 not(target_arch = "arm"),
52216 stable(feature = "neon_intrinsics", since = "1.59.0")
52217)]
52218#[cfg_attr(
52219 target_arch = "arm",
52220 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52221)]
52222pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
52223 unsafe {
52224 let ret_val: int8x8_t = transmute(a);
52225 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52226 }
52227}
52228#[doc = "Vector reinterpret cast operation"]
52229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
52230#[inline]
52231#[cfg(target_endian = "little")]
52232#[target_feature(enable = "neon")]
52233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52235#[cfg_attr(
52236 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52237 assert_instr(nop)
52238)]
52239#[cfg_attr(
52240 not(target_arch = "arm"),
52241 stable(feature = "neon_intrinsics", since = "1.59.0")
52242)]
52243#[cfg_attr(
52244 target_arch = "arm",
52245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52246)]
52247pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
52248 unsafe { transmute(a) }
52249}
52250#[doc = "Vector reinterpret cast operation"]
52251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
52252#[inline]
52253#[cfg(target_endian = "big")]
52254#[target_feature(enable = "neon")]
52255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52257#[cfg_attr(
52258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52259 assert_instr(nop)
52260)]
52261#[cfg_attr(
52262 not(target_arch = "arm"),
52263 stable(feature = "neon_intrinsics", since = "1.59.0")
52264)]
52265#[cfg_attr(
52266 target_arch = "arm",
52267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52268)]
52269pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
52270 unsafe {
52271 let ret_val: int16x4_t = transmute(a);
52272 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52273 }
52274}
52275#[doc = "Vector reinterpret cast operation"]
52276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
52277#[inline]
52278#[cfg(target_endian = "little")]
52279#[target_feature(enable = "neon")]
52280#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52281#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52282#[cfg_attr(
52283 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52284 assert_instr(nop)
52285)]
52286#[cfg_attr(
52287 not(target_arch = "arm"),
52288 stable(feature = "neon_intrinsics", since = "1.59.0")
52289)]
52290#[cfg_attr(
52291 target_arch = "arm",
52292 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52293)]
52294pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
52295 unsafe { transmute(a) }
52296}
52297#[doc = "Vector reinterpret cast operation"]
52298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
52299#[inline]
52300#[cfg(target_endian = "big")]
52301#[target_feature(enable = "neon")]
52302#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52303#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52304#[cfg_attr(
52305 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52306 assert_instr(nop)
52307)]
52308#[cfg_attr(
52309 not(target_arch = "arm"),
52310 stable(feature = "neon_intrinsics", since = "1.59.0")
52311)]
52312#[cfg_attr(
52313 target_arch = "arm",
52314 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52315)]
52316pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
52317 unsafe {
52318 let ret_val: int32x2_t = transmute(a);
52319 simd_shuffle!(ret_val, ret_val, [1, 0])
52320 }
52321}
52322#[doc = "Vector reinterpret cast operation"]
52323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"]
52324#[inline]
52325#[target_feature(enable = "neon")]
52326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52327#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52328#[cfg_attr(
52329 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52330 assert_instr(nop)
52331)]
52332#[cfg_attr(
52333 not(target_arch = "arm"),
52334 stable(feature = "neon_intrinsics", since = "1.59.0")
52335)]
52336#[cfg_attr(
52337 target_arch = "arm",
52338 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52339)]
52340pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
52341 unsafe { transmute(a) }
52342}
52343#[doc = "Vector reinterpret cast operation"]
52344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
52345#[inline]
52346#[cfg(target_endian = "little")]
52347#[target_feature(enable = "neon")]
52348#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52349#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52350#[cfg_attr(
52351 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52352 assert_instr(nop)
52353)]
52354#[cfg_attr(
52355 not(target_arch = "arm"),
52356 stable(feature = "neon_intrinsics", since = "1.59.0")
52357)]
52358#[cfg_attr(
52359 target_arch = "arm",
52360 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52361)]
52362pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
52363 unsafe { transmute(a) }
52364}
52365#[doc = "Vector reinterpret cast operation"]
52366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
52367#[inline]
52368#[cfg(target_endian = "big")]
52369#[target_feature(enable = "neon")]
52370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52371#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52372#[cfg_attr(
52373 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52374 assert_instr(nop)
52375)]
52376#[cfg_attr(
52377 not(target_arch = "arm"),
52378 stable(feature = "neon_intrinsics", since = "1.59.0")
52379)]
52380#[cfg_attr(
52381 target_arch = "arm",
52382 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52383)]
52384pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
52385 unsafe {
52386 let ret_val: uint8x8_t = transmute(a);
52387 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52388 }
52389}
52390#[doc = "Vector reinterpret cast operation"]
52391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
52392#[inline]
52393#[cfg(target_endian = "little")]
52394#[target_feature(enable = "neon")]
52395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52396#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52397#[cfg_attr(
52398 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52399 assert_instr(nop)
52400)]
52401#[cfg_attr(
52402 not(target_arch = "arm"),
52403 stable(feature = "neon_intrinsics", since = "1.59.0")
52404)]
52405#[cfg_attr(
52406 target_arch = "arm",
52407 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52408)]
52409pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
52410 unsafe { transmute(a) }
52411}
52412#[doc = "Vector reinterpret cast operation"]
52413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
52414#[inline]
52415#[cfg(target_endian = "big")]
52416#[target_feature(enable = "neon")]
52417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52419#[cfg_attr(
52420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52421 assert_instr(nop)
52422)]
52423#[cfg_attr(
52424 not(target_arch = "arm"),
52425 stable(feature = "neon_intrinsics", since = "1.59.0")
52426)]
52427#[cfg_attr(
52428 target_arch = "arm",
52429 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52430)]
52431pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
52432 unsafe {
52433 let ret_val: uint16x4_t = transmute(a);
52434 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52435 }
52436}
52437#[doc = "Vector reinterpret cast operation"]
52438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
52439#[inline]
52440#[cfg(target_endian = "little")]
52441#[target_feature(enable = "neon")]
52442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52444#[cfg_attr(
52445 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52446 assert_instr(nop)
52447)]
52448#[cfg_attr(
52449 not(target_arch = "arm"),
52450 stable(feature = "neon_intrinsics", since = "1.59.0")
52451)]
52452#[cfg_attr(
52453 target_arch = "arm",
52454 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52455)]
52456pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
52457 unsafe { transmute(a) }
52458}
52459#[doc = "Vector reinterpret cast operation"]
52460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
52461#[inline]
52462#[cfg(target_endian = "big")]
52463#[target_feature(enable = "neon")]
52464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52465#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52466#[cfg_attr(
52467 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52468 assert_instr(nop)
52469)]
52470#[cfg_attr(
52471 not(target_arch = "arm"),
52472 stable(feature = "neon_intrinsics", since = "1.59.0")
52473)]
52474#[cfg_attr(
52475 target_arch = "arm",
52476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52477)]
52478pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
52479 unsafe {
52480 let ret_val: uint32x2_t = transmute(a);
52481 simd_shuffle!(ret_val, ret_val, [1, 0])
52482 }
52483}
52484#[doc = "Vector reinterpret cast operation"]
52485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
52486#[inline]
52487#[cfg(target_endian = "little")]
52488#[target_feature(enable = "neon")]
52489#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52490#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52491#[cfg_attr(
52492 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52493 assert_instr(nop)
52494)]
52495#[cfg_attr(
52496 not(target_arch = "arm"),
52497 stable(feature = "neon_intrinsics", since = "1.59.0")
52498)]
52499#[cfg_attr(
52500 target_arch = "arm",
52501 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52502)]
52503pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
52504 unsafe { transmute(a) }
52505}
52506#[doc = "Vector reinterpret cast operation"]
52507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
52508#[inline]
52509#[cfg(target_endian = "big")]
52510#[target_feature(enable = "neon")]
52511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52513#[cfg_attr(
52514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52515 assert_instr(nop)
52516)]
52517#[cfg_attr(
52518 not(target_arch = "arm"),
52519 stable(feature = "neon_intrinsics", since = "1.59.0")
52520)]
52521#[cfg_attr(
52522 target_arch = "arm",
52523 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52524)]
52525pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
52526 unsafe {
52527 let ret_val: poly8x8_t = transmute(a);
52528 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52529 }
52530}
52531#[doc = "Vector reinterpret cast operation"]
52532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
52533#[inline]
52534#[cfg(target_endian = "little")]
52535#[target_feature(enable = "neon")]
52536#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52537#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52538#[cfg_attr(
52539 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52540 assert_instr(nop)
52541)]
52542#[cfg_attr(
52543 not(target_arch = "arm"),
52544 stable(feature = "neon_intrinsics", since = "1.59.0")
52545)]
52546#[cfg_attr(
52547 target_arch = "arm",
52548 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52549)]
52550pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
52551 unsafe { transmute(a) }
52552}
52553#[doc = "Vector reinterpret cast operation"]
52554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
52555#[inline]
52556#[cfg(target_endian = "big")]
52557#[target_feature(enable = "neon")]
52558#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52559#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52560#[cfg_attr(
52561 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52562 assert_instr(nop)
52563)]
52564#[cfg_attr(
52565 not(target_arch = "arm"),
52566 stable(feature = "neon_intrinsics", since = "1.59.0")
52567)]
52568#[cfg_attr(
52569 target_arch = "arm",
52570 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52571)]
52572pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
52573 unsafe {
52574 let ret_val: poly16x4_t = transmute(a);
52575 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52576 }
52577}
52578#[doc = "Vector reinterpret cast operation"]
52579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
52580#[inline]
52581#[cfg(target_endian = "little")]
52582#[target_feature(enable = "neon")]
52583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52585#[cfg_attr(
52586 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52587 assert_instr(nop)
52588)]
52589#[cfg_attr(
52590 not(target_arch = "arm"),
52591 stable(feature = "neon_intrinsics", since = "1.59.0")
52592)]
52593#[cfg_attr(
52594 target_arch = "arm",
52595 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52596)]
52597pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
52598 unsafe { transmute(a) }
52599}
52600#[doc = "Vector reinterpret cast operation"]
52601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
52602#[inline]
52603#[cfg(target_endian = "big")]
52604#[target_feature(enable = "neon")]
52605#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52606#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52607#[cfg_attr(
52608 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52609 assert_instr(nop)
52610)]
52611#[cfg_attr(
52612 not(target_arch = "arm"),
52613 stable(feature = "neon_intrinsics", since = "1.59.0")
52614)]
52615#[cfg_attr(
52616 target_arch = "arm",
52617 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52618)]
52619pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
52620 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52621 unsafe {
52622 let ret_val: float32x4_t = transmute(a);
52623 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52624 }
52625}
52626#[doc = "Vector reinterpret cast operation"]
52627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
52628#[inline]
52629#[cfg(target_endian = "little")]
52630#[target_feature(enable = "neon")]
52631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52632#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52633#[cfg_attr(
52634 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52635 assert_instr(nop)
52636)]
52637#[cfg_attr(
52638 not(target_arch = "arm"),
52639 stable(feature = "neon_intrinsics", since = "1.59.0")
52640)]
52641#[cfg_attr(
52642 target_arch = "arm",
52643 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52644)]
52645pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
52646 unsafe { transmute(a) }
52647}
52648#[doc = "Vector reinterpret cast operation"]
52649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
52650#[inline]
52651#[cfg(target_endian = "big")]
52652#[target_feature(enable = "neon")]
52653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52654#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52655#[cfg_attr(
52656 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52657 assert_instr(nop)
52658)]
52659#[cfg_attr(
52660 not(target_arch = "arm"),
52661 stable(feature = "neon_intrinsics", since = "1.59.0")
52662)]
52663#[cfg_attr(
52664 target_arch = "arm",
52665 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52666)]
52667pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
52668 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52669 unsafe {
52670 let ret_val: int8x16_t = transmute(a);
52671 simd_shuffle!(
52672 ret_val,
52673 ret_val,
52674 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52675 )
52676 }
52677}
52678#[doc = "Vector reinterpret cast operation"]
52679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
52680#[inline]
52681#[cfg(target_endian = "little")]
52682#[target_feature(enable = "neon")]
52683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52685#[cfg_attr(
52686 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52687 assert_instr(nop)
52688)]
52689#[cfg_attr(
52690 not(target_arch = "arm"),
52691 stable(feature = "neon_intrinsics", since = "1.59.0")
52692)]
52693#[cfg_attr(
52694 target_arch = "arm",
52695 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52696)]
52697pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
52698 unsafe { transmute(a) }
52699}
52700#[doc = "Vector reinterpret cast operation"]
52701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
52702#[inline]
52703#[cfg(target_endian = "big")]
52704#[target_feature(enable = "neon")]
52705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52707#[cfg_attr(
52708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52709 assert_instr(nop)
52710)]
52711#[cfg_attr(
52712 not(target_arch = "arm"),
52713 stable(feature = "neon_intrinsics", since = "1.59.0")
52714)]
52715#[cfg_attr(
52716 target_arch = "arm",
52717 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52718)]
52719pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
52720 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52721 unsafe {
52722 let ret_val: int16x8_t = transmute(a);
52723 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52724 }
52725}
52726#[doc = "Vector reinterpret cast operation"]
52727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
52728#[inline]
52729#[cfg(target_endian = "little")]
52730#[target_feature(enable = "neon")]
52731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52733#[cfg_attr(
52734 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52735 assert_instr(nop)
52736)]
52737#[cfg_attr(
52738 not(target_arch = "arm"),
52739 stable(feature = "neon_intrinsics", since = "1.59.0")
52740)]
52741#[cfg_attr(
52742 target_arch = "arm",
52743 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52744)]
52745pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
52746 unsafe { transmute(a) }
52747}
52748#[doc = "Vector reinterpret cast operation"]
52749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
52750#[inline]
52751#[cfg(target_endian = "big")]
52752#[target_feature(enable = "neon")]
52753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52754#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52755#[cfg_attr(
52756 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52757 assert_instr(nop)
52758)]
52759#[cfg_attr(
52760 not(target_arch = "arm"),
52761 stable(feature = "neon_intrinsics", since = "1.59.0")
52762)]
52763#[cfg_attr(
52764 target_arch = "arm",
52765 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52766)]
52767pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
52768 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52769 unsafe {
52770 let ret_val: int32x4_t = transmute(a);
52771 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52772 }
52773}
52774#[doc = "Vector reinterpret cast operation"]
52775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
52776#[inline]
52777#[cfg(target_endian = "little")]
52778#[target_feature(enable = "neon")]
52779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52781#[cfg_attr(
52782 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52783 assert_instr(nop)
52784)]
52785#[cfg_attr(
52786 not(target_arch = "arm"),
52787 stable(feature = "neon_intrinsics", since = "1.59.0")
52788)]
52789#[cfg_attr(
52790 target_arch = "arm",
52791 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52792)]
52793pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
52794 unsafe { transmute(a) }
52795}
52796#[doc = "Vector reinterpret cast operation"]
52797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
52798#[inline]
52799#[cfg(target_endian = "big")]
52800#[target_feature(enable = "neon")]
52801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52802#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52803#[cfg_attr(
52804 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52805 assert_instr(nop)
52806)]
52807#[cfg_attr(
52808 not(target_arch = "arm"),
52809 stable(feature = "neon_intrinsics", since = "1.59.0")
52810)]
52811#[cfg_attr(
52812 target_arch = "arm",
52813 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52814)]
52815pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
52816 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52817 unsafe {
52818 let ret_val: int64x2_t = transmute(a);
52819 simd_shuffle!(ret_val, ret_val, [1, 0])
52820 }
52821}
52822#[doc = "Vector reinterpret cast operation"]
52823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
52824#[inline]
52825#[cfg(target_endian = "little")]
52826#[target_feature(enable = "neon")]
52827#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52828#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52829#[cfg_attr(
52830 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52831 assert_instr(nop)
52832)]
52833#[cfg_attr(
52834 not(target_arch = "arm"),
52835 stable(feature = "neon_intrinsics", since = "1.59.0")
52836)]
52837#[cfg_attr(
52838 target_arch = "arm",
52839 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52840)]
52841pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
52842 unsafe { transmute(a) }
52843}
52844#[doc = "Vector reinterpret cast operation"]
52845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
52846#[inline]
52847#[cfg(target_endian = "big")]
52848#[target_feature(enable = "neon")]
52849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52850#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52851#[cfg_attr(
52852 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52853 assert_instr(nop)
52854)]
52855#[cfg_attr(
52856 not(target_arch = "arm"),
52857 stable(feature = "neon_intrinsics", since = "1.59.0")
52858)]
52859#[cfg_attr(
52860 target_arch = "arm",
52861 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52862)]
52863pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
52864 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52865 unsafe {
52866 let ret_val: uint8x16_t = transmute(a);
52867 simd_shuffle!(
52868 ret_val,
52869 ret_val,
52870 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52871 )
52872 }
52873}
52874#[doc = "Vector reinterpret cast operation"]
52875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
52876#[inline]
52877#[cfg(target_endian = "little")]
52878#[target_feature(enable = "neon")]
52879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52881#[cfg_attr(
52882 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52883 assert_instr(nop)
52884)]
52885#[cfg_attr(
52886 not(target_arch = "arm"),
52887 stable(feature = "neon_intrinsics", since = "1.59.0")
52888)]
52889#[cfg_attr(
52890 target_arch = "arm",
52891 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52892)]
52893pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
52894 unsafe { transmute(a) }
52895}
52896#[doc = "Vector reinterpret cast operation"]
52897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
52898#[inline]
52899#[cfg(target_endian = "big")]
52900#[target_feature(enable = "neon")]
52901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52903#[cfg_attr(
52904 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52905 assert_instr(nop)
52906)]
52907#[cfg_attr(
52908 not(target_arch = "arm"),
52909 stable(feature = "neon_intrinsics", since = "1.59.0")
52910)]
52911#[cfg_attr(
52912 target_arch = "arm",
52913 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52914)]
52915pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
52916 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52917 unsafe {
52918 let ret_val: uint16x8_t = transmute(a);
52919 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52920 }
52921}
52922#[doc = "Vector reinterpret cast operation"]
52923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
52924#[inline]
52925#[cfg(target_endian = "little")]
52926#[target_feature(enable = "neon")]
52927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52929#[cfg_attr(
52930 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52931 assert_instr(nop)
52932)]
52933#[cfg_attr(
52934 not(target_arch = "arm"),
52935 stable(feature = "neon_intrinsics", since = "1.59.0")
52936)]
52937#[cfg_attr(
52938 target_arch = "arm",
52939 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52940)]
52941pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
52942 unsafe { transmute(a) }
52943}
52944#[doc = "Vector reinterpret cast operation"]
52945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
52946#[inline]
52947#[cfg(target_endian = "big")]
52948#[target_feature(enable = "neon")]
52949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52950#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52951#[cfg_attr(
52952 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52953 assert_instr(nop)
52954)]
52955#[cfg_attr(
52956 not(target_arch = "arm"),
52957 stable(feature = "neon_intrinsics", since = "1.59.0")
52958)]
52959#[cfg_attr(
52960 target_arch = "arm",
52961 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52962)]
52963pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
52964 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52965 unsafe {
52966 let ret_val: uint32x4_t = transmute(a);
52967 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52968 }
52969}
52970#[doc = "Vector reinterpret cast operation"]
52971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
52972#[inline]
52973#[cfg(target_endian = "little")]
52974#[target_feature(enable = "neon")]
52975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52977#[cfg_attr(
52978 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52979 assert_instr(nop)
52980)]
52981#[cfg_attr(
52982 not(target_arch = "arm"),
52983 stable(feature = "neon_intrinsics", since = "1.59.0")
52984)]
52985#[cfg_attr(
52986 target_arch = "arm",
52987 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52988)]
52989pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
52990 unsafe { transmute(a) }
52991}
52992#[doc = "Vector reinterpret cast operation"]
52993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
52994#[inline]
52995#[cfg(target_endian = "big")]
52996#[target_feature(enable = "neon")]
52997#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52998#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52999#[cfg_attr(
53000 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53001 assert_instr(nop)
53002)]
53003#[cfg_attr(
53004 not(target_arch = "arm"),
53005 stable(feature = "neon_intrinsics", since = "1.59.0")
53006)]
53007#[cfg_attr(
53008 target_arch = "arm",
53009 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53010)]
53011pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
53012 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
53013 unsafe {
53014 let ret_val: poly8x16_t = transmute(a);
53015 simd_shuffle!(
53016 ret_val,
53017 ret_val,
53018 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
53019 )
53020 }
53021}
53022#[doc = "Vector reinterpret cast operation"]
53023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
53024#[inline]
53025#[cfg(target_endian = "little")]
53026#[target_feature(enable = "neon")]
53027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53029#[cfg_attr(
53030 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53031 assert_instr(nop)
53032)]
53033#[cfg_attr(
53034 not(target_arch = "arm"),
53035 stable(feature = "neon_intrinsics", since = "1.59.0")
53036)]
53037#[cfg_attr(
53038 target_arch = "arm",
53039 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53040)]
53041pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
53042 unsafe { transmute(a) }
53043}
53044#[doc = "Vector reinterpret cast operation"]
53045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
53046#[inline]
53047#[cfg(target_endian = "big")]
53048#[target_feature(enable = "neon")]
53049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53050#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53051#[cfg_attr(
53052 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53053 assert_instr(nop)
53054)]
53055#[cfg_attr(
53056 not(target_arch = "arm"),
53057 stable(feature = "neon_intrinsics", since = "1.59.0")
53058)]
53059#[cfg_attr(
53060 target_arch = "arm",
53061 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53062)]
53063pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
53064 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
53065 unsafe {
53066 let ret_val: poly16x8_t = transmute(a);
53067 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53068 }
53069}
53070#[doc = "Vector reinterpret cast operation"]
53071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
53072#[inline]
53073#[cfg(target_endian = "little")]
53074#[target_feature(enable = "neon")]
53075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53077#[cfg_attr(
53078 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53079 assert_instr(nop)
53080)]
53081#[cfg_attr(
53082 not(target_arch = "arm"),
53083 stable(feature = "neon_intrinsics", since = "1.59.0")
53084)]
53085#[cfg_attr(
53086 target_arch = "arm",
53087 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53088)]
53089pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
53090 unsafe { transmute(a) }
53091}
53092#[doc = "Vector reinterpret cast operation"]
53093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
53094#[inline]
53095#[cfg(target_endian = "big")]
53096#[target_feature(enable = "neon")]
53097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53099#[cfg_attr(
53100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53101 assert_instr(nop)
53102)]
53103#[cfg_attr(
53104 not(target_arch = "arm"),
53105 stable(feature = "neon_intrinsics", since = "1.59.0")
53106)]
53107#[cfg_attr(
53108 target_arch = "arm",
53109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53110)]
53111pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
53112 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53113 unsafe {
53114 let ret_val: float32x2_t = transmute(a);
53115 simd_shuffle!(ret_val, ret_val, [1, 0])
53116 }
53117}
53118#[doc = "Vector reinterpret cast operation"]
53119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
53120#[inline]
53121#[cfg(target_endian = "little")]
53122#[target_feature(enable = "neon")]
53123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53125#[cfg_attr(
53126 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53127 assert_instr(nop)
53128)]
53129#[cfg_attr(
53130 not(target_arch = "arm"),
53131 stable(feature = "neon_intrinsics", since = "1.59.0")
53132)]
53133#[cfg_attr(
53134 target_arch = "arm",
53135 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53136)]
53137pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
53138 unsafe { transmute(a) }
53139}
53140#[doc = "Vector reinterpret cast operation"]
53141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
53142#[inline]
53143#[cfg(target_endian = "big")]
53144#[target_feature(enable = "neon")]
53145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53146#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53147#[cfg_attr(
53148 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53149 assert_instr(nop)
53150)]
53151#[cfg_attr(
53152 not(target_arch = "arm"),
53153 stable(feature = "neon_intrinsics", since = "1.59.0")
53154)]
53155#[cfg_attr(
53156 target_arch = "arm",
53157 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53158)]
53159pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
53160 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53161 unsafe {
53162 let ret_val: int8x8_t = transmute(a);
53163 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53164 }
53165}
53166#[doc = "Vector reinterpret cast operation"]
53167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
53168#[inline]
53169#[cfg(target_endian = "little")]
53170#[target_feature(enable = "neon")]
53171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53172#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53173#[cfg_attr(
53174 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53175 assert_instr(nop)
53176)]
53177#[cfg_attr(
53178 not(target_arch = "arm"),
53179 stable(feature = "neon_intrinsics", since = "1.59.0")
53180)]
53181#[cfg_attr(
53182 target_arch = "arm",
53183 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53184)]
53185pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
53186 unsafe { transmute(a) }
53187}
53188#[doc = "Vector reinterpret cast operation"]
53189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
53190#[inline]
53191#[cfg(target_endian = "big")]
53192#[target_feature(enable = "neon")]
53193#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53194#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53195#[cfg_attr(
53196 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53197 assert_instr(nop)
53198)]
53199#[cfg_attr(
53200 not(target_arch = "arm"),
53201 stable(feature = "neon_intrinsics", since = "1.59.0")
53202)]
53203#[cfg_attr(
53204 target_arch = "arm",
53205 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53206)]
53207pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
53208 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53209 unsafe {
53210 let ret_val: int16x4_t = transmute(a);
53211 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53212 }
53213}
53214#[doc = "Vector reinterpret cast operation"]
53215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
53216#[inline]
53217#[cfg(target_endian = "little")]
53218#[target_feature(enable = "neon")]
53219#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53220#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53221#[cfg_attr(
53222 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53223 assert_instr(nop)
53224)]
53225#[cfg_attr(
53226 not(target_arch = "arm"),
53227 stable(feature = "neon_intrinsics", since = "1.59.0")
53228)]
53229#[cfg_attr(
53230 target_arch = "arm",
53231 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53232)]
53233pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
53234 unsafe { transmute(a) }
53235}
53236#[doc = "Vector reinterpret cast operation"]
53237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
53238#[inline]
53239#[cfg(target_endian = "big")]
53240#[target_feature(enable = "neon")]
53241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53243#[cfg_attr(
53244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53245 assert_instr(nop)
53246)]
53247#[cfg_attr(
53248 not(target_arch = "arm"),
53249 stable(feature = "neon_intrinsics", since = "1.59.0")
53250)]
53251#[cfg_attr(
53252 target_arch = "arm",
53253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53254)]
53255pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
53256 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53257 unsafe {
53258 let ret_val: int32x2_t = transmute(a);
53259 simd_shuffle!(ret_val, ret_val, [1, 0])
53260 }
53261}
53262#[doc = "Vector reinterpret cast operation"]
53263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
53264#[inline]
53265#[cfg(target_endian = "little")]
53266#[target_feature(enable = "neon")]
53267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53268#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53269#[cfg_attr(
53270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53271 assert_instr(nop)
53272)]
53273#[cfg_attr(
53274 not(target_arch = "arm"),
53275 stable(feature = "neon_intrinsics", since = "1.59.0")
53276)]
53277#[cfg_attr(
53278 target_arch = "arm",
53279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53280)]
53281pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
53282 unsafe { transmute(a) }
53283}
53284#[doc = "Vector reinterpret cast operation"]
53285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
53286#[inline]
53287#[cfg(target_endian = "big")]
53288#[target_feature(enable = "neon")]
53289#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53290#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53291#[cfg_attr(
53292 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53293 assert_instr(nop)
53294)]
53295#[cfg_attr(
53296 not(target_arch = "arm"),
53297 stable(feature = "neon_intrinsics", since = "1.59.0")
53298)]
53299#[cfg_attr(
53300 target_arch = "arm",
53301 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53302)]
53303pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
53304 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53305 unsafe { transmute(a) }
53306}
53307#[doc = "Vector reinterpret cast operation"]
53308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
53309#[inline]
53310#[cfg(target_endian = "little")]
53311#[target_feature(enable = "neon")]
53312#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53313#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53314#[cfg_attr(
53315 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53316 assert_instr(nop)
53317)]
53318#[cfg_attr(
53319 not(target_arch = "arm"),
53320 stable(feature = "neon_intrinsics", since = "1.59.0")
53321)]
53322#[cfg_attr(
53323 target_arch = "arm",
53324 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53325)]
53326pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
53327 unsafe { transmute(a) }
53328}
53329#[doc = "Vector reinterpret cast operation"]
53330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
53331#[inline]
53332#[cfg(target_endian = "big")]
53333#[target_feature(enable = "neon")]
53334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53335#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53336#[cfg_attr(
53337 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53338 assert_instr(nop)
53339)]
53340#[cfg_attr(
53341 not(target_arch = "arm"),
53342 stable(feature = "neon_intrinsics", since = "1.59.0")
53343)]
53344#[cfg_attr(
53345 target_arch = "arm",
53346 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53347)]
53348pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
53349 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53350 unsafe {
53351 let ret_val: uint8x8_t = transmute(a);
53352 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53353 }
53354}
53355#[doc = "Vector reinterpret cast operation"]
53356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
53357#[inline]
53358#[cfg(target_endian = "little")]
53359#[target_feature(enable = "neon")]
53360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53362#[cfg_attr(
53363 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53364 assert_instr(nop)
53365)]
53366#[cfg_attr(
53367 not(target_arch = "arm"),
53368 stable(feature = "neon_intrinsics", since = "1.59.0")
53369)]
53370#[cfg_attr(
53371 target_arch = "arm",
53372 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53373)]
53374pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
53375 unsafe { transmute(a) }
53376}
53377#[doc = "Vector reinterpret cast operation"]
53378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
53379#[inline]
53380#[cfg(target_endian = "big")]
53381#[target_feature(enable = "neon")]
53382#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53383#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53384#[cfg_attr(
53385 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53386 assert_instr(nop)
53387)]
53388#[cfg_attr(
53389 not(target_arch = "arm"),
53390 stable(feature = "neon_intrinsics", since = "1.59.0")
53391)]
53392#[cfg_attr(
53393 target_arch = "arm",
53394 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53395)]
53396pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
53397 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53398 unsafe {
53399 let ret_val: uint16x4_t = transmute(a);
53400 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53401 }
53402}
53403#[doc = "Vector reinterpret cast operation"]
53404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
53405#[inline]
53406#[cfg(target_endian = "little")]
53407#[target_feature(enable = "neon")]
53408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53410#[cfg_attr(
53411 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53412 assert_instr(nop)
53413)]
53414#[cfg_attr(
53415 not(target_arch = "arm"),
53416 stable(feature = "neon_intrinsics", since = "1.59.0")
53417)]
53418#[cfg_attr(
53419 target_arch = "arm",
53420 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53421)]
53422pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
53423 unsafe { transmute(a) }
53424}
53425#[doc = "Vector reinterpret cast operation"]
53426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
53427#[inline]
53428#[cfg(target_endian = "big")]
53429#[target_feature(enable = "neon")]
53430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53431#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53432#[cfg_attr(
53433 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53434 assert_instr(nop)
53435)]
53436#[cfg_attr(
53437 not(target_arch = "arm"),
53438 stable(feature = "neon_intrinsics", since = "1.59.0")
53439)]
53440#[cfg_attr(
53441 target_arch = "arm",
53442 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53443)]
53444pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
53445 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53446 unsafe {
53447 let ret_val: uint32x2_t = transmute(a);
53448 simd_shuffle!(ret_val, ret_val, [1, 0])
53449 }
53450}
53451#[doc = "Vector reinterpret cast operation"]
53452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
53453#[inline]
53454#[cfg(target_endian = "little")]
53455#[target_feature(enable = "neon")]
53456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53458#[cfg_attr(
53459 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53460 assert_instr(nop)
53461)]
53462#[cfg_attr(
53463 not(target_arch = "arm"),
53464 stable(feature = "neon_intrinsics", since = "1.59.0")
53465)]
53466#[cfg_attr(
53467 target_arch = "arm",
53468 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53469)]
53470pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
53471 unsafe { transmute(a) }
53472}
53473#[doc = "Vector reinterpret cast operation"]
53474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
53475#[inline]
53476#[cfg(target_endian = "big")]
53477#[target_feature(enable = "neon")]
53478#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53479#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53480#[cfg_attr(
53481 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53482 assert_instr(nop)
53483)]
53484#[cfg_attr(
53485 not(target_arch = "arm"),
53486 stable(feature = "neon_intrinsics", since = "1.59.0")
53487)]
53488#[cfg_attr(
53489 target_arch = "arm",
53490 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53491)]
53492pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
53493 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53494 unsafe { transmute(a) }
53495}
53496#[doc = "Vector reinterpret cast operation"]
53497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
53498#[inline]
53499#[cfg(target_endian = "little")]
53500#[target_feature(enable = "neon")]
53501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53503#[cfg_attr(
53504 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53505 assert_instr(nop)
53506)]
53507#[cfg_attr(
53508 not(target_arch = "arm"),
53509 stable(feature = "neon_intrinsics", since = "1.59.0")
53510)]
53511#[cfg_attr(
53512 target_arch = "arm",
53513 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53514)]
53515pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
53516 unsafe { transmute(a) }
53517}
53518#[doc = "Vector reinterpret cast operation"]
53519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
53520#[inline]
53521#[cfg(target_endian = "big")]
53522#[target_feature(enable = "neon")]
53523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53524#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53525#[cfg_attr(
53526 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53527 assert_instr(nop)
53528)]
53529#[cfg_attr(
53530 not(target_arch = "arm"),
53531 stable(feature = "neon_intrinsics", since = "1.59.0")
53532)]
53533#[cfg_attr(
53534 target_arch = "arm",
53535 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53536)]
53537pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
53538 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53539 unsafe {
53540 let ret_val: poly16x4_t = transmute(a);
53541 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53542 }
53543}
53544#[doc = "Vector reinterpret cast operation"]
53545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
53546#[inline]
53547#[cfg(target_endian = "little")]
53548#[target_feature(enable = "neon")]
53549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53550#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53551#[cfg_attr(
53552 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53553 assert_instr(nop)
53554)]
53555#[cfg_attr(
53556 not(target_arch = "arm"),
53557 stable(feature = "neon_intrinsics", since = "1.59.0")
53558)]
53559#[cfg_attr(
53560 target_arch = "arm",
53561 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53562)]
53563pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
53564 unsafe { transmute(a) }
53565}
53566#[doc = "Vector reinterpret cast operation"]
53567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
53568#[inline]
53569#[cfg(target_endian = "big")]
53570#[target_feature(enable = "neon")]
53571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53573#[cfg_attr(
53574 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53575 assert_instr(nop)
53576)]
53577#[cfg_attr(
53578 not(target_arch = "arm"),
53579 stable(feature = "neon_intrinsics", since = "1.59.0")
53580)]
53581#[cfg_attr(
53582 target_arch = "arm",
53583 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53584)]
53585pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
53586 let a: poly8x16_t =
53587 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53588 unsafe {
53589 let ret_val: float32x4_t = transmute(a);
53590 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53591 }
53592}
53593#[doc = "Vector reinterpret cast operation"]
53594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
53595#[inline]
53596#[cfg(target_endian = "little")]
53597#[target_feature(enable = "neon")]
53598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53599#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53600#[cfg_attr(
53601 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53602 assert_instr(nop)
53603)]
53604#[cfg_attr(
53605 not(target_arch = "arm"),
53606 stable(feature = "neon_intrinsics", since = "1.59.0")
53607)]
53608#[cfg_attr(
53609 target_arch = "arm",
53610 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53611)]
53612pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
53613 unsafe { transmute(a) }
53614}
53615#[doc = "Vector reinterpret cast operation"]
53616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
53617#[inline]
53618#[cfg(target_endian = "big")]
53619#[target_feature(enable = "neon")]
53620#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53622#[cfg_attr(
53623 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53624 assert_instr(nop)
53625)]
53626#[cfg_attr(
53627 not(target_arch = "arm"),
53628 stable(feature = "neon_intrinsics", since = "1.59.0")
53629)]
53630#[cfg_attr(
53631 target_arch = "arm",
53632 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53633)]
53634pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
53635 let a: poly8x16_t =
53636 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53637 unsafe {
53638 let ret_val: int8x16_t = transmute(a);
53639 simd_shuffle!(
53640 ret_val,
53641 ret_val,
53642 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
53643 )
53644 }
53645}
53646#[doc = "Vector reinterpret cast operation"]
53647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
53648#[inline]
53649#[cfg(target_endian = "little")]
53650#[target_feature(enable = "neon")]
53651#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53652#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53653#[cfg_attr(
53654 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53655 assert_instr(nop)
53656)]
53657#[cfg_attr(
53658 not(target_arch = "arm"),
53659 stable(feature = "neon_intrinsics", since = "1.59.0")
53660)]
53661#[cfg_attr(
53662 target_arch = "arm",
53663 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53664)]
53665pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
53666 unsafe { transmute(a) }
53667}
53668#[doc = "Vector reinterpret cast operation"]
53669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
53670#[inline]
53671#[cfg(target_endian = "big")]
53672#[target_feature(enable = "neon")]
53673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53674#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53675#[cfg_attr(
53676 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53677 assert_instr(nop)
53678)]
53679#[cfg_attr(
53680 not(target_arch = "arm"),
53681 stable(feature = "neon_intrinsics", since = "1.59.0")
53682)]
53683#[cfg_attr(
53684 target_arch = "arm",
53685 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53686)]
53687pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
53688 let a: poly8x16_t =
53689 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53690 unsafe {
53691 let ret_val: int16x8_t = transmute(a);
53692 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53693 }
53694}
53695#[doc = "Vector reinterpret cast operation"]
53696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
53697#[inline]
53698#[cfg(target_endian = "little")]
53699#[target_feature(enable = "neon")]
53700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53701#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53702#[cfg_attr(
53703 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53704 assert_instr(nop)
53705)]
53706#[cfg_attr(
53707 not(target_arch = "arm"),
53708 stable(feature = "neon_intrinsics", since = "1.59.0")
53709)]
53710#[cfg_attr(
53711 target_arch = "arm",
53712 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53713)]
53714pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
53715 unsafe { transmute(a) }
53716}
53717#[doc = "Vector reinterpret cast operation"]
53718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
53719#[inline]
53720#[cfg(target_endian = "big")]
53721#[target_feature(enable = "neon")]
53722#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53723#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53724#[cfg_attr(
53725 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53726 assert_instr(nop)
53727)]
53728#[cfg_attr(
53729 not(target_arch = "arm"),
53730 stable(feature = "neon_intrinsics", since = "1.59.0")
53731)]
53732#[cfg_attr(
53733 target_arch = "arm",
53734 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53735)]
53736pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
53737 let a: poly8x16_t =
53738 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53739 unsafe {
53740 let ret_val: int32x4_t = transmute(a);
53741 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53742 }
53743}
53744#[doc = "Vector reinterpret cast operation"]
53745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
53746#[inline]
53747#[cfg(target_endian = "little")]
53748#[target_feature(enable = "neon")]
53749#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53750#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53751#[cfg_attr(
53752 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53753 assert_instr(nop)
53754)]
53755#[cfg_attr(
53756 not(target_arch = "arm"),
53757 stable(feature = "neon_intrinsics", since = "1.59.0")
53758)]
53759#[cfg_attr(
53760 target_arch = "arm",
53761 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53762)]
53763pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
53764 unsafe { transmute(a) }
53765}
53766#[doc = "Vector reinterpret cast operation"]
53767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
53768#[inline]
53769#[cfg(target_endian = "big")]
53770#[target_feature(enable = "neon")]
53771#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53772#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53773#[cfg_attr(
53774 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53775 assert_instr(nop)
53776)]
53777#[cfg_attr(
53778 not(target_arch = "arm"),
53779 stable(feature = "neon_intrinsics", since = "1.59.0")
53780)]
53781#[cfg_attr(
53782 target_arch = "arm",
53783 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53784)]
53785pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
53786 let a: poly8x16_t =
53787 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53788 unsafe {
53789 let ret_val: int64x2_t = transmute(a);
53790 simd_shuffle!(ret_val, ret_val, [1, 0])
53791 }
53792}
53793#[doc = "Vector reinterpret cast operation"]
53794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
53795#[inline]
53796#[cfg(target_endian = "little")]
53797#[target_feature(enable = "neon")]
53798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53799#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53800#[cfg_attr(
53801 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53802 assert_instr(nop)
53803)]
53804#[cfg_attr(
53805 not(target_arch = "arm"),
53806 stable(feature = "neon_intrinsics", since = "1.59.0")
53807)]
53808#[cfg_attr(
53809 target_arch = "arm",
53810 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53811)]
53812pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
53813 unsafe { transmute(a) }
53814}
53815#[doc = "Vector reinterpret cast operation"]
53816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
53817#[inline]
53818#[cfg(target_endian = "big")]
53819#[target_feature(enable = "neon")]
53820#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53821#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53822#[cfg_attr(
53823 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53824 assert_instr(nop)
53825)]
53826#[cfg_attr(
53827 not(target_arch = "arm"),
53828 stable(feature = "neon_intrinsics", since = "1.59.0")
53829)]
53830#[cfg_attr(
53831 target_arch = "arm",
53832 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53833)]
53834pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
53835 let a: poly8x16_t =
53836 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53837 unsafe {
53838 let ret_val: uint8x16_t = transmute(a);
53839 simd_shuffle!(
53840 ret_val,
53841 ret_val,
53842 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
53843 )
53844 }
53845}
53846#[doc = "Vector reinterpret cast operation"]
53847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
53848#[inline]
53849#[cfg(target_endian = "little")]
53850#[target_feature(enable = "neon")]
53851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53852#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53853#[cfg_attr(
53854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53855 assert_instr(nop)
53856)]
53857#[cfg_attr(
53858 not(target_arch = "arm"),
53859 stable(feature = "neon_intrinsics", since = "1.59.0")
53860)]
53861#[cfg_attr(
53862 target_arch = "arm",
53863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53864)]
53865pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
53866 unsafe { transmute(a) }
53867}
53868#[doc = "Vector reinterpret cast operation"]
53869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
53870#[inline]
53871#[cfg(target_endian = "big")]
53872#[target_feature(enable = "neon")]
53873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53874#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53875#[cfg_attr(
53876 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53877 assert_instr(nop)
53878)]
53879#[cfg_attr(
53880 not(target_arch = "arm"),
53881 stable(feature = "neon_intrinsics", since = "1.59.0")
53882)]
53883#[cfg_attr(
53884 target_arch = "arm",
53885 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53886)]
53887pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
53888 let a: poly8x16_t =
53889 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53890 unsafe {
53891 let ret_val: uint16x8_t = transmute(a);
53892 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53893 }
53894}
53895#[doc = "Vector reinterpret cast operation"]
53896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
53897#[inline]
53898#[cfg(target_endian = "little")]
53899#[target_feature(enable = "neon")]
53900#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53901#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53902#[cfg_attr(
53903 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53904 assert_instr(nop)
53905)]
53906#[cfg_attr(
53907 not(target_arch = "arm"),
53908 stable(feature = "neon_intrinsics", since = "1.59.0")
53909)]
53910#[cfg_attr(
53911 target_arch = "arm",
53912 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53913)]
53914pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
53915 unsafe { transmute(a) }
53916}
53917#[doc = "Vector reinterpret cast operation"]
53918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
53919#[inline]
53920#[cfg(target_endian = "big")]
53921#[target_feature(enable = "neon")]
53922#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53923#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53924#[cfg_attr(
53925 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53926 assert_instr(nop)
53927)]
53928#[cfg_attr(
53929 not(target_arch = "arm"),
53930 stable(feature = "neon_intrinsics", since = "1.59.0")
53931)]
53932#[cfg_attr(
53933 target_arch = "arm",
53934 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53935)]
53936pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
53937 let a: poly8x16_t =
53938 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53939 unsafe {
53940 let ret_val: uint32x4_t = transmute(a);
53941 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53942 }
53943}
53944#[doc = "Vector reinterpret cast operation"]
53945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
53946#[inline]
53947#[cfg(target_endian = "little")]
53948#[target_feature(enable = "neon")]
53949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53950#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53951#[cfg_attr(
53952 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53953 assert_instr(nop)
53954)]
53955#[cfg_attr(
53956 not(target_arch = "arm"),
53957 stable(feature = "neon_intrinsics", since = "1.59.0")
53958)]
53959#[cfg_attr(
53960 target_arch = "arm",
53961 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53962)]
53963pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
53964 unsafe { transmute(a) }
53965}
53966#[doc = "Vector reinterpret cast operation"]
53967#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
53968#[inline]
53969#[cfg(target_endian = "big")]
53970#[target_feature(enable = "neon")]
53971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53972#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53973#[cfg_attr(
53974 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53975 assert_instr(nop)
53976)]
53977#[cfg_attr(
53978 not(target_arch = "arm"),
53979 stable(feature = "neon_intrinsics", since = "1.59.0")
53980)]
53981#[cfg_attr(
53982 target_arch = "arm",
53983 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53984)]
53985pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
53986 let a: poly8x16_t =
53987 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53988 unsafe {
53989 let ret_val: uint64x2_t = transmute(a);
53990 simd_shuffle!(ret_val, ret_val, [1, 0])
53991 }
53992}
53993#[doc = "Vector reinterpret cast operation"]
53994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
53995#[inline]
53996#[cfg(target_endian = "little")]
53997#[target_feature(enable = "neon")]
53998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53999#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54000#[cfg_attr(
54001 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54002 assert_instr(nop)
54003)]
54004#[cfg_attr(
54005 not(target_arch = "arm"),
54006 stable(feature = "neon_intrinsics", since = "1.59.0")
54007)]
54008#[cfg_attr(
54009 target_arch = "arm",
54010 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54011)]
54012pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
54013 unsafe { transmute(a) }
54014}
54015#[doc = "Vector reinterpret cast operation"]
54016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
54017#[inline]
54018#[cfg(target_endian = "big")]
54019#[target_feature(enable = "neon")]
54020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54021#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54022#[cfg_attr(
54023 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54024 assert_instr(nop)
54025)]
54026#[cfg_attr(
54027 not(target_arch = "arm"),
54028 stable(feature = "neon_intrinsics", since = "1.59.0")
54029)]
54030#[cfg_attr(
54031 target_arch = "arm",
54032 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54033)]
54034pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
54035 let a: poly8x16_t =
54036 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
54037 unsafe {
54038 let ret_val: poly16x8_t = transmute(a);
54039 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54040 }
54041}
54042#[doc = "Vector reinterpret cast operation"]
54043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
54044#[inline]
54045#[cfg(target_endian = "little")]
54046#[target_feature(enable = "neon")]
54047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54048#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54049#[cfg_attr(
54050 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54051 assert_instr(nop)
54052)]
54053#[cfg_attr(
54054 not(target_arch = "arm"),
54055 stable(feature = "neon_intrinsics", since = "1.59.0")
54056)]
54057#[cfg_attr(
54058 target_arch = "arm",
54059 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54060)]
54061pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
54062 unsafe { transmute(a) }
54063}
54064#[doc = "Vector reinterpret cast operation"]
54065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
54066#[inline]
54067#[cfg(target_endian = "big")]
54068#[target_feature(enable = "neon")]
54069#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54070#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54071#[cfg_attr(
54072 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54073 assert_instr(nop)
54074)]
54075#[cfg_attr(
54076 not(target_arch = "arm"),
54077 stable(feature = "neon_intrinsics", since = "1.59.0")
54078)]
54079#[cfg_attr(
54080 target_arch = "arm",
54081 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54082)]
54083pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
54084 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54085 unsafe {
54086 let ret_val: float32x2_t = transmute(a);
54087 simd_shuffle!(ret_val, ret_val, [1, 0])
54088 }
54089}
54090#[doc = "Vector reinterpret cast operation"]
54091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
54092#[inline]
54093#[cfg(target_endian = "little")]
54094#[target_feature(enable = "neon")]
54095#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54097#[cfg_attr(
54098 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54099 assert_instr(nop)
54100)]
54101#[cfg_attr(
54102 not(target_arch = "arm"),
54103 stable(feature = "neon_intrinsics", since = "1.59.0")
54104)]
54105#[cfg_attr(
54106 target_arch = "arm",
54107 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54108)]
54109pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
54110 unsafe { transmute(a) }
54111}
54112#[doc = "Vector reinterpret cast operation"]
54113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
54114#[inline]
54115#[cfg(target_endian = "big")]
54116#[target_feature(enable = "neon")]
54117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54118#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54119#[cfg_attr(
54120 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54121 assert_instr(nop)
54122)]
54123#[cfg_attr(
54124 not(target_arch = "arm"),
54125 stable(feature = "neon_intrinsics", since = "1.59.0")
54126)]
54127#[cfg_attr(
54128 target_arch = "arm",
54129 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54130)]
54131pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
54132 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54133 unsafe {
54134 let ret_val: int8x8_t = transmute(a);
54135 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54136 }
54137}
54138#[doc = "Vector reinterpret cast operation"]
54139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
54140#[inline]
54141#[cfg(target_endian = "little")]
54142#[target_feature(enable = "neon")]
54143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54145#[cfg_attr(
54146 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54147 assert_instr(nop)
54148)]
54149#[cfg_attr(
54150 not(target_arch = "arm"),
54151 stable(feature = "neon_intrinsics", since = "1.59.0")
54152)]
54153#[cfg_attr(
54154 target_arch = "arm",
54155 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54156)]
54157pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
54158 unsafe { transmute(a) }
54159}
54160#[doc = "Vector reinterpret cast operation"]
54161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
54162#[inline]
54163#[cfg(target_endian = "big")]
54164#[target_feature(enable = "neon")]
54165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54167#[cfg_attr(
54168 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54169 assert_instr(nop)
54170)]
54171#[cfg_attr(
54172 not(target_arch = "arm"),
54173 stable(feature = "neon_intrinsics", since = "1.59.0")
54174)]
54175#[cfg_attr(
54176 target_arch = "arm",
54177 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54178)]
54179pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
54180 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54181 unsafe {
54182 let ret_val: int16x4_t = transmute(a);
54183 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54184 }
54185}
54186#[doc = "Vector reinterpret cast operation"]
54187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
54188#[inline]
54189#[cfg(target_endian = "little")]
54190#[target_feature(enable = "neon")]
54191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54192#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54193#[cfg_attr(
54194 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54195 assert_instr(nop)
54196)]
54197#[cfg_attr(
54198 not(target_arch = "arm"),
54199 stable(feature = "neon_intrinsics", since = "1.59.0")
54200)]
54201#[cfg_attr(
54202 target_arch = "arm",
54203 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54204)]
54205pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
54206 unsafe { transmute(a) }
54207}
54208#[doc = "Vector reinterpret cast operation"]
54209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
54210#[inline]
54211#[cfg(target_endian = "big")]
54212#[target_feature(enable = "neon")]
54213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54215#[cfg_attr(
54216 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54217 assert_instr(nop)
54218)]
54219#[cfg_attr(
54220 not(target_arch = "arm"),
54221 stable(feature = "neon_intrinsics", since = "1.59.0")
54222)]
54223#[cfg_attr(
54224 target_arch = "arm",
54225 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54226)]
54227pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
54228 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54229 unsafe {
54230 let ret_val: int32x2_t = transmute(a);
54231 simd_shuffle!(ret_val, ret_val, [1, 0])
54232 }
54233}
54234#[doc = "Vector reinterpret cast operation"]
54235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
54236#[inline]
54237#[cfg(target_endian = "little")]
54238#[target_feature(enable = "neon")]
54239#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54240#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54241#[cfg_attr(
54242 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54243 assert_instr(nop)
54244)]
54245#[cfg_attr(
54246 not(target_arch = "arm"),
54247 stable(feature = "neon_intrinsics", since = "1.59.0")
54248)]
54249#[cfg_attr(
54250 target_arch = "arm",
54251 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54252)]
54253pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
54254 unsafe { transmute(a) }
54255}
54256#[doc = "Vector reinterpret cast operation"]
54257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
54258#[inline]
54259#[cfg(target_endian = "big")]
54260#[target_feature(enable = "neon")]
54261#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54263#[cfg_attr(
54264 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54265 assert_instr(nop)
54266)]
54267#[cfg_attr(
54268 not(target_arch = "arm"),
54269 stable(feature = "neon_intrinsics", since = "1.59.0")
54270)]
54271#[cfg_attr(
54272 target_arch = "arm",
54273 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54274)]
54275pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
54276 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54277 unsafe { transmute(a) }
54278}
54279#[doc = "Vector reinterpret cast operation"]
54280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
54281#[inline]
54282#[cfg(target_endian = "little")]
54283#[target_feature(enable = "neon")]
54284#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54285#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54286#[cfg_attr(
54287 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54288 assert_instr(nop)
54289)]
54290#[cfg_attr(
54291 not(target_arch = "arm"),
54292 stable(feature = "neon_intrinsics", since = "1.59.0")
54293)]
54294#[cfg_attr(
54295 target_arch = "arm",
54296 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54297)]
54298pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
54299 unsafe { transmute(a) }
54300}
54301#[doc = "Vector reinterpret cast operation"]
54302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
54303#[inline]
54304#[cfg(target_endian = "big")]
54305#[target_feature(enable = "neon")]
54306#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54307#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54308#[cfg_attr(
54309 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54310 assert_instr(nop)
54311)]
54312#[cfg_attr(
54313 not(target_arch = "arm"),
54314 stable(feature = "neon_intrinsics", since = "1.59.0")
54315)]
54316#[cfg_attr(
54317 target_arch = "arm",
54318 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54319)]
54320pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
54321 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54322 unsafe {
54323 let ret_val: uint8x8_t = transmute(a);
54324 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54325 }
54326}
54327#[doc = "Vector reinterpret cast operation"]
54328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
54329#[inline]
54330#[cfg(target_endian = "little")]
54331#[target_feature(enable = "neon")]
54332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54333#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54334#[cfg_attr(
54335 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54336 assert_instr(nop)
54337)]
54338#[cfg_attr(
54339 not(target_arch = "arm"),
54340 stable(feature = "neon_intrinsics", since = "1.59.0")
54341)]
54342#[cfg_attr(
54343 target_arch = "arm",
54344 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54345)]
54346pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
54347 unsafe { transmute(a) }
54348}
54349#[doc = "Vector reinterpret cast operation"]
54350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
54351#[inline]
54352#[cfg(target_endian = "big")]
54353#[target_feature(enable = "neon")]
54354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54355#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54356#[cfg_attr(
54357 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54358 assert_instr(nop)
54359)]
54360#[cfg_attr(
54361 not(target_arch = "arm"),
54362 stable(feature = "neon_intrinsics", since = "1.59.0")
54363)]
54364#[cfg_attr(
54365 target_arch = "arm",
54366 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54367)]
54368pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
54369 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54370 unsafe {
54371 let ret_val: uint16x4_t = transmute(a);
54372 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54373 }
54374}
54375#[doc = "Vector reinterpret cast operation"]
54376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
54377#[inline]
54378#[cfg(target_endian = "little")]
54379#[target_feature(enable = "neon")]
54380#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54381#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54382#[cfg_attr(
54383 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54384 assert_instr(nop)
54385)]
54386#[cfg_attr(
54387 not(target_arch = "arm"),
54388 stable(feature = "neon_intrinsics", since = "1.59.0")
54389)]
54390#[cfg_attr(
54391 target_arch = "arm",
54392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54393)]
54394pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
54395 unsafe { transmute(a) }
54396}
54397#[doc = "Vector reinterpret cast operation"]
54398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
54399#[inline]
54400#[cfg(target_endian = "big")]
54401#[target_feature(enable = "neon")]
54402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54404#[cfg_attr(
54405 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54406 assert_instr(nop)
54407)]
54408#[cfg_attr(
54409 not(target_arch = "arm"),
54410 stable(feature = "neon_intrinsics", since = "1.59.0")
54411)]
54412#[cfg_attr(
54413 target_arch = "arm",
54414 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54415)]
54416pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
54417 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54418 unsafe {
54419 let ret_val: uint32x2_t = transmute(a);
54420 simd_shuffle!(ret_val, ret_val, [1, 0])
54421 }
54422}
54423#[doc = "Vector reinterpret cast operation"]
54424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
54425#[inline]
54426#[cfg(target_endian = "little")]
54427#[target_feature(enable = "neon")]
54428#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54429#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54430#[cfg_attr(
54431 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54432 assert_instr(nop)
54433)]
54434#[cfg_attr(
54435 not(target_arch = "arm"),
54436 stable(feature = "neon_intrinsics", since = "1.59.0")
54437)]
54438#[cfg_attr(
54439 target_arch = "arm",
54440 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54441)]
54442pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
54443 unsafe { transmute(a) }
54444}
54445#[doc = "Vector reinterpret cast operation"]
54446#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
54447#[inline]
54448#[cfg(target_endian = "big")]
54449#[target_feature(enable = "neon")]
54450#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54451#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54452#[cfg_attr(
54453 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54454 assert_instr(nop)
54455)]
54456#[cfg_attr(
54457 not(target_arch = "arm"),
54458 stable(feature = "neon_intrinsics", since = "1.59.0")
54459)]
54460#[cfg_attr(
54461 target_arch = "arm",
54462 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54463)]
54464pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
54465 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54466 unsafe { transmute(a) }
54467}
54468#[doc = "Vector reinterpret cast operation"]
54469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
54470#[inline]
54471#[cfg(target_endian = "little")]
54472#[target_feature(enable = "neon")]
54473#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54474#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54475#[cfg_attr(
54476 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54477 assert_instr(nop)
54478)]
54479#[cfg_attr(
54480 not(target_arch = "arm"),
54481 stable(feature = "neon_intrinsics", since = "1.59.0")
54482)]
54483#[cfg_attr(
54484 target_arch = "arm",
54485 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54486)]
54487pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
54488 unsafe { transmute(a) }
54489}
54490#[doc = "Vector reinterpret cast operation"]
54491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
54492#[inline]
54493#[cfg(target_endian = "big")]
54494#[target_feature(enable = "neon")]
54495#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54496#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54497#[cfg_attr(
54498 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54499 assert_instr(nop)
54500)]
54501#[cfg_attr(
54502 not(target_arch = "arm"),
54503 stable(feature = "neon_intrinsics", since = "1.59.0")
54504)]
54505#[cfg_attr(
54506 target_arch = "arm",
54507 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54508)]
54509pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
54510 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54511 unsafe {
54512 let ret_val: poly8x8_t = transmute(a);
54513 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54514 }
54515}
54516#[doc = "Vector reinterpret cast operation"]
54517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
54518#[inline]
54519#[cfg(target_endian = "little")]
54520#[target_feature(enable = "neon")]
54521#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54522#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54523#[cfg_attr(
54524 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54525 assert_instr(nop)
54526)]
54527#[cfg_attr(
54528 not(target_arch = "arm"),
54529 stable(feature = "neon_intrinsics", since = "1.59.0")
54530)]
54531#[cfg_attr(
54532 target_arch = "arm",
54533 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54534)]
54535pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
54536 unsafe { transmute(a) }
54537}
54538#[doc = "Vector reinterpret cast operation"]
54539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
54540#[inline]
54541#[cfg(target_endian = "big")]
54542#[target_feature(enable = "neon")]
54543#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54544#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54545#[cfg_attr(
54546 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54547 assert_instr(nop)
54548)]
54549#[cfg_attr(
54550 not(target_arch = "arm"),
54551 stable(feature = "neon_intrinsics", since = "1.59.0")
54552)]
54553#[cfg_attr(
54554 target_arch = "arm",
54555 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54556)]
54557pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
54558 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54559 unsafe {
54560 let ret_val: float32x4_t = transmute(a);
54561 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54562 }
54563}
54564#[doc = "Vector reinterpret cast operation"]
54565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
54566#[inline]
54567#[cfg(target_endian = "little")]
54568#[target_feature(enable = "neon")]
54569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54570#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54571#[cfg_attr(
54572 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54573 assert_instr(nop)
54574)]
54575#[cfg_attr(
54576 not(target_arch = "arm"),
54577 stable(feature = "neon_intrinsics", since = "1.59.0")
54578)]
54579#[cfg_attr(
54580 target_arch = "arm",
54581 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54582)]
54583pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
54584 unsafe { transmute(a) }
54585}
54586#[doc = "Vector reinterpret cast operation"]
54587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
54588#[inline]
54589#[cfg(target_endian = "big")]
54590#[target_feature(enable = "neon")]
54591#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54592#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54593#[cfg_attr(
54594 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54595 assert_instr(nop)
54596)]
54597#[cfg_attr(
54598 not(target_arch = "arm"),
54599 stable(feature = "neon_intrinsics", since = "1.59.0")
54600)]
54601#[cfg_attr(
54602 target_arch = "arm",
54603 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54604)]
54605pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
54606 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54607 unsafe {
54608 let ret_val: int8x16_t = transmute(a);
54609 simd_shuffle!(
54610 ret_val,
54611 ret_val,
54612 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54613 )
54614 }
54615}
54616#[doc = "Vector reinterpret cast operation"]
54617#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
54618#[inline]
54619#[cfg(target_endian = "little")]
54620#[target_feature(enable = "neon")]
54621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54622#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54623#[cfg_attr(
54624 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54625 assert_instr(nop)
54626)]
54627#[cfg_attr(
54628 not(target_arch = "arm"),
54629 stable(feature = "neon_intrinsics", since = "1.59.0")
54630)]
54631#[cfg_attr(
54632 target_arch = "arm",
54633 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54634)]
54635pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
54636 unsafe { transmute(a) }
54637}
54638#[doc = "Vector reinterpret cast operation"]
54639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
54640#[inline]
54641#[cfg(target_endian = "big")]
54642#[target_feature(enable = "neon")]
54643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54645#[cfg_attr(
54646 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54647 assert_instr(nop)
54648)]
54649#[cfg_attr(
54650 not(target_arch = "arm"),
54651 stable(feature = "neon_intrinsics", since = "1.59.0")
54652)]
54653#[cfg_attr(
54654 target_arch = "arm",
54655 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54656)]
54657pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
54658 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54659 unsafe {
54660 let ret_val: int16x8_t = transmute(a);
54661 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54662 }
54663}
54664#[doc = "Vector reinterpret cast operation"]
54665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
54666#[inline]
54667#[cfg(target_endian = "little")]
54668#[target_feature(enable = "neon")]
54669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54671#[cfg_attr(
54672 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54673 assert_instr(nop)
54674)]
54675#[cfg_attr(
54676 not(target_arch = "arm"),
54677 stable(feature = "neon_intrinsics", since = "1.59.0")
54678)]
54679#[cfg_attr(
54680 target_arch = "arm",
54681 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54682)]
54683pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
54684 unsafe { transmute(a) }
54685}
54686#[doc = "Vector reinterpret cast operation"]
54687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
54688#[inline]
54689#[cfg(target_endian = "big")]
54690#[target_feature(enable = "neon")]
54691#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54692#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54693#[cfg_attr(
54694 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54695 assert_instr(nop)
54696)]
54697#[cfg_attr(
54698 not(target_arch = "arm"),
54699 stable(feature = "neon_intrinsics", since = "1.59.0")
54700)]
54701#[cfg_attr(
54702 target_arch = "arm",
54703 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54704)]
54705pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
54706 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54707 unsafe {
54708 let ret_val: int32x4_t = transmute(a);
54709 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54710 }
54711}
54712#[doc = "Vector reinterpret cast operation"]
54713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
54714#[inline]
54715#[cfg(target_endian = "little")]
54716#[target_feature(enable = "neon")]
54717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54718#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54719#[cfg_attr(
54720 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54721 assert_instr(nop)
54722)]
54723#[cfg_attr(
54724 not(target_arch = "arm"),
54725 stable(feature = "neon_intrinsics", since = "1.59.0")
54726)]
54727#[cfg_attr(
54728 target_arch = "arm",
54729 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54730)]
54731pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
54732 unsafe { transmute(a) }
54733}
54734#[doc = "Vector reinterpret cast operation"]
54735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
54736#[inline]
54737#[cfg(target_endian = "big")]
54738#[target_feature(enable = "neon")]
54739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54741#[cfg_attr(
54742 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54743 assert_instr(nop)
54744)]
54745#[cfg_attr(
54746 not(target_arch = "arm"),
54747 stable(feature = "neon_intrinsics", since = "1.59.0")
54748)]
54749#[cfg_attr(
54750 target_arch = "arm",
54751 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54752)]
54753pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
54754 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54755 unsafe {
54756 let ret_val: int64x2_t = transmute(a);
54757 simd_shuffle!(ret_val, ret_val, [1, 0])
54758 }
54759}
54760#[doc = "Vector reinterpret cast operation"]
54761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
54762#[inline]
54763#[cfg(target_endian = "little")]
54764#[target_feature(enable = "neon")]
54765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54766#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54767#[cfg_attr(
54768 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54769 assert_instr(nop)
54770)]
54771#[cfg_attr(
54772 not(target_arch = "arm"),
54773 stable(feature = "neon_intrinsics", since = "1.59.0")
54774)]
54775#[cfg_attr(
54776 target_arch = "arm",
54777 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54778)]
54779pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
54780 unsafe { transmute(a) }
54781}
54782#[doc = "Vector reinterpret cast operation"]
54783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
54784#[inline]
54785#[cfg(target_endian = "big")]
54786#[target_feature(enable = "neon")]
54787#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54788#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54789#[cfg_attr(
54790 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54791 assert_instr(nop)
54792)]
54793#[cfg_attr(
54794 not(target_arch = "arm"),
54795 stable(feature = "neon_intrinsics", since = "1.59.0")
54796)]
54797#[cfg_attr(
54798 target_arch = "arm",
54799 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54800)]
54801pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
54802 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54803 unsafe {
54804 let ret_val: uint8x16_t = transmute(a);
54805 simd_shuffle!(
54806 ret_val,
54807 ret_val,
54808 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54809 )
54810 }
54811}
54812#[doc = "Vector reinterpret cast operation"]
54813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
54814#[inline]
54815#[cfg(target_endian = "little")]
54816#[target_feature(enable = "neon")]
54817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54818#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54819#[cfg_attr(
54820 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54821 assert_instr(nop)
54822)]
54823#[cfg_attr(
54824 not(target_arch = "arm"),
54825 stable(feature = "neon_intrinsics", since = "1.59.0")
54826)]
54827#[cfg_attr(
54828 target_arch = "arm",
54829 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54830)]
54831pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
54832 unsafe { transmute(a) }
54833}
54834#[doc = "Vector reinterpret cast operation"]
54835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
54836#[inline]
54837#[cfg(target_endian = "big")]
54838#[target_feature(enable = "neon")]
54839#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54840#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54841#[cfg_attr(
54842 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54843 assert_instr(nop)
54844)]
54845#[cfg_attr(
54846 not(target_arch = "arm"),
54847 stable(feature = "neon_intrinsics", since = "1.59.0")
54848)]
54849#[cfg_attr(
54850 target_arch = "arm",
54851 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54852)]
54853pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
54854 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54855 unsafe {
54856 let ret_val: uint16x8_t = transmute(a);
54857 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54858 }
54859}
54860#[doc = "Vector reinterpret cast operation"]
54861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
54862#[inline]
54863#[cfg(target_endian = "little")]
54864#[target_feature(enable = "neon")]
54865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54867#[cfg_attr(
54868 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54869 assert_instr(nop)
54870)]
54871#[cfg_attr(
54872 not(target_arch = "arm"),
54873 stable(feature = "neon_intrinsics", since = "1.59.0")
54874)]
54875#[cfg_attr(
54876 target_arch = "arm",
54877 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54878)]
54879pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
54880 unsafe { transmute(a) }
54881}
54882#[doc = "Vector reinterpret cast operation"]
54883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
54884#[inline]
54885#[cfg(target_endian = "big")]
54886#[target_feature(enable = "neon")]
54887#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54888#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54889#[cfg_attr(
54890 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54891 assert_instr(nop)
54892)]
54893#[cfg_attr(
54894 not(target_arch = "arm"),
54895 stable(feature = "neon_intrinsics", since = "1.59.0")
54896)]
54897#[cfg_attr(
54898 target_arch = "arm",
54899 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54900)]
54901pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
54902 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54903 unsafe {
54904 let ret_val: uint32x4_t = transmute(a);
54905 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54906 }
54907}
54908#[doc = "Vector reinterpret cast operation"]
54909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
54910#[inline]
54911#[cfg(target_endian = "little")]
54912#[target_feature(enable = "neon")]
54913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54914#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54915#[cfg_attr(
54916 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54917 assert_instr(nop)
54918)]
54919#[cfg_attr(
54920 not(target_arch = "arm"),
54921 stable(feature = "neon_intrinsics", since = "1.59.0")
54922)]
54923#[cfg_attr(
54924 target_arch = "arm",
54925 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54926)]
54927pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
54928 unsafe { transmute(a) }
54929}
54930#[doc = "Vector reinterpret cast operation"]
54931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
54932#[inline]
54933#[cfg(target_endian = "big")]
54934#[target_feature(enable = "neon")]
54935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54936#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54937#[cfg_attr(
54938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54939 assert_instr(nop)
54940)]
54941#[cfg_attr(
54942 not(target_arch = "arm"),
54943 stable(feature = "neon_intrinsics", since = "1.59.0")
54944)]
54945#[cfg_attr(
54946 target_arch = "arm",
54947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54948)]
54949pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
54950 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54951 unsafe {
54952 let ret_val: uint64x2_t = transmute(a);
54953 simd_shuffle!(ret_val, ret_val, [1, 0])
54954 }
54955}
54956#[doc = "Vector reinterpret cast operation"]
54957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
54958#[inline]
54959#[cfg(target_endian = "little")]
54960#[target_feature(enable = "neon")]
54961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54962#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54963#[cfg_attr(
54964 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54965 assert_instr(nop)
54966)]
54967#[cfg_attr(
54968 not(target_arch = "arm"),
54969 stable(feature = "neon_intrinsics", since = "1.59.0")
54970)]
54971#[cfg_attr(
54972 target_arch = "arm",
54973 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54974)]
54975pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
54976 unsafe { transmute(a) }
54977}
54978#[doc = "Vector reinterpret cast operation"]
54979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
54980#[inline]
54981#[cfg(target_endian = "big")]
54982#[target_feature(enable = "neon")]
54983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54985#[cfg_attr(
54986 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54987 assert_instr(nop)
54988)]
54989#[cfg_attr(
54990 not(target_arch = "arm"),
54991 stable(feature = "neon_intrinsics", since = "1.59.0")
54992)]
54993#[cfg_attr(
54994 target_arch = "arm",
54995 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54996)]
54997pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
54998 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54999 unsafe {
55000 let ret_val: poly8x16_t = transmute(a);
55001 simd_shuffle!(
55002 ret_val,
55003 ret_val,
55004 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
55005 )
55006 }
55007}
55008#[doc = "Vector reinterpret cast operation"]
55009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
55010#[inline]
55011#[cfg(target_endian = "little")]
55012#[target_feature(enable = "neon,aes")]
55013#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55014#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55015#[cfg_attr(
55016 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55017 assert_instr(nop)
55018)]
55019#[cfg_attr(
55020 not(target_arch = "arm"),
55021 stable(feature = "neon_intrinsics", since = "1.59.0")
55022)]
55023#[cfg_attr(
55024 target_arch = "arm",
55025 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55026)]
55027pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
55028 unsafe { transmute(a) }
55029}
55030#[doc = "Vector reinterpret cast operation"]
55031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
55032#[inline]
55033#[cfg(target_endian = "big")]
55034#[target_feature(enable = "neon,aes")]
55035#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55036#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55037#[cfg_attr(
55038 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55039 assert_instr(nop)
55040)]
55041#[cfg_attr(
55042 not(target_arch = "arm"),
55043 stable(feature = "neon_intrinsics", since = "1.59.0")
55044)]
55045#[cfg_attr(
55046 target_arch = "arm",
55047 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55048)]
55049pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
55050 unsafe {
55051 let ret_val: int8x16_t = transmute(a);
55052 simd_shuffle!(
55053 ret_val,
55054 ret_val,
55055 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
55056 )
55057 }
55058}
55059#[doc = "Vector reinterpret cast operation"]
55060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
55061#[inline]
55062#[cfg(target_endian = "little")]
55063#[target_feature(enable = "neon,aes")]
55064#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55065#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55066#[cfg_attr(
55067 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55068 assert_instr(nop)
55069)]
55070#[cfg_attr(
55071 not(target_arch = "arm"),
55072 stable(feature = "neon_intrinsics", since = "1.59.0")
55073)]
55074#[cfg_attr(
55075 target_arch = "arm",
55076 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55077)]
55078pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
55079 unsafe { transmute(a) }
55080}
55081#[doc = "Vector reinterpret cast operation"]
55082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
55083#[inline]
55084#[cfg(target_endian = "big")]
55085#[target_feature(enable = "neon,aes")]
55086#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55087#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55088#[cfg_attr(
55089 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55090 assert_instr(nop)
55091)]
55092#[cfg_attr(
55093 not(target_arch = "arm"),
55094 stable(feature = "neon_intrinsics", since = "1.59.0")
55095)]
55096#[cfg_attr(
55097 target_arch = "arm",
55098 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55099)]
55100pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
55101 unsafe {
55102 let ret_val: int16x8_t = transmute(a);
55103 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
55104 }
55105}
55106#[doc = "Vector reinterpret cast operation"]
55107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
55108#[inline]
55109#[cfg(target_endian = "little")]
55110#[target_feature(enable = "neon,aes")]
55111#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55113#[cfg_attr(
55114 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55115 assert_instr(nop)
55116)]
55117#[cfg_attr(
55118 not(target_arch = "arm"),
55119 stable(feature = "neon_intrinsics", since = "1.59.0")
55120)]
55121#[cfg_attr(
55122 target_arch = "arm",
55123 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55124)]
55125pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
55126 unsafe { transmute(a) }
55127}
55128#[doc = "Vector reinterpret cast operation"]
55129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
55130#[inline]
55131#[cfg(target_endian = "big")]
55132#[target_feature(enable = "neon,aes")]
55133#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55135#[cfg_attr(
55136 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55137 assert_instr(nop)
55138)]
55139#[cfg_attr(
55140 not(target_arch = "arm"),
55141 stable(feature = "neon_intrinsics", since = "1.59.0")
55142)]
55143#[cfg_attr(
55144 target_arch = "arm",
55145 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55146)]
55147pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
55148 unsafe {
55149 let ret_val: int32x4_t = transmute(a);
55150 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
55151 }
55152}
55153#[doc = "Vector reinterpret cast operation"]
55154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
55155#[inline]
55156#[cfg(target_endian = "little")]
55157#[target_feature(enable = "neon,aes")]
55158#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55160#[cfg_attr(
55161 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55162 assert_instr(nop)
55163)]
55164#[cfg_attr(
55165 not(target_arch = "arm"),
55166 stable(feature = "neon_intrinsics", since = "1.59.0")
55167)]
55168#[cfg_attr(
55169 target_arch = "arm",
55170 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55171)]
55172pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
55173 unsafe { transmute(a) }
55174}
55175#[doc = "Vector reinterpret cast operation"]
55176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
55177#[inline]
55178#[cfg(target_endian = "big")]
55179#[target_feature(enable = "neon,aes")]
55180#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55181#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55182#[cfg_attr(
55183 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55184 assert_instr(nop)
55185)]
55186#[cfg_attr(
55187 not(target_arch = "arm"),
55188 stable(feature = "neon_intrinsics", since = "1.59.0")
55189)]
55190#[cfg_attr(
55191 target_arch = "arm",
55192 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55193)]
55194pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
55195 unsafe {
55196 let ret_val: int64x2_t = transmute(a);
55197 simd_shuffle!(ret_val, ret_val, [1, 0])
55198 }
55199}
55200#[doc = "Vector reinterpret cast operation"]
55201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
55202#[inline]
55203#[cfg(target_endian = "little")]
55204#[target_feature(enable = "neon,aes")]
55205#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55206#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55207#[cfg_attr(
55208 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55209 assert_instr(nop)
55210)]
55211#[cfg_attr(
55212 not(target_arch = "arm"),
55213 stable(feature = "neon_intrinsics", since = "1.59.0")
55214)]
55215#[cfg_attr(
55216 target_arch = "arm",
55217 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55218)]
55219pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
55220 unsafe { transmute(a) }
55221}
55222#[doc = "Vector reinterpret cast operation"]
55223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
55224#[inline]
55225#[cfg(target_endian = "big")]
55226#[target_feature(enable = "neon,aes")]
55227#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55229#[cfg_attr(
55230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55231 assert_instr(nop)
55232)]
55233#[cfg_attr(
55234 not(target_arch = "arm"),
55235 stable(feature = "neon_intrinsics", since = "1.59.0")
55236)]
55237#[cfg_attr(
55238 target_arch = "arm",
55239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55240)]
55241pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
55242 unsafe {
55243 let ret_val: uint8x16_t = transmute(a);
55244 simd_shuffle!(
55245 ret_val,
55246 ret_val,
55247 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
55248 )
55249 }
55250}
55251#[doc = "Vector reinterpret cast operation"]
55252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
55253#[inline]
55254#[cfg(target_endian = "little")]
55255#[target_feature(enable = "neon,aes")]
55256#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55257#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55258#[cfg_attr(
55259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55260 assert_instr(nop)
55261)]
55262#[cfg_attr(
55263 not(target_arch = "arm"),
55264 stable(feature = "neon_intrinsics", since = "1.59.0")
55265)]
55266#[cfg_attr(
55267 target_arch = "arm",
55268 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55269)]
55270pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
55271 unsafe { transmute(a) }
55272}
55273#[doc = "Vector reinterpret cast operation"]
55274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
55275#[inline]
55276#[cfg(target_endian = "big")]
55277#[target_feature(enable = "neon,aes")]
55278#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55279#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55280#[cfg_attr(
55281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55282 assert_instr(nop)
55283)]
55284#[cfg_attr(
55285 not(target_arch = "arm"),
55286 stable(feature = "neon_intrinsics", since = "1.59.0")
55287)]
55288#[cfg_attr(
55289 target_arch = "arm",
55290 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55291)]
55292pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
55293 unsafe {
55294 let ret_val: uint16x8_t = transmute(a);
55295 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
55296 }
55297}
55298#[doc = "Vector reinterpret cast operation"]
55299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
55300#[inline]
55301#[cfg(target_endian = "little")]
55302#[target_feature(enable = "neon,aes")]
55303#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55304#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55305#[cfg_attr(
55306 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55307 assert_instr(nop)
55308)]
55309#[cfg_attr(
55310 not(target_arch = "arm"),
55311 stable(feature = "neon_intrinsics", since = "1.59.0")
55312)]
55313#[cfg_attr(
55314 target_arch = "arm",
55315 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55316)]
55317pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
55318 unsafe { transmute(a) }
55319}
55320#[doc = "Vector reinterpret cast operation"]
55321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
55322#[inline]
55323#[cfg(target_endian = "big")]
55324#[target_feature(enable = "neon,aes")]
55325#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55327#[cfg_attr(
55328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55329 assert_instr(nop)
55330)]
55331#[cfg_attr(
55332 not(target_arch = "arm"),
55333 stable(feature = "neon_intrinsics", since = "1.59.0")
55334)]
55335#[cfg_attr(
55336 target_arch = "arm",
55337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55338)]
55339pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
55340 unsafe {
55341 let ret_val: uint32x4_t = transmute(a);
55342 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
55343 }
55344}
55345#[doc = "Vector reinterpret cast operation"]
55346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
55347#[inline]
55348#[cfg(target_endian = "little")]
55349#[target_feature(enable = "neon,aes")]
55350#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55351#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55352#[cfg_attr(
55353 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55354 assert_instr(nop)
55355)]
55356#[cfg_attr(
55357 not(target_arch = "arm"),
55358 stable(feature = "neon_intrinsics", since = "1.59.0")
55359)]
55360#[cfg_attr(
55361 target_arch = "arm",
55362 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55363)]
55364pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
55365 unsafe { transmute(a) }
55366}
55367#[doc = "Vector reinterpret cast operation"]
55368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
55369#[inline]
55370#[cfg(target_endian = "big")]
55371#[target_feature(enable = "neon,aes")]
55372#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55373#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55374#[cfg_attr(
55375 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55376 assert_instr(nop)
55377)]
55378#[cfg_attr(
55379 not(target_arch = "arm"),
55380 stable(feature = "neon_intrinsics", since = "1.59.0")
55381)]
55382#[cfg_attr(
55383 target_arch = "arm",
55384 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55385)]
55386pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
55387 unsafe {
55388 let ret_val: uint64x2_t = transmute(a);
55389 simd_shuffle!(ret_val, ret_val, [1, 0])
55390 }
55391}
55392#[doc = "Vector reinterpret cast operation"]
55393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
55394#[inline]
55395#[cfg(target_endian = "little")]
55396#[target_feature(enable = "neon,aes")]
55397#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55398#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55399#[cfg_attr(
55400 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55401 assert_instr(nop)
55402)]
55403#[cfg_attr(
55404 not(target_arch = "arm"),
55405 stable(feature = "neon_intrinsics", since = "1.59.0")
55406)]
55407#[cfg_attr(
55408 target_arch = "arm",
55409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55410)]
55411pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
55412 unsafe { transmute(a) }
55413}
55414#[doc = "Vector reinterpret cast operation"]
55415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
55416#[inline]
55417#[cfg(target_endian = "big")]
55418#[target_feature(enable = "neon,aes")]
55419#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55420#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55421#[cfg_attr(
55422 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55423 assert_instr(nop)
55424)]
55425#[cfg_attr(
55426 not(target_arch = "arm"),
55427 stable(feature = "neon_intrinsics", since = "1.59.0")
55428)]
55429#[cfg_attr(
55430 target_arch = "arm",
55431 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55432)]
55433pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
55434 unsafe {
55435 let ret_val: poly8x16_t = transmute(a);
55436 simd_shuffle!(
55437 ret_val,
55438 ret_val,
55439 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
55440 )
55441 }
55442}
55443#[doc = "Vector reinterpret cast operation"]
55444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
55445#[inline]
55446#[cfg(target_endian = "little")]
55447#[target_feature(enable = "neon,aes")]
55448#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55449#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55450#[cfg_attr(
55451 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55452 assert_instr(nop)
55453)]
55454#[cfg_attr(
55455 not(target_arch = "arm"),
55456 stable(feature = "neon_intrinsics", since = "1.59.0")
55457)]
55458#[cfg_attr(
55459 target_arch = "arm",
55460 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55461)]
55462pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
55463 unsafe { transmute(a) }
55464}
55465#[doc = "Vector reinterpret cast operation"]
55466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
55467#[inline]
55468#[cfg(target_endian = "big")]
55469#[target_feature(enable = "neon,aes")]
55470#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55471#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55472#[cfg_attr(
55473 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55474 assert_instr(nop)
55475)]
55476#[cfg_attr(
55477 not(target_arch = "arm"),
55478 stable(feature = "neon_intrinsics", since = "1.59.0")
55479)]
55480#[cfg_attr(
55481 target_arch = "arm",
55482 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55483)]
55484pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
55485 unsafe {
55486 let ret_val: poly16x8_t = transmute(a);
55487 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
55488 }
55489}
55490#[doc = "Vector reinterpret cast operation"]
55491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
55492#[inline]
55493#[cfg(target_endian = "little")]
55494#[target_feature(enable = "neon,aes")]
55495#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55496#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55497#[cfg_attr(
55498 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55499 assert_instr(nop)
55500)]
55501#[cfg_attr(
55502 not(target_arch = "arm"),
55503 stable(feature = "neon_intrinsics", since = "1.59.0")
55504)]
55505#[cfg_attr(
55506 target_arch = "arm",
55507 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55508)]
55509pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
55510 unsafe { transmute(a) }
55511}
55512#[doc = "Vector reinterpret cast operation"]
55513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
55514#[inline]
55515#[cfg(target_endian = "big")]
55516#[target_feature(enable = "neon,aes")]
55517#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55518#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55519#[cfg_attr(
55520 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55521 assert_instr(nop)
55522)]
55523#[cfg_attr(
55524 not(target_arch = "arm"),
55525 stable(feature = "neon_intrinsics", since = "1.59.0")
55526)]
55527#[cfg_attr(
55528 target_arch = "arm",
55529 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55530)]
55531pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
55532 unsafe {
55533 let ret_val: poly64x2_t = transmute(a);
55534 simd_shuffle!(ret_val, ret_val, [1, 0])
55535 }
55536}
55537#[doc = "Vector reinterpret cast operation"]
55538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
55539#[inline]
55540#[cfg(target_endian = "little")]
55541#[target_feature(enable = "neon,aes")]
55542#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55544#[cfg_attr(
55545 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55546 assert_instr(nop)
55547)]
55548#[cfg_attr(
55549 not(target_arch = "arm"),
55550 stable(feature = "neon_intrinsics", since = "1.59.0")
55551)]
55552#[cfg_attr(
55553 target_arch = "arm",
55554 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55555)]
55556pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
55557 unsafe { transmute(a) }
55558}
55559#[doc = "Vector reinterpret cast operation"]
55560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
55561#[inline]
55562#[cfg(target_endian = "big")]
55563#[target_feature(enable = "neon,aes")]
55564#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55565#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55566#[cfg_attr(
55567 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55568 assert_instr(nop)
55569)]
55570#[cfg_attr(
55571 not(target_arch = "arm"),
55572 stable(feature = "neon_intrinsics", since = "1.59.0")
55573)]
55574#[cfg_attr(
55575 target_arch = "arm",
55576 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55577)]
55578pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
55579 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55580 unsafe { transmute(a) }
55581}
55582#[doc = "Vector reinterpret cast operation"]
55583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
55584#[inline]
55585#[cfg(target_endian = "little")]
55586#[target_feature(enable = "neon,aes")]
55587#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55588#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55589#[cfg_attr(
55590 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55591 assert_instr(nop)
55592)]
55593#[cfg_attr(
55594 not(target_arch = "arm"),
55595 stable(feature = "neon_intrinsics", since = "1.59.0")
55596)]
55597#[cfg_attr(
55598 target_arch = "arm",
55599 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55600)]
55601pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
55602 unsafe { transmute(a) }
55603}
55604#[doc = "Vector reinterpret cast operation"]
55605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
55606#[inline]
55607#[cfg(target_endian = "big")]
55608#[target_feature(enable = "neon,aes")]
55609#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55611#[cfg_attr(
55612 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55613 assert_instr(nop)
55614)]
55615#[cfg_attr(
55616 not(target_arch = "arm"),
55617 stable(feature = "neon_intrinsics", since = "1.59.0")
55618)]
55619#[cfg_attr(
55620 target_arch = "arm",
55621 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55622)]
55623pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
55624 let a: int8x16_t =
55625 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
55626 unsafe { transmute(a) }
55627}
55628#[doc = "Vector reinterpret cast operation"]
55629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
55630#[inline]
55631#[cfg(target_endian = "little")]
55632#[target_feature(enable = "neon,aes")]
55633#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55634#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55635#[cfg_attr(
55636 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55637 assert_instr(nop)
55638)]
55639#[cfg_attr(
55640 not(target_arch = "arm"),
55641 stable(feature = "neon_intrinsics", since = "1.59.0")
55642)]
55643#[cfg_attr(
55644 target_arch = "arm",
55645 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55646)]
55647pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
55648 unsafe { transmute(a) }
55649}
55650#[doc = "Vector reinterpret cast operation"]
55651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
55652#[inline]
55653#[cfg(target_endian = "big")]
55654#[target_feature(enable = "neon,aes")]
55655#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55656#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55657#[cfg_attr(
55658 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55659 assert_instr(nop)
55660)]
55661#[cfg_attr(
55662 not(target_arch = "arm"),
55663 stable(feature = "neon_intrinsics", since = "1.59.0")
55664)]
55665#[cfg_attr(
55666 target_arch = "arm",
55667 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55668)]
55669pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
55670 let a: int8x16_t =
55671 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
55672 unsafe {
55673 let ret_val: poly64x2_t = transmute(a);
55674 simd_shuffle!(ret_val, ret_val, [1, 0])
55675 }
55676}
55677#[doc = "Vector reinterpret cast operation"]
55678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
55679#[inline]
55680#[cfg(target_endian = "little")]
55681#[target_feature(enable = "neon,aes")]
55682#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55683#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55684#[cfg_attr(
55685 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55686 assert_instr(nop)
55687)]
55688#[cfg_attr(
55689 not(target_arch = "arm"),
55690 stable(feature = "neon_intrinsics", since = "1.59.0")
55691)]
55692#[cfg_attr(
55693 target_arch = "arm",
55694 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55695)]
55696pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
55697 unsafe { transmute(a) }
55698}
55699#[doc = "Vector reinterpret cast operation"]
55700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
55701#[inline]
55702#[cfg(target_endian = "big")]
55703#[target_feature(enable = "neon,aes")]
55704#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55706#[cfg_attr(
55707 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55708 assert_instr(nop)
55709)]
55710#[cfg_attr(
55711 not(target_arch = "arm"),
55712 stable(feature = "neon_intrinsics", since = "1.59.0")
55713)]
55714#[cfg_attr(
55715 target_arch = "arm",
55716 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55717)]
55718pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
55719 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55720 unsafe { transmute(a) }
55721}
55722#[doc = "Vector reinterpret cast operation"]
55723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
55724#[inline]
55725#[cfg(target_endian = "little")]
55726#[target_feature(enable = "neon,aes")]
55727#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55728#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55729#[cfg_attr(
55730 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55731 assert_instr(nop)
55732)]
55733#[cfg_attr(
55734 not(target_arch = "arm"),
55735 stable(feature = "neon_intrinsics", since = "1.59.0")
55736)]
55737#[cfg_attr(
55738 target_arch = "arm",
55739 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55740)]
55741pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
55742 unsafe { transmute(a) }
55743}
55744#[doc = "Vector reinterpret cast operation"]
55745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
55746#[inline]
55747#[cfg(target_endian = "big")]
55748#[target_feature(enable = "neon,aes")]
55749#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55750#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55751#[cfg_attr(
55752 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55753 assert_instr(nop)
55754)]
55755#[cfg_attr(
55756 not(target_arch = "arm"),
55757 stable(feature = "neon_intrinsics", since = "1.59.0")
55758)]
55759#[cfg_attr(
55760 target_arch = "arm",
55761 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55762)]
55763pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
55764 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55765 unsafe { transmute(a) }
55766}
55767#[doc = "Vector reinterpret cast operation"]
55768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
55769#[inline]
55770#[cfg(target_endian = "little")]
55771#[target_feature(enable = "neon,aes")]
55772#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55773#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55774#[cfg_attr(
55775 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55776 assert_instr(nop)
55777)]
55778#[cfg_attr(
55779 not(target_arch = "arm"),
55780 stable(feature = "neon_intrinsics", since = "1.59.0")
55781)]
55782#[cfg_attr(
55783 target_arch = "arm",
55784 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55785)]
55786pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
55787 unsafe { transmute(a) }
55788}
55789#[doc = "Vector reinterpret cast operation"]
55790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
55791#[inline]
55792#[cfg(target_endian = "big")]
55793#[target_feature(enable = "neon,aes")]
55794#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55795#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55796#[cfg_attr(
55797 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55798 assert_instr(nop)
55799)]
55800#[cfg_attr(
55801 not(target_arch = "arm"),
55802 stable(feature = "neon_intrinsics", since = "1.59.0")
55803)]
55804#[cfg_attr(
55805 target_arch = "arm",
55806 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55807)]
55808pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
55809 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55810 unsafe {
55811 let ret_val: poly64x2_t = transmute(a);
55812 simd_shuffle!(ret_val, ret_val, [1, 0])
55813 }
55814}
55815#[doc = "Vector reinterpret cast operation"]
55816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
55817#[inline]
55818#[cfg(target_endian = "little")]
55819#[target_feature(enable = "neon,aes")]
55820#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55821#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55822#[cfg_attr(
55823 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55824 assert_instr(nop)
55825)]
55826#[cfg_attr(
55827 not(target_arch = "arm"),
55828 stable(feature = "neon_intrinsics", since = "1.59.0")
55829)]
55830#[cfg_attr(
55831 target_arch = "arm",
55832 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55833)]
55834pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
55835 unsafe { transmute(a) }
55836}
55837#[doc = "Vector reinterpret cast operation"]
55838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
55839#[inline]
55840#[cfg(target_endian = "big")]
55841#[target_feature(enable = "neon,aes")]
55842#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55844#[cfg_attr(
55845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55846 assert_instr(nop)
55847)]
55848#[cfg_attr(
55849 not(target_arch = "arm"),
55850 stable(feature = "neon_intrinsics", since = "1.59.0")
55851)]
55852#[cfg_attr(
55853 target_arch = "arm",
55854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55855)]
55856pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
55857 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
55858 unsafe { transmute(a) }
55859}
55860#[doc = "Vector reinterpret cast operation"]
55861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
55862#[inline]
55863#[cfg(target_endian = "little")]
55864#[target_feature(enable = "neon,aes")]
55865#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55867#[cfg_attr(
55868 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55869 assert_instr(nop)
55870)]
55871#[cfg_attr(
55872 not(target_arch = "arm"),
55873 stable(feature = "neon_intrinsics", since = "1.59.0")
55874)]
55875#[cfg_attr(
55876 target_arch = "arm",
55877 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55878)]
55879pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
55880 unsafe { transmute(a) }
55881}
55882#[doc = "Vector reinterpret cast operation"]
55883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
55884#[inline]
55885#[cfg(target_endian = "big")]
55886#[target_feature(enable = "neon,aes")]
55887#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55888#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55889#[cfg_attr(
55890 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55891 assert_instr(nop)
55892)]
55893#[cfg_attr(
55894 not(target_arch = "arm"),
55895 stable(feature = "neon_intrinsics", since = "1.59.0")
55896)]
55897#[cfg_attr(
55898 target_arch = "arm",
55899 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55900)]
55901pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
55902 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55903 unsafe { transmute(a) }
55904}
55905#[doc = "Vector reinterpret cast operation"]
55906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
55907#[inline]
55908#[cfg(target_endian = "little")]
55909#[target_feature(enable = "neon,aes")]
55910#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55911#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55912#[cfg_attr(
55913 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55914 assert_instr(nop)
55915)]
55916#[cfg_attr(
55917 not(target_arch = "arm"),
55918 stable(feature = "neon_intrinsics", since = "1.59.0")
55919)]
55920#[cfg_attr(
55921 target_arch = "arm",
55922 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55923)]
55924pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
55925 unsafe { transmute(a) }
55926}
55927#[doc = "Vector reinterpret cast operation"]
55928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
55929#[inline]
55930#[cfg(target_endian = "big")]
55931#[target_feature(enable = "neon,aes")]
55932#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55933#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55934#[cfg_attr(
55935 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55936 assert_instr(nop)
55937)]
55938#[cfg_attr(
55939 not(target_arch = "arm"),
55940 stable(feature = "neon_intrinsics", since = "1.59.0")
55941)]
55942#[cfg_attr(
55943 target_arch = "arm",
55944 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55945)]
55946pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
55947 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55948 unsafe {
55949 let ret_val: poly64x2_t = transmute(a);
55950 simd_shuffle!(ret_val, ret_val, [1, 0])
55951 }
55952}
55953#[doc = "Vector reinterpret cast operation"]
55954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
55955#[inline]
55956#[cfg(target_endian = "little")]
55957#[target_feature(enable = "neon,aes")]
55958#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55960#[cfg_attr(
55961 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55962 assert_instr(nop)
55963)]
55964#[cfg_attr(
55965 not(target_arch = "arm"),
55966 stable(feature = "neon_intrinsics", since = "1.59.0")
55967)]
55968#[cfg_attr(
55969 target_arch = "arm",
55970 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55971)]
55972pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
55973 unsafe { transmute(a) }
55974}
55975#[doc = "Vector reinterpret cast operation"]
55976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
55977#[inline]
55978#[cfg(target_endian = "big")]
55979#[target_feature(enable = "neon,aes")]
55980#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55981#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55982#[cfg_attr(
55983 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55984 assert_instr(nop)
55985)]
55986#[cfg_attr(
55987 not(target_arch = "arm"),
55988 stable(feature = "neon_intrinsics", since = "1.59.0")
55989)]
55990#[cfg_attr(
55991 target_arch = "arm",
55992 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55993)]
55994pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
55995 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
55996 unsafe { transmute(a) }
55997}
55998#[doc = "Vector reinterpret cast operation"]
55999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
56000#[inline]
56001#[cfg(target_endian = "little")]
56002#[target_feature(enable = "neon,aes")]
56003#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56005#[cfg_attr(
56006 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56007 assert_instr(nop)
56008)]
56009#[cfg_attr(
56010 not(target_arch = "arm"),
56011 stable(feature = "neon_intrinsics", since = "1.59.0")
56012)]
56013#[cfg_attr(
56014 target_arch = "arm",
56015 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56016)]
56017pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
56018 unsafe { transmute(a) }
56019}
56020#[doc = "Vector reinterpret cast operation"]
56021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
56022#[inline]
56023#[cfg(target_endian = "big")]
56024#[target_feature(enable = "neon,aes")]
56025#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56026#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56027#[cfg_attr(
56028 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56029 assert_instr(nop)
56030)]
56031#[cfg_attr(
56032 not(target_arch = "arm"),
56033 stable(feature = "neon_intrinsics", since = "1.59.0")
56034)]
56035#[cfg_attr(
56036 target_arch = "arm",
56037 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56038)]
56039pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
56040 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56041 unsafe { transmute(a) }
56042}
56043#[doc = "Vector reinterpret cast operation"]
56044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
56045#[inline]
56046#[cfg(target_endian = "little")]
56047#[target_feature(enable = "neon,aes")]
56048#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56049#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56050#[cfg_attr(
56051 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56052 assert_instr(nop)
56053)]
56054#[cfg_attr(
56055 not(target_arch = "arm"),
56056 stable(feature = "neon_intrinsics", since = "1.59.0")
56057)]
56058#[cfg_attr(
56059 target_arch = "arm",
56060 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56061)]
56062pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
56063 unsafe { transmute(a) }
56064}
56065#[doc = "Vector reinterpret cast operation"]
56066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
56067#[inline]
56068#[cfg(target_endian = "big")]
56069#[target_feature(enable = "neon,aes")]
56070#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56071#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56072#[cfg_attr(
56073 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56074 assert_instr(nop)
56075)]
56076#[cfg_attr(
56077 not(target_arch = "arm"),
56078 stable(feature = "neon_intrinsics", since = "1.59.0")
56079)]
56080#[cfg_attr(
56081 target_arch = "arm",
56082 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56083)]
56084pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
56085 let a: uint8x16_t =
56086 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56087 unsafe { transmute(a) }
56088}
56089#[doc = "Vector reinterpret cast operation"]
56090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
56091#[inline]
56092#[cfg(target_endian = "little")]
56093#[target_feature(enable = "neon,aes")]
56094#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56095#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56096#[cfg_attr(
56097 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56098 assert_instr(nop)
56099)]
56100#[cfg_attr(
56101 not(target_arch = "arm"),
56102 stable(feature = "neon_intrinsics", since = "1.59.0")
56103)]
56104#[cfg_attr(
56105 target_arch = "arm",
56106 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56107)]
56108pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
56109 unsafe { transmute(a) }
56110}
56111#[doc = "Vector reinterpret cast operation"]
56112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
56113#[inline]
56114#[cfg(target_endian = "big")]
56115#[target_feature(enable = "neon,aes")]
56116#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56118#[cfg_attr(
56119 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56120 assert_instr(nop)
56121)]
56122#[cfg_attr(
56123 not(target_arch = "arm"),
56124 stable(feature = "neon_intrinsics", since = "1.59.0")
56125)]
56126#[cfg_attr(
56127 target_arch = "arm",
56128 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56129)]
56130pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
56131 let a: uint8x16_t =
56132 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56133 unsafe {
56134 let ret_val: poly64x2_t = transmute(a);
56135 simd_shuffle!(ret_val, ret_val, [1, 0])
56136 }
56137}
56138#[doc = "Vector reinterpret cast operation"]
56139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
56140#[inline]
56141#[cfg(target_endian = "little")]
56142#[target_feature(enable = "neon,aes")]
56143#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56145#[cfg_attr(
56146 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56147 assert_instr(nop)
56148)]
56149#[cfg_attr(
56150 not(target_arch = "arm"),
56151 stable(feature = "neon_intrinsics", since = "1.59.0")
56152)]
56153#[cfg_attr(
56154 target_arch = "arm",
56155 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56156)]
56157pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
56158 unsafe { transmute(a) }
56159}
56160#[doc = "Vector reinterpret cast operation"]
56161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
56162#[inline]
56163#[cfg(target_endian = "big")]
56164#[target_feature(enable = "neon,aes")]
56165#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56167#[cfg_attr(
56168 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56169 assert_instr(nop)
56170)]
56171#[cfg_attr(
56172 not(target_arch = "arm"),
56173 stable(feature = "neon_intrinsics", since = "1.59.0")
56174)]
56175#[cfg_attr(
56176 target_arch = "arm",
56177 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56178)]
56179pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
56180 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56181 unsafe { transmute(a) }
56182}
56183#[doc = "Vector reinterpret cast operation"]
56184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
56185#[inline]
56186#[cfg(target_endian = "little")]
56187#[target_feature(enable = "neon,aes")]
56188#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56189#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56190#[cfg_attr(
56191 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56192 assert_instr(nop)
56193)]
56194#[cfg_attr(
56195 not(target_arch = "arm"),
56196 stable(feature = "neon_intrinsics", since = "1.59.0")
56197)]
56198#[cfg_attr(
56199 target_arch = "arm",
56200 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56201)]
56202pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
56203 unsafe { transmute(a) }
56204}
56205#[doc = "Vector reinterpret cast operation"]
56206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
56207#[inline]
56208#[cfg(target_endian = "big")]
56209#[target_feature(enable = "neon,aes")]
56210#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56211#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56212#[cfg_attr(
56213 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56214 assert_instr(nop)
56215)]
56216#[cfg_attr(
56217 not(target_arch = "arm"),
56218 stable(feature = "neon_intrinsics", since = "1.59.0")
56219)]
56220#[cfg_attr(
56221 target_arch = "arm",
56222 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56223)]
56224pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
56225 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56226 unsafe { transmute(a) }
56227}
56228#[doc = "Vector reinterpret cast operation"]
56229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
56230#[inline]
56231#[cfg(target_endian = "little")]
56232#[target_feature(enable = "neon,aes")]
56233#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56235#[cfg_attr(
56236 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56237 assert_instr(nop)
56238)]
56239#[cfg_attr(
56240 not(target_arch = "arm"),
56241 stable(feature = "neon_intrinsics", since = "1.59.0")
56242)]
56243#[cfg_attr(
56244 target_arch = "arm",
56245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56246)]
56247pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
56248 unsafe { transmute(a) }
56249}
56250#[doc = "Vector reinterpret cast operation"]
56251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
56252#[inline]
56253#[cfg(target_endian = "big")]
56254#[target_feature(enable = "neon,aes")]
56255#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56257#[cfg_attr(
56258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56259 assert_instr(nop)
56260)]
56261#[cfg_attr(
56262 not(target_arch = "arm"),
56263 stable(feature = "neon_intrinsics", since = "1.59.0")
56264)]
56265#[cfg_attr(
56266 target_arch = "arm",
56267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56268)]
56269pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
56270 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56271 unsafe {
56272 let ret_val: poly64x2_t = transmute(a);
56273 simd_shuffle!(ret_val, ret_val, [1, 0])
56274 }
56275}
56276#[doc = "Vector reinterpret cast operation"]
56277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
56278#[inline]
56279#[cfg(target_endian = "little")]
56280#[target_feature(enable = "neon,aes")]
56281#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56283#[cfg_attr(
56284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56285 assert_instr(nop)
56286)]
56287#[cfg_attr(
56288 not(target_arch = "arm"),
56289 stable(feature = "neon_intrinsics", since = "1.59.0")
56290)]
56291#[cfg_attr(
56292 target_arch = "arm",
56293 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56294)]
56295pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
56296 unsafe { transmute(a) }
56297}
56298#[doc = "Vector reinterpret cast operation"]
56299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
56300#[inline]
56301#[cfg(target_endian = "big")]
56302#[target_feature(enable = "neon,aes")]
56303#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56304#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56305#[cfg_attr(
56306 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56307 assert_instr(nop)
56308)]
56309#[cfg_attr(
56310 not(target_arch = "arm"),
56311 stable(feature = "neon_intrinsics", since = "1.59.0")
56312)]
56313#[cfg_attr(
56314 target_arch = "arm",
56315 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56316)]
56317pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
56318 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56319 unsafe { transmute(a) }
56320}
56321#[doc = "Vector reinterpret cast operation"]
56322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
56323#[inline]
56324#[cfg(target_endian = "little")]
56325#[target_feature(enable = "neon,aes")]
56326#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56327#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56328#[cfg_attr(
56329 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56330 assert_instr(nop)
56331)]
56332#[cfg_attr(
56333 not(target_arch = "arm"),
56334 stable(feature = "neon_intrinsics", since = "1.59.0")
56335)]
56336#[cfg_attr(
56337 target_arch = "arm",
56338 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56339)]
56340pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
56341 unsafe { transmute(a) }
56342}
56343#[doc = "Vector reinterpret cast operation"]
56344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
56345#[inline]
56346#[cfg(target_endian = "big")]
56347#[target_feature(enable = "neon,aes")]
56348#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56349#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56350#[cfg_attr(
56351 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56352 assert_instr(nop)
56353)]
56354#[cfg_attr(
56355 not(target_arch = "arm"),
56356 stable(feature = "neon_intrinsics", since = "1.59.0")
56357)]
56358#[cfg_attr(
56359 target_arch = "arm",
56360 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56361)]
56362pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
56363 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56364 unsafe { transmute(a) }
56365}
56366#[doc = "Vector reinterpret cast operation"]
56367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
56368#[inline]
56369#[cfg(target_endian = "little")]
56370#[target_feature(enable = "neon,aes")]
56371#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56373#[cfg_attr(
56374 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56375 assert_instr(nop)
56376)]
56377#[cfg_attr(
56378 not(target_arch = "arm"),
56379 stable(feature = "neon_intrinsics", since = "1.59.0")
56380)]
56381#[cfg_attr(
56382 target_arch = "arm",
56383 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56384)]
56385pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
56386 unsafe { transmute(a) }
56387}
56388#[doc = "Vector reinterpret cast operation"]
56389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
56390#[inline]
56391#[cfg(target_endian = "big")]
56392#[target_feature(enable = "neon,aes")]
56393#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56395#[cfg_attr(
56396 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56397 assert_instr(nop)
56398)]
56399#[cfg_attr(
56400 not(target_arch = "arm"),
56401 stable(feature = "neon_intrinsics", since = "1.59.0")
56402)]
56403#[cfg_attr(
56404 target_arch = "arm",
56405 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56406)]
56407pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
56408 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56409 unsafe {
56410 let ret_val: poly64x2_t = transmute(a);
56411 simd_shuffle!(ret_val, ret_val, [1, 0])
56412 }
56413}
56414#[doc = "Vector reinterpret cast operation"]
56415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
56416#[inline]
56417#[cfg(target_endian = "little")]
56418#[target_feature(enable = "neon,aes")]
56419#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56420#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56421#[cfg_attr(
56422 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56423 assert_instr(nop)
56424)]
56425#[cfg_attr(
56426 not(target_arch = "arm"),
56427 stable(feature = "neon_intrinsics", since = "1.59.0")
56428)]
56429#[cfg_attr(
56430 target_arch = "arm",
56431 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56432)]
56433pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
56434 unsafe { transmute(a) }
56435}
56436#[doc = "Vector reinterpret cast operation"]
56437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
56438#[inline]
56439#[cfg(target_endian = "big")]
56440#[target_feature(enable = "neon,aes")]
56441#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56443#[cfg_attr(
56444 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56445 assert_instr(nop)
56446)]
56447#[cfg_attr(
56448 not(target_arch = "arm"),
56449 stable(feature = "neon_intrinsics", since = "1.59.0")
56450)]
56451#[cfg_attr(
56452 target_arch = "arm",
56453 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56454)]
56455pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
56456 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56457 unsafe { transmute(a) }
56458}
56459#[doc = "Vector reinterpret cast operation"]
56460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
56461#[inline]
56462#[cfg(target_endian = "little")]
56463#[target_feature(enable = "neon,aes")]
56464#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56465#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56466#[cfg_attr(
56467 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56468 assert_instr(nop)
56469)]
56470#[cfg_attr(
56471 not(target_arch = "arm"),
56472 stable(feature = "neon_intrinsics", since = "1.59.0")
56473)]
56474#[cfg_attr(
56475 target_arch = "arm",
56476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56477)]
56478pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
56479 unsafe { transmute(a) }
56480}
56481#[doc = "Vector reinterpret cast operation"]
56482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
56483#[inline]
56484#[cfg(target_endian = "big")]
56485#[target_feature(enable = "neon,aes")]
56486#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56488#[cfg_attr(
56489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56490 assert_instr(nop)
56491)]
56492#[cfg_attr(
56493 not(target_arch = "arm"),
56494 stable(feature = "neon_intrinsics", since = "1.59.0")
56495)]
56496#[cfg_attr(
56497 target_arch = "arm",
56498 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56499)]
56500pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
56501 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56502 unsafe { transmute(a) }
56503}
56504#[doc = "Vector reinterpret cast operation"]
56505#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
56506#[inline]
56507#[cfg(target_endian = "little")]
56508#[target_feature(enable = "neon,aes")]
56509#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56511#[cfg_attr(
56512 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56513 assert_instr(nop)
56514)]
56515#[cfg_attr(
56516 not(target_arch = "arm"),
56517 stable(feature = "neon_intrinsics", since = "1.59.0")
56518)]
56519#[cfg_attr(
56520 target_arch = "arm",
56521 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56522)]
56523pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
56524 unsafe { transmute(a) }
56525}
56526#[doc = "Vector reinterpret cast operation"]
56527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
56528#[inline]
56529#[cfg(target_endian = "big")]
56530#[target_feature(enable = "neon,aes")]
56531#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56533#[cfg_attr(
56534 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56535 assert_instr(nop)
56536)]
56537#[cfg_attr(
56538 not(target_arch = "arm"),
56539 stable(feature = "neon_intrinsics", since = "1.59.0")
56540)]
56541#[cfg_attr(
56542 target_arch = "arm",
56543 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56544)]
56545pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
56546 let a: poly8x16_t =
56547 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56548 unsafe { transmute(a) }
56549}
56550#[doc = "Vector reinterpret cast operation"]
56551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
56552#[inline]
56553#[cfg(target_endian = "little")]
56554#[target_feature(enable = "neon,aes")]
56555#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56556#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56557#[cfg_attr(
56558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56559 assert_instr(nop)
56560)]
56561#[cfg_attr(
56562 not(target_arch = "arm"),
56563 stable(feature = "neon_intrinsics", since = "1.59.0")
56564)]
56565#[cfg_attr(
56566 target_arch = "arm",
56567 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56568)]
56569pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
56570 unsafe { transmute(a) }
56571}
56572#[doc = "Vector reinterpret cast operation"]
56573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
56574#[inline]
56575#[cfg(target_endian = "big")]
56576#[target_feature(enable = "neon,aes")]
56577#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56579#[cfg_attr(
56580 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56581 assert_instr(nop)
56582)]
56583#[cfg_attr(
56584 not(target_arch = "arm"),
56585 stable(feature = "neon_intrinsics", since = "1.59.0")
56586)]
56587#[cfg_attr(
56588 target_arch = "arm",
56589 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56590)]
56591pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
56592 let a: poly8x16_t =
56593 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56594 unsafe {
56595 let ret_val: poly64x2_t = transmute(a);
56596 simd_shuffle!(ret_val, ret_val, [1, 0])
56597 }
56598}
56599#[doc = "Vector reinterpret cast operation"]
56600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
56601#[inline]
56602#[cfg(target_endian = "little")]
56603#[target_feature(enable = "neon,aes")]
56604#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56606#[cfg_attr(
56607 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56608 assert_instr(nop)
56609)]
56610#[cfg_attr(
56611 not(target_arch = "arm"),
56612 stable(feature = "neon_intrinsics", since = "1.59.0")
56613)]
56614#[cfg_attr(
56615 target_arch = "arm",
56616 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56617)]
56618pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
56619 unsafe { transmute(a) }
56620}
56621#[doc = "Vector reinterpret cast operation"]
56622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
56623#[inline]
56624#[cfg(target_endian = "big")]
56625#[target_feature(enable = "neon,aes")]
56626#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56627#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56628#[cfg_attr(
56629 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56630 assert_instr(nop)
56631)]
56632#[cfg_attr(
56633 not(target_arch = "arm"),
56634 stable(feature = "neon_intrinsics", since = "1.59.0")
56635)]
56636#[cfg_attr(
56637 target_arch = "arm",
56638 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56639)]
56640pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
56641 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56642 unsafe { transmute(a) }
56643}
56644#[doc = "Vector reinterpret cast operation"]
56645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
56646#[inline]
56647#[cfg(target_endian = "little")]
56648#[target_feature(enable = "neon,aes")]
56649#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56650#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56651#[cfg_attr(
56652 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56653 assert_instr(nop)
56654)]
56655#[cfg_attr(
56656 not(target_arch = "arm"),
56657 stable(feature = "neon_intrinsics", since = "1.59.0")
56658)]
56659#[cfg_attr(
56660 target_arch = "arm",
56661 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56662)]
56663pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
56664 unsafe { transmute(a) }
56665}
56666#[doc = "Vector reinterpret cast operation"]
56667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
56668#[inline]
56669#[cfg(target_endian = "big")]
56670#[target_feature(enable = "neon,aes")]
56671#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56673#[cfg_attr(
56674 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56675 assert_instr(nop)
56676)]
56677#[cfg_attr(
56678 not(target_arch = "arm"),
56679 stable(feature = "neon_intrinsics", since = "1.59.0")
56680)]
56681#[cfg_attr(
56682 target_arch = "arm",
56683 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56684)]
56685pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
56686 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56687 unsafe { transmute(a) }
56688}
56689#[doc = "Vector reinterpret cast operation"]
56690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
56691#[inline]
56692#[cfg(target_endian = "little")]
56693#[target_feature(enable = "neon,aes")]
56694#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56695#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56696#[cfg_attr(
56697 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56698 assert_instr(nop)
56699)]
56700#[cfg_attr(
56701 not(target_arch = "arm"),
56702 stable(feature = "neon_intrinsics", since = "1.59.0")
56703)]
56704#[cfg_attr(
56705 target_arch = "arm",
56706 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56707)]
56708pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
56709 unsafe { transmute(a) }
56710}
56711#[doc = "Vector reinterpret cast operation"]
56712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
56713#[inline]
56714#[cfg(target_endian = "big")]
56715#[target_feature(enable = "neon,aes")]
56716#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56717#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56718#[cfg_attr(
56719 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56720 assert_instr(nop)
56721)]
56722#[cfg_attr(
56723 not(target_arch = "arm"),
56724 stable(feature = "neon_intrinsics", since = "1.59.0")
56725)]
56726#[cfg_attr(
56727 target_arch = "arm",
56728 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56729)]
56730pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
56731 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56732 unsafe {
56733 let ret_val: poly64x2_t = transmute(a);
56734 simd_shuffle!(ret_val, ret_val, [1, 0])
56735 }
56736}
56737#[doc = "Vector reinterpret cast operation"]
56738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
56739#[inline]
56740#[cfg(target_endian = "little")]
56741#[target_feature(enable = "neon,aes")]
56742#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56743#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56744#[cfg_attr(
56745 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56746 assert_instr(nop)
56747)]
56748#[cfg_attr(
56749 not(target_arch = "arm"),
56750 stable(feature = "neon_intrinsics", since = "1.59.0")
56751)]
56752#[cfg_attr(
56753 target_arch = "arm",
56754 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56755)]
56756pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
56757 unsafe { transmute(a) }
56758}
56759#[doc = "Vector reinterpret cast operation"]
56760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
56761#[inline]
56762#[cfg(target_endian = "big")]
56763#[target_feature(enable = "neon,aes")]
56764#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56766#[cfg_attr(
56767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56768 assert_instr(nop)
56769)]
56770#[cfg_attr(
56771 not(target_arch = "arm"),
56772 stable(feature = "neon_intrinsics", since = "1.59.0")
56773)]
56774#[cfg_attr(
56775 target_arch = "arm",
56776 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56777)]
56778pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
56779 unsafe {
56780 let ret_val: int8x8_t = transmute(a);
56781 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56782 }
56783}
56784#[doc = "Vector reinterpret cast operation"]
56785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
56786#[inline]
56787#[cfg(target_endian = "little")]
56788#[target_feature(enable = "neon,aes")]
56789#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56790#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56791#[cfg_attr(
56792 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56793 assert_instr(nop)
56794)]
56795#[cfg_attr(
56796 not(target_arch = "arm"),
56797 stable(feature = "neon_intrinsics", since = "1.59.0")
56798)]
56799#[cfg_attr(
56800 target_arch = "arm",
56801 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56802)]
56803pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
56804 unsafe { transmute(a) }
56805}
56806#[doc = "Vector reinterpret cast operation"]
56807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
56808#[inline]
56809#[cfg(target_endian = "big")]
56810#[target_feature(enable = "neon,aes")]
56811#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56812#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56813#[cfg_attr(
56814 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56815 assert_instr(nop)
56816)]
56817#[cfg_attr(
56818 not(target_arch = "arm"),
56819 stable(feature = "neon_intrinsics", since = "1.59.0")
56820)]
56821#[cfg_attr(
56822 target_arch = "arm",
56823 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56824)]
56825pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
56826 unsafe {
56827 let ret_val: int16x4_t = transmute(a);
56828 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
56829 }
56830}
56831#[doc = "Vector reinterpret cast operation"]
56832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
56833#[inline]
56834#[cfg(target_endian = "little")]
56835#[target_feature(enable = "neon,aes")]
56836#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56837#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56838#[cfg_attr(
56839 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56840 assert_instr(nop)
56841)]
56842#[cfg_attr(
56843 not(target_arch = "arm"),
56844 stable(feature = "neon_intrinsics", since = "1.59.0")
56845)]
56846#[cfg_attr(
56847 target_arch = "arm",
56848 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56849)]
56850pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
56851 unsafe { transmute(a) }
56852}
56853#[doc = "Vector reinterpret cast operation"]
56854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
56855#[inline]
56856#[cfg(target_endian = "big")]
56857#[target_feature(enable = "neon,aes")]
56858#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56859#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56860#[cfg_attr(
56861 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56862 assert_instr(nop)
56863)]
56864#[cfg_attr(
56865 not(target_arch = "arm"),
56866 stable(feature = "neon_intrinsics", since = "1.59.0")
56867)]
56868#[cfg_attr(
56869 target_arch = "arm",
56870 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56871)]
56872pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
56873 unsafe {
56874 let ret_val: int32x2_t = transmute(a);
56875 simd_shuffle!(ret_val, ret_val, [1, 0])
56876 }
56877}
56878#[doc = "Vector reinterpret cast operation"]
56879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
56880#[inline]
56881#[cfg(target_endian = "little")]
56882#[target_feature(enable = "neon,aes")]
56883#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56885#[cfg_attr(
56886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56887 assert_instr(nop)
56888)]
56889#[cfg_attr(
56890 not(target_arch = "arm"),
56891 stable(feature = "neon_intrinsics", since = "1.59.0")
56892)]
56893#[cfg_attr(
56894 target_arch = "arm",
56895 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56896)]
56897pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
56898 unsafe { transmute(a) }
56899}
56900#[doc = "Vector reinterpret cast operation"]
56901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
56902#[inline]
56903#[cfg(target_endian = "big")]
56904#[target_feature(enable = "neon,aes")]
56905#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56907#[cfg_attr(
56908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56909 assert_instr(nop)
56910)]
56911#[cfg_attr(
56912 not(target_arch = "arm"),
56913 stable(feature = "neon_intrinsics", since = "1.59.0")
56914)]
56915#[cfg_attr(
56916 target_arch = "arm",
56917 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56918)]
56919pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
56920 unsafe {
56921 let ret_val: uint8x8_t = transmute(a);
56922 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56923 }
56924}
56925#[doc = "Vector reinterpret cast operation"]
56926#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
56927#[inline]
56928#[cfg(target_endian = "little")]
56929#[target_feature(enable = "neon,aes")]
56930#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56931#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56932#[cfg_attr(
56933 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56934 assert_instr(nop)
56935)]
56936#[cfg_attr(
56937 not(target_arch = "arm"),
56938 stable(feature = "neon_intrinsics", since = "1.59.0")
56939)]
56940#[cfg_attr(
56941 target_arch = "arm",
56942 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56943)]
56944pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
56945 unsafe { transmute(a) }
56946}
56947#[doc = "Vector reinterpret cast operation"]
56948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
56949#[inline]
56950#[cfg(target_endian = "big")]
56951#[target_feature(enable = "neon,aes")]
56952#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56953#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56954#[cfg_attr(
56955 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56956 assert_instr(nop)
56957)]
56958#[cfg_attr(
56959 not(target_arch = "arm"),
56960 stable(feature = "neon_intrinsics", since = "1.59.0")
56961)]
56962#[cfg_attr(
56963 target_arch = "arm",
56964 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56965)]
56966pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
56967 unsafe {
56968 let ret_val: uint16x4_t = transmute(a);
56969 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
56970 }
56971}
56972#[doc = "Vector reinterpret cast operation"]
56973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
56974#[inline]
56975#[cfg(target_endian = "little")]
56976#[target_feature(enable = "neon,aes")]
56977#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56978#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56979#[cfg_attr(
56980 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56981 assert_instr(nop)
56982)]
56983#[cfg_attr(
56984 not(target_arch = "arm"),
56985 stable(feature = "neon_intrinsics", since = "1.59.0")
56986)]
56987#[cfg_attr(
56988 target_arch = "arm",
56989 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56990)]
56991pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
56992 unsafe { transmute(a) }
56993}
56994#[doc = "Vector reinterpret cast operation"]
56995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
56996#[inline]
56997#[cfg(target_endian = "big")]
56998#[target_feature(enable = "neon,aes")]
56999#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57000#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57001#[cfg_attr(
57002 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57003 assert_instr(nop)
57004)]
57005#[cfg_attr(
57006 not(target_arch = "arm"),
57007 stable(feature = "neon_intrinsics", since = "1.59.0")
57008)]
57009#[cfg_attr(
57010 target_arch = "arm",
57011 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57012)]
57013pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
57014 unsafe {
57015 let ret_val: uint32x2_t = transmute(a);
57016 simd_shuffle!(ret_val, ret_val, [1, 0])
57017 }
57018}
57019#[doc = "Vector reinterpret cast operation"]
57020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
57021#[inline]
57022#[cfg(target_endian = "little")]
57023#[target_feature(enable = "neon,aes")]
57024#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57025#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57026#[cfg_attr(
57027 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57028 assert_instr(nop)
57029)]
57030#[cfg_attr(
57031 not(target_arch = "arm"),
57032 stable(feature = "neon_intrinsics", since = "1.59.0")
57033)]
57034#[cfg_attr(
57035 target_arch = "arm",
57036 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57037)]
57038pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
57039 unsafe { transmute(a) }
57040}
57041#[doc = "Vector reinterpret cast operation"]
57042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
57043#[inline]
57044#[cfg(target_endian = "big")]
57045#[target_feature(enable = "neon,aes")]
57046#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57047#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57048#[cfg_attr(
57049 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57050 assert_instr(nop)
57051)]
57052#[cfg_attr(
57053 not(target_arch = "arm"),
57054 stable(feature = "neon_intrinsics", since = "1.59.0")
57055)]
57056#[cfg_attr(
57057 target_arch = "arm",
57058 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57059)]
57060pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
57061 unsafe {
57062 let ret_val: poly8x8_t = transmute(a);
57063 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57064 }
57065}
57066#[doc = "Vector reinterpret cast operation"]
57067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
57068#[inline]
57069#[cfg(target_endian = "little")]
57070#[target_feature(enable = "neon,aes")]
57071#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57072#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57073#[cfg_attr(
57074 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57075 assert_instr(nop)
57076)]
57077#[cfg_attr(
57078 not(target_arch = "arm"),
57079 stable(feature = "neon_intrinsics", since = "1.59.0")
57080)]
57081#[cfg_attr(
57082 target_arch = "arm",
57083 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57084)]
57085pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
57086 unsafe { transmute(a) }
57087}
57088#[doc = "Vector reinterpret cast operation"]
57089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
57090#[inline]
57091#[cfg(target_endian = "big")]
57092#[target_feature(enable = "neon,aes")]
57093#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57094#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57095#[cfg_attr(
57096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57097 assert_instr(nop)
57098)]
57099#[cfg_attr(
57100 not(target_arch = "arm"),
57101 stable(feature = "neon_intrinsics", since = "1.59.0")
57102)]
57103#[cfg_attr(
57104 target_arch = "arm",
57105 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57106)]
57107pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
57108 unsafe {
57109 let ret_val: poly16x4_t = transmute(a);
57110 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
57111 }
57112}
57113#[doc = "Vector reinterpret cast operation"]
57114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
57115#[inline]
57116#[cfg(target_endian = "little")]
57117#[target_feature(enable = "neon,aes")]
57118#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57119#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57120#[cfg_attr(
57121 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57122 assert_instr(nop)
57123)]
57124#[cfg_attr(
57125 not(target_arch = "arm"),
57126 stable(feature = "neon_intrinsics", since = "1.59.0")
57127)]
57128#[cfg_attr(
57129 target_arch = "arm",
57130 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57131)]
57132pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
57133 unsafe { transmute(a) }
57134}
57135#[doc = "Vector reinterpret cast operation"]
57136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
57137#[inline]
57138#[cfg(target_endian = "big")]
57139#[target_feature(enable = "neon,aes")]
57140#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57142#[cfg_attr(
57143 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57144 assert_instr(nop)
57145)]
57146#[cfg_attr(
57147 not(target_arch = "arm"),
57148 stable(feature = "neon_intrinsics", since = "1.59.0")
57149)]
57150#[cfg_attr(
57151 target_arch = "arm",
57152 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57153)]
57154pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
57155 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57156 unsafe { transmute(a) }
57157}
57158#[doc = "Vector reinterpret cast operation"]
57159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
57160#[inline]
57161#[cfg(target_endian = "little")]
57162#[target_feature(enable = "neon,aes")]
57163#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57165#[cfg_attr(
57166 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57167 assert_instr(nop)
57168)]
57169#[cfg_attr(
57170 not(target_arch = "arm"),
57171 stable(feature = "neon_intrinsics", since = "1.59.0")
57172)]
57173#[cfg_attr(
57174 target_arch = "arm",
57175 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57176)]
57177pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
57178 unsafe { transmute(a) }
57179}
57180#[doc = "Vector reinterpret cast operation"]
57181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
57182#[inline]
57183#[cfg(target_endian = "big")]
57184#[target_feature(enable = "neon,aes")]
57185#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57187#[cfg_attr(
57188 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57189 assert_instr(nop)
57190)]
57191#[cfg_attr(
57192 not(target_arch = "arm"),
57193 stable(feature = "neon_intrinsics", since = "1.59.0")
57194)]
57195#[cfg_attr(
57196 target_arch = "arm",
57197 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57198)]
57199pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
57200 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57201 unsafe {
57202 let ret_val: int8x16_t = transmute(a);
57203 simd_shuffle!(
57204 ret_val,
57205 ret_val,
57206 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
57207 )
57208 }
57209}
57210#[doc = "Vector reinterpret cast operation"]
57211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
57212#[inline]
57213#[cfg(target_endian = "little")]
57214#[target_feature(enable = "neon,aes")]
57215#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57216#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57217#[cfg_attr(
57218 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57219 assert_instr(nop)
57220)]
57221#[cfg_attr(
57222 not(target_arch = "arm"),
57223 stable(feature = "neon_intrinsics", since = "1.59.0")
57224)]
57225#[cfg_attr(
57226 target_arch = "arm",
57227 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57228)]
57229pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
57230 unsafe { transmute(a) }
57231}
57232#[doc = "Vector reinterpret cast operation"]
57233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
57234#[inline]
57235#[cfg(target_endian = "big")]
57236#[target_feature(enable = "neon,aes")]
57237#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57238#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57239#[cfg_attr(
57240 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57241 assert_instr(nop)
57242)]
57243#[cfg_attr(
57244 not(target_arch = "arm"),
57245 stable(feature = "neon_intrinsics", since = "1.59.0")
57246)]
57247#[cfg_attr(
57248 target_arch = "arm",
57249 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57250)]
57251pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
57252 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57253 unsafe {
57254 let ret_val: int16x8_t = transmute(a);
57255 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57256 }
57257}
57258#[doc = "Vector reinterpret cast operation"]
57259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
57260#[inline]
57261#[cfg(target_endian = "little")]
57262#[target_feature(enable = "neon,aes")]
57263#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57264#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57265#[cfg_attr(
57266 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57267 assert_instr(nop)
57268)]
57269#[cfg_attr(
57270 not(target_arch = "arm"),
57271 stable(feature = "neon_intrinsics", since = "1.59.0")
57272)]
57273#[cfg_attr(
57274 target_arch = "arm",
57275 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57276)]
57277pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
57278 unsafe { transmute(a) }
57279}
57280#[doc = "Vector reinterpret cast operation"]
57281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
57282#[inline]
57283#[cfg(target_endian = "big")]
57284#[target_feature(enable = "neon,aes")]
57285#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57286#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57287#[cfg_attr(
57288 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57289 assert_instr(nop)
57290)]
57291#[cfg_attr(
57292 not(target_arch = "arm"),
57293 stable(feature = "neon_intrinsics", since = "1.59.0")
57294)]
57295#[cfg_attr(
57296 target_arch = "arm",
57297 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57298)]
57299pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
57300 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57301 unsafe {
57302 let ret_val: int32x4_t = transmute(a);
57303 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
57304 }
57305}
57306#[doc = "Vector reinterpret cast operation"]
57307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
57308#[inline]
57309#[cfg(target_endian = "little")]
57310#[target_feature(enable = "neon,aes")]
57311#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57312#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57313#[cfg_attr(
57314 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57315 assert_instr(nop)
57316)]
57317#[cfg_attr(
57318 not(target_arch = "arm"),
57319 stable(feature = "neon_intrinsics", since = "1.59.0")
57320)]
57321#[cfg_attr(
57322 target_arch = "arm",
57323 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57324)]
57325pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
57326 unsafe { transmute(a) }
57327}
57328#[doc = "Vector reinterpret cast operation"]
57329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
57330#[inline]
57331#[cfg(target_endian = "big")]
57332#[target_feature(enable = "neon,aes")]
57333#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57334#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57335#[cfg_attr(
57336 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57337 assert_instr(nop)
57338)]
57339#[cfg_attr(
57340 not(target_arch = "arm"),
57341 stable(feature = "neon_intrinsics", since = "1.59.0")
57342)]
57343#[cfg_attr(
57344 target_arch = "arm",
57345 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57346)]
57347pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
57348 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57349 unsafe {
57350 let ret_val: uint8x16_t = transmute(a);
57351 simd_shuffle!(
57352 ret_val,
57353 ret_val,
57354 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
57355 )
57356 }
57357}
57358#[doc = "Vector reinterpret cast operation"]
57359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
57360#[inline]
57361#[cfg(target_endian = "little")]
57362#[target_feature(enable = "neon,aes")]
57363#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57364#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57365#[cfg_attr(
57366 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57367 assert_instr(nop)
57368)]
57369#[cfg_attr(
57370 not(target_arch = "arm"),
57371 stable(feature = "neon_intrinsics", since = "1.59.0")
57372)]
57373#[cfg_attr(
57374 target_arch = "arm",
57375 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57376)]
57377pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
57378 unsafe { transmute(a) }
57379}
57380#[doc = "Vector reinterpret cast operation"]
57381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
57382#[inline]
57383#[cfg(target_endian = "big")]
57384#[target_feature(enable = "neon,aes")]
57385#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57386#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57387#[cfg_attr(
57388 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57389 assert_instr(nop)
57390)]
57391#[cfg_attr(
57392 not(target_arch = "arm"),
57393 stable(feature = "neon_intrinsics", since = "1.59.0")
57394)]
57395#[cfg_attr(
57396 target_arch = "arm",
57397 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57398)]
57399pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
57400 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57401 unsafe {
57402 let ret_val: uint16x8_t = transmute(a);
57403 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57404 }
57405}
57406#[doc = "Vector reinterpret cast operation"]
57407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
57408#[inline]
57409#[cfg(target_endian = "little")]
57410#[target_feature(enable = "neon,aes")]
57411#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57412#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57413#[cfg_attr(
57414 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57415 assert_instr(nop)
57416)]
57417#[cfg_attr(
57418 not(target_arch = "arm"),
57419 stable(feature = "neon_intrinsics", since = "1.59.0")
57420)]
57421#[cfg_attr(
57422 target_arch = "arm",
57423 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57424)]
57425pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
57426 unsafe { transmute(a) }
57427}
57428#[doc = "Vector reinterpret cast operation"]
57429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
57430#[inline]
57431#[cfg(target_endian = "big")]
57432#[target_feature(enable = "neon,aes")]
57433#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57435#[cfg_attr(
57436 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57437 assert_instr(nop)
57438)]
57439#[cfg_attr(
57440 not(target_arch = "arm"),
57441 stable(feature = "neon_intrinsics", since = "1.59.0")
57442)]
57443#[cfg_attr(
57444 target_arch = "arm",
57445 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57446)]
57447pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
57448 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57449 unsafe {
57450 let ret_val: uint32x4_t = transmute(a);
57451 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
57452 }
57453}
57454#[doc = "Vector reinterpret cast operation"]
57455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
57456#[inline]
57457#[cfg(target_endian = "little")]
57458#[target_feature(enable = "neon,aes")]
57459#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57461#[cfg_attr(
57462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57463 assert_instr(nop)
57464)]
57465#[cfg_attr(
57466 not(target_arch = "arm"),
57467 stable(feature = "neon_intrinsics", since = "1.59.0")
57468)]
57469#[cfg_attr(
57470 target_arch = "arm",
57471 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57472)]
57473pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
57474 unsafe { transmute(a) }
57475}
57476#[doc = "Vector reinterpret cast operation"]
57477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
57478#[inline]
57479#[cfg(target_endian = "big")]
57480#[target_feature(enable = "neon,aes")]
57481#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57482#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57483#[cfg_attr(
57484 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57485 assert_instr(nop)
57486)]
57487#[cfg_attr(
57488 not(target_arch = "arm"),
57489 stable(feature = "neon_intrinsics", since = "1.59.0")
57490)]
57491#[cfg_attr(
57492 target_arch = "arm",
57493 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57494)]
57495pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
57496 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57497 unsafe {
57498 let ret_val: poly8x16_t = transmute(a);
57499 simd_shuffle!(
57500 ret_val,
57501 ret_val,
57502 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
57503 )
57504 }
57505}
57506#[doc = "Vector reinterpret cast operation"]
57507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
57508#[inline]
57509#[cfg(target_endian = "little")]
57510#[target_feature(enable = "neon,aes")]
57511#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57513#[cfg_attr(
57514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57515 assert_instr(nop)
57516)]
57517#[cfg_attr(
57518 not(target_arch = "arm"),
57519 stable(feature = "neon_intrinsics", since = "1.59.0")
57520)]
57521#[cfg_attr(
57522 target_arch = "arm",
57523 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57524)]
57525pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
57526 unsafe { transmute(a) }
57527}
57528#[doc = "Vector reinterpret cast operation"]
57529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
57530#[inline]
57531#[cfg(target_endian = "big")]
57532#[target_feature(enable = "neon,aes")]
57533#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57534#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57535#[cfg_attr(
57536 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57537 assert_instr(nop)
57538)]
57539#[cfg_attr(
57540 not(target_arch = "arm"),
57541 stable(feature = "neon_intrinsics", since = "1.59.0")
57542)]
57543#[cfg_attr(
57544 target_arch = "arm",
57545 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57546)]
57547pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
57548 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57549 unsafe {
57550 let ret_val: poly16x8_t = transmute(a);
57551 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57552 }
57553}
57554#[doc = "Reversing vector elements (swap endianness)"]
57555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"]
57556#[inline]
57557#[target_feature(enable = "neon")]
57558#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57559#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57560#[cfg_attr(
57561 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57562 assert_instr(rev16)
57563)]
57564#[cfg_attr(
57565 not(target_arch = "arm"),
57566 stable(feature = "neon_intrinsics", since = "1.59.0")
57567)]
57568#[cfg_attr(
57569 target_arch = "arm",
57570 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57571)]
57572pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t {
57573 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57574}
57575#[doc = "Reversing vector elements (swap endianness)"]
57576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"]
57577#[inline]
57578#[target_feature(enable = "neon")]
57579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57580#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57581#[cfg_attr(
57582 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57583 assert_instr(rev16)
57584)]
57585#[cfg_attr(
57586 not(target_arch = "arm"),
57587 stable(feature = "neon_intrinsics", since = "1.59.0")
57588)]
57589#[cfg_attr(
57590 target_arch = "arm",
57591 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57592)]
57593pub fn vrev16_s8(a: int8x8_t) -> int8x8_t {
57594 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57595}
57596#[doc = "Reversing vector elements (swap endianness)"]
57597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"]
57598#[inline]
57599#[target_feature(enable = "neon")]
57600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57601#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57602#[cfg_attr(
57603 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57604 assert_instr(rev16)
57605)]
57606#[cfg_attr(
57607 not(target_arch = "arm"),
57608 stable(feature = "neon_intrinsics", since = "1.59.0")
57609)]
57610#[cfg_attr(
57611 target_arch = "arm",
57612 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57613)]
57614pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t {
57615 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57616}
57617#[doc = "Reversing vector elements (swap endianness)"]
57618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"]
57619#[inline]
57620#[target_feature(enable = "neon")]
57621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57622#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57623#[cfg_attr(
57624 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57625 assert_instr(rev16)
57626)]
57627#[cfg_attr(
57628 not(target_arch = "arm"),
57629 stable(feature = "neon_intrinsics", since = "1.59.0")
57630)]
57631#[cfg_attr(
57632 target_arch = "arm",
57633 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57634)]
57635pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t {
57636 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57637}
57638#[doc = "Reversing vector elements (swap endianness)"]
57639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"]
57640#[inline]
57641#[target_feature(enable = "neon")]
57642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57643#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57644#[cfg_attr(
57645 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57646 assert_instr(rev16)
57647)]
57648#[cfg_attr(
57649 not(target_arch = "arm"),
57650 stable(feature = "neon_intrinsics", since = "1.59.0")
57651)]
57652#[cfg_attr(
57653 target_arch = "arm",
57654 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57655)]
57656pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t {
57657 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57658}
57659#[doc = "Reversing vector elements (swap endianness)"]
57660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"]
57661#[inline]
57662#[target_feature(enable = "neon")]
57663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57664#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57665#[cfg_attr(
57666 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57667 assert_instr(rev16)
57668)]
57669#[cfg_attr(
57670 not(target_arch = "arm"),
57671 stable(feature = "neon_intrinsics", since = "1.59.0")
57672)]
57673#[cfg_attr(
57674 target_arch = "arm",
57675 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57676)]
57677pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t {
57678 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57679}
57680#[doc = "Reversing vector elements (swap endianness)"]
57681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"]
57682#[inline]
57683#[target_feature(enable = "neon")]
57684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57685#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57686#[cfg_attr(
57687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57688 assert_instr(rev32)
57689)]
57690#[cfg_attr(
57691 not(target_arch = "arm"),
57692 stable(feature = "neon_intrinsics", since = "1.59.0")
57693)]
57694#[cfg_attr(
57695 target_arch = "arm",
57696 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57697)]
57698pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t {
57699 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57700}
57701#[doc = "Reversing vector elements (swap endianness)"]
57702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"]
57703#[inline]
57704#[target_feature(enable = "neon")]
57705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57706#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57707#[cfg_attr(
57708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57709 assert_instr(rev32)
57710)]
57711#[cfg_attr(
57712 not(target_arch = "arm"),
57713 stable(feature = "neon_intrinsics", since = "1.59.0")
57714)]
57715#[cfg_attr(
57716 target_arch = "arm",
57717 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57718)]
57719pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t {
57720 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57721}
57722#[doc = "Reversing vector elements (swap endianness)"]
57723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"]
57724#[inline]
57725#[target_feature(enable = "neon")]
57726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57727#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57728#[cfg_attr(
57729 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57730 assert_instr(rev32)
57731)]
57732#[cfg_attr(
57733 not(target_arch = "arm"),
57734 stable(feature = "neon_intrinsics", since = "1.59.0")
57735)]
57736#[cfg_attr(
57737 target_arch = "arm",
57738 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57739)]
57740pub fn vrev32_s16(a: int16x4_t) -> int16x4_t {
57741 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57742}
57743#[doc = "Reversing vector elements (swap endianness)"]
57744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"]
57745#[inline]
57746#[target_feature(enable = "neon")]
57747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57748#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57749#[cfg_attr(
57750 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57751 assert_instr(rev32)
57752)]
57753#[cfg_attr(
57754 not(target_arch = "arm"),
57755 stable(feature = "neon_intrinsics", since = "1.59.0")
57756)]
57757#[cfg_attr(
57758 target_arch = "arm",
57759 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57760)]
57761pub fn vrev32_s8(a: int8x8_t) -> int8x8_t {
57762 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57763}
57764#[doc = "Reversing vector elements (swap endianness)"]
57765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"]
57766#[inline]
57767#[target_feature(enable = "neon")]
57768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57769#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57770#[cfg_attr(
57771 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57772 assert_instr(rev32)
57773)]
57774#[cfg_attr(
57775 not(target_arch = "arm"),
57776 stable(feature = "neon_intrinsics", since = "1.59.0")
57777)]
57778#[cfg_attr(
57779 target_arch = "arm",
57780 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57781)]
57782pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t {
57783 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57784}
57785#[doc = "Reversing vector elements (swap endianness)"]
57786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"]
57787#[inline]
57788#[target_feature(enable = "neon")]
57789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57790#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57791#[cfg_attr(
57792 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57793 assert_instr(rev32)
57794)]
57795#[cfg_attr(
57796 not(target_arch = "arm"),
57797 stable(feature = "neon_intrinsics", since = "1.59.0")
57798)]
57799#[cfg_attr(
57800 target_arch = "arm",
57801 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57802)]
57803pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t {
57804 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57805}
57806#[doc = "Reversing vector elements (swap endianness)"]
57807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"]
57808#[inline]
57809#[target_feature(enable = "neon")]
57810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57811#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57812#[cfg_attr(
57813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57814 assert_instr(rev32)
57815)]
57816#[cfg_attr(
57817 not(target_arch = "arm"),
57818 stable(feature = "neon_intrinsics", since = "1.59.0")
57819)]
57820#[cfg_attr(
57821 target_arch = "arm",
57822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57823)]
57824pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t {
57825 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57826}
57827#[doc = "Reversing vector elements (swap endianness)"]
57828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"]
57829#[inline]
57830#[target_feature(enable = "neon")]
57831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57832#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57833#[cfg_attr(
57834 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57835 assert_instr(rev32)
57836)]
57837#[cfg_attr(
57838 not(target_arch = "arm"),
57839 stable(feature = "neon_intrinsics", since = "1.59.0")
57840)]
57841#[cfg_attr(
57842 target_arch = "arm",
57843 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57844)]
57845pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t {
57846 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57847}
57848#[doc = "Reversing vector elements (swap endianness)"]
57849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"]
57850#[inline]
57851#[target_feature(enable = "neon")]
57852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57853#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57854#[cfg_attr(
57855 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57856 assert_instr(rev32)
57857)]
57858#[cfg_attr(
57859 not(target_arch = "arm"),
57860 stable(feature = "neon_intrinsics", since = "1.59.0")
57861)]
57862#[cfg_attr(
57863 target_arch = "arm",
57864 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57865)]
57866pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t {
57867 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57868}
57869#[doc = "Reversing vector elements (swap endianness)"]
57870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"]
57871#[inline]
57872#[target_feature(enable = "neon")]
57873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57874#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57875#[cfg_attr(
57876 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57877 assert_instr(rev32)
57878)]
57879#[cfg_attr(
57880 not(target_arch = "arm"),
57881 stable(feature = "neon_intrinsics", since = "1.59.0")
57882)]
57883#[cfg_attr(
57884 target_arch = "arm",
57885 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57886)]
57887pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t {
57888 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57889}
57890#[doc = "Reversing vector elements (swap endianness)"]
57891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"]
57892#[inline]
57893#[target_feature(enable = "neon")]
57894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57895#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57896#[cfg_attr(
57897 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57898 assert_instr(rev32)
57899)]
57900#[cfg_attr(
57901 not(target_arch = "arm"),
57902 stable(feature = "neon_intrinsics", since = "1.59.0")
57903)]
57904#[cfg_attr(
57905 target_arch = "arm",
57906 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57907)]
57908pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t {
57909 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57910}
57911#[doc = "Reversing vector elements (swap endianness)"]
57912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"]
57913#[inline]
57914#[target_feature(enable = "neon")]
57915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57916#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57917#[cfg_attr(
57918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57919 assert_instr(rev32)
57920)]
57921#[cfg_attr(
57922 not(target_arch = "arm"),
57923 stable(feature = "neon_intrinsics", since = "1.59.0")
57924)]
57925#[cfg_attr(
57926 target_arch = "arm",
57927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57928)]
57929pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t {
57930 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57931}
57932#[doc = "Reversing vector elements (swap endianness)"]
57933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"]
57934#[inline]
57935#[target_feature(enable = "neon")]
57936#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57937#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
57938#[cfg_attr(
57939 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57940 assert_instr(rev64)
57941)]
57942#[cfg_attr(
57943 not(target_arch = "arm"),
57944 stable(feature = "neon_intrinsics", since = "1.59.0")
57945)]
57946#[cfg_attr(
57947 target_arch = "arm",
57948 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57949)]
57950pub fn vrev64_f32(a: float32x2_t) -> float32x2_t {
57951 unsafe { simd_shuffle!(a, a, [1, 0]) }
57952}
57953#[doc = "Reversing vector elements (swap endianness)"]
57954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"]
57955#[inline]
57956#[target_feature(enable = "neon")]
57957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57958#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
57959#[cfg_attr(
57960 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57961 assert_instr(rev64)
57962)]
57963#[cfg_attr(
57964 not(target_arch = "arm"),
57965 stable(feature = "neon_intrinsics", since = "1.59.0")
57966)]
57967#[cfg_attr(
57968 target_arch = "arm",
57969 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57970)]
57971pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t {
57972 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
57973}
57974#[doc = "Reversing vector elements (swap endianness)"]
57975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"]
57976#[inline]
57977#[target_feature(enable = "neon")]
57978#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57979#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
57980#[cfg_attr(
57981 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57982 assert_instr(rev64)
57983)]
57984#[cfg_attr(
57985 not(target_arch = "arm"),
57986 stable(feature = "neon_intrinsics", since = "1.59.0")
57987)]
57988#[cfg_attr(
57989 target_arch = "arm",
57990 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57991)]
57992pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t {
57993 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
57994}
57995#[doc = "Reversing vector elements (swap endianness)"]
57996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"]
57997#[inline]
57998#[target_feature(enable = "neon")]
57999#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58000#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58001#[cfg_attr(
58002 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58003 assert_instr(rev64)
58004)]
58005#[cfg_attr(
58006 not(target_arch = "arm"),
58007 stable(feature = "neon_intrinsics", since = "1.59.0")
58008)]
58009#[cfg_attr(
58010 target_arch = "arm",
58011 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58012)]
58013pub fn vrev64_s16(a: int16x4_t) -> int16x4_t {
58014 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
58015}
58016#[doc = "Reversing vector elements (swap endianness)"]
58017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"]
58018#[inline]
58019#[target_feature(enable = "neon")]
58020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58021#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58022#[cfg_attr(
58023 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58024 assert_instr(rev64)
58025)]
58026#[cfg_attr(
58027 not(target_arch = "arm"),
58028 stable(feature = "neon_intrinsics", since = "1.59.0")
58029)]
58030#[cfg_attr(
58031 target_arch = "arm",
58032 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58033)]
58034pub fn vrev64_s32(a: int32x2_t) -> int32x2_t {
58035 unsafe { simd_shuffle!(a, a, [1, 0]) }
58036}
58037#[doc = "Reversing vector elements (swap endianness)"]
58038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"]
58039#[inline]
58040#[target_feature(enable = "neon")]
58041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58042#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58043#[cfg_attr(
58044 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58045 assert_instr(rev64)
58046)]
58047#[cfg_attr(
58048 not(target_arch = "arm"),
58049 stable(feature = "neon_intrinsics", since = "1.59.0")
58050)]
58051#[cfg_attr(
58052 target_arch = "arm",
58053 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58054)]
58055pub fn vrev64_s8(a: int8x8_t) -> int8x8_t {
58056 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
58057}
58058#[doc = "Reversing vector elements (swap endianness)"]
58059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"]
58060#[inline]
58061#[target_feature(enable = "neon")]
58062#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58063#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58064#[cfg_attr(
58065 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58066 assert_instr(rev64)
58067)]
58068#[cfg_attr(
58069 not(target_arch = "arm"),
58070 stable(feature = "neon_intrinsics", since = "1.59.0")
58071)]
58072#[cfg_attr(
58073 target_arch = "arm",
58074 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58075)]
58076pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t {
58077 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
58078}
58079#[doc = "Reversing vector elements (swap endianness)"]
58080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"]
58081#[inline]
58082#[target_feature(enable = "neon")]
58083#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58084#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58085#[cfg_attr(
58086 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58087 assert_instr(rev64)
58088)]
58089#[cfg_attr(
58090 not(target_arch = "arm"),
58091 stable(feature = "neon_intrinsics", since = "1.59.0")
58092)]
58093#[cfg_attr(
58094 target_arch = "arm",
58095 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58096)]
58097pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t {
58098 unsafe { simd_shuffle!(a, a, [1, 0]) }
58099}
58100#[doc = "Reversing vector elements (swap endianness)"]
58101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"]
58102#[inline]
58103#[target_feature(enable = "neon")]
58104#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58105#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58106#[cfg_attr(
58107 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58108 assert_instr(rev64)
58109)]
58110#[cfg_attr(
58111 not(target_arch = "arm"),
58112 stable(feature = "neon_intrinsics", since = "1.59.0")
58113)]
58114#[cfg_attr(
58115 target_arch = "arm",
58116 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58117)]
58118pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t {
58119 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
58120}
58121#[doc = "Reversing vector elements (swap endianness)"]
58122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"]
58123#[inline]
58124#[target_feature(enable = "neon")]
58125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58126#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58127#[cfg_attr(
58128 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58129 assert_instr(rev64)
58130)]
58131#[cfg_attr(
58132 not(target_arch = "arm"),
58133 stable(feature = "neon_intrinsics", since = "1.59.0")
58134)]
58135#[cfg_attr(
58136 target_arch = "arm",
58137 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58138)]
58139pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t {
58140 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
58141}
58142#[doc = "Reversing vector elements (swap endianness)"]
58143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"]
58144#[inline]
58145#[target_feature(enable = "neon")]
58146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58147#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58148#[cfg_attr(
58149 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58150 assert_instr(rev64)
58151)]
58152#[cfg_attr(
58153 not(target_arch = "arm"),
58154 stable(feature = "neon_intrinsics", since = "1.59.0")
58155)]
58156#[cfg_attr(
58157 target_arch = "arm",
58158 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58159)]
58160pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t {
58161 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58162}
58163#[doc = "Reversing vector elements (swap endianness)"]
58164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"]
58165#[inline]
58166#[target_feature(enable = "neon")]
58167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58168#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58169#[cfg_attr(
58170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58171 assert_instr(rev64)
58172)]
58173#[cfg_attr(
58174 not(target_arch = "arm"),
58175 stable(feature = "neon_intrinsics", since = "1.59.0")
58176)]
58177#[cfg_attr(
58178 target_arch = "arm",
58179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58180)]
58181pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t {
58182 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
58183}
58184#[doc = "Reversing vector elements (swap endianness)"]
58185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"]
58186#[inline]
58187#[target_feature(enable = "neon")]
58188#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58189#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58190#[cfg_attr(
58191 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58192 assert_instr(rev64)
58193)]
58194#[cfg_attr(
58195 not(target_arch = "arm"),
58196 stable(feature = "neon_intrinsics", since = "1.59.0")
58197)]
58198#[cfg_attr(
58199 target_arch = "arm",
58200 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58201)]
58202pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t {
58203 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58204}
58205#[doc = "Reversing vector elements (swap endianness)"]
58206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"]
58207#[inline]
58208#[target_feature(enable = "neon")]
58209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58210#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58211#[cfg_attr(
58212 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58213 assert_instr(rev64)
58214)]
58215#[cfg_attr(
58216 not(target_arch = "arm"),
58217 stable(feature = "neon_intrinsics", since = "1.59.0")
58218)]
58219#[cfg_attr(
58220 target_arch = "arm",
58221 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58222)]
58223pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t {
58224 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
58225}
58226#[doc = "Reversing vector elements (swap endianness)"]
58227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"]
58228#[inline]
58229#[target_feature(enable = "neon")]
58230#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58231#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58232#[cfg_attr(
58233 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58234 assert_instr(rev64)
58235)]
58236#[cfg_attr(
58237 not(target_arch = "arm"),
58238 stable(feature = "neon_intrinsics", since = "1.59.0")
58239)]
58240#[cfg_attr(
58241 target_arch = "arm",
58242 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58243)]
58244pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t {
58245 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
58246}
58247#[doc = "Reversing vector elements (swap endianness)"]
58248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"]
58249#[inline]
58250#[target_feature(enable = "neon")]
58251#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58252#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
58253#[cfg_attr(
58254 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58255 assert_instr(rev64)
58256)]
58257#[cfg_attr(
58258 not(target_arch = "arm"),
58259 stable(feature = "neon_intrinsics", since = "1.59.0")
58260)]
58261#[cfg_attr(
58262 target_arch = "arm",
58263 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58264)]
58265pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t {
58266 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58267}
58268#[doc = "Reversing vector elements (swap endianness)"]
58269#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"]
58270#[inline]
58271#[target_feature(enable = "neon")]
58272#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58273#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
58274#[cfg_attr(
58275 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58276 assert_instr(rev64)
58277)]
58278#[cfg_attr(
58279 not(target_arch = "arm"),
58280 stable(feature = "neon_intrinsics", since = "1.59.0")
58281)]
58282#[cfg_attr(
58283 target_arch = "arm",
58284 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58285)]
58286pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t {
58287 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
58288}
58289#[doc = "Reversing vector elements (swap endianness)"]
58290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"]
58291#[inline]
58292#[target_feature(enable = "neon")]
58293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58294#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
58295#[cfg_attr(
58296 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58297 assert_instr(rev64)
58298)]
58299#[cfg_attr(
58300 not(target_arch = "arm"),
58301 stable(feature = "neon_intrinsics", since = "1.59.0")
58302)]
58303#[cfg_attr(
58304 target_arch = "arm",
58305 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58306)]
58307pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t {
58308 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
58309}
58310#[doc = "Reverse elements in 64-bit doublewords"]
58311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"]
58312#[inline]
58313#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58314#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
58315#[cfg_attr(
58316 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58317 assert_instr(rev64)
58318)]
58319#[target_feature(enable = "neon,fp16")]
58320#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58321pub fn vrev64_f16(a: float16x4_t) -> float16x4_t {
58322 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
58323}
58324#[doc = "Reverse elements in 64-bit doublewords"]
58325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"]
58326#[inline]
58327#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58328#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
58329#[cfg_attr(
58330 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58331 assert_instr(rev64)
58332)]
58333#[target_feature(enable = "neon,fp16")]
58334#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58335pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t {
58336 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
58337}
58338#[doc = "Rounding halving add"]
58339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"]
58340#[inline]
58341#[target_feature(enable = "neon")]
58342#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58343#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
58344#[cfg_attr(
58345 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58346 assert_instr(srhadd)
58347)]
58348#[cfg_attr(
58349 not(target_arch = "arm"),
58350 stable(feature = "neon_intrinsics", since = "1.59.0")
58351)]
58352#[cfg_attr(
58353 target_arch = "arm",
58354 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58355)]
58356pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
58357 unsafe extern "unadjusted" {
58358 #[cfg_attr(
58359 any(target_arch = "aarch64", target_arch = "arm64ec"),
58360 link_name = "llvm.aarch64.neon.srhadd.v8i8"
58361 )]
58362 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i8")]
58363 fn _vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
58364 }
58365 unsafe { _vrhadd_s8(a, b) }
58366}
58367#[doc = "Rounding halving add"]
58368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"]
58369#[inline]
58370#[target_feature(enable = "neon")]
58371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58372#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
58373#[cfg_attr(
58374 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58375 assert_instr(srhadd)
58376)]
58377#[cfg_attr(
58378 not(target_arch = "arm"),
58379 stable(feature = "neon_intrinsics", since = "1.59.0")
58380)]
58381#[cfg_attr(
58382 target_arch = "arm",
58383 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58384)]
58385pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
58386 unsafe extern "unadjusted" {
58387 #[cfg_attr(
58388 any(target_arch = "aarch64", target_arch = "arm64ec"),
58389 link_name = "llvm.aarch64.neon.srhadd.v16i8"
58390 )]
58391 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v16i8")]
58392 fn _vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
58393 }
58394 unsafe { _vrhaddq_s8(a, b) }
58395}
58396#[doc = "Rounding halving add"]
58397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"]
58398#[inline]
58399#[target_feature(enable = "neon")]
58400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58401#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
58402#[cfg_attr(
58403 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58404 assert_instr(srhadd)
58405)]
58406#[cfg_attr(
58407 not(target_arch = "arm"),
58408 stable(feature = "neon_intrinsics", since = "1.59.0")
58409)]
58410#[cfg_attr(
58411 target_arch = "arm",
58412 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58413)]
58414pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
58415 unsafe extern "unadjusted" {
58416 #[cfg_attr(
58417 any(target_arch = "aarch64", target_arch = "arm64ec"),
58418 link_name = "llvm.aarch64.neon.srhadd.v4i16"
58419 )]
58420 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i16")]
58421 fn _vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
58422 }
58423 unsafe { _vrhadd_s16(a, b) }
58424}
58425#[doc = "Rounding halving add"]
58426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"]
58427#[inline]
58428#[target_feature(enable = "neon")]
58429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58430#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
58431#[cfg_attr(
58432 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58433 assert_instr(srhadd)
58434)]
58435#[cfg_attr(
58436 not(target_arch = "arm"),
58437 stable(feature = "neon_intrinsics", since = "1.59.0")
58438)]
58439#[cfg_attr(
58440 target_arch = "arm",
58441 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58442)]
58443pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
58444 unsafe extern "unadjusted" {
58445 #[cfg_attr(
58446 any(target_arch = "aarch64", target_arch = "arm64ec"),
58447 link_name = "llvm.aarch64.neon.srhadd.v8i16"
58448 )]
58449 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i16")]
58450 fn _vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
58451 }
58452 unsafe { _vrhaddq_s16(a, b) }
58453}
58454#[doc = "Rounding halving add"]
58455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"]
58456#[inline]
58457#[target_feature(enable = "neon")]
58458#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58459#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
58460#[cfg_attr(
58461 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58462 assert_instr(srhadd)
58463)]
58464#[cfg_attr(
58465 not(target_arch = "arm"),
58466 stable(feature = "neon_intrinsics", since = "1.59.0")
58467)]
58468#[cfg_attr(
58469 target_arch = "arm",
58470 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58471)]
58472pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
58473 unsafe extern "unadjusted" {
58474 #[cfg_attr(
58475 any(target_arch = "aarch64", target_arch = "arm64ec"),
58476 link_name = "llvm.aarch64.neon.srhadd.v2i32"
58477 )]
58478 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v2i32")]
58479 fn _vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
58480 }
58481 unsafe { _vrhadd_s32(a, b) }
58482}
58483#[doc = "Rounding halving add"]
58484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"]
58485#[inline]
58486#[target_feature(enable = "neon")]
58487#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58488#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
58489#[cfg_attr(
58490 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58491 assert_instr(srhadd)
58492)]
58493#[cfg_attr(
58494 not(target_arch = "arm"),
58495 stable(feature = "neon_intrinsics", since = "1.59.0")
58496)]
58497#[cfg_attr(
58498 target_arch = "arm",
58499 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58500)]
58501pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
58502 unsafe extern "unadjusted" {
58503 #[cfg_attr(
58504 any(target_arch = "aarch64", target_arch = "arm64ec"),
58505 link_name = "llvm.aarch64.neon.srhadd.v4i32"
58506 )]
58507 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i32")]
58508 fn _vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
58509 }
58510 unsafe { _vrhaddq_s32(a, b) }
58511}
58512#[doc = "Rounding halving add"]
58513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"]
58514#[inline]
58515#[target_feature(enable = "neon")]
58516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58517#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
58518#[cfg_attr(
58519 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58520 assert_instr(urhadd)
58521)]
58522#[cfg_attr(
58523 not(target_arch = "arm"),
58524 stable(feature = "neon_intrinsics", since = "1.59.0")
58525)]
58526#[cfg_attr(
58527 target_arch = "arm",
58528 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58529)]
58530pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
58531 unsafe extern "unadjusted" {
58532 #[cfg_attr(
58533 any(target_arch = "aarch64", target_arch = "arm64ec"),
58534 link_name = "llvm.aarch64.neon.urhadd.v8i8"
58535 )]
58536 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i8")]
58537 fn _vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
58538 }
58539 unsafe { _vrhadd_u8(a, b) }
58540}
58541#[doc = "Rounding halving add"]
58542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"]
58543#[inline]
58544#[target_feature(enable = "neon")]
58545#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58546#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
58547#[cfg_attr(
58548 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58549 assert_instr(urhadd)
58550)]
58551#[cfg_attr(
58552 not(target_arch = "arm"),
58553 stable(feature = "neon_intrinsics", since = "1.59.0")
58554)]
58555#[cfg_attr(
58556 target_arch = "arm",
58557 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58558)]
58559pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
58560 unsafe extern "unadjusted" {
58561 #[cfg_attr(
58562 any(target_arch = "aarch64", target_arch = "arm64ec"),
58563 link_name = "llvm.aarch64.neon.urhadd.v16i8"
58564 )]
58565 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v16i8")]
58566 fn _vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
58567 }
58568 unsafe { _vrhaddq_u8(a, b) }
58569}
58570#[doc = "Rounding halving add"]
58571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"]
58572#[inline]
58573#[target_feature(enable = "neon")]
58574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58575#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
58576#[cfg_attr(
58577 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58578 assert_instr(urhadd)
58579)]
58580#[cfg_attr(
58581 not(target_arch = "arm"),
58582 stable(feature = "neon_intrinsics", since = "1.59.0")
58583)]
58584#[cfg_attr(
58585 target_arch = "arm",
58586 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58587)]
58588pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
58589 unsafe extern "unadjusted" {
58590 #[cfg_attr(
58591 any(target_arch = "aarch64", target_arch = "arm64ec"),
58592 link_name = "llvm.aarch64.neon.urhadd.v4i16"
58593 )]
58594 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i16")]
58595 fn _vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
58596 }
58597 unsafe { _vrhadd_u16(a, b) }
58598}
58599#[doc = "Rounding halving add"]
58600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"]
58601#[inline]
58602#[target_feature(enable = "neon")]
58603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58604#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
58605#[cfg_attr(
58606 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58607 assert_instr(urhadd)
58608)]
58609#[cfg_attr(
58610 not(target_arch = "arm"),
58611 stable(feature = "neon_intrinsics", since = "1.59.0")
58612)]
58613#[cfg_attr(
58614 target_arch = "arm",
58615 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58616)]
58617pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
58618 unsafe extern "unadjusted" {
58619 #[cfg_attr(
58620 any(target_arch = "aarch64", target_arch = "arm64ec"),
58621 link_name = "llvm.aarch64.neon.urhadd.v8i16"
58622 )]
58623 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i16")]
58624 fn _vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
58625 }
58626 unsafe { _vrhaddq_u16(a, b) }
58627}
58628#[doc = "Rounding halving add"]
58629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"]
58630#[inline]
58631#[target_feature(enable = "neon")]
58632#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58633#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
58634#[cfg_attr(
58635 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58636 assert_instr(urhadd)
58637)]
58638#[cfg_attr(
58639 not(target_arch = "arm"),
58640 stable(feature = "neon_intrinsics", since = "1.59.0")
58641)]
58642#[cfg_attr(
58643 target_arch = "arm",
58644 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58645)]
58646pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
58647 unsafe extern "unadjusted" {
58648 #[cfg_attr(
58649 any(target_arch = "aarch64", target_arch = "arm64ec"),
58650 link_name = "llvm.aarch64.neon.urhadd.v2i32"
58651 )]
58652 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v2i32")]
58653 fn _vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
58654 }
58655 unsafe { _vrhadd_u32(a, b) }
58656}
58657#[doc = "Rounding halving add"]
58658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"]
58659#[inline]
58660#[target_feature(enable = "neon")]
58661#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58662#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
58663#[cfg_attr(
58664 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58665 assert_instr(urhadd)
58666)]
58667#[cfg_attr(
58668 not(target_arch = "arm"),
58669 stable(feature = "neon_intrinsics", since = "1.59.0")
58670)]
58671#[cfg_attr(
58672 target_arch = "arm",
58673 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58674)]
58675pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
58676 unsafe extern "unadjusted" {
58677 #[cfg_attr(
58678 any(target_arch = "aarch64", target_arch = "arm64ec"),
58679 link_name = "llvm.aarch64.neon.urhadd.v4i32"
58680 )]
58681 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i32")]
58682 fn _vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
58683 }
58684 unsafe { _vrhaddq_u32(a, b) }
58685}
58686#[doc = "Floating-point round to integral, to nearest with ties to even"]
58687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"]
58688#[inline]
58689#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58690#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58691#[cfg_attr(
58692 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58693 assert_instr(frintn)
58694)]
58695#[target_feature(enable = "neon,fp16")]
58696#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58697pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
58698 unsafe extern "unadjusted" {
58699 #[cfg_attr(
58700 any(target_arch = "aarch64", target_arch = "arm64ec"),
58701 link_name = "llvm.aarch64.neon.frintn.v4f16"
58702 )]
58703 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f16")]
58704 fn _vrndn_f16(a: float16x4_t) -> float16x4_t;
58705 }
58706 unsafe { _vrndn_f16(a) }
58707}
58708#[doc = "Floating-point round to integral, to nearest with ties to even"]
58709#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"]
58710#[inline]
58711#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58712#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58713#[cfg_attr(
58714 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58715 assert_instr(frintn)
58716)]
58717#[target_feature(enable = "neon,fp16")]
58718#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58719pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t {
58720 unsafe extern "unadjusted" {
58721 #[cfg_attr(
58722 any(target_arch = "aarch64", target_arch = "arm64ec"),
58723 link_name = "llvm.aarch64.neon.frintn.v8f16"
58724 )]
58725 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v8f16")]
58726 fn _vrndnq_f16(a: float16x8_t) -> float16x8_t;
58727 }
58728 unsafe { _vrndnq_f16(a) }
58729}
58730#[doc = "Floating-point round to integral, to nearest with ties to even"]
58731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"]
58732#[inline]
58733#[target_feature(enable = "neon")]
58734#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58735#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58736#[cfg_attr(
58737 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58738 assert_instr(frintn)
58739)]
58740#[cfg_attr(
58741 not(target_arch = "arm"),
58742 stable(feature = "neon_intrinsics", since = "1.59.0")
58743)]
58744#[cfg_attr(
58745 target_arch = "arm",
58746 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58747)]
58748pub fn vrndn_f32(a: float32x2_t) -> float32x2_t {
58749 unsafe extern "unadjusted" {
58750 #[cfg_attr(
58751 any(target_arch = "aarch64", target_arch = "arm64ec"),
58752 link_name = "llvm.aarch64.neon.frintn.v2f32"
58753 )]
58754 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v2f32")]
58755 fn _vrndn_f32(a: float32x2_t) -> float32x2_t;
58756 }
58757 unsafe { _vrndn_f32(a) }
58758}
58759#[doc = "Floating-point round to integral, to nearest with ties to even"]
58760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"]
58761#[inline]
58762#[target_feature(enable = "neon")]
58763#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58764#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58765#[cfg_attr(
58766 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58767 assert_instr(frintn)
58768)]
58769#[cfg_attr(
58770 not(target_arch = "arm"),
58771 stable(feature = "neon_intrinsics", since = "1.59.0")
58772)]
58773#[cfg_attr(
58774 target_arch = "arm",
58775 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58776)]
58777pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t {
58778 unsafe extern "unadjusted" {
58779 #[cfg_attr(
58780 any(target_arch = "aarch64", target_arch = "arm64ec"),
58781 link_name = "llvm.aarch64.neon.frintn.v4f32"
58782 )]
58783 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f32")]
58784 fn _vrndnq_f32(a: float32x4_t) -> float32x4_t;
58785 }
58786 unsafe { _vrndnq_f32(a) }
58787}
58788#[doc = "Signed rounding shift left"]
58789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"]
58790#[inline]
58791#[target_feature(enable = "neon")]
58792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58793#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58794#[cfg_attr(
58795 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58796 assert_instr(srshl)
58797)]
58798#[cfg_attr(
58799 not(target_arch = "arm"),
58800 stable(feature = "neon_intrinsics", since = "1.59.0")
58801)]
58802#[cfg_attr(
58803 target_arch = "arm",
58804 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58805)]
58806pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
58807 unsafe extern "unadjusted" {
58808 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i8")]
58809 #[cfg_attr(
58810 any(target_arch = "aarch64", target_arch = "arm64ec"),
58811 link_name = "llvm.aarch64.neon.srshl.v8i8"
58812 )]
58813 fn _vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
58814 }
58815 unsafe { _vrshl_s8(a, b) }
58816}
58817#[doc = "Signed rounding shift left"]
58818#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"]
58819#[inline]
58820#[target_feature(enable = "neon")]
58821#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58822#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58823#[cfg_attr(
58824 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58825 assert_instr(srshl)
58826)]
58827#[cfg_attr(
58828 not(target_arch = "arm"),
58829 stable(feature = "neon_intrinsics", since = "1.59.0")
58830)]
58831#[cfg_attr(
58832 target_arch = "arm",
58833 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58834)]
58835pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
58836 unsafe extern "unadjusted" {
58837 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v16i8")]
58838 #[cfg_attr(
58839 any(target_arch = "aarch64", target_arch = "arm64ec"),
58840 link_name = "llvm.aarch64.neon.srshl.v16i8"
58841 )]
58842 fn _vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
58843 }
58844 unsafe { _vrshlq_s8(a, b) }
58845}
58846#[doc = "Signed rounding shift left"]
58847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"]
58848#[inline]
58849#[target_feature(enable = "neon")]
58850#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58851#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58852#[cfg_attr(
58853 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58854 assert_instr(srshl)
58855)]
58856#[cfg_attr(
58857 not(target_arch = "arm"),
58858 stable(feature = "neon_intrinsics", since = "1.59.0")
58859)]
58860#[cfg_attr(
58861 target_arch = "arm",
58862 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58863)]
58864pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
58865 unsafe extern "unadjusted" {
58866 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i16")]
58867 #[cfg_attr(
58868 any(target_arch = "aarch64", target_arch = "arm64ec"),
58869 link_name = "llvm.aarch64.neon.srshl.v4i16"
58870 )]
58871 fn _vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
58872 }
58873 unsafe { _vrshl_s16(a, b) }
58874}
58875#[doc = "Signed rounding shift left"]
58876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"]
58877#[inline]
58878#[target_feature(enable = "neon")]
58879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58881#[cfg_attr(
58882 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58883 assert_instr(srshl)
58884)]
58885#[cfg_attr(
58886 not(target_arch = "arm"),
58887 stable(feature = "neon_intrinsics", since = "1.59.0")
58888)]
58889#[cfg_attr(
58890 target_arch = "arm",
58891 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58892)]
58893pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
58894 unsafe extern "unadjusted" {
58895 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i16")]
58896 #[cfg_attr(
58897 any(target_arch = "aarch64", target_arch = "arm64ec"),
58898 link_name = "llvm.aarch64.neon.srshl.v8i16"
58899 )]
58900 fn _vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
58901 }
58902 unsafe { _vrshlq_s16(a, b) }
58903}
58904#[doc = "Signed rounding shift left"]
58905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"]
58906#[inline]
58907#[target_feature(enable = "neon")]
58908#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58909#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58910#[cfg_attr(
58911 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58912 assert_instr(srshl)
58913)]
58914#[cfg_attr(
58915 not(target_arch = "arm"),
58916 stable(feature = "neon_intrinsics", since = "1.59.0")
58917)]
58918#[cfg_attr(
58919 target_arch = "arm",
58920 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58921)]
58922pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
58923 unsafe extern "unadjusted" {
58924 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i32")]
58925 #[cfg_attr(
58926 any(target_arch = "aarch64", target_arch = "arm64ec"),
58927 link_name = "llvm.aarch64.neon.srshl.v2i32"
58928 )]
58929 fn _vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
58930 }
58931 unsafe { _vrshl_s32(a, b) }
58932}
58933#[doc = "Signed rounding shift left"]
58934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"]
58935#[inline]
58936#[target_feature(enable = "neon")]
58937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58938#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58939#[cfg_attr(
58940 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58941 assert_instr(srshl)
58942)]
58943#[cfg_attr(
58944 not(target_arch = "arm"),
58945 stable(feature = "neon_intrinsics", since = "1.59.0")
58946)]
58947#[cfg_attr(
58948 target_arch = "arm",
58949 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58950)]
58951pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
58952 unsafe extern "unadjusted" {
58953 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i32")]
58954 #[cfg_attr(
58955 any(target_arch = "aarch64", target_arch = "arm64ec"),
58956 link_name = "llvm.aarch64.neon.srshl.v4i32"
58957 )]
58958 fn _vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
58959 }
58960 unsafe { _vrshlq_s32(a, b) }
58961}
58962#[doc = "Signed rounding shift left"]
58963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"]
58964#[inline]
58965#[target_feature(enable = "neon")]
58966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58967#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58968#[cfg_attr(
58969 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58970 assert_instr(srshl)
58971)]
58972#[cfg_attr(
58973 not(target_arch = "arm"),
58974 stable(feature = "neon_intrinsics", since = "1.59.0")
58975)]
58976#[cfg_attr(
58977 target_arch = "arm",
58978 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58979)]
58980pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
58981 unsafe extern "unadjusted" {
58982 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v1i64")]
58983 #[cfg_attr(
58984 any(target_arch = "aarch64", target_arch = "arm64ec"),
58985 link_name = "llvm.aarch64.neon.srshl.v1i64"
58986 )]
58987 fn _vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
58988 }
58989 unsafe { _vrshl_s64(a, b) }
58990}
58991#[doc = "Signed rounding shift left"]
58992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"]
58993#[inline]
58994#[target_feature(enable = "neon")]
58995#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58996#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58997#[cfg_attr(
58998 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58999 assert_instr(srshl)
59000)]
59001#[cfg_attr(
59002 not(target_arch = "arm"),
59003 stable(feature = "neon_intrinsics", since = "1.59.0")
59004)]
59005#[cfg_attr(
59006 target_arch = "arm",
59007 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59008)]
59009pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
59010 unsafe extern "unadjusted" {
59011 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i64")]
59012 #[cfg_attr(
59013 any(target_arch = "aarch64", target_arch = "arm64ec"),
59014 link_name = "llvm.aarch64.neon.srshl.v2i64"
59015 )]
59016 fn _vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
59017 }
59018 unsafe { _vrshlq_s64(a, b) }
59019}
59020#[doc = "Unsigned rounding shift left"]
59021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"]
59022#[inline]
59023#[target_feature(enable = "neon")]
59024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59025#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59026#[cfg_attr(
59027 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59028 assert_instr(urshl)
59029)]
59030#[cfg_attr(
59031 not(target_arch = "arm"),
59032 stable(feature = "neon_intrinsics", since = "1.59.0")
59033)]
59034#[cfg_attr(
59035 target_arch = "arm",
59036 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59037)]
59038pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
59039 unsafe extern "unadjusted" {
59040 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i8")]
59041 #[cfg_attr(
59042 any(target_arch = "aarch64", target_arch = "arm64ec"),
59043 link_name = "llvm.aarch64.neon.urshl.v8i8"
59044 )]
59045 fn _vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
59046 }
59047 unsafe { _vrshl_u8(a, b) }
59048}
59049#[doc = "Unsigned rounding shift left"]
59050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"]
59051#[inline]
59052#[target_feature(enable = "neon")]
59053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59055#[cfg_attr(
59056 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59057 assert_instr(urshl)
59058)]
59059#[cfg_attr(
59060 not(target_arch = "arm"),
59061 stable(feature = "neon_intrinsics", since = "1.59.0")
59062)]
59063#[cfg_attr(
59064 target_arch = "arm",
59065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59066)]
59067pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
59068 unsafe extern "unadjusted" {
59069 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v16i8")]
59070 #[cfg_attr(
59071 any(target_arch = "aarch64", target_arch = "arm64ec"),
59072 link_name = "llvm.aarch64.neon.urshl.v16i8"
59073 )]
59074 fn _vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
59075 }
59076 unsafe { _vrshlq_u8(a, b) }
59077}
59078#[doc = "Unsigned rounding shift left"]
59079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"]
59080#[inline]
59081#[target_feature(enable = "neon")]
59082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59083#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59084#[cfg_attr(
59085 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59086 assert_instr(urshl)
59087)]
59088#[cfg_attr(
59089 not(target_arch = "arm"),
59090 stable(feature = "neon_intrinsics", since = "1.59.0")
59091)]
59092#[cfg_attr(
59093 target_arch = "arm",
59094 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59095)]
59096pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
59097 unsafe extern "unadjusted" {
59098 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i16")]
59099 #[cfg_attr(
59100 any(target_arch = "aarch64", target_arch = "arm64ec"),
59101 link_name = "llvm.aarch64.neon.urshl.v4i16"
59102 )]
59103 fn _vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
59104 }
59105 unsafe { _vrshl_u16(a, b) }
59106}
59107#[doc = "Unsigned rounding shift left"]
59108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"]
59109#[inline]
59110#[target_feature(enable = "neon")]
59111#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59112#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59113#[cfg_attr(
59114 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59115 assert_instr(urshl)
59116)]
59117#[cfg_attr(
59118 not(target_arch = "arm"),
59119 stable(feature = "neon_intrinsics", since = "1.59.0")
59120)]
59121#[cfg_attr(
59122 target_arch = "arm",
59123 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59124)]
59125pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
59126 unsafe extern "unadjusted" {
59127 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i16")]
59128 #[cfg_attr(
59129 any(target_arch = "aarch64", target_arch = "arm64ec"),
59130 link_name = "llvm.aarch64.neon.urshl.v8i16"
59131 )]
59132 fn _vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
59133 }
59134 unsafe { _vrshlq_u16(a, b) }
59135}
59136#[doc = "Unsigned rounding shift left"]
59137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"]
59138#[inline]
59139#[target_feature(enable = "neon")]
59140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59142#[cfg_attr(
59143 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59144 assert_instr(urshl)
59145)]
59146#[cfg_attr(
59147 not(target_arch = "arm"),
59148 stable(feature = "neon_intrinsics", since = "1.59.0")
59149)]
59150#[cfg_attr(
59151 target_arch = "arm",
59152 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59153)]
59154pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
59155 unsafe extern "unadjusted" {
59156 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i32")]
59157 #[cfg_attr(
59158 any(target_arch = "aarch64", target_arch = "arm64ec"),
59159 link_name = "llvm.aarch64.neon.urshl.v2i32"
59160 )]
59161 fn _vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
59162 }
59163 unsafe { _vrshl_u32(a, b) }
59164}
59165#[doc = "Unsigned rounding shift left"]
59166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"]
59167#[inline]
59168#[target_feature(enable = "neon")]
59169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59171#[cfg_attr(
59172 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59173 assert_instr(urshl)
59174)]
59175#[cfg_attr(
59176 not(target_arch = "arm"),
59177 stable(feature = "neon_intrinsics", since = "1.59.0")
59178)]
59179#[cfg_attr(
59180 target_arch = "arm",
59181 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59182)]
59183pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
59184 unsafe extern "unadjusted" {
59185 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i32")]
59186 #[cfg_attr(
59187 any(target_arch = "aarch64", target_arch = "arm64ec"),
59188 link_name = "llvm.aarch64.neon.urshl.v4i32"
59189 )]
59190 fn _vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
59191 }
59192 unsafe { _vrshlq_u32(a, b) }
59193}
59194#[doc = "Unsigned rounding shift left"]
59195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"]
59196#[inline]
59197#[target_feature(enable = "neon")]
59198#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59199#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59200#[cfg_attr(
59201 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59202 assert_instr(urshl)
59203)]
59204#[cfg_attr(
59205 not(target_arch = "arm"),
59206 stable(feature = "neon_intrinsics", since = "1.59.0")
59207)]
59208#[cfg_attr(
59209 target_arch = "arm",
59210 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59211)]
59212pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
59213 unsafe extern "unadjusted" {
59214 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v1i64")]
59215 #[cfg_attr(
59216 any(target_arch = "aarch64", target_arch = "arm64ec"),
59217 link_name = "llvm.aarch64.neon.urshl.v1i64"
59218 )]
59219 fn _vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
59220 }
59221 unsafe { _vrshl_u64(a, b) }
59222}
59223#[doc = "Unsigned rounding shift left"]
59224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"]
59225#[inline]
59226#[target_feature(enable = "neon")]
59227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
59229#[cfg_attr(
59230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59231 assert_instr(urshl)
59232)]
59233#[cfg_attr(
59234 not(target_arch = "arm"),
59235 stable(feature = "neon_intrinsics", since = "1.59.0")
59236)]
59237#[cfg_attr(
59238 target_arch = "arm",
59239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59240)]
59241pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
59242 unsafe extern "unadjusted" {
59243 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i64")]
59244 #[cfg_attr(
59245 any(target_arch = "aarch64", target_arch = "arm64ec"),
59246 link_name = "llvm.aarch64.neon.urshl.v2i64"
59247 )]
59248 fn _vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
59249 }
59250 unsafe { _vrshlq_u64(a, b) }
59251}
59252#[doc = "Signed rounding shift right"]
59253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"]
59254#[inline]
59255#[target_feature(enable = "neon")]
59256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59257#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59258#[cfg_attr(
59259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59260 assert_instr(srshr, N = 2)
59261)]
59262#[rustc_legacy_const_generics(1)]
59263#[cfg_attr(
59264 not(target_arch = "arm"),
59265 stable(feature = "neon_intrinsics", since = "1.59.0")
59266)]
59267#[cfg_attr(
59268 target_arch = "arm",
59269 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59270)]
59271pub fn vrshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
59272 static_assert!(N >= 1 && N <= 8);
59273 vrshl_s8(a, vdup_n_s8(-N as _))
59274}
59275#[doc = "Signed rounding shift right"]
59276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"]
59277#[inline]
59278#[target_feature(enable = "neon")]
59279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59280#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59281#[cfg_attr(
59282 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59283 assert_instr(srshr, N = 2)
59284)]
59285#[rustc_legacy_const_generics(1)]
59286#[cfg_attr(
59287 not(target_arch = "arm"),
59288 stable(feature = "neon_intrinsics", since = "1.59.0")
59289)]
59290#[cfg_attr(
59291 target_arch = "arm",
59292 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59293)]
59294pub fn vrshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
59295 static_assert!(N >= 1 && N <= 8);
59296 vrshlq_s8(a, vdupq_n_s8(-N as _))
59297}
59298#[doc = "Signed rounding shift right"]
59299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"]
59300#[inline]
59301#[target_feature(enable = "neon")]
59302#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59303#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59304#[cfg_attr(
59305 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59306 assert_instr(srshr, N = 2)
59307)]
59308#[rustc_legacy_const_generics(1)]
59309#[cfg_attr(
59310 not(target_arch = "arm"),
59311 stable(feature = "neon_intrinsics", since = "1.59.0")
59312)]
59313#[cfg_attr(
59314 target_arch = "arm",
59315 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59316)]
59317pub fn vrshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
59318 static_assert!(N >= 1 && N <= 16);
59319 vrshl_s16(a, vdup_n_s16(-N as _))
59320}
59321#[doc = "Signed rounding shift right"]
59322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"]
59323#[inline]
59324#[target_feature(enable = "neon")]
59325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59327#[cfg_attr(
59328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59329 assert_instr(srshr, N = 2)
59330)]
59331#[rustc_legacy_const_generics(1)]
59332#[cfg_attr(
59333 not(target_arch = "arm"),
59334 stable(feature = "neon_intrinsics", since = "1.59.0")
59335)]
59336#[cfg_attr(
59337 target_arch = "arm",
59338 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59339)]
59340pub fn vrshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
59341 static_assert!(N >= 1 && N <= 16);
59342 vrshlq_s16(a, vdupq_n_s16(-N as _))
59343}
59344#[doc = "Signed rounding shift right"]
59345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"]
59346#[inline]
59347#[target_feature(enable = "neon")]
59348#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59349#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59350#[cfg_attr(
59351 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59352 assert_instr(srshr, N = 2)
59353)]
59354#[rustc_legacy_const_generics(1)]
59355#[cfg_attr(
59356 not(target_arch = "arm"),
59357 stable(feature = "neon_intrinsics", since = "1.59.0")
59358)]
59359#[cfg_attr(
59360 target_arch = "arm",
59361 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59362)]
59363pub fn vrshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
59364 static_assert!(N >= 1 && N <= 32);
59365 vrshl_s32(a, vdup_n_s32(-N as _))
59366}
59367#[doc = "Signed rounding shift right"]
59368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"]
59369#[inline]
59370#[target_feature(enable = "neon")]
59371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59373#[cfg_attr(
59374 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59375 assert_instr(srshr, N = 2)
59376)]
59377#[rustc_legacy_const_generics(1)]
59378#[cfg_attr(
59379 not(target_arch = "arm"),
59380 stable(feature = "neon_intrinsics", since = "1.59.0")
59381)]
59382#[cfg_attr(
59383 target_arch = "arm",
59384 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59385)]
59386pub fn vrshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
59387 static_assert!(N >= 1 && N <= 32);
59388 vrshlq_s32(a, vdupq_n_s32(-N as _))
59389}
59390#[doc = "Signed rounding shift right"]
59391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"]
59392#[inline]
59393#[target_feature(enable = "neon")]
59394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59396#[cfg_attr(
59397 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59398 assert_instr(srshr, N = 2)
59399)]
59400#[rustc_legacy_const_generics(1)]
59401#[cfg_attr(
59402 not(target_arch = "arm"),
59403 stable(feature = "neon_intrinsics", since = "1.59.0")
59404)]
59405#[cfg_attr(
59406 target_arch = "arm",
59407 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59408)]
59409pub fn vrshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
59410 static_assert!(N >= 1 && N <= 64);
59411 vrshl_s64(a, vdup_n_s64(-N as _))
59412}
59413#[doc = "Signed rounding shift right"]
59414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"]
59415#[inline]
59416#[target_feature(enable = "neon")]
59417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59419#[cfg_attr(
59420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59421 assert_instr(srshr, N = 2)
59422)]
59423#[rustc_legacy_const_generics(1)]
59424#[cfg_attr(
59425 not(target_arch = "arm"),
59426 stable(feature = "neon_intrinsics", since = "1.59.0")
59427)]
59428#[cfg_attr(
59429 target_arch = "arm",
59430 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59431)]
59432pub fn vrshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
59433 static_assert!(N >= 1 && N <= 64);
59434 vrshlq_s64(a, vdupq_n_s64(-N as _))
59435}
59436#[doc = "Unsigned rounding shift right"]
59437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"]
59438#[inline]
59439#[target_feature(enable = "neon")]
59440#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59441#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59442#[cfg_attr(
59443 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59444 assert_instr(urshr, N = 2)
59445)]
59446#[rustc_legacy_const_generics(1)]
59447#[cfg_attr(
59448 not(target_arch = "arm"),
59449 stable(feature = "neon_intrinsics", since = "1.59.0")
59450)]
59451#[cfg_attr(
59452 target_arch = "arm",
59453 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59454)]
59455pub fn vrshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
59456 static_assert!(N >= 1 && N <= 8);
59457 vrshl_u8(a, vdup_n_s8(-N as _))
59458}
59459#[doc = "Unsigned rounding shift right"]
59460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"]
59461#[inline]
59462#[target_feature(enable = "neon")]
59463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59465#[cfg_attr(
59466 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59467 assert_instr(urshr, N = 2)
59468)]
59469#[rustc_legacy_const_generics(1)]
59470#[cfg_attr(
59471 not(target_arch = "arm"),
59472 stable(feature = "neon_intrinsics", since = "1.59.0")
59473)]
59474#[cfg_attr(
59475 target_arch = "arm",
59476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59477)]
59478pub fn vrshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
59479 static_assert!(N >= 1 && N <= 8);
59480 vrshlq_u8(a, vdupq_n_s8(-N as _))
59481}
59482#[doc = "Unsigned rounding shift right"]
59483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"]
59484#[inline]
59485#[target_feature(enable = "neon")]
59486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59488#[cfg_attr(
59489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59490 assert_instr(urshr, N = 2)
59491)]
59492#[rustc_legacy_const_generics(1)]
59493#[cfg_attr(
59494 not(target_arch = "arm"),
59495 stable(feature = "neon_intrinsics", since = "1.59.0")
59496)]
59497#[cfg_attr(
59498 target_arch = "arm",
59499 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59500)]
59501pub fn vrshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
59502 static_assert!(N >= 1 && N <= 16);
59503 vrshl_u16(a, vdup_n_s16(-N as _))
59504}
59505#[doc = "Unsigned rounding shift right"]
59506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"]
59507#[inline]
59508#[target_feature(enable = "neon")]
59509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59511#[cfg_attr(
59512 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59513 assert_instr(urshr, N = 2)
59514)]
59515#[rustc_legacy_const_generics(1)]
59516#[cfg_attr(
59517 not(target_arch = "arm"),
59518 stable(feature = "neon_intrinsics", since = "1.59.0")
59519)]
59520#[cfg_attr(
59521 target_arch = "arm",
59522 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59523)]
59524pub fn vrshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
59525 static_assert!(N >= 1 && N <= 16);
59526 vrshlq_u16(a, vdupq_n_s16(-N as _))
59527}
59528#[doc = "Unsigned rounding shift right"]
59529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"]
59530#[inline]
59531#[target_feature(enable = "neon")]
59532#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59533#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59534#[cfg_attr(
59535 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59536 assert_instr(urshr, N = 2)
59537)]
59538#[rustc_legacy_const_generics(1)]
59539#[cfg_attr(
59540 not(target_arch = "arm"),
59541 stable(feature = "neon_intrinsics", since = "1.59.0")
59542)]
59543#[cfg_attr(
59544 target_arch = "arm",
59545 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59546)]
59547pub fn vrshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
59548 static_assert!(N >= 1 && N <= 32);
59549 vrshl_u32(a, vdup_n_s32(-N as _))
59550}
59551#[doc = "Unsigned rounding shift right"]
59552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"]
59553#[inline]
59554#[target_feature(enable = "neon")]
59555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59556#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59557#[cfg_attr(
59558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59559 assert_instr(urshr, N = 2)
59560)]
59561#[rustc_legacy_const_generics(1)]
59562#[cfg_attr(
59563 not(target_arch = "arm"),
59564 stable(feature = "neon_intrinsics", since = "1.59.0")
59565)]
59566#[cfg_attr(
59567 target_arch = "arm",
59568 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59569)]
59570pub fn vrshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
59571 static_assert!(N >= 1 && N <= 32);
59572 vrshlq_u32(a, vdupq_n_s32(-N as _))
59573}
59574#[doc = "Unsigned rounding shift right"]
59575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"]
59576#[inline]
59577#[target_feature(enable = "neon")]
59578#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59579#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59580#[cfg_attr(
59581 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59582 assert_instr(urshr, N = 2)
59583)]
59584#[rustc_legacy_const_generics(1)]
59585#[cfg_attr(
59586 not(target_arch = "arm"),
59587 stable(feature = "neon_intrinsics", since = "1.59.0")
59588)]
59589#[cfg_attr(
59590 target_arch = "arm",
59591 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59592)]
59593pub fn vrshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
59594 static_assert!(N >= 1 && N <= 64);
59595 vrshl_u64(a, vdup_n_s64(-N as _))
59596}
59597#[doc = "Unsigned rounding shift right"]
59598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"]
59599#[inline]
59600#[target_feature(enable = "neon")]
59601#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59602#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59603#[cfg_attr(
59604 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59605 assert_instr(urshr, N = 2)
59606)]
59607#[rustc_legacy_const_generics(1)]
59608#[cfg_attr(
59609 not(target_arch = "arm"),
59610 stable(feature = "neon_intrinsics", since = "1.59.0")
59611)]
59612#[cfg_attr(
59613 target_arch = "arm",
59614 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59615)]
59616pub fn vrshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
59617 static_assert!(N >= 1 && N <= 64);
59618 vrshlq_u64(a, vdupq_n_s64(-N as _))
59619}
59620#[doc = "Rounding shift right narrow"]
59621#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
59622#[inline]
59623#[cfg(target_arch = "arm")]
59624#[target_feature(enable = "neon,v7")]
59625#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59626#[rustc_legacy_const_generics(1)]
59627#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59628pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
59629 static_assert!(N >= 1 && N <= 8);
59630 unsafe extern "unadjusted" {
59631 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v8i8")]
59632 fn _vrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
59633 }
59634 unsafe {
59635 _vrshrn_n_s16(
59636 a,
59637 const {
59638 int16x8_t([
59639 -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
59640 -N as i16,
59641 ])
59642 },
59643 )
59644 }
59645}
59646#[doc = "Rounding shift right narrow"]
59647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
59648#[inline]
59649#[cfg(target_arch = "arm")]
59650#[target_feature(enable = "neon,v7")]
59651#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59652#[rustc_legacy_const_generics(1)]
59653#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59654pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
59655 static_assert!(N >= 1 && N <= 16);
59656 unsafe extern "unadjusted" {
59657 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v4i16")]
59658 fn _vrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
59659 }
59660 unsafe {
59661 _vrshrn_n_s32(
59662 a,
59663 const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
59664 )
59665 }
59666}
59667#[doc = "Rounding shift right narrow"]
59668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
59669#[inline]
59670#[cfg(target_arch = "arm")]
59671#[target_feature(enable = "neon,v7")]
59672#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59673#[rustc_legacy_const_generics(1)]
59674#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59675pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
59676 static_assert!(N >= 1 && N <= 32);
59677 unsafe extern "unadjusted" {
59678 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v2i32")]
59679 fn _vrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
59680 }
59681 unsafe { _vrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
59682}
59683#[doc = "Rounding shift right narrow"]
59684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
59685#[inline]
59686#[target_feature(enable = "neon")]
59687#[cfg(not(target_arch = "arm"))]
59688#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59689#[rustc_legacy_const_generics(1)]
59690#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59691pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
59692 static_assert!(N >= 1 && N <= 8);
59693 unsafe extern "unadjusted" {
59694 #[cfg_attr(
59695 any(target_arch = "aarch64", target_arch = "arm64ec"),
59696 link_name = "llvm.aarch64.neon.rshrn.v8i8"
59697 )]
59698 fn _vrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
59699 }
59700 unsafe { _vrshrn_n_s16(a, N) }
59701}
59702#[doc = "Rounding shift right narrow"]
59703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
59704#[inline]
59705#[target_feature(enable = "neon")]
59706#[cfg(not(target_arch = "arm"))]
59707#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59708#[rustc_legacy_const_generics(1)]
59709#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59710pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
59711 static_assert!(N >= 1 && N <= 16);
59712 unsafe extern "unadjusted" {
59713 #[cfg_attr(
59714 any(target_arch = "aarch64", target_arch = "arm64ec"),
59715 link_name = "llvm.aarch64.neon.rshrn.v4i16"
59716 )]
59717 fn _vrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
59718 }
59719 unsafe { _vrshrn_n_s32(a, N) }
59720}
59721#[doc = "Rounding shift right narrow"]
59722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
59723#[inline]
59724#[target_feature(enable = "neon")]
59725#[cfg(not(target_arch = "arm"))]
59726#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59727#[rustc_legacy_const_generics(1)]
59728#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59729pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
59730 static_assert!(N >= 1 && N <= 32);
59731 unsafe extern "unadjusted" {
59732 #[cfg_attr(
59733 any(target_arch = "aarch64", target_arch = "arm64ec"),
59734 link_name = "llvm.aarch64.neon.rshrn.v2i32"
59735 )]
59736 fn _vrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
59737 }
59738 unsafe { _vrshrn_n_s64(a, N) }
59739}
59740#[doc = "Rounding shift right narrow"]
59741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"]
59742#[inline]
59743#[target_feature(enable = "neon")]
59744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59745#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59746#[cfg_attr(
59747 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59748 assert_instr(rshrn, N = 2)
59749)]
59750#[rustc_legacy_const_generics(1)]
59751#[cfg_attr(
59752 not(target_arch = "arm"),
59753 stable(feature = "neon_intrinsics", since = "1.59.0")
59754)]
59755#[cfg_attr(
59756 target_arch = "arm",
59757 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59758)]
59759pub fn vrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
59760 static_assert!(N >= 1 && N <= 8);
59761 unsafe { transmute(vrshrn_n_s16::<N>(transmute(a))) }
59762}
59763#[doc = "Rounding shift right narrow"]
59764#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"]
59765#[inline]
59766#[target_feature(enable = "neon")]
59767#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59768#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59769#[cfg_attr(
59770 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59771 assert_instr(rshrn, N = 2)
59772)]
59773#[rustc_legacy_const_generics(1)]
59774#[cfg_attr(
59775 not(target_arch = "arm"),
59776 stable(feature = "neon_intrinsics", since = "1.59.0")
59777)]
59778#[cfg_attr(
59779 target_arch = "arm",
59780 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59781)]
59782pub fn vrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
59783 static_assert!(N >= 1 && N <= 16);
59784 unsafe { transmute(vrshrn_n_s32::<N>(transmute(a))) }
59785}
59786#[doc = "Rounding shift right narrow"]
59787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"]
59788#[inline]
59789#[target_feature(enable = "neon")]
59790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59791#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59792#[cfg_attr(
59793 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59794 assert_instr(rshrn, N = 2)
59795)]
59796#[rustc_legacy_const_generics(1)]
59797#[cfg_attr(
59798 not(target_arch = "arm"),
59799 stable(feature = "neon_intrinsics", since = "1.59.0")
59800)]
59801#[cfg_attr(
59802 target_arch = "arm",
59803 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59804)]
59805pub fn vrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
59806 static_assert!(N >= 1 && N <= 32);
59807 unsafe { transmute(vrshrn_n_s64::<N>(transmute(a))) }
59808}
59809#[doc = "Reciprocal square-root estimate."]
59810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"]
59811#[inline]
59812#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59813#[target_feature(enable = "neon,fp16")]
59814#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59815#[cfg_attr(
59816 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59817 assert_instr(frsqrte)
59818)]
59819#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59820pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t {
59821 unsafe extern "unadjusted" {
59822 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f16")]
59823 #[cfg_attr(
59824 any(target_arch = "aarch64", target_arch = "arm64ec"),
59825 link_name = "llvm.aarch64.neon.frsqrte.v4f16"
59826 )]
59827 fn _vrsqrte_f16(a: float16x4_t) -> float16x4_t;
59828 }
59829 unsafe { _vrsqrte_f16(a) }
59830}
59831#[doc = "Reciprocal square-root estimate."]
59832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"]
59833#[inline]
59834#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59835#[target_feature(enable = "neon,fp16")]
59836#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59837#[cfg_attr(
59838 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59839 assert_instr(frsqrte)
59840)]
59841#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59842pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t {
59843 unsafe extern "unadjusted" {
59844 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v8f16")]
59845 #[cfg_attr(
59846 any(target_arch = "aarch64", target_arch = "arm64ec"),
59847 link_name = "llvm.aarch64.neon.frsqrte.v8f16"
59848 )]
59849 fn _vrsqrteq_f16(a: float16x8_t) -> float16x8_t;
59850 }
59851 unsafe { _vrsqrteq_f16(a) }
59852}
59853#[doc = "Reciprocal square-root estimate."]
59854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"]
59855#[inline]
59856#[target_feature(enable = "neon")]
59857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59858#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59859#[cfg_attr(
59860 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59861 assert_instr(frsqrte)
59862)]
59863#[cfg_attr(
59864 not(target_arch = "arm"),
59865 stable(feature = "neon_intrinsics", since = "1.59.0")
59866)]
59867#[cfg_attr(
59868 target_arch = "arm",
59869 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59870)]
59871pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t {
59872 unsafe extern "unadjusted" {
59873 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")]
59874 #[cfg_attr(
59875 any(target_arch = "aarch64", target_arch = "arm64ec"),
59876 link_name = "llvm.aarch64.neon.frsqrte.v2f32"
59877 )]
59878 fn _vrsqrte_f32(a: float32x2_t) -> float32x2_t;
59879 }
59880 unsafe { _vrsqrte_f32(a) }
59881}
59882#[doc = "Reciprocal square-root estimate."]
59883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"]
59884#[inline]
59885#[target_feature(enable = "neon")]
59886#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59887#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59888#[cfg_attr(
59889 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59890 assert_instr(frsqrte)
59891)]
59892#[cfg_attr(
59893 not(target_arch = "arm"),
59894 stable(feature = "neon_intrinsics", since = "1.59.0")
59895)]
59896#[cfg_attr(
59897 target_arch = "arm",
59898 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59899)]
59900pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t {
59901 unsafe extern "unadjusted" {
59902 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f32")]
59903 #[cfg_attr(
59904 any(target_arch = "aarch64", target_arch = "arm64ec"),
59905 link_name = "llvm.aarch64.neon.frsqrte.v4f32"
59906 )]
59907 fn _vrsqrteq_f32(a: float32x4_t) -> float32x4_t;
59908 }
59909 unsafe { _vrsqrteq_f32(a) }
59910}
59911#[doc = "Unsigned reciprocal square root estimate"]
59912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"]
59913#[inline]
59914#[target_feature(enable = "neon")]
59915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59917#[cfg_attr(
59918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59919 assert_instr(ursqrte)
59920)]
59921#[cfg_attr(
59922 not(target_arch = "arm"),
59923 stable(feature = "neon_intrinsics", since = "1.59.0")
59924)]
59925#[cfg_attr(
59926 target_arch = "arm",
59927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59928)]
59929pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t {
59930 unsafe extern "unadjusted" {
59931 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2i32")]
59932 #[cfg_attr(
59933 any(target_arch = "aarch64", target_arch = "arm64ec"),
59934 link_name = "llvm.aarch64.neon.ursqrte.v2i32"
59935 )]
59936 fn _vrsqrte_u32(a: uint32x2_t) -> uint32x2_t;
59937 }
59938 unsafe { _vrsqrte_u32(a) }
59939}
59940#[doc = "Unsigned reciprocal square root estimate"]
59941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"]
59942#[inline]
59943#[target_feature(enable = "neon")]
59944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59946#[cfg_attr(
59947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59948 assert_instr(ursqrte)
59949)]
59950#[cfg_attr(
59951 not(target_arch = "arm"),
59952 stable(feature = "neon_intrinsics", since = "1.59.0")
59953)]
59954#[cfg_attr(
59955 target_arch = "arm",
59956 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59957)]
59958pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t {
59959 unsafe extern "unadjusted" {
59960 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4i32")]
59961 #[cfg_attr(
59962 any(target_arch = "aarch64", target_arch = "arm64ec"),
59963 link_name = "llvm.aarch64.neon.ursqrte.v4i32"
59964 )]
59965 fn _vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t;
59966 }
59967 unsafe { _vrsqrteq_u32(a) }
59968}
59969#[doc = "Floating-point reciprocal square root step"]
59970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"]
59971#[inline]
59972#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59973#[target_feature(enable = "neon,fp16")]
59974#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
59975#[cfg_attr(
59976 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59977 assert_instr(frsqrts)
59978)]
59979#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59980pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
59981 unsafe extern "unadjusted" {
59982 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f16")]
59983 #[cfg_attr(
59984 any(target_arch = "aarch64", target_arch = "arm64ec"),
59985 link_name = "llvm.aarch64.neon.frsqrts.v4f16"
59986 )]
59987 fn _vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
59988 }
59989 unsafe { _vrsqrts_f16(a, b) }
59990}
59991#[doc = "Floating-point reciprocal square root step"]
59992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"]
59993#[inline]
59994#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59995#[target_feature(enable = "neon,fp16")]
59996#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
59997#[cfg_attr(
59998 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59999 assert_instr(frsqrts)
60000)]
60001#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60002pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
60003 unsafe extern "unadjusted" {
60004 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v8f16")]
60005 #[cfg_attr(
60006 any(target_arch = "aarch64", target_arch = "arm64ec"),
60007 link_name = "llvm.aarch64.neon.frsqrts.v8f16"
60008 )]
60009 fn _vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
60010 }
60011 unsafe { _vrsqrtsq_f16(a, b) }
60012}
60013#[doc = "Floating-point reciprocal square root step"]
60014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"]
60015#[inline]
60016#[target_feature(enable = "neon")]
60017#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60018#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
60019#[cfg_attr(
60020 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60021 assert_instr(frsqrts)
60022)]
60023#[cfg_attr(
60024 not(target_arch = "arm"),
60025 stable(feature = "neon_intrinsics", since = "1.59.0")
60026)]
60027#[cfg_attr(
60028 target_arch = "arm",
60029 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60030)]
60031pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
60032 unsafe extern "unadjusted" {
60033 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v2f32")]
60034 #[cfg_attr(
60035 any(target_arch = "aarch64", target_arch = "arm64ec"),
60036 link_name = "llvm.aarch64.neon.frsqrts.v2f32"
60037 )]
60038 fn _vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
60039 }
60040 unsafe { _vrsqrts_f32(a, b) }
60041}
60042#[doc = "Floating-point reciprocal square root step"]
60043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"]
60044#[inline]
60045#[target_feature(enable = "neon")]
60046#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60047#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
60048#[cfg_attr(
60049 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60050 assert_instr(frsqrts)
60051)]
60052#[cfg_attr(
60053 not(target_arch = "arm"),
60054 stable(feature = "neon_intrinsics", since = "1.59.0")
60055)]
60056#[cfg_attr(
60057 target_arch = "arm",
60058 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60059)]
60060pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
60061 unsafe extern "unadjusted" {
60062 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f32")]
60063 #[cfg_attr(
60064 any(target_arch = "aarch64", target_arch = "arm64ec"),
60065 link_name = "llvm.aarch64.neon.frsqrts.v4f32"
60066 )]
60067 fn _vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
60068 }
60069 unsafe { _vrsqrtsq_f32(a, b) }
60070}
60071#[doc = "Signed rounding shift right and accumulate"]
60072#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"]
60073#[inline]
60074#[target_feature(enable = "neon")]
60075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60077#[cfg_attr(
60078 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60079 assert_instr(srsra, N = 2)
60080)]
60081#[rustc_legacy_const_generics(2)]
60082#[cfg_attr(
60083 not(target_arch = "arm"),
60084 stable(feature = "neon_intrinsics", since = "1.59.0")
60085)]
60086#[cfg_attr(
60087 target_arch = "arm",
60088 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60089)]
60090pub fn vrsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
60091 static_assert!(N >= 1 && N <= 8);
60092 unsafe { simd_add(a, vrshr_n_s8::<N>(b)) }
60093}
60094#[doc = "Signed rounding shift right and accumulate"]
60095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"]
60096#[inline]
60097#[target_feature(enable = "neon")]
60098#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60099#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60100#[cfg_attr(
60101 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60102 assert_instr(srsra, N = 2)
60103)]
60104#[rustc_legacy_const_generics(2)]
60105#[cfg_attr(
60106 not(target_arch = "arm"),
60107 stable(feature = "neon_intrinsics", since = "1.59.0")
60108)]
60109#[cfg_attr(
60110 target_arch = "arm",
60111 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60112)]
60113pub fn vrsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
60114 static_assert!(N >= 1 && N <= 8);
60115 unsafe { simd_add(a, vrshrq_n_s8::<N>(b)) }
60116}
60117#[doc = "Signed rounding shift right and accumulate"]
60118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"]
60119#[inline]
60120#[target_feature(enable = "neon")]
60121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60122#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60123#[cfg_attr(
60124 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60125 assert_instr(srsra, N = 2)
60126)]
60127#[rustc_legacy_const_generics(2)]
60128#[cfg_attr(
60129 not(target_arch = "arm"),
60130 stable(feature = "neon_intrinsics", since = "1.59.0")
60131)]
60132#[cfg_attr(
60133 target_arch = "arm",
60134 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60135)]
60136pub fn vrsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
60137 static_assert!(N >= 1 && N <= 16);
60138 unsafe { simd_add(a, vrshr_n_s16::<N>(b)) }
60139}
60140#[doc = "Signed rounding shift right and accumulate"]
60141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"]
60142#[inline]
60143#[target_feature(enable = "neon")]
60144#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60145#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60146#[cfg_attr(
60147 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60148 assert_instr(srsra, N = 2)
60149)]
60150#[rustc_legacy_const_generics(2)]
60151#[cfg_attr(
60152 not(target_arch = "arm"),
60153 stable(feature = "neon_intrinsics", since = "1.59.0")
60154)]
60155#[cfg_attr(
60156 target_arch = "arm",
60157 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60158)]
60159pub fn vrsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
60160 static_assert!(N >= 1 && N <= 16);
60161 unsafe { simd_add(a, vrshrq_n_s16::<N>(b)) }
60162}
60163#[doc = "Signed rounding shift right and accumulate"]
60164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"]
60165#[inline]
60166#[target_feature(enable = "neon")]
60167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60168#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60169#[cfg_attr(
60170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60171 assert_instr(srsra, N = 2)
60172)]
60173#[rustc_legacy_const_generics(2)]
60174#[cfg_attr(
60175 not(target_arch = "arm"),
60176 stable(feature = "neon_intrinsics", since = "1.59.0")
60177)]
60178#[cfg_attr(
60179 target_arch = "arm",
60180 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60181)]
60182pub fn vrsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
60183 static_assert!(N >= 1 && N <= 32);
60184 unsafe { simd_add(a, vrshr_n_s32::<N>(b)) }
60185}
60186#[doc = "Signed rounding shift right and accumulate"]
60187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"]
60188#[inline]
60189#[target_feature(enable = "neon")]
60190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60191#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60192#[cfg_attr(
60193 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60194 assert_instr(srsra, N = 2)
60195)]
60196#[rustc_legacy_const_generics(2)]
60197#[cfg_attr(
60198 not(target_arch = "arm"),
60199 stable(feature = "neon_intrinsics", since = "1.59.0")
60200)]
60201#[cfg_attr(
60202 target_arch = "arm",
60203 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60204)]
60205pub fn vrsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
60206 static_assert!(N >= 1 && N <= 32);
60207 unsafe { simd_add(a, vrshrq_n_s32::<N>(b)) }
60208}
60209#[doc = "Signed rounding shift right and accumulate"]
60210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"]
60211#[inline]
60212#[target_feature(enable = "neon")]
60213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60215#[cfg_attr(
60216 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60217 assert_instr(srsra, N = 2)
60218)]
60219#[rustc_legacy_const_generics(2)]
60220#[cfg_attr(
60221 not(target_arch = "arm"),
60222 stable(feature = "neon_intrinsics", since = "1.59.0")
60223)]
60224#[cfg_attr(
60225 target_arch = "arm",
60226 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60227)]
60228pub fn vrsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
60229 static_assert!(N >= 1 && N <= 64);
60230 unsafe { simd_add(a, vrshr_n_s64::<N>(b)) }
60231}
60232#[doc = "Signed rounding shift right and accumulate"]
60233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"]
60234#[inline]
60235#[target_feature(enable = "neon")]
60236#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60237#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60238#[cfg_attr(
60239 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60240 assert_instr(srsra, N = 2)
60241)]
60242#[rustc_legacy_const_generics(2)]
60243#[cfg_attr(
60244 not(target_arch = "arm"),
60245 stable(feature = "neon_intrinsics", since = "1.59.0")
60246)]
60247#[cfg_attr(
60248 target_arch = "arm",
60249 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60250)]
60251pub fn vrsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
60252 static_assert!(N >= 1 && N <= 64);
60253 unsafe { simd_add(a, vrshrq_n_s64::<N>(b)) }
60254}
60255#[doc = "Unsigned rounding shift right and accumulate"]
60256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"]
60257#[inline]
60258#[target_feature(enable = "neon")]
60259#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60260#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60261#[cfg_attr(
60262 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60263 assert_instr(ursra, N = 2)
60264)]
60265#[rustc_legacy_const_generics(2)]
60266#[cfg_attr(
60267 not(target_arch = "arm"),
60268 stable(feature = "neon_intrinsics", since = "1.59.0")
60269)]
60270#[cfg_attr(
60271 target_arch = "arm",
60272 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60273)]
60274pub fn vrsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
60275 static_assert!(N >= 1 && N <= 8);
60276 unsafe { simd_add(a, vrshr_n_u8::<N>(b)) }
60277}
60278#[doc = "Unsigned rounding shift right and accumulate"]
60279#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"]
60280#[inline]
60281#[target_feature(enable = "neon")]
60282#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60283#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60284#[cfg_attr(
60285 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60286 assert_instr(ursra, N = 2)
60287)]
60288#[rustc_legacy_const_generics(2)]
60289#[cfg_attr(
60290 not(target_arch = "arm"),
60291 stable(feature = "neon_intrinsics", since = "1.59.0")
60292)]
60293#[cfg_attr(
60294 target_arch = "arm",
60295 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60296)]
60297pub fn vrsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
60298 static_assert!(N >= 1 && N <= 8);
60299 unsafe { simd_add(a, vrshrq_n_u8::<N>(b)) }
60300}
60301#[doc = "Unsigned rounding shift right and accumulate"]
60302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"]
60303#[inline]
60304#[target_feature(enable = "neon")]
60305#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60306#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60307#[cfg_attr(
60308 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60309 assert_instr(ursra, N = 2)
60310)]
60311#[rustc_legacy_const_generics(2)]
60312#[cfg_attr(
60313 not(target_arch = "arm"),
60314 stable(feature = "neon_intrinsics", since = "1.59.0")
60315)]
60316#[cfg_attr(
60317 target_arch = "arm",
60318 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60319)]
60320pub fn vrsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
60321 static_assert!(N >= 1 && N <= 16);
60322 unsafe { simd_add(a, vrshr_n_u16::<N>(b)) }
60323}
60324#[doc = "Unsigned rounding shift right and accumulate"]
60325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"]
60326#[inline]
60327#[target_feature(enable = "neon")]
60328#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60329#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60330#[cfg_attr(
60331 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60332 assert_instr(ursra, N = 2)
60333)]
60334#[rustc_legacy_const_generics(2)]
60335#[cfg_attr(
60336 not(target_arch = "arm"),
60337 stable(feature = "neon_intrinsics", since = "1.59.0")
60338)]
60339#[cfg_attr(
60340 target_arch = "arm",
60341 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60342)]
60343pub fn vrsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
60344 static_assert!(N >= 1 && N <= 16);
60345 unsafe { simd_add(a, vrshrq_n_u16::<N>(b)) }
60346}
60347#[doc = "Unsigned rounding shift right and accumulate"]
60348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"]
60349#[inline]
60350#[target_feature(enable = "neon")]
60351#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60352#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60353#[cfg_attr(
60354 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60355 assert_instr(ursra, N = 2)
60356)]
60357#[rustc_legacy_const_generics(2)]
60358#[cfg_attr(
60359 not(target_arch = "arm"),
60360 stable(feature = "neon_intrinsics", since = "1.59.0")
60361)]
60362#[cfg_attr(
60363 target_arch = "arm",
60364 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60365)]
60366pub fn vrsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
60367 static_assert!(N >= 1 && N <= 32);
60368 unsafe { simd_add(a, vrshr_n_u32::<N>(b)) }
60369}
60370#[doc = "Unsigned rounding shift right and accumulate"]
60371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"]
60372#[inline]
60373#[target_feature(enable = "neon")]
60374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60376#[cfg_attr(
60377 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60378 assert_instr(ursra, N = 2)
60379)]
60380#[rustc_legacy_const_generics(2)]
60381#[cfg_attr(
60382 not(target_arch = "arm"),
60383 stable(feature = "neon_intrinsics", since = "1.59.0")
60384)]
60385#[cfg_attr(
60386 target_arch = "arm",
60387 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60388)]
60389pub fn vrsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
60390 static_assert!(N >= 1 && N <= 32);
60391 unsafe { simd_add(a, vrshrq_n_u32::<N>(b)) }
60392}
60393#[doc = "Unsigned rounding shift right and accumulate"]
60394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"]
60395#[inline]
60396#[target_feature(enable = "neon")]
60397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60398#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60399#[cfg_attr(
60400 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60401 assert_instr(ursra, N = 2)
60402)]
60403#[rustc_legacy_const_generics(2)]
60404#[cfg_attr(
60405 not(target_arch = "arm"),
60406 stable(feature = "neon_intrinsics", since = "1.59.0")
60407)]
60408#[cfg_attr(
60409 target_arch = "arm",
60410 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60411)]
60412pub fn vrsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
60413 static_assert!(N >= 1 && N <= 64);
60414 unsafe { simd_add(a, vrshr_n_u64::<N>(b)) }
60415}
60416#[doc = "Unsigned rounding shift right and accumulate"]
60417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"]
60418#[inline]
60419#[target_feature(enable = "neon")]
60420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60421#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
60422#[cfg_attr(
60423 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60424 assert_instr(ursra, N = 2)
60425)]
60426#[rustc_legacy_const_generics(2)]
60427#[cfg_attr(
60428 not(target_arch = "arm"),
60429 stable(feature = "neon_intrinsics", since = "1.59.0")
60430)]
60431#[cfg_attr(
60432 target_arch = "arm",
60433 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60434)]
60435pub fn vrsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
60436 static_assert!(N >= 1 && N <= 64);
60437 unsafe { simd_add(a, vrshrq_n_u64::<N>(b)) }
60438}
60439#[doc = "Rounding subtract returning high narrow"]
60440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"]
60441#[inline]
60442#[target_feature(enable = "neon")]
60443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60445#[cfg_attr(
60446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60447 assert_instr(rsubhn)
60448)]
60449#[cfg_attr(
60450 not(target_arch = "arm"),
60451 stable(feature = "neon_intrinsics", since = "1.59.0")
60452)]
60453#[cfg_attr(
60454 target_arch = "arm",
60455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60456)]
60457pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
60458 unsafe extern "unadjusted" {
60459 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")]
60460 #[cfg_attr(
60461 any(target_arch = "aarch64", target_arch = "arm64ec"),
60462 link_name = "llvm.aarch64.neon.rsubhn.v8i8"
60463 )]
60464 fn _vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t;
60465 }
60466 unsafe { _vrsubhn_s16(a, b) }
60467}
60468#[doc = "Rounding subtract returning high narrow"]
60469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"]
60470#[inline]
60471#[target_feature(enable = "neon")]
60472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60474#[cfg_attr(
60475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60476 assert_instr(rsubhn)
60477)]
60478#[cfg_attr(
60479 not(target_arch = "arm"),
60480 stable(feature = "neon_intrinsics", since = "1.59.0")
60481)]
60482#[cfg_attr(
60483 target_arch = "arm",
60484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60485)]
60486pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
60487 unsafe extern "unadjusted" {
60488 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")]
60489 #[cfg_attr(
60490 any(target_arch = "aarch64", target_arch = "arm64ec"),
60491 link_name = "llvm.aarch64.neon.rsubhn.v4i16"
60492 )]
60493 fn _vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t;
60494 }
60495 unsafe { _vrsubhn_s32(a, b) }
60496}
60497#[doc = "Rounding subtract returning high narrow"]
60498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"]
60499#[inline]
60500#[target_feature(enable = "neon")]
60501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60503#[cfg_attr(
60504 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60505 assert_instr(rsubhn)
60506)]
60507#[cfg_attr(
60508 not(target_arch = "arm"),
60509 stable(feature = "neon_intrinsics", since = "1.59.0")
60510)]
60511#[cfg_attr(
60512 target_arch = "arm",
60513 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60514)]
60515pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
60516 unsafe extern "unadjusted" {
60517 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")]
60518 #[cfg_attr(
60519 any(target_arch = "aarch64", target_arch = "arm64ec"),
60520 link_name = "llvm.aarch64.neon.rsubhn.v2i32"
60521 )]
60522 fn _vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t;
60523 }
60524 unsafe { _vrsubhn_s64(a, b) }
60525}
60526#[doc = "Rounding subtract returning high narrow"]
60527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
60528#[inline]
60529#[cfg(target_endian = "little")]
60530#[target_feature(enable = "neon")]
60531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60533#[cfg_attr(
60534 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60535 assert_instr(rsubhn)
60536)]
60537#[cfg_attr(
60538 not(target_arch = "arm"),
60539 stable(feature = "neon_intrinsics", since = "1.59.0")
60540)]
60541#[cfg_attr(
60542 target_arch = "arm",
60543 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60544)]
60545pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
60546 unsafe { transmute(vrsubhn_s16(transmute(a), transmute(b))) }
60547}
60548#[doc = "Rounding subtract returning high narrow"]
60549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
60550#[inline]
60551#[cfg(target_endian = "big")]
60552#[target_feature(enable = "neon")]
60553#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60554#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60555#[cfg_attr(
60556 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60557 assert_instr(rsubhn)
60558)]
60559#[cfg_attr(
60560 not(target_arch = "arm"),
60561 stable(feature = "neon_intrinsics", since = "1.59.0")
60562)]
60563#[cfg_attr(
60564 target_arch = "arm",
60565 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60566)]
60567pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
60568 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
60569 let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
60570 unsafe {
60571 let ret_val: uint8x8_t = transmute(vrsubhn_s16(transmute(a), transmute(b)));
60572 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
60573 }
60574}
60575#[doc = "Rounding subtract returning high narrow"]
60576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
60577#[inline]
60578#[cfg(target_endian = "little")]
60579#[target_feature(enable = "neon")]
60580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60581#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60582#[cfg_attr(
60583 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60584 assert_instr(rsubhn)
60585)]
60586#[cfg_attr(
60587 not(target_arch = "arm"),
60588 stable(feature = "neon_intrinsics", since = "1.59.0")
60589)]
60590#[cfg_attr(
60591 target_arch = "arm",
60592 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60593)]
60594pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
60595 unsafe { transmute(vrsubhn_s32(transmute(a), transmute(b))) }
60596}
60597#[doc = "Rounding subtract returning high narrow"]
60598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
60599#[inline]
60600#[cfg(target_endian = "big")]
60601#[target_feature(enable = "neon")]
60602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60603#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60604#[cfg_attr(
60605 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60606 assert_instr(rsubhn)
60607)]
60608#[cfg_attr(
60609 not(target_arch = "arm"),
60610 stable(feature = "neon_intrinsics", since = "1.59.0")
60611)]
60612#[cfg_attr(
60613 target_arch = "arm",
60614 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60615)]
60616pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
60617 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
60618 let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
60619 unsafe {
60620 let ret_val: uint16x4_t = transmute(vrsubhn_s32(transmute(a), transmute(b)));
60621 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
60622 }
60623}
60624#[doc = "Rounding subtract returning high narrow"]
60625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
60626#[inline]
60627#[cfg(target_endian = "little")]
60628#[target_feature(enable = "neon")]
60629#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60630#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60631#[cfg_attr(
60632 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60633 assert_instr(rsubhn)
60634)]
60635#[cfg_attr(
60636 not(target_arch = "arm"),
60637 stable(feature = "neon_intrinsics", since = "1.59.0")
60638)]
60639#[cfg_attr(
60640 target_arch = "arm",
60641 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60642)]
60643pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
60644 unsafe { transmute(vrsubhn_s64(transmute(a), transmute(b))) }
60645}
60646#[doc = "Rounding subtract returning high narrow"]
60647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
60648#[inline]
60649#[cfg(target_endian = "big")]
60650#[target_feature(enable = "neon")]
60651#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60652#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60653#[cfg_attr(
60654 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60655 assert_instr(rsubhn)
60656)]
60657#[cfg_attr(
60658 not(target_arch = "arm"),
60659 stable(feature = "neon_intrinsics", since = "1.59.0")
60660)]
60661#[cfg_attr(
60662 target_arch = "arm",
60663 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60664)]
60665pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
60666 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
60667 let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
60668 unsafe {
60669 let ret_val: uint32x2_t = transmute(vrsubhn_s64(transmute(a), transmute(b)));
60670 simd_shuffle!(ret_val, ret_val, [1, 0])
60671 }
60672}
60673#[doc = "Insert vector element from another vector element"]
60674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"]
60675#[inline]
60676#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60677#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60678#[cfg_attr(
60679 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60680 assert_instr(nop, LANE = 0)
60681)]
60682#[rustc_legacy_const_generics(2)]
60683#[target_feature(enable = "neon,fp16")]
60684#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60685pub fn vset_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> float16x4_t {
60686 static_assert_uimm_bits!(LANE, 2);
60687 unsafe { simd_insert!(b, LANE as u32, a) }
60688}
60689#[doc = "Insert vector element from another vector element"]
60690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"]
60691#[inline]
60692#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60693#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60694#[cfg_attr(
60695 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60696 assert_instr(nop, LANE = 0)
60697)]
60698#[rustc_legacy_const_generics(2)]
60699#[target_feature(enable = "neon,fp16")]
60700#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60701pub fn vsetq_lane_f16<const LANE: i32>(a: f16, b: float16x8_t) -> float16x8_t {
60702 static_assert_uimm_bits!(LANE, 3);
60703 unsafe { simd_insert!(b, LANE as u32, a) }
60704}
60705#[doc = "Insert vector element from another vector element"]
60706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"]
60707#[inline]
60708#[target_feature(enable = "neon")]
60709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60711#[cfg_attr(
60712 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60713 assert_instr(nop, LANE = 0)
60714)]
60715#[rustc_legacy_const_generics(2)]
60716#[cfg_attr(
60717 not(target_arch = "arm"),
60718 stable(feature = "neon_intrinsics", since = "1.59.0")
60719)]
60720#[cfg_attr(
60721 target_arch = "arm",
60722 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60723)]
60724pub fn vset_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> float32x2_t {
60725 static_assert_uimm_bits!(LANE, 1);
60726 unsafe { simd_insert!(b, LANE as u32, a) }
60727}
60728#[doc = "Insert vector element from another vector element"]
60729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"]
60730#[inline]
60731#[target_feature(enable = "neon")]
60732#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60733#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60734#[cfg_attr(
60735 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60736 assert_instr(nop, LANE = 0)
60737)]
60738#[rustc_legacy_const_generics(2)]
60739#[cfg_attr(
60740 not(target_arch = "arm"),
60741 stable(feature = "neon_intrinsics", since = "1.59.0")
60742)]
60743#[cfg_attr(
60744 target_arch = "arm",
60745 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60746)]
60747pub fn vsetq_lane_f32<const LANE: i32>(a: f32, b: float32x4_t) -> float32x4_t {
60748 static_assert_uimm_bits!(LANE, 2);
60749 unsafe { simd_insert!(b, LANE as u32, a) }
60750}
60751#[doc = "Insert vector element from another vector element"]
60752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"]
60753#[inline]
60754#[target_feature(enable = "neon")]
60755#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60756#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60757#[cfg_attr(
60758 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60759 assert_instr(nop, LANE = 0)
60760)]
60761#[rustc_legacy_const_generics(2)]
60762#[cfg_attr(
60763 not(target_arch = "arm"),
60764 stable(feature = "neon_intrinsics", since = "1.59.0")
60765)]
60766#[cfg_attr(
60767 target_arch = "arm",
60768 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60769)]
60770pub fn vset_lane_s8<const LANE: i32>(a: i8, b: int8x8_t) -> int8x8_t {
60771 static_assert_uimm_bits!(LANE, 3);
60772 unsafe { simd_insert!(b, LANE as u32, a) }
60773}
60774#[doc = "Insert vector element from another vector element"]
60775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"]
60776#[inline]
60777#[target_feature(enable = "neon")]
60778#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60779#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60780#[cfg_attr(
60781 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60782 assert_instr(nop, LANE = 0)
60783)]
60784#[rustc_legacy_const_generics(2)]
60785#[cfg_attr(
60786 not(target_arch = "arm"),
60787 stable(feature = "neon_intrinsics", since = "1.59.0")
60788)]
60789#[cfg_attr(
60790 target_arch = "arm",
60791 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60792)]
60793pub fn vsetq_lane_s8<const LANE: i32>(a: i8, b: int8x16_t) -> int8x16_t {
60794 static_assert_uimm_bits!(LANE, 4);
60795 unsafe { simd_insert!(b, LANE as u32, a) }
60796}
60797#[doc = "Insert vector element from another vector element"]
60798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"]
60799#[inline]
60800#[target_feature(enable = "neon")]
60801#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60802#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60803#[cfg_attr(
60804 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60805 assert_instr(nop, LANE = 0)
60806)]
60807#[rustc_legacy_const_generics(2)]
60808#[cfg_attr(
60809 not(target_arch = "arm"),
60810 stable(feature = "neon_intrinsics", since = "1.59.0")
60811)]
60812#[cfg_attr(
60813 target_arch = "arm",
60814 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60815)]
60816pub fn vset_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> int16x4_t {
60817 static_assert_uimm_bits!(LANE, 2);
60818 unsafe { simd_insert!(b, LANE as u32, a) }
60819}
60820#[doc = "Insert vector element from another vector element"]
60821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"]
60822#[inline]
60823#[target_feature(enable = "neon")]
60824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60825#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60826#[cfg_attr(
60827 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60828 assert_instr(nop, LANE = 0)
60829)]
60830#[rustc_legacy_const_generics(2)]
60831#[cfg_attr(
60832 not(target_arch = "arm"),
60833 stable(feature = "neon_intrinsics", since = "1.59.0")
60834)]
60835#[cfg_attr(
60836 target_arch = "arm",
60837 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60838)]
60839pub fn vsetq_lane_s16<const LANE: i32>(a: i16, b: int16x8_t) -> int16x8_t {
60840 static_assert_uimm_bits!(LANE, 3);
60841 unsafe { simd_insert!(b, LANE as u32, a) }
60842}
60843#[doc = "Insert vector element from another vector element"]
60844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"]
60845#[inline]
60846#[target_feature(enable = "neon")]
60847#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60848#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60849#[cfg_attr(
60850 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60851 assert_instr(nop, LANE = 0)
60852)]
60853#[rustc_legacy_const_generics(2)]
60854#[cfg_attr(
60855 not(target_arch = "arm"),
60856 stable(feature = "neon_intrinsics", since = "1.59.0")
60857)]
60858#[cfg_attr(
60859 target_arch = "arm",
60860 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60861)]
60862pub fn vset_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> int32x2_t {
60863 static_assert_uimm_bits!(LANE, 1);
60864 unsafe { simd_insert!(b, LANE as u32, a) }
60865}
60866#[doc = "Insert vector element from another vector element"]
60867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"]
60868#[inline]
60869#[target_feature(enable = "neon")]
60870#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60871#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60872#[cfg_attr(
60873 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60874 assert_instr(nop, LANE = 0)
60875)]
60876#[rustc_legacy_const_generics(2)]
60877#[cfg_attr(
60878 not(target_arch = "arm"),
60879 stable(feature = "neon_intrinsics", since = "1.59.0")
60880)]
60881#[cfg_attr(
60882 target_arch = "arm",
60883 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60884)]
60885pub fn vsetq_lane_s32<const LANE: i32>(a: i32, b: int32x4_t) -> int32x4_t {
60886 static_assert_uimm_bits!(LANE, 2);
60887 unsafe { simd_insert!(b, LANE as u32, a) }
60888}
60889#[doc = "Insert vector element from another vector element"]
60890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"]
60891#[inline]
60892#[target_feature(enable = "neon")]
60893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60894#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60895#[cfg_attr(
60896 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60897 assert_instr(nop, LANE = 0)
60898)]
60899#[rustc_legacy_const_generics(2)]
60900#[cfg_attr(
60901 not(target_arch = "arm"),
60902 stable(feature = "neon_intrinsics", since = "1.59.0")
60903)]
60904#[cfg_attr(
60905 target_arch = "arm",
60906 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60907)]
60908pub fn vsetq_lane_s64<const LANE: i32>(a: i64, b: int64x2_t) -> int64x2_t {
60909 static_assert_uimm_bits!(LANE, 1);
60910 unsafe { simd_insert!(b, LANE as u32, a) }
60911}
60912#[doc = "Insert vector element from another vector element"]
60913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"]
60914#[inline]
60915#[target_feature(enable = "neon")]
60916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60917#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60918#[cfg_attr(
60919 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60920 assert_instr(nop, LANE = 0)
60921)]
60922#[rustc_legacy_const_generics(2)]
60923#[cfg_attr(
60924 not(target_arch = "arm"),
60925 stable(feature = "neon_intrinsics", since = "1.59.0")
60926)]
60927#[cfg_attr(
60928 target_arch = "arm",
60929 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60930)]
60931pub fn vset_lane_u8<const LANE: i32>(a: u8, b: uint8x8_t) -> uint8x8_t {
60932 static_assert_uimm_bits!(LANE, 3);
60933 unsafe { simd_insert!(b, LANE as u32, a) }
60934}
60935#[doc = "Insert vector element from another vector element"]
60936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"]
60937#[inline]
60938#[target_feature(enable = "neon")]
60939#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60940#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60941#[cfg_attr(
60942 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60943 assert_instr(nop, LANE = 0)
60944)]
60945#[rustc_legacy_const_generics(2)]
60946#[cfg_attr(
60947 not(target_arch = "arm"),
60948 stable(feature = "neon_intrinsics", since = "1.59.0")
60949)]
60950#[cfg_attr(
60951 target_arch = "arm",
60952 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60953)]
60954pub fn vsetq_lane_u8<const LANE: i32>(a: u8, b: uint8x16_t) -> uint8x16_t {
60955 static_assert_uimm_bits!(LANE, 4);
60956 unsafe { simd_insert!(b, LANE as u32, a) }
60957}
60958#[doc = "Insert vector element from another vector element"]
60959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"]
60960#[inline]
60961#[target_feature(enable = "neon")]
60962#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60963#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60964#[cfg_attr(
60965 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60966 assert_instr(nop, LANE = 0)
60967)]
60968#[rustc_legacy_const_generics(2)]
60969#[cfg_attr(
60970 not(target_arch = "arm"),
60971 stable(feature = "neon_intrinsics", since = "1.59.0")
60972)]
60973#[cfg_attr(
60974 target_arch = "arm",
60975 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60976)]
60977pub fn vset_lane_u16<const LANE: i32>(a: u16, b: uint16x4_t) -> uint16x4_t {
60978 static_assert_uimm_bits!(LANE, 2);
60979 unsafe { simd_insert!(b, LANE as u32, a) }
60980}
60981#[doc = "Insert vector element from another vector element"]
60982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"]
60983#[inline]
60984#[target_feature(enable = "neon")]
60985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60986#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60987#[cfg_attr(
60988 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60989 assert_instr(nop, LANE = 0)
60990)]
60991#[rustc_legacy_const_generics(2)]
60992#[cfg_attr(
60993 not(target_arch = "arm"),
60994 stable(feature = "neon_intrinsics", since = "1.59.0")
60995)]
60996#[cfg_attr(
60997 target_arch = "arm",
60998 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60999)]
61000pub fn vsetq_lane_u16<const LANE: i32>(a: u16, b: uint16x8_t) -> uint16x8_t {
61001 static_assert_uimm_bits!(LANE, 3);
61002 unsafe { simd_insert!(b, LANE as u32, a) }
61003}
61004#[doc = "Insert vector element from another vector element"]
61005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"]
61006#[inline]
61007#[target_feature(enable = "neon")]
61008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61009#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61010#[cfg_attr(
61011 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61012 assert_instr(nop, LANE = 0)
61013)]
61014#[rustc_legacy_const_generics(2)]
61015#[cfg_attr(
61016 not(target_arch = "arm"),
61017 stable(feature = "neon_intrinsics", since = "1.59.0")
61018)]
61019#[cfg_attr(
61020 target_arch = "arm",
61021 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61022)]
61023pub fn vset_lane_u32<const LANE: i32>(a: u32, b: uint32x2_t) -> uint32x2_t {
61024 static_assert_uimm_bits!(LANE, 1);
61025 unsafe { simd_insert!(b, LANE as u32, a) }
61026}
61027#[doc = "Insert vector element from another vector element"]
61028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"]
61029#[inline]
61030#[target_feature(enable = "neon")]
61031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61033#[cfg_attr(
61034 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61035 assert_instr(nop, LANE = 0)
61036)]
61037#[rustc_legacy_const_generics(2)]
61038#[cfg_attr(
61039 not(target_arch = "arm"),
61040 stable(feature = "neon_intrinsics", since = "1.59.0")
61041)]
61042#[cfg_attr(
61043 target_arch = "arm",
61044 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61045)]
61046pub fn vsetq_lane_u32<const LANE: i32>(a: u32, b: uint32x4_t) -> uint32x4_t {
61047 static_assert_uimm_bits!(LANE, 2);
61048 unsafe { simd_insert!(b, LANE as u32, a) }
61049}
61050#[doc = "Insert vector element from another vector element"]
61051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"]
61052#[inline]
61053#[target_feature(enable = "neon")]
61054#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61055#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61056#[cfg_attr(
61057 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61058 assert_instr(nop, LANE = 0)
61059)]
61060#[rustc_legacy_const_generics(2)]
61061#[cfg_attr(
61062 not(target_arch = "arm"),
61063 stable(feature = "neon_intrinsics", since = "1.59.0")
61064)]
61065#[cfg_attr(
61066 target_arch = "arm",
61067 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61068)]
61069pub fn vsetq_lane_u64<const LANE: i32>(a: u64, b: uint64x2_t) -> uint64x2_t {
61070 static_assert_uimm_bits!(LANE, 1);
61071 unsafe { simd_insert!(b, LANE as u32, a) }
61072}
61073#[doc = "Insert vector element from another vector element"]
61074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"]
61075#[inline]
61076#[target_feature(enable = "neon")]
61077#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61078#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61079#[cfg_attr(
61080 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61081 assert_instr(nop, LANE = 0)
61082)]
61083#[rustc_legacy_const_generics(2)]
61084#[cfg_attr(
61085 not(target_arch = "arm"),
61086 stable(feature = "neon_intrinsics", since = "1.59.0")
61087)]
61088#[cfg_attr(
61089 target_arch = "arm",
61090 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61091)]
61092pub fn vset_lane_p8<const LANE: i32>(a: p8, b: poly8x8_t) -> poly8x8_t {
61093 static_assert_uimm_bits!(LANE, 3);
61094 unsafe { simd_insert!(b, LANE as u32, a) }
61095}
61096#[doc = "Insert vector element from another vector element"]
61097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"]
61098#[inline]
61099#[target_feature(enable = "neon")]
61100#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61101#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61102#[cfg_attr(
61103 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61104 assert_instr(nop, LANE = 0)
61105)]
61106#[rustc_legacy_const_generics(2)]
61107#[cfg_attr(
61108 not(target_arch = "arm"),
61109 stable(feature = "neon_intrinsics", since = "1.59.0")
61110)]
61111#[cfg_attr(
61112 target_arch = "arm",
61113 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61114)]
61115pub fn vsetq_lane_p8<const LANE: i32>(a: p8, b: poly8x16_t) -> poly8x16_t {
61116 static_assert_uimm_bits!(LANE, 4);
61117 unsafe { simd_insert!(b, LANE as u32, a) }
61118}
61119#[doc = "Insert vector element from another vector element"]
61120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"]
61121#[inline]
61122#[target_feature(enable = "neon")]
61123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61125#[cfg_attr(
61126 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61127 assert_instr(nop, LANE = 0)
61128)]
61129#[rustc_legacy_const_generics(2)]
61130#[cfg_attr(
61131 not(target_arch = "arm"),
61132 stable(feature = "neon_intrinsics", since = "1.59.0")
61133)]
61134#[cfg_attr(
61135 target_arch = "arm",
61136 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61137)]
61138pub fn vset_lane_p16<const LANE: i32>(a: p16, b: poly16x4_t) -> poly16x4_t {
61139 static_assert_uimm_bits!(LANE, 2);
61140 unsafe { simd_insert!(b, LANE as u32, a) }
61141}
61142#[doc = "Insert vector element from another vector element"]
61143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"]
61144#[inline]
61145#[target_feature(enable = "neon")]
61146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61147#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61148#[cfg_attr(
61149 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61150 assert_instr(nop, LANE = 0)
61151)]
61152#[rustc_legacy_const_generics(2)]
61153#[cfg_attr(
61154 not(target_arch = "arm"),
61155 stable(feature = "neon_intrinsics", since = "1.59.0")
61156)]
61157#[cfg_attr(
61158 target_arch = "arm",
61159 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61160)]
61161pub fn vsetq_lane_p16<const LANE: i32>(a: p16, b: poly16x8_t) -> poly16x8_t {
61162 static_assert_uimm_bits!(LANE, 3);
61163 unsafe { simd_insert!(b, LANE as u32, a) }
61164}
61165#[doc = "Insert vector element from another vector element"]
61166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"]
61167#[inline]
61168#[target_feature(enable = "neon,aes")]
61169#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61171#[cfg_attr(
61172 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61173 assert_instr(nop, LANE = 0)
61174)]
61175#[rustc_legacy_const_generics(2)]
61176#[cfg_attr(
61177 not(target_arch = "arm"),
61178 stable(feature = "neon_intrinsics", since = "1.59.0")
61179)]
61180#[cfg_attr(
61181 target_arch = "arm",
61182 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61183)]
61184pub fn vset_lane_p64<const LANE: i32>(a: p64, b: poly64x1_t) -> poly64x1_t {
61185 static_assert!(LANE == 0);
61186 unsafe { simd_insert!(b, LANE as u32, a) }
61187}
61188#[doc = "Insert vector element from another vector element"]
61189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"]
61190#[inline]
61191#[target_feature(enable = "neon")]
61192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61193#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61194#[cfg_attr(
61195 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61196 assert_instr(nop, LANE = 0)
61197)]
61198#[rustc_legacy_const_generics(2)]
61199#[cfg_attr(
61200 not(target_arch = "arm"),
61201 stable(feature = "neon_intrinsics", since = "1.59.0")
61202)]
61203#[cfg_attr(
61204 target_arch = "arm",
61205 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61206)]
61207pub fn vset_lane_s64<const LANE: i32>(a: i64, b: int64x1_t) -> int64x1_t {
61208 static_assert!(LANE == 0);
61209 unsafe { simd_insert!(b, LANE as u32, a) }
61210}
61211#[doc = "Insert vector element from another vector element"]
61212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"]
61213#[inline]
61214#[target_feature(enable = "neon")]
61215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61216#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61217#[cfg_attr(
61218 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61219 assert_instr(nop, LANE = 0)
61220)]
61221#[rustc_legacy_const_generics(2)]
61222#[cfg_attr(
61223 not(target_arch = "arm"),
61224 stable(feature = "neon_intrinsics", since = "1.59.0")
61225)]
61226#[cfg_attr(
61227 target_arch = "arm",
61228 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61229)]
61230pub fn vset_lane_u64<const LANE: i32>(a: u64, b: uint64x1_t) -> uint64x1_t {
61231 static_assert!(LANE == 0);
61232 unsafe { simd_insert!(b, LANE as u32, a) }
61233}
61234#[doc = "Insert vector element from another vector element"]
61235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"]
61236#[inline]
61237#[target_feature(enable = "neon,aes")]
61238#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61239#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
61240#[cfg_attr(
61241 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61242 assert_instr(nop, LANE = 0)
61243)]
61244#[rustc_legacy_const_generics(2)]
61245#[cfg_attr(
61246 not(target_arch = "arm"),
61247 stable(feature = "neon_intrinsics", since = "1.59.0")
61248)]
61249#[cfg_attr(
61250 target_arch = "arm",
61251 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61252)]
61253pub fn vsetq_lane_p64<const LANE: i32>(a: p64, b: poly64x2_t) -> poly64x2_t {
61254 static_assert_uimm_bits!(LANE, 1);
61255 unsafe { simd_insert!(b, LANE as u32, a) }
61256}
61257#[doc = "SHA1 hash update accelerator, choose."]
61258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"]
61259#[inline]
61260#[target_feature(enable = "sha2")]
61261#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61262#[cfg_attr(test, assert_instr(sha1c))]
61263#[cfg_attr(
61264 target_arch = "arm",
61265 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61266)]
61267#[cfg_attr(
61268 not(target_arch = "arm"),
61269 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61270)]
61271pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
61272 unsafe extern "unadjusted" {
61273 #[cfg_attr(
61274 any(target_arch = "aarch64", target_arch = "arm64ec"),
61275 link_name = "llvm.aarch64.crypto.sha1c"
61276 )]
61277 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")]
61278 fn _vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
61279 }
61280 unsafe { _vsha1cq_u32(hash_abcd, hash_e, wk) }
61281}
61282#[doc = "SHA1 fixed rotate."]
61283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"]
61284#[inline]
61285#[target_feature(enable = "sha2")]
61286#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61287#[cfg_attr(test, assert_instr(sha1h))]
61288#[cfg_attr(
61289 target_arch = "arm",
61290 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61291)]
61292#[cfg_attr(
61293 not(target_arch = "arm"),
61294 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61295)]
61296pub fn vsha1h_u32(hash_e: u32) -> u32 {
61297 unsafe extern "unadjusted" {
61298 #[cfg_attr(
61299 any(target_arch = "aarch64", target_arch = "arm64ec"),
61300 link_name = "llvm.aarch64.crypto.sha1h"
61301 )]
61302 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")]
61303 fn _vsha1h_u32(hash_e: u32) -> u32;
61304 }
61305 unsafe { _vsha1h_u32(hash_e) }
61306}
61307#[doc = "SHA1 hash update accelerator, majority"]
61308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"]
61309#[inline]
61310#[target_feature(enable = "sha2")]
61311#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61312#[cfg_attr(test, assert_instr(sha1m))]
61313#[cfg_attr(
61314 target_arch = "arm",
61315 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61316)]
61317#[cfg_attr(
61318 not(target_arch = "arm"),
61319 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61320)]
61321pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
61322 unsafe extern "unadjusted" {
61323 #[cfg_attr(
61324 any(target_arch = "aarch64", target_arch = "arm64ec"),
61325 link_name = "llvm.aarch64.crypto.sha1m"
61326 )]
61327 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")]
61328 fn _vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
61329 }
61330 unsafe { _vsha1mq_u32(hash_abcd, hash_e, wk) }
61331}
61332#[doc = "SHA1 hash update accelerator, parity"]
61333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"]
61334#[inline]
61335#[target_feature(enable = "sha2")]
61336#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61337#[cfg_attr(test, assert_instr(sha1p))]
61338#[cfg_attr(
61339 target_arch = "arm",
61340 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61341)]
61342#[cfg_attr(
61343 not(target_arch = "arm"),
61344 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61345)]
61346pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
61347 unsafe extern "unadjusted" {
61348 #[cfg_attr(
61349 any(target_arch = "aarch64", target_arch = "arm64ec"),
61350 link_name = "llvm.aarch64.crypto.sha1p"
61351 )]
61352 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")]
61353 fn _vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
61354 }
61355 unsafe { _vsha1pq_u32(hash_abcd, hash_e, wk) }
61356}
61357#[doc = "SHA1 schedule update accelerator, first part."]
61358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"]
61359#[inline]
61360#[target_feature(enable = "sha2")]
61361#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61362#[cfg_attr(test, assert_instr(sha1su0))]
61363#[cfg_attr(
61364 target_arch = "arm",
61365 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61366)]
61367#[cfg_attr(
61368 not(target_arch = "arm"),
61369 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61370)]
61371pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
61372 unsafe extern "unadjusted" {
61373 #[cfg_attr(
61374 any(target_arch = "aarch64", target_arch = "arm64ec"),
61375 link_name = "llvm.aarch64.crypto.sha1su0"
61376 )]
61377 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")]
61378 fn _vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t;
61379 }
61380 unsafe { _vsha1su0q_u32(w0_3, w4_7, w8_11) }
61381}
61382#[doc = "SHA1 schedule update accelerator, second part."]
61383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"]
61384#[inline]
61385#[target_feature(enable = "sha2")]
61386#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61387#[cfg_attr(test, assert_instr(sha1su1))]
61388#[cfg_attr(
61389 target_arch = "arm",
61390 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61391)]
61392#[cfg_attr(
61393 not(target_arch = "arm"),
61394 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61395)]
61396pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
61397 unsafe extern "unadjusted" {
61398 #[cfg_attr(
61399 any(target_arch = "aarch64", target_arch = "arm64ec"),
61400 link_name = "llvm.aarch64.crypto.sha1su1"
61401 )]
61402 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")]
61403 fn _vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
61404 }
61405 unsafe { _vsha1su1q_u32(tw0_3, w12_15) }
61406}
61407#[doc = "SHA1 schedule update accelerator, upper part."]
61408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"]
61409#[inline]
61410#[target_feature(enable = "sha2")]
61411#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61412#[cfg_attr(test, assert_instr(sha256h2))]
61413#[cfg_attr(
61414 target_arch = "arm",
61415 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61416)]
61417#[cfg_attr(
61418 not(target_arch = "arm"),
61419 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61420)]
61421pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t {
61422 unsafe extern "unadjusted" {
61423 #[cfg_attr(
61424 any(target_arch = "aarch64", target_arch = "arm64ec"),
61425 link_name = "llvm.aarch64.crypto.sha256h2"
61426 )]
61427 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")]
61428 fn _vsha256h2q_u32(
61429 hash_abcd: uint32x4_t,
61430 hash_efgh: uint32x4_t,
61431 wk: uint32x4_t,
61432 ) -> uint32x4_t;
61433 }
61434 unsafe { _vsha256h2q_u32(hash_abcd, hash_efgh, wk) }
61435}
61436#[doc = "SHA1 schedule update accelerator, first part."]
61437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"]
61438#[inline]
61439#[target_feature(enable = "sha2")]
61440#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61441#[cfg_attr(test, assert_instr(sha256h))]
61442#[cfg_attr(
61443 target_arch = "arm",
61444 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61445)]
61446#[cfg_attr(
61447 not(target_arch = "arm"),
61448 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61449)]
61450pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t {
61451 unsafe extern "unadjusted" {
61452 #[cfg_attr(
61453 any(target_arch = "aarch64", target_arch = "arm64ec"),
61454 link_name = "llvm.aarch64.crypto.sha256h"
61455 )]
61456 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")]
61457 fn _vsha256hq_u32(
61458 hash_abcd: uint32x4_t,
61459 hash_efgh: uint32x4_t,
61460 wk: uint32x4_t,
61461 ) -> uint32x4_t;
61462 }
61463 unsafe { _vsha256hq_u32(hash_abcd, hash_efgh, wk) }
61464}
61465#[doc = "SHA256 schedule update accelerator, first part."]
61466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"]
61467#[inline]
61468#[target_feature(enable = "sha2")]
61469#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61470#[cfg_attr(test, assert_instr(sha256su0))]
61471#[cfg_attr(
61472 target_arch = "arm",
61473 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61474)]
61475#[cfg_attr(
61476 not(target_arch = "arm"),
61477 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61478)]
61479pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
61480 unsafe extern "unadjusted" {
61481 #[cfg_attr(
61482 any(target_arch = "aarch64", target_arch = "arm64ec"),
61483 link_name = "llvm.aarch64.crypto.sha256su0"
61484 )]
61485 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")]
61486 fn _vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t;
61487 }
61488 unsafe { _vsha256su0q_u32(w0_3, w4_7) }
61489}
61490#[doc = "SHA256 schedule update accelerator, second part."]
61491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"]
61492#[inline]
61493#[target_feature(enable = "sha2")]
61494#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61495#[cfg_attr(test, assert_instr(sha256su1))]
61496#[cfg_attr(
61497 target_arch = "arm",
61498 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61499)]
61500#[cfg_attr(
61501 not(target_arch = "arm"),
61502 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61503)]
61504pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
61505 unsafe extern "unadjusted" {
61506 #[cfg_attr(
61507 any(target_arch = "aarch64", target_arch = "arm64ec"),
61508 link_name = "llvm.aarch64.crypto.sha256su1"
61509 )]
61510 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")]
61511 fn _vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t)
61512 -> uint32x4_t;
61513 }
61514 unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) }
61515}
61516#[doc = "Shift Right and Insert (immediate)"]
61517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v16i8)"]
61518#[inline]
61519#[target_feature(enable = "neon")]
61520#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61521fn vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
61522 unsafe extern "unadjusted" {
61523 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")]
61524 fn _vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t;
61525 }
61526 unsafe { _vshiftins_v16i8(a, b, c) }
61527}
61528#[doc = "Shift Right and Insert (immediate)"]
61529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v1i64)"]
61530#[inline]
61531#[target_feature(enable = "neon")]
61532#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61533fn vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
61534 unsafe extern "unadjusted" {
61535 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")]
61536 fn _vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t;
61537 }
61538 unsafe { _vshiftins_v1i64(a, b, c) }
61539}
61540#[doc = "Shift Right and Insert (immediate)"]
61541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i32)"]
61542#[inline]
61543#[target_feature(enable = "neon")]
61544#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61545fn vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
61546 unsafe extern "unadjusted" {
61547 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")]
61548 fn _vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t;
61549 }
61550 unsafe { _vshiftins_v2i32(a, b, c) }
61551}
61552#[doc = "Shift Right and Insert (immediate)"]
61553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i64)"]
61554#[inline]
61555#[target_feature(enable = "neon")]
61556#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61557fn vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
61558 unsafe extern "unadjusted" {
61559 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")]
61560 fn _vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t;
61561 }
61562 unsafe { _vshiftins_v2i64(a, b, c) }
61563}
61564#[doc = "Shift Right and Insert (immediate)"]
61565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i16)"]
61566#[inline]
61567#[target_feature(enable = "neon")]
61568#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61569fn vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
61570 unsafe extern "unadjusted" {
61571 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")]
61572 fn _vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t;
61573 }
61574 unsafe { _vshiftins_v4i16(a, b, c) }
61575}
61576#[doc = "Shift Right and Insert (immediate)"]
61577#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i32)"]
61578#[inline]
61579#[target_feature(enable = "neon")]
61580#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61581fn vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
61582 unsafe extern "unadjusted" {
61583 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")]
61584 fn _vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
61585 }
61586 unsafe { _vshiftins_v4i32(a, b, c) }
61587}
61588#[doc = "Shift Right and Insert (immediate)"]
61589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i16)"]
61590#[inline]
61591#[target_feature(enable = "neon")]
61592#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61593fn vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
61594 unsafe extern "unadjusted" {
61595 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")]
61596 fn _vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
61597 }
61598 unsafe { _vshiftins_v8i16(a, b, c) }
61599}
61600#[doc = "Shift Right and Insert (immediate)"]
61601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i8)"]
61602#[inline]
61603#[target_feature(enable = "neon")]
61604#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61605fn vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
61606 unsafe extern "unadjusted" {
61607 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")]
61608 fn _vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
61609 }
61610 unsafe { _vshiftins_v8i8(a, b, c) }
61611}
61612#[doc = "Shift left"]
61613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"]
61614#[inline]
61615#[target_feature(enable = "neon")]
61616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61618#[cfg_attr(
61619 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61620 assert_instr(shl, N = 2)
61621)]
61622#[rustc_legacy_const_generics(1)]
61623#[cfg_attr(
61624 not(target_arch = "arm"),
61625 stable(feature = "neon_intrinsics", since = "1.59.0")
61626)]
61627#[cfg_attr(
61628 target_arch = "arm",
61629 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61630)]
61631pub fn vshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
61632 static_assert_uimm_bits!(N, 3);
61633 unsafe { simd_shl(a, vdup_n_s8(N as _)) }
61634}
61635#[doc = "Shift left"]
61636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"]
61637#[inline]
61638#[target_feature(enable = "neon")]
61639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61640#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61641#[cfg_attr(
61642 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61643 assert_instr(shl, N = 2)
61644)]
61645#[rustc_legacy_const_generics(1)]
61646#[cfg_attr(
61647 not(target_arch = "arm"),
61648 stable(feature = "neon_intrinsics", since = "1.59.0")
61649)]
61650#[cfg_attr(
61651 target_arch = "arm",
61652 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61653)]
61654pub fn vshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
61655 static_assert_uimm_bits!(N, 3);
61656 unsafe { simd_shl(a, vdupq_n_s8(N as _)) }
61657}
61658#[doc = "Shift left"]
61659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"]
61660#[inline]
61661#[target_feature(enable = "neon")]
61662#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61663#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61664#[cfg_attr(
61665 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61666 assert_instr(shl, N = 2)
61667)]
61668#[rustc_legacy_const_generics(1)]
61669#[cfg_attr(
61670 not(target_arch = "arm"),
61671 stable(feature = "neon_intrinsics", since = "1.59.0")
61672)]
61673#[cfg_attr(
61674 target_arch = "arm",
61675 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61676)]
61677pub fn vshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
61678 static_assert_uimm_bits!(N, 4);
61679 unsafe { simd_shl(a, vdup_n_s16(N as _)) }
61680}
61681#[doc = "Shift left"]
61682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"]
61683#[inline]
61684#[target_feature(enable = "neon")]
61685#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61686#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61687#[cfg_attr(
61688 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61689 assert_instr(shl, N = 2)
61690)]
61691#[rustc_legacy_const_generics(1)]
61692#[cfg_attr(
61693 not(target_arch = "arm"),
61694 stable(feature = "neon_intrinsics", since = "1.59.0")
61695)]
61696#[cfg_attr(
61697 target_arch = "arm",
61698 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61699)]
61700pub fn vshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
61701 static_assert_uimm_bits!(N, 4);
61702 unsafe { simd_shl(a, vdupq_n_s16(N as _)) }
61703}
61704#[doc = "Shift left"]
61705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"]
61706#[inline]
61707#[target_feature(enable = "neon")]
61708#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61709#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61710#[cfg_attr(
61711 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61712 assert_instr(shl, N = 2)
61713)]
61714#[rustc_legacy_const_generics(1)]
61715#[cfg_attr(
61716 not(target_arch = "arm"),
61717 stable(feature = "neon_intrinsics", since = "1.59.0")
61718)]
61719#[cfg_attr(
61720 target_arch = "arm",
61721 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61722)]
61723pub fn vshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
61724 static_assert_uimm_bits!(N, 5);
61725 unsafe { simd_shl(a, vdup_n_s32(N as _)) }
61726}
61727#[doc = "Shift left"]
61728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"]
61729#[inline]
61730#[target_feature(enable = "neon")]
61731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61733#[cfg_attr(
61734 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61735 assert_instr(shl, N = 2)
61736)]
61737#[rustc_legacy_const_generics(1)]
61738#[cfg_attr(
61739 not(target_arch = "arm"),
61740 stable(feature = "neon_intrinsics", since = "1.59.0")
61741)]
61742#[cfg_attr(
61743 target_arch = "arm",
61744 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61745)]
61746pub fn vshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
61747 static_assert_uimm_bits!(N, 5);
61748 unsafe { simd_shl(a, vdupq_n_s32(N as _)) }
61749}
61750#[doc = "Shift left"]
61751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"]
61752#[inline]
61753#[target_feature(enable = "neon")]
61754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61755#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61756#[cfg_attr(
61757 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61758 assert_instr(shl, N = 2)
61759)]
61760#[rustc_legacy_const_generics(1)]
61761#[cfg_attr(
61762 not(target_arch = "arm"),
61763 stable(feature = "neon_intrinsics", since = "1.59.0")
61764)]
61765#[cfg_attr(
61766 target_arch = "arm",
61767 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61768)]
61769pub fn vshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
61770 static_assert_uimm_bits!(N, 6);
61771 unsafe { simd_shl(a, vdup_n_s64(N as _)) }
61772}
61773#[doc = "Shift left"]
61774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"]
61775#[inline]
61776#[target_feature(enable = "neon")]
61777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61778#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61779#[cfg_attr(
61780 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61781 assert_instr(shl, N = 2)
61782)]
61783#[rustc_legacy_const_generics(1)]
61784#[cfg_attr(
61785 not(target_arch = "arm"),
61786 stable(feature = "neon_intrinsics", since = "1.59.0")
61787)]
61788#[cfg_attr(
61789 target_arch = "arm",
61790 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61791)]
61792pub fn vshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
61793 static_assert_uimm_bits!(N, 6);
61794 unsafe { simd_shl(a, vdupq_n_s64(N as _)) }
61795}
61796#[doc = "Shift left"]
61797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"]
61798#[inline]
61799#[target_feature(enable = "neon")]
61800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61801#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61802#[cfg_attr(
61803 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61804 assert_instr(shl, N = 2)
61805)]
61806#[rustc_legacy_const_generics(1)]
61807#[cfg_attr(
61808 not(target_arch = "arm"),
61809 stable(feature = "neon_intrinsics", since = "1.59.0")
61810)]
61811#[cfg_attr(
61812 target_arch = "arm",
61813 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61814)]
61815pub fn vshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
61816 static_assert_uimm_bits!(N, 3);
61817 unsafe { simd_shl(a, vdup_n_u8(N as _)) }
61818}
61819#[doc = "Shift left"]
61820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"]
61821#[inline]
61822#[target_feature(enable = "neon")]
61823#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61824#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61825#[cfg_attr(
61826 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61827 assert_instr(shl, N = 2)
61828)]
61829#[rustc_legacy_const_generics(1)]
61830#[cfg_attr(
61831 not(target_arch = "arm"),
61832 stable(feature = "neon_intrinsics", since = "1.59.0")
61833)]
61834#[cfg_attr(
61835 target_arch = "arm",
61836 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61837)]
61838pub fn vshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
61839 static_assert_uimm_bits!(N, 3);
61840 unsafe { simd_shl(a, vdupq_n_u8(N as _)) }
61841}
61842#[doc = "Shift left"]
61843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"]
61844#[inline]
61845#[target_feature(enable = "neon")]
61846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61847#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61848#[cfg_attr(
61849 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61850 assert_instr(shl, N = 2)
61851)]
61852#[rustc_legacy_const_generics(1)]
61853#[cfg_attr(
61854 not(target_arch = "arm"),
61855 stable(feature = "neon_intrinsics", since = "1.59.0")
61856)]
61857#[cfg_attr(
61858 target_arch = "arm",
61859 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61860)]
61861pub fn vshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
61862 static_assert_uimm_bits!(N, 4);
61863 unsafe { simd_shl(a, vdup_n_u16(N as _)) }
61864}
61865#[doc = "Shift left"]
61866#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"]
61867#[inline]
61868#[target_feature(enable = "neon")]
61869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61870#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61871#[cfg_attr(
61872 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61873 assert_instr(shl, N = 2)
61874)]
61875#[rustc_legacy_const_generics(1)]
61876#[cfg_attr(
61877 not(target_arch = "arm"),
61878 stable(feature = "neon_intrinsics", since = "1.59.0")
61879)]
61880#[cfg_attr(
61881 target_arch = "arm",
61882 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61883)]
61884pub fn vshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
61885 static_assert_uimm_bits!(N, 4);
61886 unsafe { simd_shl(a, vdupq_n_u16(N as _)) }
61887}
61888#[doc = "Shift left"]
61889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"]
61890#[inline]
61891#[target_feature(enable = "neon")]
61892#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61893#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61894#[cfg_attr(
61895 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61896 assert_instr(shl, N = 2)
61897)]
61898#[rustc_legacy_const_generics(1)]
61899#[cfg_attr(
61900 not(target_arch = "arm"),
61901 stable(feature = "neon_intrinsics", since = "1.59.0")
61902)]
61903#[cfg_attr(
61904 target_arch = "arm",
61905 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61906)]
61907pub fn vshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
61908 static_assert_uimm_bits!(N, 5);
61909 unsafe { simd_shl(a, vdup_n_u32(N as _)) }
61910}
61911#[doc = "Shift left"]
61912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"]
61913#[inline]
61914#[target_feature(enable = "neon")]
61915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61917#[cfg_attr(
61918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61919 assert_instr(shl, N = 2)
61920)]
61921#[rustc_legacy_const_generics(1)]
61922#[cfg_attr(
61923 not(target_arch = "arm"),
61924 stable(feature = "neon_intrinsics", since = "1.59.0")
61925)]
61926#[cfg_attr(
61927 target_arch = "arm",
61928 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61929)]
61930pub fn vshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
61931 static_assert_uimm_bits!(N, 5);
61932 unsafe { simd_shl(a, vdupq_n_u32(N as _)) }
61933}
61934#[doc = "Shift left"]
61935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"]
61936#[inline]
61937#[target_feature(enable = "neon")]
61938#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61939#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61940#[cfg_attr(
61941 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61942 assert_instr(shl, N = 2)
61943)]
61944#[rustc_legacy_const_generics(1)]
61945#[cfg_attr(
61946 not(target_arch = "arm"),
61947 stable(feature = "neon_intrinsics", since = "1.59.0")
61948)]
61949#[cfg_attr(
61950 target_arch = "arm",
61951 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61952)]
61953pub fn vshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
61954 static_assert_uimm_bits!(N, 6);
61955 unsafe { simd_shl(a, vdup_n_u64(N as _)) }
61956}
61957#[doc = "Shift left"]
61958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"]
61959#[inline]
61960#[target_feature(enable = "neon")]
61961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61962#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61963#[cfg_attr(
61964 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61965 assert_instr(shl, N = 2)
61966)]
61967#[rustc_legacy_const_generics(1)]
61968#[cfg_attr(
61969 not(target_arch = "arm"),
61970 stable(feature = "neon_intrinsics", since = "1.59.0")
61971)]
61972#[cfg_attr(
61973 target_arch = "arm",
61974 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61975)]
61976pub fn vshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
61977 static_assert_uimm_bits!(N, 6);
61978 unsafe { simd_shl(a, vdupq_n_u64(N as _)) }
61979}
61980#[doc = "Signed Shift left"]
61981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"]
61982#[inline]
61983#[target_feature(enable = "neon")]
61984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61986#[cfg_attr(
61987 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61988 assert_instr(sshl)
61989)]
61990#[cfg_attr(
61991 not(target_arch = "arm"),
61992 stable(feature = "neon_intrinsics", since = "1.59.0")
61993)]
61994#[cfg_attr(
61995 target_arch = "arm",
61996 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61997)]
61998pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
61999 unsafe extern "unadjusted" {
62000 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i8")]
62001 #[cfg_attr(
62002 any(target_arch = "aarch64", target_arch = "arm64ec"),
62003 link_name = "llvm.aarch64.neon.sshl.v8i8"
62004 )]
62005 fn _vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
62006 }
62007 unsafe { _vshl_s8(a, b) }
62008}
62009#[doc = "Signed Shift left"]
62010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"]
62011#[inline]
62012#[target_feature(enable = "neon")]
62013#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62014#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62015#[cfg_attr(
62016 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62017 assert_instr(sshl)
62018)]
62019#[cfg_attr(
62020 not(target_arch = "arm"),
62021 stable(feature = "neon_intrinsics", since = "1.59.0")
62022)]
62023#[cfg_attr(
62024 target_arch = "arm",
62025 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62026)]
62027pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
62028 unsafe extern "unadjusted" {
62029 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v16i8")]
62030 #[cfg_attr(
62031 any(target_arch = "aarch64", target_arch = "arm64ec"),
62032 link_name = "llvm.aarch64.neon.sshl.v16i8"
62033 )]
62034 fn _vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
62035 }
62036 unsafe { _vshlq_s8(a, b) }
62037}
62038#[doc = "Signed Shift left"]
62039#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"]
62040#[inline]
62041#[target_feature(enable = "neon")]
62042#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62043#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62044#[cfg_attr(
62045 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62046 assert_instr(sshl)
62047)]
62048#[cfg_attr(
62049 not(target_arch = "arm"),
62050 stable(feature = "neon_intrinsics", since = "1.59.0")
62051)]
62052#[cfg_attr(
62053 target_arch = "arm",
62054 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62055)]
62056pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
62057 unsafe extern "unadjusted" {
62058 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i16")]
62059 #[cfg_attr(
62060 any(target_arch = "aarch64", target_arch = "arm64ec"),
62061 link_name = "llvm.aarch64.neon.sshl.v4i16"
62062 )]
62063 fn _vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
62064 }
62065 unsafe { _vshl_s16(a, b) }
62066}
62067#[doc = "Signed Shift left"]
62068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"]
62069#[inline]
62070#[target_feature(enable = "neon")]
62071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62072#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62073#[cfg_attr(
62074 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62075 assert_instr(sshl)
62076)]
62077#[cfg_attr(
62078 not(target_arch = "arm"),
62079 stable(feature = "neon_intrinsics", since = "1.59.0")
62080)]
62081#[cfg_attr(
62082 target_arch = "arm",
62083 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62084)]
62085pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
62086 unsafe extern "unadjusted" {
62087 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i16")]
62088 #[cfg_attr(
62089 any(target_arch = "aarch64", target_arch = "arm64ec"),
62090 link_name = "llvm.aarch64.neon.sshl.v8i16"
62091 )]
62092 fn _vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
62093 }
62094 unsafe { _vshlq_s16(a, b) }
62095}
62096#[doc = "Signed Shift left"]
62097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"]
62098#[inline]
62099#[target_feature(enable = "neon")]
62100#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62101#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62102#[cfg_attr(
62103 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62104 assert_instr(sshl)
62105)]
62106#[cfg_attr(
62107 not(target_arch = "arm"),
62108 stable(feature = "neon_intrinsics", since = "1.59.0")
62109)]
62110#[cfg_attr(
62111 target_arch = "arm",
62112 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62113)]
62114pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
62115 unsafe extern "unadjusted" {
62116 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i32")]
62117 #[cfg_attr(
62118 any(target_arch = "aarch64", target_arch = "arm64ec"),
62119 link_name = "llvm.aarch64.neon.sshl.v2i32"
62120 )]
62121 fn _vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
62122 }
62123 unsafe { _vshl_s32(a, b) }
62124}
62125#[doc = "Signed Shift left"]
62126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"]
62127#[inline]
62128#[target_feature(enable = "neon")]
62129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62130#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62131#[cfg_attr(
62132 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62133 assert_instr(sshl)
62134)]
62135#[cfg_attr(
62136 not(target_arch = "arm"),
62137 stable(feature = "neon_intrinsics", since = "1.59.0")
62138)]
62139#[cfg_attr(
62140 target_arch = "arm",
62141 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62142)]
62143pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
62144 unsafe extern "unadjusted" {
62145 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i32")]
62146 #[cfg_attr(
62147 any(target_arch = "aarch64", target_arch = "arm64ec"),
62148 link_name = "llvm.aarch64.neon.sshl.v4i32"
62149 )]
62150 fn _vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
62151 }
62152 unsafe { _vshlq_s32(a, b) }
62153}
62154#[doc = "Signed Shift left"]
62155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"]
62156#[inline]
62157#[target_feature(enable = "neon")]
62158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62159#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62160#[cfg_attr(
62161 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62162 assert_instr(sshl)
62163)]
62164#[cfg_attr(
62165 not(target_arch = "arm"),
62166 stable(feature = "neon_intrinsics", since = "1.59.0")
62167)]
62168#[cfg_attr(
62169 target_arch = "arm",
62170 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62171)]
62172pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
62173 unsafe extern "unadjusted" {
62174 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v1i64")]
62175 #[cfg_attr(
62176 any(target_arch = "aarch64", target_arch = "arm64ec"),
62177 link_name = "llvm.aarch64.neon.sshl.v1i64"
62178 )]
62179 fn _vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
62180 }
62181 unsafe { _vshl_s64(a, b) }
62182}
62183#[doc = "Signed Shift left"]
62184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"]
62185#[inline]
62186#[target_feature(enable = "neon")]
62187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62189#[cfg_attr(
62190 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62191 assert_instr(sshl)
62192)]
62193#[cfg_attr(
62194 not(target_arch = "arm"),
62195 stable(feature = "neon_intrinsics", since = "1.59.0")
62196)]
62197#[cfg_attr(
62198 target_arch = "arm",
62199 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62200)]
62201pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
62202 unsafe extern "unadjusted" {
62203 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i64")]
62204 #[cfg_attr(
62205 any(target_arch = "aarch64", target_arch = "arm64ec"),
62206 link_name = "llvm.aarch64.neon.sshl.v2i64"
62207 )]
62208 fn _vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
62209 }
62210 unsafe { _vshlq_s64(a, b) }
62211}
62212#[doc = "Unsigned Shift left"]
62213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"]
62214#[inline]
62215#[target_feature(enable = "neon")]
62216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62217#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62218#[cfg_attr(
62219 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62220 assert_instr(ushl)
62221)]
62222#[cfg_attr(
62223 not(target_arch = "arm"),
62224 stable(feature = "neon_intrinsics", since = "1.59.0")
62225)]
62226#[cfg_attr(
62227 target_arch = "arm",
62228 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62229)]
62230pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
62231 unsafe extern "unadjusted" {
62232 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i8")]
62233 #[cfg_attr(
62234 any(target_arch = "aarch64", target_arch = "arm64ec"),
62235 link_name = "llvm.aarch64.neon.ushl.v8i8"
62236 )]
62237 fn _vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
62238 }
62239 unsafe { _vshl_u8(a, b) }
62240}
62241#[doc = "Unsigned Shift left"]
62242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"]
62243#[inline]
62244#[target_feature(enable = "neon")]
62245#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62246#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62247#[cfg_attr(
62248 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62249 assert_instr(ushl)
62250)]
62251#[cfg_attr(
62252 not(target_arch = "arm"),
62253 stable(feature = "neon_intrinsics", since = "1.59.0")
62254)]
62255#[cfg_attr(
62256 target_arch = "arm",
62257 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62258)]
62259pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
62260 unsafe extern "unadjusted" {
62261 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v16i8")]
62262 #[cfg_attr(
62263 any(target_arch = "aarch64", target_arch = "arm64ec"),
62264 link_name = "llvm.aarch64.neon.ushl.v16i8"
62265 )]
62266 fn _vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
62267 }
62268 unsafe { _vshlq_u8(a, b) }
62269}
62270#[doc = "Unsigned Shift left"]
62271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"]
62272#[inline]
62273#[target_feature(enable = "neon")]
62274#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62275#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62276#[cfg_attr(
62277 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62278 assert_instr(ushl)
62279)]
62280#[cfg_attr(
62281 not(target_arch = "arm"),
62282 stable(feature = "neon_intrinsics", since = "1.59.0")
62283)]
62284#[cfg_attr(
62285 target_arch = "arm",
62286 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62287)]
62288pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
62289 unsafe extern "unadjusted" {
62290 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i16")]
62291 #[cfg_attr(
62292 any(target_arch = "aarch64", target_arch = "arm64ec"),
62293 link_name = "llvm.aarch64.neon.ushl.v4i16"
62294 )]
62295 fn _vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
62296 }
62297 unsafe { _vshl_u16(a, b) }
62298}
62299#[doc = "Unsigned Shift left"]
62300#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"]
62301#[inline]
62302#[target_feature(enable = "neon")]
62303#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62304#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62305#[cfg_attr(
62306 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62307 assert_instr(ushl)
62308)]
62309#[cfg_attr(
62310 not(target_arch = "arm"),
62311 stable(feature = "neon_intrinsics", since = "1.59.0")
62312)]
62313#[cfg_attr(
62314 target_arch = "arm",
62315 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62316)]
62317pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
62318 unsafe extern "unadjusted" {
62319 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i16")]
62320 #[cfg_attr(
62321 any(target_arch = "aarch64", target_arch = "arm64ec"),
62322 link_name = "llvm.aarch64.neon.ushl.v8i16"
62323 )]
62324 fn _vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
62325 }
62326 unsafe { _vshlq_u16(a, b) }
62327}
62328#[doc = "Unsigned Shift left"]
62329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"]
62330#[inline]
62331#[target_feature(enable = "neon")]
62332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62333#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62334#[cfg_attr(
62335 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62336 assert_instr(ushl)
62337)]
62338#[cfg_attr(
62339 not(target_arch = "arm"),
62340 stable(feature = "neon_intrinsics", since = "1.59.0")
62341)]
62342#[cfg_attr(
62343 target_arch = "arm",
62344 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62345)]
62346pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
62347 unsafe extern "unadjusted" {
62348 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i32")]
62349 #[cfg_attr(
62350 any(target_arch = "aarch64", target_arch = "arm64ec"),
62351 link_name = "llvm.aarch64.neon.ushl.v2i32"
62352 )]
62353 fn _vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
62354 }
62355 unsafe { _vshl_u32(a, b) }
62356}
62357#[doc = "Unsigned Shift left"]
62358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"]
62359#[inline]
62360#[target_feature(enable = "neon")]
62361#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62362#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62363#[cfg_attr(
62364 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62365 assert_instr(ushl)
62366)]
62367#[cfg_attr(
62368 not(target_arch = "arm"),
62369 stable(feature = "neon_intrinsics", since = "1.59.0")
62370)]
62371#[cfg_attr(
62372 target_arch = "arm",
62373 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62374)]
62375pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
62376 unsafe extern "unadjusted" {
62377 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i32")]
62378 #[cfg_attr(
62379 any(target_arch = "aarch64", target_arch = "arm64ec"),
62380 link_name = "llvm.aarch64.neon.ushl.v4i32"
62381 )]
62382 fn _vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
62383 }
62384 unsafe { _vshlq_u32(a, b) }
62385}
62386#[doc = "Unsigned Shift left"]
62387#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"]
62388#[inline]
62389#[target_feature(enable = "neon")]
62390#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62391#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62392#[cfg_attr(
62393 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62394 assert_instr(ushl)
62395)]
62396#[cfg_attr(
62397 not(target_arch = "arm"),
62398 stable(feature = "neon_intrinsics", since = "1.59.0")
62399)]
62400#[cfg_attr(
62401 target_arch = "arm",
62402 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62403)]
62404pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
62405 unsafe extern "unadjusted" {
62406 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v1i64")]
62407 #[cfg_attr(
62408 any(target_arch = "aarch64", target_arch = "arm64ec"),
62409 link_name = "llvm.aarch64.neon.ushl.v1i64"
62410 )]
62411 fn _vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
62412 }
62413 unsafe { _vshl_u64(a, b) }
62414}
62415#[doc = "Unsigned Shift left"]
62416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"]
62417#[inline]
62418#[target_feature(enable = "neon")]
62419#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62420#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
62421#[cfg_attr(
62422 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62423 assert_instr(ushl)
62424)]
62425#[cfg_attr(
62426 not(target_arch = "arm"),
62427 stable(feature = "neon_intrinsics", since = "1.59.0")
62428)]
62429#[cfg_attr(
62430 target_arch = "arm",
62431 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62432)]
62433pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
62434 unsafe extern "unadjusted" {
62435 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i64")]
62436 #[cfg_attr(
62437 any(target_arch = "aarch64", target_arch = "arm64ec"),
62438 link_name = "llvm.aarch64.neon.ushl.v2i64"
62439 )]
62440 fn _vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
62441 }
62442 unsafe { _vshlq_u64(a, b) }
62443}
62444#[doc = "Signed shift left long"]
62445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"]
62446#[inline]
62447#[target_feature(enable = "neon")]
62448#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62449#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))]
62450#[cfg_attr(
62451 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62452 assert_instr(sshll, N = 2)
62453)]
62454#[rustc_legacy_const_generics(1)]
62455#[cfg_attr(
62456 not(target_arch = "arm"),
62457 stable(feature = "neon_intrinsics", since = "1.59.0")
62458)]
62459#[cfg_attr(
62460 target_arch = "arm",
62461 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62462)]
62463pub fn vshll_n_s16<const N: i32>(a: int16x4_t) -> int32x4_t {
62464 static_assert!(N >= 0 && N <= 16);
62465 unsafe { simd_shl(simd_cast(a), vdupq_n_s32(N as _)) }
62466}
62467#[doc = "Signed shift left long"]
62468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"]
62469#[inline]
62470#[target_feature(enable = "neon")]
62471#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62472#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))]
62473#[cfg_attr(
62474 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62475 assert_instr(sshll, N = 2)
62476)]
62477#[rustc_legacy_const_generics(1)]
62478#[cfg_attr(
62479 not(target_arch = "arm"),
62480 stable(feature = "neon_intrinsics", since = "1.59.0")
62481)]
62482#[cfg_attr(
62483 target_arch = "arm",
62484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62485)]
62486pub fn vshll_n_s32<const N: i32>(a: int32x2_t) -> int64x2_t {
62487 static_assert!(N >= 0 && N <= 32);
62488 unsafe { simd_shl(simd_cast(a), vdupq_n_s64(N as _)) }
62489}
62490#[doc = "Signed shift left long"]
62491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"]
62492#[inline]
62493#[target_feature(enable = "neon")]
62494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62495#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))]
62496#[cfg_attr(
62497 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62498 assert_instr(sshll, N = 2)
62499)]
62500#[rustc_legacy_const_generics(1)]
62501#[cfg_attr(
62502 not(target_arch = "arm"),
62503 stable(feature = "neon_intrinsics", since = "1.59.0")
62504)]
62505#[cfg_attr(
62506 target_arch = "arm",
62507 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62508)]
62509pub fn vshll_n_s8<const N: i32>(a: int8x8_t) -> int16x8_t {
62510 static_assert!(N >= 0 && N <= 8);
62511 unsafe { simd_shl(simd_cast(a), vdupq_n_s16(N as _)) }
62512}
62513#[doc = "Signed shift left long"]
62514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"]
62515#[inline]
62516#[target_feature(enable = "neon")]
62517#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62518#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))]
62519#[cfg_attr(
62520 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62521 assert_instr(ushll, N = 2)
62522)]
62523#[rustc_legacy_const_generics(1)]
62524#[cfg_attr(
62525 not(target_arch = "arm"),
62526 stable(feature = "neon_intrinsics", since = "1.59.0")
62527)]
62528#[cfg_attr(
62529 target_arch = "arm",
62530 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62531)]
62532pub fn vshll_n_u16<const N: i32>(a: uint16x4_t) -> uint32x4_t {
62533 static_assert!(N >= 0 && N <= 16);
62534 unsafe { simd_shl(simd_cast(a), vdupq_n_u32(N as _)) }
62535}
62536#[doc = "Signed shift left long"]
62537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"]
62538#[inline]
62539#[target_feature(enable = "neon")]
62540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62541#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))]
62542#[cfg_attr(
62543 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62544 assert_instr(ushll, N = 2)
62545)]
62546#[rustc_legacy_const_generics(1)]
62547#[cfg_attr(
62548 not(target_arch = "arm"),
62549 stable(feature = "neon_intrinsics", since = "1.59.0")
62550)]
62551#[cfg_attr(
62552 target_arch = "arm",
62553 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62554)]
62555pub fn vshll_n_u32<const N: i32>(a: uint32x2_t) -> uint64x2_t {
62556 static_assert!(N >= 0 && N <= 32);
62557 unsafe { simd_shl(simd_cast(a), vdupq_n_u64(N as _)) }
62558}
62559#[doc = "Signed shift left long"]
62560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"]
62561#[inline]
62562#[target_feature(enable = "neon")]
62563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62564#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))]
62565#[cfg_attr(
62566 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62567 assert_instr(ushll, N = 2)
62568)]
62569#[rustc_legacy_const_generics(1)]
62570#[cfg_attr(
62571 not(target_arch = "arm"),
62572 stable(feature = "neon_intrinsics", since = "1.59.0")
62573)]
62574#[cfg_attr(
62575 target_arch = "arm",
62576 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62577)]
62578pub fn vshll_n_u8<const N: i32>(a: uint8x8_t) -> uint16x8_t {
62579 static_assert!(N >= 0 && N <= 8);
62580 unsafe { simd_shl(simd_cast(a), vdupq_n_u16(N as _)) }
62581}
62582#[doc = "Shift right"]
62583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"]
62584#[inline]
62585#[target_feature(enable = "neon")]
62586#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62587#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
62588#[cfg_attr(
62589 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62590 assert_instr(sshr, N = 2)
62591)]
62592#[rustc_legacy_const_generics(1)]
62593#[cfg_attr(
62594 not(target_arch = "arm"),
62595 stable(feature = "neon_intrinsics", since = "1.59.0")
62596)]
62597#[cfg_attr(
62598 target_arch = "arm",
62599 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62600)]
62601pub fn vshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
62602 static_assert!(N >= 1 && N <= 8);
62603 let n: i32 = if N == 8 { 7 } else { N };
62604 unsafe { simd_shr(a, vdup_n_s8(n as _)) }
62605}
62606#[doc = "Shift right"]
62607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"]
62608#[inline]
62609#[target_feature(enable = "neon")]
62610#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62611#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
62612#[cfg_attr(
62613 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62614 assert_instr(sshr, N = 2)
62615)]
62616#[rustc_legacy_const_generics(1)]
62617#[cfg_attr(
62618 not(target_arch = "arm"),
62619 stable(feature = "neon_intrinsics", since = "1.59.0")
62620)]
62621#[cfg_attr(
62622 target_arch = "arm",
62623 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62624)]
62625pub fn vshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
62626 static_assert!(N >= 1 && N <= 8);
62627 let n: i32 = if N == 8 { 7 } else { N };
62628 unsafe { simd_shr(a, vdupq_n_s8(n as _)) }
62629}
62630#[doc = "Shift right"]
62631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"]
62632#[inline]
62633#[target_feature(enable = "neon")]
62634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62635#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
62636#[cfg_attr(
62637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62638 assert_instr(sshr, N = 2)
62639)]
62640#[rustc_legacy_const_generics(1)]
62641#[cfg_attr(
62642 not(target_arch = "arm"),
62643 stable(feature = "neon_intrinsics", since = "1.59.0")
62644)]
62645#[cfg_attr(
62646 target_arch = "arm",
62647 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62648)]
62649pub fn vshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
62650 static_assert!(N >= 1 && N <= 16);
62651 let n: i32 = if N == 16 { 15 } else { N };
62652 unsafe { simd_shr(a, vdup_n_s16(n as _)) }
62653}
62654#[doc = "Shift right"]
62655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"]
62656#[inline]
62657#[target_feature(enable = "neon")]
62658#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62659#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
62660#[cfg_attr(
62661 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62662 assert_instr(sshr, N = 2)
62663)]
62664#[rustc_legacy_const_generics(1)]
62665#[cfg_attr(
62666 not(target_arch = "arm"),
62667 stable(feature = "neon_intrinsics", since = "1.59.0")
62668)]
62669#[cfg_attr(
62670 target_arch = "arm",
62671 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62672)]
62673pub fn vshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
62674 static_assert!(N >= 1 && N <= 16);
62675 let n: i32 = if N == 16 { 15 } else { N };
62676 unsafe { simd_shr(a, vdupq_n_s16(n as _)) }
62677}
62678#[doc = "Shift right"]
62679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"]
62680#[inline]
62681#[target_feature(enable = "neon")]
62682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62683#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
62684#[cfg_attr(
62685 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62686 assert_instr(sshr, N = 2)
62687)]
62688#[rustc_legacy_const_generics(1)]
62689#[cfg_attr(
62690 not(target_arch = "arm"),
62691 stable(feature = "neon_intrinsics", since = "1.59.0")
62692)]
62693#[cfg_attr(
62694 target_arch = "arm",
62695 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62696)]
62697pub fn vshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
62698 static_assert!(N >= 1 && N <= 32);
62699 let n: i32 = if N == 32 { 31 } else { N };
62700 unsafe { simd_shr(a, vdup_n_s32(n as _)) }
62701}
62702#[doc = "Shift right"]
62703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"]
62704#[inline]
62705#[target_feature(enable = "neon")]
62706#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62707#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
62708#[cfg_attr(
62709 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62710 assert_instr(sshr, N = 2)
62711)]
62712#[rustc_legacy_const_generics(1)]
62713#[cfg_attr(
62714 not(target_arch = "arm"),
62715 stable(feature = "neon_intrinsics", since = "1.59.0")
62716)]
62717#[cfg_attr(
62718 target_arch = "arm",
62719 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62720)]
62721pub fn vshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
62722 static_assert!(N >= 1 && N <= 32);
62723 let n: i32 = if N == 32 { 31 } else { N };
62724 unsafe { simd_shr(a, vdupq_n_s32(n as _)) }
62725}
62726#[doc = "Shift right"]
62727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"]
62728#[inline]
62729#[target_feature(enable = "neon")]
62730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62731#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
62732#[cfg_attr(
62733 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62734 assert_instr(sshr, N = 2)
62735)]
62736#[rustc_legacy_const_generics(1)]
62737#[cfg_attr(
62738 not(target_arch = "arm"),
62739 stable(feature = "neon_intrinsics", since = "1.59.0")
62740)]
62741#[cfg_attr(
62742 target_arch = "arm",
62743 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62744)]
62745pub fn vshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
62746 static_assert!(N >= 1 && N <= 64);
62747 let n: i32 = if N == 64 { 63 } else { N };
62748 unsafe { simd_shr(a, vdup_n_s64(n as _)) }
62749}
62750#[doc = "Shift right"]
62751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"]
62752#[inline]
62753#[target_feature(enable = "neon")]
62754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62755#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
62756#[cfg_attr(
62757 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62758 assert_instr(sshr, N = 2)
62759)]
62760#[rustc_legacy_const_generics(1)]
62761#[cfg_attr(
62762 not(target_arch = "arm"),
62763 stable(feature = "neon_intrinsics", since = "1.59.0")
62764)]
62765#[cfg_attr(
62766 target_arch = "arm",
62767 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62768)]
62769pub fn vshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
62770 static_assert!(N >= 1 && N <= 64);
62771 let n: i32 = if N == 64 { 63 } else { N };
62772 unsafe { simd_shr(a, vdupq_n_s64(n as _)) }
62773}
62774#[doc = "Shift right"]
62775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"]
62776#[inline]
62777#[target_feature(enable = "neon")]
62778#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62779#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
62780#[cfg_attr(
62781 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62782 assert_instr(ushr, N = 2)
62783)]
62784#[rustc_legacy_const_generics(1)]
62785#[cfg_attr(
62786 not(target_arch = "arm"),
62787 stable(feature = "neon_intrinsics", since = "1.59.0")
62788)]
62789#[cfg_attr(
62790 target_arch = "arm",
62791 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62792)]
62793pub fn vshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
62794 static_assert!(N >= 1 && N <= 8);
62795 let n: i32 = if N == 8 {
62796 return vdup_n_u8(0);
62797 } else {
62798 N
62799 };
62800 unsafe { simd_shr(a, vdup_n_u8(n as _)) }
62801}
62802#[doc = "Shift right"]
62803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"]
62804#[inline]
62805#[target_feature(enable = "neon")]
62806#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62807#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
62808#[cfg_attr(
62809 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62810 assert_instr(ushr, N = 2)
62811)]
62812#[rustc_legacy_const_generics(1)]
62813#[cfg_attr(
62814 not(target_arch = "arm"),
62815 stable(feature = "neon_intrinsics", since = "1.59.0")
62816)]
62817#[cfg_attr(
62818 target_arch = "arm",
62819 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62820)]
62821pub fn vshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
62822 static_assert!(N >= 1 && N <= 8);
62823 let n: i32 = if N == 8 {
62824 return vdupq_n_u8(0);
62825 } else {
62826 N
62827 };
62828 unsafe { simd_shr(a, vdupq_n_u8(n as _)) }
62829}
62830#[doc = "Shift right"]
62831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"]
62832#[inline]
62833#[target_feature(enable = "neon")]
62834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62835#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
62836#[cfg_attr(
62837 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62838 assert_instr(ushr, N = 2)
62839)]
62840#[rustc_legacy_const_generics(1)]
62841#[cfg_attr(
62842 not(target_arch = "arm"),
62843 stable(feature = "neon_intrinsics", since = "1.59.0")
62844)]
62845#[cfg_attr(
62846 target_arch = "arm",
62847 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62848)]
62849pub fn vshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
62850 static_assert!(N >= 1 && N <= 16);
62851 let n: i32 = if N == 16 {
62852 return vdup_n_u16(0);
62853 } else {
62854 N
62855 };
62856 unsafe { simd_shr(a, vdup_n_u16(n as _)) }
62857}
62858#[doc = "Shift right"]
62859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"]
62860#[inline]
62861#[target_feature(enable = "neon")]
62862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62863#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
62864#[cfg_attr(
62865 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62866 assert_instr(ushr, N = 2)
62867)]
62868#[rustc_legacy_const_generics(1)]
62869#[cfg_attr(
62870 not(target_arch = "arm"),
62871 stable(feature = "neon_intrinsics", since = "1.59.0")
62872)]
62873#[cfg_attr(
62874 target_arch = "arm",
62875 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62876)]
62877pub fn vshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
62878 static_assert!(N >= 1 && N <= 16);
62879 let n: i32 = if N == 16 {
62880 return vdupq_n_u16(0);
62881 } else {
62882 N
62883 };
62884 unsafe { simd_shr(a, vdupq_n_u16(n as _)) }
62885}
62886#[doc = "Shift right"]
62887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"]
62888#[inline]
62889#[target_feature(enable = "neon")]
62890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62891#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
62892#[cfg_attr(
62893 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62894 assert_instr(ushr, N = 2)
62895)]
62896#[rustc_legacy_const_generics(1)]
62897#[cfg_attr(
62898 not(target_arch = "arm"),
62899 stable(feature = "neon_intrinsics", since = "1.59.0")
62900)]
62901#[cfg_attr(
62902 target_arch = "arm",
62903 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62904)]
62905pub fn vshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
62906 static_assert!(N >= 1 && N <= 32);
62907 let n: i32 = if N == 32 {
62908 return vdup_n_u32(0);
62909 } else {
62910 N
62911 };
62912 unsafe { simd_shr(a, vdup_n_u32(n as _)) }
62913}
62914#[doc = "Shift right"]
62915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"]
62916#[inline]
62917#[target_feature(enable = "neon")]
62918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62919#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
62920#[cfg_attr(
62921 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62922 assert_instr(ushr, N = 2)
62923)]
62924#[rustc_legacy_const_generics(1)]
62925#[cfg_attr(
62926 not(target_arch = "arm"),
62927 stable(feature = "neon_intrinsics", since = "1.59.0")
62928)]
62929#[cfg_attr(
62930 target_arch = "arm",
62931 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62932)]
62933pub fn vshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
62934 static_assert!(N >= 1 && N <= 32);
62935 let n: i32 = if N == 32 {
62936 return vdupq_n_u32(0);
62937 } else {
62938 N
62939 };
62940 unsafe { simd_shr(a, vdupq_n_u32(n as _)) }
62941}
62942#[doc = "Shift right"]
62943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"]
62944#[inline]
62945#[target_feature(enable = "neon")]
62946#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62947#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
62948#[cfg_attr(
62949 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62950 assert_instr(ushr, N = 2)
62951)]
62952#[rustc_legacy_const_generics(1)]
62953#[cfg_attr(
62954 not(target_arch = "arm"),
62955 stable(feature = "neon_intrinsics", since = "1.59.0")
62956)]
62957#[cfg_attr(
62958 target_arch = "arm",
62959 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62960)]
62961pub fn vshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
62962 static_assert!(N >= 1 && N <= 64);
62963 let n: i32 = if N == 64 {
62964 return vdup_n_u64(0);
62965 } else {
62966 N
62967 };
62968 unsafe { simd_shr(a, vdup_n_u64(n as _)) }
62969}
62970#[doc = "Shift right"]
62971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"]
62972#[inline]
62973#[target_feature(enable = "neon")]
62974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62975#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
62976#[cfg_attr(
62977 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62978 assert_instr(ushr, N = 2)
62979)]
62980#[rustc_legacy_const_generics(1)]
62981#[cfg_attr(
62982 not(target_arch = "arm"),
62983 stable(feature = "neon_intrinsics", since = "1.59.0")
62984)]
62985#[cfg_attr(
62986 target_arch = "arm",
62987 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62988)]
62989pub fn vshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
62990 static_assert!(N >= 1 && N <= 64);
62991 let n: i32 = if N == 64 {
62992 return vdupq_n_u64(0);
62993 } else {
62994 N
62995 };
62996 unsafe { simd_shr(a, vdupq_n_u64(n as _)) }
62997}
62998#[doc = "Shift right narrow"]
62999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"]
63000#[inline]
63001#[target_feature(enable = "neon")]
63002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63003#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
63004#[cfg_attr(
63005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63006 assert_instr(shrn, N = 2)
63007)]
63008#[rustc_legacy_const_generics(1)]
63009#[cfg_attr(
63010 not(target_arch = "arm"),
63011 stable(feature = "neon_intrinsics", since = "1.59.0")
63012)]
63013#[cfg_attr(
63014 target_arch = "arm",
63015 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63016)]
63017pub fn vshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
63018 static_assert!(N >= 1 && N <= 8);
63019 unsafe { simd_cast(simd_shr(a, vdupq_n_s16(N as _))) }
63020}
63021#[doc = "Shift right narrow"]
63022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"]
63023#[inline]
63024#[target_feature(enable = "neon")]
63025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63026#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
63027#[cfg_attr(
63028 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63029 assert_instr(shrn, N = 2)
63030)]
63031#[rustc_legacy_const_generics(1)]
63032#[cfg_attr(
63033 not(target_arch = "arm"),
63034 stable(feature = "neon_intrinsics", since = "1.59.0")
63035)]
63036#[cfg_attr(
63037 target_arch = "arm",
63038 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63039)]
63040pub fn vshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
63041 static_assert!(N >= 1 && N <= 16);
63042 unsafe { simd_cast(simd_shr(a, vdupq_n_s32(N as _))) }
63043}
63044#[doc = "Shift right narrow"]
63045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"]
63046#[inline]
63047#[target_feature(enable = "neon")]
63048#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63049#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
63050#[cfg_attr(
63051 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63052 assert_instr(shrn, N = 2)
63053)]
63054#[rustc_legacy_const_generics(1)]
63055#[cfg_attr(
63056 not(target_arch = "arm"),
63057 stable(feature = "neon_intrinsics", since = "1.59.0")
63058)]
63059#[cfg_attr(
63060 target_arch = "arm",
63061 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63062)]
63063pub fn vshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
63064 static_assert!(N >= 1 && N <= 32);
63065 unsafe { simd_cast(simd_shr(a, vdupq_n_s64(N as _))) }
63066}
63067#[doc = "Shift right narrow"]
63068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"]
63069#[inline]
63070#[target_feature(enable = "neon")]
63071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63072#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
63073#[cfg_attr(
63074 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63075 assert_instr(shrn, N = 2)
63076)]
63077#[rustc_legacy_const_generics(1)]
63078#[cfg_attr(
63079 not(target_arch = "arm"),
63080 stable(feature = "neon_intrinsics", since = "1.59.0")
63081)]
63082#[cfg_attr(
63083 target_arch = "arm",
63084 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63085)]
63086pub fn vshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
63087 static_assert!(N >= 1 && N <= 8);
63088 unsafe { simd_cast(simd_shr(a, vdupq_n_u16(N as _))) }
63089}
63090#[doc = "Shift right narrow"]
63091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"]
63092#[inline]
63093#[target_feature(enable = "neon")]
63094#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63095#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
63096#[cfg_attr(
63097 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63098 assert_instr(shrn, N = 2)
63099)]
63100#[rustc_legacy_const_generics(1)]
63101#[cfg_attr(
63102 not(target_arch = "arm"),
63103 stable(feature = "neon_intrinsics", since = "1.59.0")
63104)]
63105#[cfg_attr(
63106 target_arch = "arm",
63107 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63108)]
63109pub fn vshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
63110 static_assert!(N >= 1 && N <= 16);
63111 unsafe { simd_cast(simd_shr(a, vdupq_n_u32(N as _))) }
63112}
63113#[doc = "Shift right narrow"]
63114#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"]
63115#[inline]
63116#[target_feature(enable = "neon")]
63117#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63118#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
63119#[cfg_attr(
63120 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63121 assert_instr(shrn, N = 2)
63122)]
63123#[rustc_legacy_const_generics(1)]
63124#[cfg_attr(
63125 not(target_arch = "arm"),
63126 stable(feature = "neon_intrinsics", since = "1.59.0")
63127)]
63128#[cfg_attr(
63129 target_arch = "arm",
63130 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63131)]
63132pub fn vshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
63133 static_assert!(N >= 1 && N <= 32);
63134 unsafe { simd_cast(simd_shr(a, vdupq_n_u64(N as _))) }
63135}
63136#[doc = "Shift Left and Insert (immediate)"]
63137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
63138#[inline]
63139#[cfg(target_arch = "arm")]
63140#[target_feature(enable = "neon,v7")]
63141#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63142#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63143#[rustc_legacy_const_generics(2)]
63144pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
63145 static_assert_uimm_bits!(N, 3);
63146 vshiftins_v8i8(a, b, int8x8_t::splat(N as i8))
63147}
63148#[doc = "Shift Left and Insert (immediate)"]
63149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
63150#[inline]
63151#[cfg(target_arch = "arm")]
63152#[target_feature(enable = "neon,v7")]
63153#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63154#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63155#[rustc_legacy_const_generics(2)]
63156pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
63157 static_assert_uimm_bits!(N, 3);
63158 vshiftins_v16i8(a, b, int8x16_t::splat(N as i8))
63159}
63160#[doc = "Shift Left and Insert (immediate)"]
63161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
63162#[inline]
63163#[cfg(target_arch = "arm")]
63164#[target_feature(enable = "neon,v7")]
63165#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63166#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63167#[rustc_legacy_const_generics(2)]
63168pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
63169 static_assert_uimm_bits!(N, 4);
63170 vshiftins_v4i16(a, b, int16x4_t::splat(N as i16))
63171}
63172#[doc = "Shift Left and Insert (immediate)"]
63173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
63174#[inline]
63175#[cfg(target_arch = "arm")]
63176#[target_feature(enable = "neon,v7")]
63177#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63178#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63179#[rustc_legacy_const_generics(2)]
63180pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
63181 static_assert_uimm_bits!(N, 4);
63182 vshiftins_v8i16(a, b, int16x8_t::splat(N as i16))
63183}
63184#[doc = "Shift Left and Insert (immediate)"]
63185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
63186#[inline]
63187#[cfg(target_arch = "arm")]
63188#[target_feature(enable = "neon,v7")]
63189#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63190#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63191#[rustc_legacy_const_generics(2)]
63192pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
63193 static_assert!(N >= 0 && N <= 31);
63194 vshiftins_v2i32(a, b, int32x2_t::splat(N))
63195}
63196#[doc = "Shift Left and Insert (immediate)"]
63197#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
63198#[inline]
63199#[cfg(target_arch = "arm")]
63200#[target_feature(enable = "neon,v7")]
63201#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63202#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63203#[rustc_legacy_const_generics(2)]
63204pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
63205 static_assert!(N >= 0 && N <= 31);
63206 vshiftins_v4i32(a, b, int32x4_t::splat(N))
63207}
63208#[doc = "Shift Left and Insert (immediate)"]
63209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
63210#[inline]
63211#[cfg(target_arch = "arm")]
63212#[target_feature(enable = "neon,v7")]
63213#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63214#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63215#[rustc_legacy_const_generics(2)]
63216pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
63217 static_assert!(N >= 0 && N <= 63);
63218 vshiftins_v1i64(a, b, int64x1_t::splat(N as i64))
63219}
63220#[doc = "Shift Left and Insert (immediate)"]
63221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
63222#[inline]
63223#[cfg(target_arch = "arm")]
63224#[target_feature(enable = "neon,v7")]
63225#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63226#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63227#[rustc_legacy_const_generics(2)]
63228pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
63229 static_assert!(N >= 0 && N <= 63);
63230 vshiftins_v2i64(a, b, int64x2_t::splat(N as i64))
63231}
63232#[doc = "Shift Left and Insert (immediate)"]
63233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
63234#[inline]
63235#[cfg(target_arch = "arm")]
63236#[target_feature(enable = "neon,v7")]
63237#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63238#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63239#[rustc_legacy_const_generics(2)]
63240pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
63241 static_assert_uimm_bits!(N, 3);
63242 unsafe {
63243 transmute(vshiftins_v8i8(
63244 transmute(a),
63245 transmute(b),
63246 int8x8_t::splat(N as i8),
63247 ))
63248 }
63249}
63250#[doc = "Shift Left and Insert (immediate)"]
63251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
63252#[inline]
63253#[cfg(target_arch = "arm")]
63254#[target_feature(enable = "neon,v7")]
63255#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63256#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63257#[rustc_legacy_const_generics(2)]
63258pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
63259 static_assert_uimm_bits!(N, 3);
63260 unsafe {
63261 transmute(vshiftins_v16i8(
63262 transmute(a),
63263 transmute(b),
63264 int8x16_t::splat(N as i8),
63265 ))
63266 }
63267}
63268#[doc = "Shift Left and Insert (immediate)"]
63269#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
63270#[inline]
63271#[cfg(target_arch = "arm")]
63272#[target_feature(enable = "neon,v7")]
63273#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63274#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63275#[rustc_legacy_const_generics(2)]
63276pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
63277 static_assert_uimm_bits!(N, 4);
63278 unsafe {
63279 transmute(vshiftins_v4i16(
63280 transmute(a),
63281 transmute(b),
63282 int16x4_t::splat(N as i16),
63283 ))
63284 }
63285}
63286#[doc = "Shift Left and Insert (immediate)"]
63287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
63288#[inline]
63289#[cfg(target_arch = "arm")]
63290#[target_feature(enable = "neon,v7")]
63291#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63292#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63293#[rustc_legacy_const_generics(2)]
63294pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
63295 static_assert_uimm_bits!(N, 4);
63296 unsafe {
63297 transmute(vshiftins_v8i16(
63298 transmute(a),
63299 transmute(b),
63300 int16x8_t::splat(N as i16),
63301 ))
63302 }
63303}
63304#[doc = "Shift Left and Insert (immediate)"]
63305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
63306#[inline]
63307#[cfg(target_arch = "arm")]
63308#[target_feature(enable = "neon,v7")]
63309#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63310#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63311#[rustc_legacy_const_generics(2)]
63312pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
63313 static_assert!(N >= 0 && N <= 31);
63314 unsafe {
63315 transmute(vshiftins_v2i32(
63316 transmute(a),
63317 transmute(b),
63318 int32x2_t::splat(N as i32),
63319 ))
63320 }
63321}
63322#[doc = "Shift Left and Insert (immediate)"]
63323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
63324#[inline]
63325#[cfg(target_arch = "arm")]
63326#[target_feature(enable = "neon,v7")]
63327#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63328#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
63329#[rustc_legacy_const_generics(2)]
63330pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
63331 static_assert!(N >= 0 && N <= 31);
63332 unsafe {
63333 transmute(vshiftins_v4i32(
63334 transmute(a),
63335 transmute(b),
63336 int32x4_t::splat(N as i32),
63337 ))
63338 }
63339}
63340#[doc = "Shift Left and Insert (immediate)"]
63341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
63342#[inline]
63343#[cfg(target_arch = "arm")]
63344#[target_feature(enable = "neon,v7")]
63345#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63346#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63347#[rustc_legacy_const_generics(2)]
63348pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
63349 static_assert!(N >= 0 && N <= 63);
63350 unsafe {
63351 transmute(vshiftins_v1i64(
63352 transmute(a),
63353 transmute(b),
63354 int64x1_t::splat(N as i64),
63355 ))
63356 }
63357}
63358#[doc = "Shift Left and Insert (immediate)"]
63359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
63360#[inline]
63361#[cfg(target_arch = "arm")]
63362#[target_feature(enable = "neon,v7")]
63363#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63364#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
63365#[rustc_legacy_const_generics(2)]
63366pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
63367 static_assert!(N >= 0 && N <= 63);
63368 unsafe {
63369 transmute(vshiftins_v2i64(
63370 transmute(a),
63371 transmute(b),
63372 int64x2_t::splat(N as i64),
63373 ))
63374 }
63375}
63376#[doc = "Shift Left and Insert (immediate)"]
63377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
63378#[inline]
63379#[cfg(target_arch = "arm")]
63380#[target_feature(enable = "neon,v7")]
63381#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63382#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63383#[rustc_legacy_const_generics(2)]
63384pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
63385 static_assert_uimm_bits!(N, 3);
63386 unsafe {
63387 transmute(vshiftins_v8i8(
63388 transmute(a),
63389 transmute(b),
63390 int8x8_t::splat(N as i8),
63391 ))
63392 }
63393}
63394#[doc = "Shift Left and Insert (immediate)"]
63395#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
63396#[inline]
63397#[cfg(target_arch = "arm")]
63398#[target_feature(enable = "neon,v7")]
63399#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63400#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
63401#[rustc_legacy_const_generics(2)]
63402pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
63403 static_assert_uimm_bits!(N, 3);
63404 unsafe {
63405 transmute(vshiftins_v16i8(
63406 transmute(a),
63407 transmute(b),
63408 int8x16_t::splat(N as i8),
63409 ))
63410 }
63411}
63412#[doc = "Shift Left and Insert (immediate)"]
63413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
63414#[inline]
63415#[cfg(target_arch = "arm")]
63416#[target_feature(enable = "neon,v7")]
63417#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63418#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63419#[rustc_legacy_const_generics(2)]
63420pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
63421 static_assert_uimm_bits!(N, 4);
63422 unsafe {
63423 transmute(vshiftins_v4i16(
63424 transmute(a),
63425 transmute(b),
63426 int16x4_t::splat(N as i16),
63427 ))
63428 }
63429}
63430#[doc = "Shift Left and Insert (immediate)"]
63431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
63432#[inline]
63433#[cfg(target_arch = "arm")]
63434#[target_feature(enable = "neon,v7")]
63435#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63436#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63437#[rustc_legacy_const_generics(2)]
63438pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
63439 static_assert_uimm_bits!(N, 4);
63440 unsafe {
63441 transmute(vshiftins_v8i16(
63442 transmute(a),
63443 transmute(b),
63444 int16x8_t::splat(N as i16),
63445 ))
63446 }
63447}
63448#[doc = "Signed shift right and accumulate"]
63449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"]
63450#[inline]
63451#[target_feature(enable = "neon")]
63452#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63453#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63454#[cfg_attr(
63455 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63456 assert_instr(ssra, N = 2)
63457)]
63458#[rustc_legacy_const_generics(2)]
63459#[cfg_attr(
63460 not(target_arch = "arm"),
63461 stable(feature = "neon_intrinsics", since = "1.59.0")
63462)]
63463#[cfg_attr(
63464 target_arch = "arm",
63465 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63466)]
63467pub fn vsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
63468 static_assert!(N >= 1 && N <= 8);
63469 unsafe { simd_add(a, vshr_n_s8::<N>(b)) }
63470}
63471#[doc = "Signed shift right and accumulate"]
63472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"]
63473#[inline]
63474#[target_feature(enable = "neon")]
63475#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63476#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63477#[cfg_attr(
63478 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63479 assert_instr(ssra, N = 2)
63480)]
63481#[rustc_legacy_const_generics(2)]
63482#[cfg_attr(
63483 not(target_arch = "arm"),
63484 stable(feature = "neon_intrinsics", since = "1.59.0")
63485)]
63486#[cfg_attr(
63487 target_arch = "arm",
63488 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63489)]
63490pub fn vsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
63491 static_assert!(N >= 1 && N <= 8);
63492 unsafe { simd_add(a, vshrq_n_s8::<N>(b)) }
63493}
63494#[doc = "Signed shift right and accumulate"]
63495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"]
63496#[inline]
63497#[target_feature(enable = "neon")]
63498#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63499#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63500#[cfg_attr(
63501 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63502 assert_instr(ssra, N = 2)
63503)]
63504#[rustc_legacy_const_generics(2)]
63505#[cfg_attr(
63506 not(target_arch = "arm"),
63507 stable(feature = "neon_intrinsics", since = "1.59.0")
63508)]
63509#[cfg_attr(
63510 target_arch = "arm",
63511 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63512)]
63513pub fn vsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
63514 static_assert!(N >= 1 && N <= 16);
63515 unsafe { simd_add(a, vshr_n_s16::<N>(b)) }
63516}
63517#[doc = "Signed shift right and accumulate"]
63518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"]
63519#[inline]
63520#[target_feature(enable = "neon")]
63521#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63522#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63523#[cfg_attr(
63524 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63525 assert_instr(ssra, N = 2)
63526)]
63527#[rustc_legacy_const_generics(2)]
63528#[cfg_attr(
63529 not(target_arch = "arm"),
63530 stable(feature = "neon_intrinsics", since = "1.59.0")
63531)]
63532#[cfg_attr(
63533 target_arch = "arm",
63534 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63535)]
63536pub fn vsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
63537 static_assert!(N >= 1 && N <= 16);
63538 unsafe { simd_add(a, vshrq_n_s16::<N>(b)) }
63539}
63540#[doc = "Signed shift right and accumulate"]
63541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"]
63542#[inline]
63543#[target_feature(enable = "neon")]
63544#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63545#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63546#[cfg_attr(
63547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63548 assert_instr(ssra, N = 2)
63549)]
63550#[rustc_legacy_const_generics(2)]
63551#[cfg_attr(
63552 not(target_arch = "arm"),
63553 stable(feature = "neon_intrinsics", since = "1.59.0")
63554)]
63555#[cfg_attr(
63556 target_arch = "arm",
63557 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63558)]
63559pub fn vsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
63560 static_assert!(N >= 1 && N <= 32);
63561 unsafe { simd_add(a, vshr_n_s32::<N>(b)) }
63562}
63563#[doc = "Signed shift right and accumulate"]
63564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"]
63565#[inline]
63566#[target_feature(enable = "neon")]
63567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63568#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63569#[cfg_attr(
63570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63571 assert_instr(ssra, N = 2)
63572)]
63573#[rustc_legacy_const_generics(2)]
63574#[cfg_attr(
63575 not(target_arch = "arm"),
63576 stable(feature = "neon_intrinsics", since = "1.59.0")
63577)]
63578#[cfg_attr(
63579 target_arch = "arm",
63580 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63581)]
63582pub fn vsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
63583 static_assert!(N >= 1 && N <= 32);
63584 unsafe { simd_add(a, vshrq_n_s32::<N>(b)) }
63585}
63586#[doc = "Signed shift right and accumulate"]
63587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"]
63588#[inline]
63589#[target_feature(enable = "neon")]
63590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63591#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63592#[cfg_attr(
63593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63594 assert_instr(ssra, N = 2)
63595)]
63596#[rustc_legacy_const_generics(2)]
63597#[cfg_attr(
63598 not(target_arch = "arm"),
63599 stable(feature = "neon_intrinsics", since = "1.59.0")
63600)]
63601#[cfg_attr(
63602 target_arch = "arm",
63603 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63604)]
63605pub fn vsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
63606 static_assert!(N >= 1 && N <= 64);
63607 unsafe { simd_add(a, vshr_n_s64::<N>(b)) }
63608}
63609#[doc = "Signed shift right and accumulate"]
63610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"]
63611#[inline]
63612#[target_feature(enable = "neon")]
63613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63614#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63615#[cfg_attr(
63616 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63617 assert_instr(ssra, N = 2)
63618)]
63619#[rustc_legacy_const_generics(2)]
63620#[cfg_attr(
63621 not(target_arch = "arm"),
63622 stable(feature = "neon_intrinsics", since = "1.59.0")
63623)]
63624#[cfg_attr(
63625 target_arch = "arm",
63626 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63627)]
63628pub fn vsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
63629 static_assert!(N >= 1 && N <= 64);
63630 unsafe { simd_add(a, vshrq_n_s64::<N>(b)) }
63631}
63632#[doc = "Unsigned shift right and accumulate"]
63633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"]
63634#[inline]
63635#[target_feature(enable = "neon")]
63636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63638#[cfg_attr(
63639 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63640 assert_instr(usra, N = 2)
63641)]
63642#[rustc_legacy_const_generics(2)]
63643#[cfg_attr(
63644 not(target_arch = "arm"),
63645 stable(feature = "neon_intrinsics", since = "1.59.0")
63646)]
63647#[cfg_attr(
63648 target_arch = "arm",
63649 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63650)]
63651pub fn vsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
63652 static_assert!(N >= 1 && N <= 8);
63653 unsafe { simd_add(a, vshr_n_u8::<N>(b)) }
63654}
63655#[doc = "Unsigned shift right and accumulate"]
63656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"]
63657#[inline]
63658#[target_feature(enable = "neon")]
63659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63660#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63661#[cfg_attr(
63662 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63663 assert_instr(usra, N = 2)
63664)]
63665#[rustc_legacy_const_generics(2)]
63666#[cfg_attr(
63667 not(target_arch = "arm"),
63668 stable(feature = "neon_intrinsics", since = "1.59.0")
63669)]
63670#[cfg_attr(
63671 target_arch = "arm",
63672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63673)]
63674pub fn vsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
63675 static_assert!(N >= 1 && N <= 8);
63676 unsafe { simd_add(a, vshrq_n_u8::<N>(b)) }
63677}
63678#[doc = "Unsigned shift right and accumulate"]
63679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"]
63680#[inline]
63681#[target_feature(enable = "neon")]
63682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63683#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63684#[cfg_attr(
63685 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63686 assert_instr(usra, N = 2)
63687)]
63688#[rustc_legacy_const_generics(2)]
63689#[cfg_attr(
63690 not(target_arch = "arm"),
63691 stable(feature = "neon_intrinsics", since = "1.59.0")
63692)]
63693#[cfg_attr(
63694 target_arch = "arm",
63695 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63696)]
63697pub fn vsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
63698 static_assert!(N >= 1 && N <= 16);
63699 unsafe { simd_add(a, vshr_n_u16::<N>(b)) }
63700}
63701#[doc = "Unsigned shift right and accumulate"]
63702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"]
63703#[inline]
63704#[target_feature(enable = "neon")]
63705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63707#[cfg_attr(
63708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63709 assert_instr(usra, N = 2)
63710)]
63711#[rustc_legacy_const_generics(2)]
63712#[cfg_attr(
63713 not(target_arch = "arm"),
63714 stable(feature = "neon_intrinsics", since = "1.59.0")
63715)]
63716#[cfg_attr(
63717 target_arch = "arm",
63718 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63719)]
63720pub fn vsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
63721 static_assert!(N >= 1 && N <= 16);
63722 unsafe { simd_add(a, vshrq_n_u16::<N>(b)) }
63723}
63724#[doc = "Unsigned shift right and accumulate"]
63725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"]
63726#[inline]
63727#[target_feature(enable = "neon")]
63728#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63729#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63730#[cfg_attr(
63731 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63732 assert_instr(usra, N = 2)
63733)]
63734#[rustc_legacy_const_generics(2)]
63735#[cfg_attr(
63736 not(target_arch = "arm"),
63737 stable(feature = "neon_intrinsics", since = "1.59.0")
63738)]
63739#[cfg_attr(
63740 target_arch = "arm",
63741 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63742)]
63743pub fn vsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
63744 static_assert!(N >= 1 && N <= 32);
63745 unsafe { simd_add(a, vshr_n_u32::<N>(b)) }
63746}
63747#[doc = "Unsigned shift right and accumulate"]
63748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"]
63749#[inline]
63750#[target_feature(enable = "neon")]
63751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63752#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63753#[cfg_attr(
63754 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63755 assert_instr(usra, N = 2)
63756)]
63757#[rustc_legacy_const_generics(2)]
63758#[cfg_attr(
63759 not(target_arch = "arm"),
63760 stable(feature = "neon_intrinsics", since = "1.59.0")
63761)]
63762#[cfg_attr(
63763 target_arch = "arm",
63764 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63765)]
63766pub fn vsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
63767 static_assert!(N >= 1 && N <= 32);
63768 unsafe { simd_add(a, vshrq_n_u32::<N>(b)) }
63769}
63770#[doc = "Unsigned shift right and accumulate"]
63771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"]
63772#[inline]
63773#[target_feature(enable = "neon")]
63774#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63775#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63776#[cfg_attr(
63777 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63778 assert_instr(usra, N = 2)
63779)]
63780#[rustc_legacy_const_generics(2)]
63781#[cfg_attr(
63782 not(target_arch = "arm"),
63783 stable(feature = "neon_intrinsics", since = "1.59.0")
63784)]
63785#[cfg_attr(
63786 target_arch = "arm",
63787 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63788)]
63789pub fn vsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
63790 static_assert!(N >= 1 && N <= 64);
63791 unsafe { simd_add(a, vshr_n_u64::<N>(b)) }
63792}
63793#[doc = "Unsigned shift right and accumulate"]
63794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"]
63795#[inline]
63796#[target_feature(enable = "neon")]
63797#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63798#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63799#[cfg_attr(
63800 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63801 assert_instr(usra, N = 2)
63802)]
63803#[rustc_legacy_const_generics(2)]
63804#[cfg_attr(
63805 not(target_arch = "arm"),
63806 stable(feature = "neon_intrinsics", since = "1.59.0")
63807)]
63808#[cfg_attr(
63809 target_arch = "arm",
63810 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63811)]
63812pub fn vsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
63813 static_assert!(N >= 1 && N <= 64);
63814 unsafe { simd_add(a, vshrq_n_u64::<N>(b)) }
63815}
63816#[doc = "Shift Right and Insert (immediate)"]
63817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
63818#[inline]
63819#[target_feature(enable = "neon,v7")]
63820#[cfg(target_arch = "arm")]
63821#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63822#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63823#[rustc_legacy_const_generics(2)]
63824pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
63825 static_assert!(1 <= N && N <= 8);
63826 vshiftins_v8i8(a, b, int8x8_t::splat(-N as i8))
63827}
63828#[doc = "Shift Right and Insert (immediate)"]
63829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
63830#[inline]
63831#[target_feature(enable = "neon,v7")]
63832#[cfg(target_arch = "arm")]
63833#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63834#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63835#[rustc_legacy_const_generics(2)]
63836pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
63837 static_assert!(1 <= N && N <= 8);
63838 vshiftins_v16i8(a, b, int8x16_t::splat(-N as i8))
63839}
63840#[doc = "Shift Right and Insert (immediate)"]
63841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
63842#[inline]
63843#[target_feature(enable = "neon,v7")]
63844#[cfg(target_arch = "arm")]
63845#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63846#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63847#[rustc_legacy_const_generics(2)]
63848pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
63849 static_assert!(1 <= N && N <= 16);
63850 vshiftins_v4i16(a, b, int16x4_t::splat(-N as i16))
63851}
63852#[doc = "Shift Right and Insert (immediate)"]
63853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
63854#[inline]
63855#[target_feature(enable = "neon,v7")]
63856#[cfg(target_arch = "arm")]
63857#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63858#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63859#[rustc_legacy_const_generics(2)]
63860pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
63861 static_assert!(1 <= N && N <= 16);
63862 vshiftins_v8i16(a, b, int16x8_t::splat(-N as i16))
63863}
63864#[doc = "Shift Right and Insert (immediate)"]
63865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
63866#[inline]
63867#[target_feature(enable = "neon,v7")]
63868#[cfg(target_arch = "arm")]
63869#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63870#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63871#[rustc_legacy_const_generics(2)]
63872pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
63873 static_assert!(1 <= N && N <= 32);
63874 vshiftins_v2i32(a, b, int32x2_t::splat(-N as i32))
63875}
63876#[doc = "Shift Right and Insert (immediate)"]
63877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
63878#[inline]
63879#[target_feature(enable = "neon,v7")]
63880#[cfg(target_arch = "arm")]
63881#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63882#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63883#[rustc_legacy_const_generics(2)]
63884pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
63885 static_assert!(1 <= N && N <= 32);
63886 vshiftins_v4i32(a, b, int32x4_t::splat(-N as i32))
63887}
63888#[doc = "Shift Right and Insert (immediate)"]
63889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
63890#[inline]
63891#[target_feature(enable = "neon,v7")]
63892#[cfg(target_arch = "arm")]
63893#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63894#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63895#[rustc_legacy_const_generics(2)]
63896pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
63897 static_assert!(1 <= N && N <= 64);
63898 vshiftins_v1i64(a, b, int64x1_t::splat(-N as i64))
63899}
63900#[doc = "Shift Right and Insert (immediate)"]
63901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
63902#[inline]
63903#[target_feature(enable = "neon,v7")]
63904#[cfg(target_arch = "arm")]
63905#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63906#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63907#[rustc_legacy_const_generics(2)]
63908pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
63909 static_assert!(1 <= N && N <= 64);
63910 vshiftins_v2i64(a, b, int64x2_t::splat(-N as i64))
63911}
63912#[doc = "Shift Right and Insert (immediate)"]
63913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
63914#[inline]
63915#[cfg(target_arch = "arm")]
63916#[target_feature(enable = "neon,v7")]
63917#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63918#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63919#[rustc_legacy_const_generics(2)]
63920pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
63921 static_assert!(1 <= N && N <= 8);
63922 unsafe {
63923 transmute(vshiftins_v8i8(
63924 transmute(a),
63925 transmute(b),
63926 int8x8_t::splat(-N as i8),
63927 ))
63928 }
63929}
63930#[doc = "Shift Right and Insert (immediate)"]
63931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
63932#[inline]
63933#[cfg(target_arch = "arm")]
63934#[target_feature(enable = "neon,v7")]
63935#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63936#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63937#[rustc_legacy_const_generics(2)]
63938pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
63939 static_assert!(1 <= N && N <= 8);
63940 unsafe {
63941 transmute(vshiftins_v16i8(
63942 transmute(a),
63943 transmute(b),
63944 int8x16_t::splat(-N as i8),
63945 ))
63946 }
63947}
63948#[doc = "Shift Right and Insert (immediate)"]
63949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
63950#[inline]
63951#[cfg(target_arch = "arm")]
63952#[target_feature(enable = "neon,v7")]
63953#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63954#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63955#[rustc_legacy_const_generics(2)]
63956pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
63957 static_assert!(1 <= N && N <= 16);
63958 unsafe {
63959 transmute(vshiftins_v4i16(
63960 transmute(a),
63961 transmute(b),
63962 int16x4_t::splat(-N as i16),
63963 ))
63964 }
63965}
63966#[doc = "Shift Right and Insert (immediate)"]
63967#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
63968#[inline]
63969#[cfg(target_arch = "arm")]
63970#[target_feature(enable = "neon,v7")]
63971#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63972#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63973#[rustc_legacy_const_generics(2)]
63974pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
63975 static_assert!(1 <= N && N <= 16);
63976 unsafe {
63977 transmute(vshiftins_v8i16(
63978 transmute(a),
63979 transmute(b),
63980 int16x8_t::splat(-N as i16),
63981 ))
63982 }
63983}
63984#[doc = "Shift Right and Insert (immediate)"]
63985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
63986#[inline]
63987#[cfg(target_arch = "arm")]
63988#[target_feature(enable = "neon,v7")]
63989#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63990#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63991#[rustc_legacy_const_generics(2)]
63992pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
63993 static_assert!(1 <= N && N <= 32);
63994 unsafe {
63995 transmute(vshiftins_v2i32(
63996 transmute(a),
63997 transmute(b),
63998 int32x2_t::splat(-N),
63999 ))
64000 }
64001}
64002#[doc = "Shift Right and Insert (immediate)"]
64003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
64004#[inline]
64005#[cfg(target_arch = "arm")]
64006#[target_feature(enable = "neon,v7")]
64007#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64008#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
64009#[rustc_legacy_const_generics(2)]
64010pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
64011 static_assert!(1 <= N && N <= 32);
64012 unsafe {
64013 transmute(vshiftins_v4i32(
64014 transmute(a),
64015 transmute(b),
64016 int32x4_t::splat(-N),
64017 ))
64018 }
64019}
64020#[doc = "Shift Right and Insert (immediate)"]
64021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
64022#[inline]
64023#[cfg(target_arch = "arm")]
64024#[target_feature(enable = "neon,v7")]
64025#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64026#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
64027#[rustc_legacy_const_generics(2)]
64028pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
64029 static_assert!(1 <= N && N <= 64);
64030 unsafe {
64031 transmute(vshiftins_v1i64(
64032 transmute(a),
64033 transmute(b),
64034 int64x1_t::splat(-N as i64),
64035 ))
64036 }
64037}
64038#[doc = "Shift Right and Insert (immediate)"]
64039#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
64040#[inline]
64041#[cfg(target_arch = "arm")]
64042#[target_feature(enable = "neon,v7")]
64043#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64044#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
64045#[rustc_legacy_const_generics(2)]
64046pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
64047 static_assert!(1 <= N && N <= 64);
64048 unsafe {
64049 transmute(vshiftins_v2i64(
64050 transmute(a),
64051 transmute(b),
64052 int64x2_t::splat(-N as i64),
64053 ))
64054 }
64055}
64056#[doc = "Shift Right and Insert (immediate)"]
64057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
64058#[inline]
64059#[cfg(target_arch = "arm")]
64060#[target_feature(enable = "neon,v7")]
64061#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64062#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
64063#[rustc_legacy_const_generics(2)]
64064pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
64065 static_assert!(1 <= N && N <= 8);
64066 unsafe {
64067 transmute(vshiftins_v8i8(
64068 transmute(a),
64069 transmute(b),
64070 int8x8_t::splat(-N as i8),
64071 ))
64072 }
64073}
64074#[doc = "Shift Right and Insert (immediate)"]
64075#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
64076#[inline]
64077#[cfg(target_arch = "arm")]
64078#[target_feature(enable = "neon,v7")]
64079#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64080#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
64081#[rustc_legacy_const_generics(2)]
64082pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
64083 static_assert!(1 <= N && N <= 8);
64084 unsafe {
64085 transmute(vshiftins_v16i8(
64086 transmute(a),
64087 transmute(b),
64088 int8x16_t::splat(-N as i8),
64089 ))
64090 }
64091}
64092#[doc = "Shift Right and Insert (immediate)"]
64093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
64094#[inline]
64095#[cfg(target_arch = "arm")]
64096#[target_feature(enable = "neon,v7")]
64097#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64098#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
64099#[rustc_legacy_const_generics(2)]
64100pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
64101 static_assert!(1 <= N && N <= 16);
64102 unsafe {
64103 transmute(vshiftins_v4i16(
64104 transmute(a),
64105 transmute(b),
64106 int16x4_t::splat(-N as i16),
64107 ))
64108 }
64109}
64110#[doc = "Shift Right and Insert (immediate)"]
64111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
64112#[inline]
64113#[cfg(target_arch = "arm")]
64114#[target_feature(enable = "neon,v7")]
64115#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64116#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
64117#[rustc_legacy_const_generics(2)]
64118pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
64119 static_assert!(1 <= N && N <= 16);
64120 unsafe {
64121 transmute(vshiftins_v8i16(
64122 transmute(a),
64123 transmute(b),
64124 int16x8_t::splat(-N as i16),
64125 ))
64126 }
64127}
64128#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
64130#[doc = "## Safety"]
64131#[doc = " * Neon instrinsic unsafe"]
64132#[inline]
64133#[cfg(target_arch = "arm")]
64134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64135#[target_feature(enable = "neon,fp16")]
64136#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64137#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64138pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
64139 vst1_v4f16(
64140 ptr as *const i8,
64141 transmute(a),
64142 crate::mem::align_of::<f16>() as i32,
64143 )
64144}
64145#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
64147#[doc = "## Safety"]
64148#[doc = " * Neon instrinsic unsafe"]
64149#[inline]
64150#[cfg(target_arch = "arm")]
64151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64152#[target_feature(enable = "neon,fp16")]
64153#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64154#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64155pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
64156 vst1q_v8f16(
64157 ptr as *const i8,
64158 transmute(a),
64159 crate::mem::align_of::<f16>() as i32,
64160 )
64161}
64162#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
64164#[doc = "## Safety"]
64165#[doc = " * Neon instrinsic unsafe"]
64166#[inline]
64167#[cfg(target_arch = "arm")]
64168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64169#[cfg_attr(test, assert_instr(vst1))]
64170#[target_feature(enable = "neon,fp16")]
64171#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64172pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
64173 unsafe extern "unadjusted" {
64174 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0f16.v4f16")]
64175 fn _vst1_f16_x2(ptr: *mut f16, a: float16x4_t, b: float16x4_t);
64176 }
64177 _vst1_f16_x2(a, b.0, b.1)
64178}
64179#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
64181#[doc = "## Safety"]
64182#[doc = " * Neon instrinsic unsafe"]
64183#[inline]
64184#[cfg(target_arch = "arm")]
64185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64186#[cfg_attr(test, assert_instr(vst1))]
64187#[target_feature(enable = "neon,fp16")]
64188#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64189pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
64190 unsafe extern "unadjusted" {
64191 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0f16.v8f16")]
64192 fn _vst1q_f16_x2(ptr: *mut f16, a: float16x8_t, b: float16x8_t);
64193 }
64194 _vst1q_f16_x2(a, b.0, b.1)
64195}
64196#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64197#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
64198#[doc = "## Safety"]
64199#[doc = " * Neon instrinsic unsafe"]
64200#[inline]
64201#[cfg(not(target_arch = "arm"))]
64202#[cfg_attr(test, assert_instr(st1))]
64203#[target_feature(enable = "neon,fp16")]
64204#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64205pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
64206 unsafe extern "unadjusted" {
64207 #[cfg_attr(
64208 any(target_arch = "aarch64", target_arch = "arm64ec"),
64209 link_name = "llvm.aarch64.neon.st1x2.v4f16.p0f16"
64210 )]
64211 fn _vst1_f16_x2(a: float16x4_t, b: float16x4_t, ptr: *mut f16);
64212 }
64213 _vst1_f16_x2(b.0, b.1, a)
64214}
64215#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
64217#[doc = "## Safety"]
64218#[doc = " * Neon instrinsic unsafe"]
64219#[inline]
64220#[cfg(not(target_arch = "arm"))]
64221#[cfg_attr(test, assert_instr(st1))]
64222#[target_feature(enable = "neon,fp16")]
64223#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64224pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
64225 unsafe extern "unadjusted" {
64226 #[cfg_attr(
64227 any(target_arch = "aarch64", target_arch = "arm64ec"),
64228 link_name = "llvm.aarch64.neon.st1x2.v8f16.p0f16"
64229 )]
64230 fn _vst1q_f16_x2(a: float16x8_t, b: float16x8_t, ptr: *mut f16);
64231 }
64232 _vst1q_f16_x2(b.0, b.1, a)
64233}
64234#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
64236#[doc = "## Safety"]
64237#[doc = " * Neon instrinsic unsafe"]
64238#[inline]
64239#[cfg(target_arch = "arm")]
64240#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64241#[cfg_attr(test, assert_instr(vst1))]
64242#[target_feature(enable = "neon,fp16")]
64243#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64244pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
64245 unsafe extern "unadjusted" {
64246 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0f16.v4f16")]
64247 fn _vst1_f16_x3(ptr: *mut f16, a: float16x4_t, b: float16x4_t, c: float16x4_t);
64248 }
64249 _vst1_f16_x3(a, b.0, b.1, b.2)
64250}
64251#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
64253#[doc = "## Safety"]
64254#[doc = " * Neon instrinsic unsafe"]
64255#[inline]
64256#[cfg(target_arch = "arm")]
64257#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64258#[cfg_attr(test, assert_instr(vst1))]
64259#[target_feature(enable = "neon,fp16")]
64260#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64261pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
64262 unsafe extern "unadjusted" {
64263 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0f16.v8f16")]
64264 fn _vst1q_f16_x3(ptr: *mut f16, a: float16x8_t, b: float16x8_t, c: float16x8_t);
64265 }
64266 _vst1q_f16_x3(a, b.0, b.1, b.2)
64267}
64268#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64269#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
64270#[doc = "## Safety"]
64271#[doc = " * Neon instrinsic unsafe"]
64272#[inline]
64273#[cfg(not(target_arch = "arm"))]
64274#[cfg_attr(test, assert_instr(st1))]
64275#[target_feature(enable = "neon,fp16")]
64276#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64277pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
64278 unsafe extern "unadjusted" {
64279 #[cfg_attr(
64280 any(target_arch = "aarch64", target_arch = "arm64ec"),
64281 link_name = "llvm.aarch64.neon.st1x3.v4f16.p0f16"
64282 )]
64283 fn _vst1_f16_x3(a: float16x4_t, b: float16x4_t, c: float16x4_t, ptr: *mut f16);
64284 }
64285 _vst1_f16_x3(b.0, b.1, b.2, a)
64286}
64287#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
64289#[doc = "## Safety"]
64290#[doc = " * Neon instrinsic unsafe"]
64291#[inline]
64292#[cfg(not(target_arch = "arm"))]
64293#[cfg_attr(test, assert_instr(st1))]
64294#[target_feature(enable = "neon,fp16")]
64295#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64296pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
64297 unsafe extern "unadjusted" {
64298 #[cfg_attr(
64299 any(target_arch = "aarch64", target_arch = "arm64ec"),
64300 link_name = "llvm.aarch64.neon.st1x3.v8f16.p0f16"
64301 )]
64302 fn _vst1q_f16_x3(a: float16x8_t, b: float16x8_t, c: float16x8_t, ptr: *mut f16);
64303 }
64304 _vst1q_f16_x3(b.0, b.1, b.2, a)
64305}
64306#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
64308#[doc = "## Safety"]
64309#[doc = " * Neon instrinsic unsafe"]
64310#[inline]
64311#[cfg(target_arch = "arm")]
64312#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64313#[target_feature(enable = "neon,fp16")]
64314#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64315#[cfg_attr(test, assert_instr(vst1))]
64316pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
64317 unsafe extern "unadjusted" {
64318 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f16.v4f16")]
64319 fn _vst1_f16_x4(
64320 ptr: *mut f16,
64321 a: float16x4_t,
64322 b: float16x4_t,
64323 c: float16x4_t,
64324 d: float16x4_t,
64325 );
64326 }
64327 _vst1_f16_x4(a, b.0, b.1, b.2, b.3)
64328}
64329#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
64331#[doc = "## Safety"]
64332#[doc = " * Neon instrinsic unsafe"]
64333#[inline]
64334#[cfg(target_arch = "arm")]
64335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64336#[target_feature(enable = "neon,fp16")]
64337#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64338#[cfg_attr(test, assert_instr(vst1))]
64339pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
64340 unsafe extern "unadjusted" {
64341 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f16.v8f16")]
64342 fn _vst1q_f16_x4(
64343 ptr: *mut f16,
64344 a: float16x8_t,
64345 b: float16x8_t,
64346 c: float16x8_t,
64347 d: float16x8_t,
64348 );
64349 }
64350 _vst1q_f16_x4(a, b.0, b.1, b.2, b.3)
64351}
64352#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
64354#[doc = "## Safety"]
64355#[doc = " * Neon instrinsic unsafe"]
64356#[inline]
64357#[cfg(not(target_arch = "arm"))]
64358#[cfg_attr(test, assert_instr(st1))]
64359#[target_feature(enable = "neon,fp16")]
64360#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64361pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
64362 unsafe extern "unadjusted" {
64363 #[cfg_attr(
64364 any(target_arch = "aarch64", target_arch = "arm64ec"),
64365 link_name = "llvm.aarch64.neon.st1x4.v4f16.p0f16"
64366 )]
64367 fn _vst1_f16_x4(
64368 a: float16x4_t,
64369 b: float16x4_t,
64370 c: float16x4_t,
64371 d: float16x4_t,
64372 ptr: *mut f16,
64373 );
64374 }
64375 _vst1_f16_x4(b.0, b.1, b.2, b.3, a)
64376}
64377#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
64379#[doc = "## Safety"]
64380#[doc = " * Neon instrinsic unsafe"]
64381#[inline]
64382#[cfg(not(target_arch = "arm"))]
64383#[cfg_attr(test, assert_instr(st1))]
64384#[target_feature(enable = "neon,fp16")]
64385#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64386pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
64387 unsafe extern "unadjusted" {
64388 #[cfg_attr(
64389 any(target_arch = "aarch64", target_arch = "arm64ec"),
64390 link_name = "llvm.aarch64.neon.st1x4.v8f16.p0f16"
64391 )]
64392 fn _vst1q_f16_x4(
64393 a: float16x8_t,
64394 b: float16x8_t,
64395 c: float16x8_t,
64396 d: float16x8_t,
64397 ptr: *mut f16,
64398 );
64399 }
64400 _vst1q_f16_x4(b.0, b.1, b.2, b.3, a)
64401}
64402#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
64404#[doc = "## Safety"]
64405#[doc = " * Neon instrinsic unsafe"]
64406#[inline]
64407#[target_feature(enable = "neon")]
64408#[cfg(target_arch = "arm")]
64409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64410#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64411#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64412pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
64413 vst1_v2f32(
64414 ptr as *const i8,
64415 transmute(a),
64416 crate::mem::align_of::<f32>() as i32,
64417 )
64418}
64419#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
64421#[doc = "## Safety"]
64422#[doc = " * Neon instrinsic unsafe"]
64423#[inline]
64424#[target_feature(enable = "neon")]
64425#[cfg(target_arch = "arm")]
64426#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64427#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64428#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64429pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
64430 vst1q_v4f32(
64431 ptr as *const i8,
64432 transmute(a),
64433 crate::mem::align_of::<f32>() as i32,
64434 )
64435}
64436#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
64438#[doc = "## Safety"]
64439#[doc = " * Neon instrinsic unsafe"]
64440#[inline]
64441#[target_feature(enable = "neon")]
64442#[cfg(target_arch = "arm")]
64443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64444#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64445#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64446pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
64447 vst1_v8i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
64448}
64449#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
64451#[doc = "## Safety"]
64452#[doc = " * Neon instrinsic unsafe"]
64453#[inline]
64454#[target_feature(enable = "neon")]
64455#[cfg(target_arch = "arm")]
64456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64457#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64458#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64459pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
64460 vst1q_v16i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
64461}
64462#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
64464#[doc = "## Safety"]
64465#[doc = " * Neon instrinsic unsafe"]
64466#[inline]
64467#[target_feature(enable = "neon")]
64468#[cfg(target_arch = "arm")]
64469#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64470#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64471#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64472pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
64473 vst1_v4i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
64474}
64475#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
64477#[doc = "## Safety"]
64478#[doc = " * Neon instrinsic unsafe"]
64479#[inline]
64480#[target_feature(enable = "neon")]
64481#[cfg(target_arch = "arm")]
64482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64483#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64484#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64485pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
64486 vst1q_v8i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
64487}
64488#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64489#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
64490#[doc = "## Safety"]
64491#[doc = " * Neon instrinsic unsafe"]
64492#[inline]
64493#[target_feature(enable = "neon")]
64494#[cfg(target_arch = "arm")]
64495#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64496#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64497#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64498pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
64499 vst1_v2i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
64500}
64501#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
64503#[doc = "## Safety"]
64504#[doc = " * Neon instrinsic unsafe"]
64505#[inline]
64506#[target_feature(enable = "neon")]
64507#[cfg(target_arch = "arm")]
64508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64509#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64510#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64511pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
64512 vst1q_v4i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
64513}
64514#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
64516#[doc = "## Safety"]
64517#[doc = " * Neon instrinsic unsafe"]
64518#[inline]
64519#[target_feature(enable = "neon")]
64520#[cfg(target_arch = "arm")]
64521#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64522#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64523#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64524pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
64525 vst1_v1i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
64526}
64527#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
64529#[doc = "## Safety"]
64530#[doc = " * Neon instrinsic unsafe"]
64531#[inline]
64532#[target_feature(enable = "neon")]
64533#[cfg(target_arch = "arm")]
64534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64535#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64536#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64537pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
64538 vst1q_v2i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
64539}
64540#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
64542#[doc = "## Safety"]
64543#[doc = " * Neon instrinsic unsafe"]
64544#[inline]
64545#[target_feature(enable = "neon")]
64546#[cfg(target_arch = "arm")]
64547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64548#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64549#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64550pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
64551 vst1_v8i8(
64552 ptr as *const i8,
64553 transmute(a),
64554 crate::mem::align_of::<u8>() as i32,
64555 )
64556}
64557#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
64559#[doc = "## Safety"]
64560#[doc = " * Neon instrinsic unsafe"]
64561#[inline]
64562#[target_feature(enable = "neon")]
64563#[cfg(target_arch = "arm")]
64564#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64565#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64566#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64567pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
64568 vst1q_v16i8(
64569 ptr as *const i8,
64570 transmute(a),
64571 crate::mem::align_of::<u8>() as i32,
64572 )
64573}
64574#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
64576#[doc = "## Safety"]
64577#[doc = " * Neon instrinsic unsafe"]
64578#[inline]
64579#[target_feature(enable = "neon")]
64580#[cfg(target_arch = "arm")]
64581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64582#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64583#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64584pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
64585 vst1_v4i16(
64586 ptr as *const i8,
64587 transmute(a),
64588 crate::mem::align_of::<u16>() as i32,
64589 )
64590}
64591#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
64593#[doc = "## Safety"]
64594#[doc = " * Neon instrinsic unsafe"]
64595#[inline]
64596#[target_feature(enable = "neon")]
64597#[cfg(target_arch = "arm")]
64598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64599#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64600#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64601pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
64602 vst1q_v8i16(
64603 ptr as *const i8,
64604 transmute(a),
64605 crate::mem::align_of::<u16>() as i32,
64606 )
64607}
64608#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
64610#[doc = "## Safety"]
64611#[doc = " * Neon instrinsic unsafe"]
64612#[inline]
64613#[target_feature(enable = "neon")]
64614#[cfg(target_arch = "arm")]
64615#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64616#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64617#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64618pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
64619 vst1_v2i32(
64620 ptr as *const i8,
64621 transmute(a),
64622 crate::mem::align_of::<u32>() as i32,
64623 )
64624}
64625#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
64627#[doc = "## Safety"]
64628#[doc = " * Neon instrinsic unsafe"]
64629#[inline]
64630#[target_feature(enable = "neon")]
64631#[cfg(target_arch = "arm")]
64632#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64633#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64634#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64635pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
64636 vst1q_v4i32(
64637 ptr as *const i8,
64638 transmute(a),
64639 crate::mem::align_of::<u32>() as i32,
64640 )
64641}
64642#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
64644#[doc = "## Safety"]
64645#[doc = " * Neon instrinsic unsafe"]
64646#[inline]
64647#[target_feature(enable = "neon")]
64648#[cfg(target_arch = "arm")]
64649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64650#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64651#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64652pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
64653 vst1_v1i64(
64654 ptr as *const i8,
64655 transmute(a),
64656 crate::mem::align_of::<u64>() as i32,
64657 )
64658}
64659#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
64661#[doc = "## Safety"]
64662#[doc = " * Neon instrinsic unsafe"]
64663#[inline]
64664#[target_feature(enable = "neon")]
64665#[cfg(target_arch = "arm")]
64666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64667#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64668#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64669pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
64670 vst1q_v2i64(
64671 ptr as *const i8,
64672 transmute(a),
64673 crate::mem::align_of::<u64>() as i32,
64674 )
64675}
64676#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64677#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
64678#[doc = "## Safety"]
64679#[doc = " * Neon instrinsic unsafe"]
64680#[inline]
64681#[target_feature(enable = "neon")]
64682#[cfg(target_arch = "arm")]
64683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64684#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64685#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64686pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
64687 vst1_v8i8(
64688 ptr as *const i8,
64689 transmute(a),
64690 crate::mem::align_of::<p8>() as i32,
64691 )
64692}
64693#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
64695#[doc = "## Safety"]
64696#[doc = " * Neon instrinsic unsafe"]
64697#[inline]
64698#[target_feature(enable = "neon")]
64699#[cfg(target_arch = "arm")]
64700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64701#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64702#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64703pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
64704 vst1q_v16i8(
64705 ptr as *const i8,
64706 transmute(a),
64707 crate::mem::align_of::<p8>() as i32,
64708 )
64709}
64710#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
64712#[doc = "## Safety"]
64713#[doc = " * Neon instrinsic unsafe"]
64714#[inline]
64715#[target_feature(enable = "neon")]
64716#[cfg(target_arch = "arm")]
64717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64718#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64719#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64720pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
64721 vst1_v4i16(
64722 ptr as *const i8,
64723 transmute(a),
64724 crate::mem::align_of::<p16>() as i32,
64725 )
64726}
64727#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
64729#[doc = "## Safety"]
64730#[doc = " * Neon instrinsic unsafe"]
64731#[inline]
64732#[target_feature(enable = "neon")]
64733#[cfg(target_arch = "arm")]
64734#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64735#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64736#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64737pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
64738 vst1q_v8i16(
64739 ptr as *const i8,
64740 transmute(a),
64741 crate::mem::align_of::<p16>() as i32,
64742 )
64743}
64744#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
64746#[doc = "## Safety"]
64747#[doc = " * Neon instrinsic unsafe"]
64748#[inline]
64749#[target_feature(enable = "neon")]
64750#[cfg(target_arch = "arm")]
64751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64752#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64753#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64754pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
64755 vst1_v1i64(
64756 ptr as *const i8,
64757 transmute(a),
64758 crate::mem::align_of::<p64>() as i32,
64759 )
64760}
64761#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
64763#[doc = "## Safety"]
64764#[doc = " * Neon instrinsic unsafe"]
64765#[inline]
64766#[target_feature(enable = "neon")]
64767#[cfg(target_arch = "arm")]
64768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64769#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64770#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64771pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
64772 vst1q_v2i64(
64773 ptr as *const i8,
64774 transmute(a),
64775 crate::mem::align_of::<p64>() as i32,
64776 )
64777}
64778#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
64780#[doc = "## Safety"]
64781#[doc = " * Neon instrinsic unsafe"]
64782#[inline]
64783#[cfg(target_arch = "arm")]
64784#[target_feature(enable = "neon,v7")]
64785#[cfg_attr(test, assert_instr(vst1))]
64786#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64787pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
64788 unsafe extern "unadjusted" {
64789 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2f32.p0")]
64790 fn _vst1_f32_x2(ptr: *mut f32, a: float32x2_t, b: float32x2_t);
64791 }
64792 _vst1_f32_x2(a, b.0, b.1)
64793}
64794#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
64796#[doc = "## Safety"]
64797#[doc = " * Neon instrinsic unsafe"]
64798#[inline]
64799#[cfg(target_arch = "arm")]
64800#[target_feature(enable = "neon,v7")]
64801#[cfg_attr(test, assert_instr(vst1))]
64802#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64803pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
64804 unsafe extern "unadjusted" {
64805 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4f32.p0")]
64806 fn _vst1q_f32_x2(ptr: *mut f32, a: float32x4_t, b: float32x4_t);
64807 }
64808 _vst1q_f32_x2(a, b.0, b.1)
64809}
64810#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
64812#[doc = "## Safety"]
64813#[doc = " * Neon instrinsic unsafe"]
64814#[inline]
64815#[target_feature(enable = "neon")]
64816#[cfg(not(target_arch = "arm"))]
64817#[cfg_attr(test, assert_instr(st1))]
64818#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64819pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
64820 unsafe extern "unadjusted" {
64821 #[cfg_attr(
64822 any(target_arch = "aarch64", target_arch = "arm64ec"),
64823 link_name = "llvm.aarch64.neon.st1x2.v2f32.p0f32"
64824 )]
64825 fn _vst1_f32_x2(a: float32x2_t, b: float32x2_t, ptr: *mut f32);
64826 }
64827 _vst1_f32_x2(b.0, b.1, a)
64828}
64829#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
64831#[doc = "## Safety"]
64832#[doc = " * Neon instrinsic unsafe"]
64833#[inline]
64834#[target_feature(enable = "neon")]
64835#[cfg(not(target_arch = "arm"))]
64836#[cfg_attr(test, assert_instr(st1))]
64837#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64838pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
64839 unsafe extern "unadjusted" {
64840 #[cfg_attr(
64841 any(target_arch = "aarch64", target_arch = "arm64ec"),
64842 link_name = "llvm.aarch64.neon.st1x2.v4f32.p0f32"
64843 )]
64844 fn _vst1q_f32_x2(a: float32x4_t, b: float32x4_t, ptr: *mut f32);
64845 }
64846 _vst1q_f32_x2(b.0, b.1, a)
64847}
64848#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"]
64850#[doc = "## Safety"]
64851#[doc = " * Neon instrinsic unsafe"]
64852#[inline]
64853#[target_feature(enable = "neon")]
64854#[cfg(not(target_arch = "arm"))]
64855#[cfg_attr(test, assert_instr(st1))]
64856#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64857pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) {
64858 unsafe extern "unadjusted" {
64859 #[cfg_attr(
64860 any(target_arch = "aarch64", target_arch = "arm64ec"),
64861 link_name = "llvm.aarch64.neon.st1x3.v2f32.p0f32"
64862 )]
64863 fn _vst1_f32_x3(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut f32);
64864 }
64865 _vst1_f32_x3(b.0, b.1, b.2, a)
64866}
64867#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"]
64869#[doc = "## Safety"]
64870#[doc = " * Neon instrinsic unsafe"]
64871#[inline]
64872#[target_feature(enable = "neon")]
64873#[cfg(not(target_arch = "arm"))]
64874#[cfg_attr(test, assert_instr(st1))]
64875#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64876pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) {
64877 unsafe extern "unadjusted" {
64878 #[cfg_attr(
64879 any(target_arch = "aarch64", target_arch = "arm64ec"),
64880 link_name = "llvm.aarch64.neon.st1x3.v4f32.p0f32"
64881 )]
64882 fn _vst1q_f32_x3(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut f32);
64883 }
64884 _vst1q_f32_x3(b.0, b.1, b.2, a)
64885}
64886#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
64888#[doc = "## Safety"]
64889#[doc = " * Neon instrinsic unsafe"]
64890#[inline]
64891#[cfg(target_arch = "arm")]
64892#[target_feature(enable = "neon,v7")]
64893#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64894#[cfg_attr(test, assert_instr(vst1))]
64895pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
64896 unsafe extern "unadjusted" {
64897 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f32.v2f32.p0")]
64898 fn _vst1_f32_x4(
64899 ptr: *mut f32,
64900 a: float32x2_t,
64901 b: float32x2_t,
64902 c: float32x2_t,
64903 d: float32x2_t,
64904 );
64905 }
64906 _vst1_f32_x4(a, b.0, b.1, b.2, b.3)
64907}
64908#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
64910#[doc = "## Safety"]
64911#[doc = " * Neon instrinsic unsafe"]
64912#[inline]
64913#[cfg(target_arch = "arm")]
64914#[target_feature(enable = "neon,v7")]
64915#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64916#[cfg_attr(test, assert_instr(vst1))]
64917pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
64918 unsafe extern "unadjusted" {
64919 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f32.v4f32.p0")]
64920 fn _vst1q_f32_x4(
64921 ptr: *mut f32,
64922 a: float32x4_t,
64923 b: float32x4_t,
64924 c: float32x4_t,
64925 d: float32x4_t,
64926 );
64927 }
64928 _vst1q_f32_x4(a, b.0, b.1, b.2, b.3)
64929}
64930#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
64932#[doc = "## Safety"]
64933#[doc = " * Neon instrinsic unsafe"]
64934#[inline]
64935#[target_feature(enable = "neon")]
64936#[cfg(not(target_arch = "arm"))]
64937#[cfg_attr(test, assert_instr(st1))]
64938#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64939pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
64940 unsafe extern "unadjusted" {
64941 #[cfg_attr(
64942 any(target_arch = "aarch64", target_arch = "arm64ec"),
64943 link_name = "llvm.aarch64.neon.st1x4.v2f32.p0f32"
64944 )]
64945 fn _vst1_f32_x4(
64946 a: float32x2_t,
64947 b: float32x2_t,
64948 c: float32x2_t,
64949 d: float32x2_t,
64950 ptr: *mut f32,
64951 );
64952 }
64953 _vst1_f32_x4(b.0, b.1, b.2, b.3, a)
64954}
64955#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64956#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
64957#[doc = "## Safety"]
64958#[doc = " * Neon instrinsic unsafe"]
64959#[inline]
64960#[target_feature(enable = "neon")]
64961#[cfg(not(target_arch = "arm"))]
64962#[cfg_attr(test, assert_instr(st1))]
64963#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64964pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
64965 unsafe extern "unadjusted" {
64966 #[cfg_attr(
64967 any(target_arch = "aarch64", target_arch = "arm64ec"),
64968 link_name = "llvm.aarch64.neon.st1x4.v4f32.p0f32"
64969 )]
64970 fn _vst1q_f32_x4(
64971 a: float32x4_t,
64972 b: float32x4_t,
64973 c: float32x4_t,
64974 d: float32x4_t,
64975 ptr: *mut f32,
64976 );
64977 }
64978 _vst1q_f32_x4(b.0, b.1, b.2, b.3, a)
64979}
64980#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"]
64982#[doc = "## Safety"]
64983#[doc = " * Neon instrinsic unsafe"]
64984#[inline]
64985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64986#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64987#[cfg_attr(
64988 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64989 assert_instr(nop, LANE = 0)
64990)]
64991#[rustc_legacy_const_generics(2)]
64992#[target_feature(enable = "neon,fp16")]
64993#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64994pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
64995 static_assert_uimm_bits!(LANE, 2);
64996 *a = simd_extract!(b, LANE as u32);
64997}
64998#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64999#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"]
65000#[doc = "## Safety"]
65001#[doc = " * Neon instrinsic unsafe"]
65002#[inline]
65003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65005#[cfg_attr(
65006 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65007 assert_instr(nop, LANE = 0)
65008)]
65009#[rustc_legacy_const_generics(2)]
65010#[target_feature(enable = "neon,fp16")]
65011#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
65012pub unsafe fn vst1q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8_t) {
65013 static_assert_uimm_bits!(LANE, 3);
65014 *a = simd_extract!(b, LANE as u32);
65015}
65016#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"]
65018#[doc = "## Safety"]
65019#[doc = " * Neon instrinsic unsafe"]
65020#[inline]
65021#[target_feature(enable = "neon")]
65022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65023#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65024#[cfg_attr(
65025 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65026 assert_instr(nop, LANE = 0)
65027)]
65028#[rustc_legacy_const_generics(2)]
65029#[cfg_attr(
65030 not(target_arch = "arm"),
65031 stable(feature = "neon_intrinsics", since = "1.59.0")
65032)]
65033#[cfg_attr(
65034 target_arch = "arm",
65035 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65036)]
65037pub unsafe fn vst1_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2_t) {
65038 static_assert_uimm_bits!(LANE, 1);
65039 *a = simd_extract!(b, LANE as u32);
65040}
65041#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"]
65043#[doc = "## Safety"]
65044#[doc = " * Neon instrinsic unsafe"]
65045#[inline]
65046#[target_feature(enable = "neon")]
65047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65048#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65049#[cfg_attr(
65050 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65051 assert_instr(nop, LANE = 0)
65052)]
65053#[rustc_legacy_const_generics(2)]
65054#[cfg_attr(
65055 not(target_arch = "arm"),
65056 stable(feature = "neon_intrinsics", since = "1.59.0")
65057)]
65058#[cfg_attr(
65059 target_arch = "arm",
65060 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65061)]
65062pub unsafe fn vst1q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4_t) {
65063 static_assert_uimm_bits!(LANE, 2);
65064 *a = simd_extract!(b, LANE as u32);
65065}
65066#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"]
65068#[doc = "## Safety"]
65069#[doc = " * Neon instrinsic unsafe"]
65070#[inline]
65071#[target_feature(enable = "neon")]
65072#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65073#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65074#[cfg_attr(
65075 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65076 assert_instr(nop, LANE = 0)
65077)]
65078#[rustc_legacy_const_generics(2)]
65079#[cfg_attr(
65080 not(target_arch = "arm"),
65081 stable(feature = "neon_intrinsics", since = "1.59.0")
65082)]
65083#[cfg_attr(
65084 target_arch = "arm",
65085 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65086)]
65087pub unsafe fn vst1_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8_t) {
65088 static_assert_uimm_bits!(LANE, 3);
65089 *a = simd_extract!(b, LANE as u32);
65090}
65091#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"]
65093#[doc = "## Safety"]
65094#[doc = " * Neon instrinsic unsafe"]
65095#[inline]
65096#[target_feature(enable = "neon")]
65097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65099#[cfg_attr(
65100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65101 assert_instr(nop, LANE = 0)
65102)]
65103#[rustc_legacy_const_generics(2)]
65104#[cfg_attr(
65105 not(target_arch = "arm"),
65106 stable(feature = "neon_intrinsics", since = "1.59.0")
65107)]
65108#[cfg_attr(
65109 target_arch = "arm",
65110 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65111)]
65112pub unsafe fn vst1q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16_t) {
65113 static_assert_uimm_bits!(LANE, 4);
65114 *a = simd_extract!(b, LANE as u32);
65115}
65116#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"]
65118#[doc = "## Safety"]
65119#[doc = " * Neon instrinsic unsafe"]
65120#[inline]
65121#[target_feature(enable = "neon")]
65122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65123#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65124#[cfg_attr(
65125 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65126 assert_instr(nop, LANE = 0)
65127)]
65128#[rustc_legacy_const_generics(2)]
65129#[cfg_attr(
65130 not(target_arch = "arm"),
65131 stable(feature = "neon_intrinsics", since = "1.59.0")
65132)]
65133#[cfg_attr(
65134 target_arch = "arm",
65135 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65136)]
65137pub unsafe fn vst1_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4_t) {
65138 static_assert_uimm_bits!(LANE, 2);
65139 *a = simd_extract!(b, LANE as u32);
65140}
65141#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"]
65143#[doc = "## Safety"]
65144#[doc = " * Neon instrinsic unsafe"]
65145#[inline]
65146#[target_feature(enable = "neon")]
65147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65149#[cfg_attr(
65150 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65151 assert_instr(nop, LANE = 0)
65152)]
65153#[rustc_legacy_const_generics(2)]
65154#[cfg_attr(
65155 not(target_arch = "arm"),
65156 stable(feature = "neon_intrinsics", since = "1.59.0")
65157)]
65158#[cfg_attr(
65159 target_arch = "arm",
65160 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65161)]
65162pub unsafe fn vst1q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8_t) {
65163 static_assert_uimm_bits!(LANE, 3);
65164 *a = simd_extract!(b, LANE as u32);
65165}
65166#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"]
65168#[doc = "## Safety"]
65169#[doc = " * Neon instrinsic unsafe"]
65170#[inline]
65171#[target_feature(enable = "neon")]
65172#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65173#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65174#[cfg_attr(
65175 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65176 assert_instr(nop, LANE = 0)
65177)]
65178#[rustc_legacy_const_generics(2)]
65179#[cfg_attr(
65180 not(target_arch = "arm"),
65181 stable(feature = "neon_intrinsics", since = "1.59.0")
65182)]
65183#[cfg_attr(
65184 target_arch = "arm",
65185 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65186)]
65187pub unsafe fn vst1_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2_t) {
65188 static_assert_uimm_bits!(LANE, 1);
65189 *a = simd_extract!(b, LANE as u32);
65190}
65191#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"]
65193#[doc = "## Safety"]
65194#[doc = " * Neon instrinsic unsafe"]
65195#[inline]
65196#[target_feature(enable = "neon")]
65197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65198#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65199#[cfg_attr(
65200 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65201 assert_instr(nop, LANE = 0)
65202)]
65203#[rustc_legacy_const_generics(2)]
65204#[cfg_attr(
65205 not(target_arch = "arm"),
65206 stable(feature = "neon_intrinsics", since = "1.59.0")
65207)]
65208#[cfg_attr(
65209 target_arch = "arm",
65210 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65211)]
65212pub unsafe fn vst1q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4_t) {
65213 static_assert_uimm_bits!(LANE, 2);
65214 *a = simd_extract!(b, LANE as u32);
65215}
65216#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"]
65218#[doc = "## Safety"]
65219#[doc = " * Neon instrinsic unsafe"]
65220#[inline]
65221#[target_feature(enable = "neon")]
65222#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65223#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65224#[cfg_attr(
65225 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65226 assert_instr(nop, LANE = 0)
65227)]
65228#[rustc_legacy_const_generics(2)]
65229#[cfg_attr(
65230 not(target_arch = "arm"),
65231 stable(feature = "neon_intrinsics", since = "1.59.0")
65232)]
65233#[cfg_attr(
65234 target_arch = "arm",
65235 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65236)]
65237pub unsafe fn vst1q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2_t) {
65238 static_assert_uimm_bits!(LANE, 1);
65239 *a = simd_extract!(b, LANE as u32);
65240}
65241#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"]
65243#[doc = "## Safety"]
65244#[doc = " * Neon instrinsic unsafe"]
65245#[inline]
65246#[target_feature(enable = "neon")]
65247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65249#[cfg_attr(
65250 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65251 assert_instr(nop, LANE = 0)
65252)]
65253#[rustc_legacy_const_generics(2)]
65254#[cfg_attr(
65255 not(target_arch = "arm"),
65256 stable(feature = "neon_intrinsics", since = "1.59.0")
65257)]
65258#[cfg_attr(
65259 target_arch = "arm",
65260 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65261)]
65262pub unsafe fn vst1_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8_t) {
65263 static_assert_uimm_bits!(LANE, 3);
65264 *a = simd_extract!(b, LANE as u32);
65265}
65266#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"]
65268#[doc = "## Safety"]
65269#[doc = " * Neon instrinsic unsafe"]
65270#[inline]
65271#[target_feature(enable = "neon")]
65272#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65273#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65274#[cfg_attr(
65275 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65276 assert_instr(nop, LANE = 0)
65277)]
65278#[rustc_legacy_const_generics(2)]
65279#[cfg_attr(
65280 not(target_arch = "arm"),
65281 stable(feature = "neon_intrinsics", since = "1.59.0")
65282)]
65283#[cfg_attr(
65284 target_arch = "arm",
65285 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65286)]
65287pub unsafe fn vst1q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16_t) {
65288 static_assert_uimm_bits!(LANE, 4);
65289 *a = simd_extract!(b, LANE as u32);
65290}
65291#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"]
65293#[doc = "## Safety"]
65294#[doc = " * Neon instrinsic unsafe"]
65295#[inline]
65296#[target_feature(enable = "neon")]
65297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65299#[cfg_attr(
65300 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65301 assert_instr(nop, LANE = 0)
65302)]
65303#[rustc_legacy_const_generics(2)]
65304#[cfg_attr(
65305 not(target_arch = "arm"),
65306 stable(feature = "neon_intrinsics", since = "1.59.0")
65307)]
65308#[cfg_attr(
65309 target_arch = "arm",
65310 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65311)]
65312pub unsafe fn vst1_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4_t) {
65313 static_assert_uimm_bits!(LANE, 2);
65314 *a = simd_extract!(b, LANE as u32);
65315}
65316#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"]
65318#[doc = "## Safety"]
65319#[doc = " * Neon instrinsic unsafe"]
65320#[inline]
65321#[target_feature(enable = "neon")]
65322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65323#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65324#[cfg_attr(
65325 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65326 assert_instr(nop, LANE = 0)
65327)]
65328#[rustc_legacy_const_generics(2)]
65329#[cfg_attr(
65330 not(target_arch = "arm"),
65331 stable(feature = "neon_intrinsics", since = "1.59.0")
65332)]
65333#[cfg_attr(
65334 target_arch = "arm",
65335 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65336)]
65337pub unsafe fn vst1q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8_t) {
65338 static_assert_uimm_bits!(LANE, 3);
65339 *a = simd_extract!(b, LANE as u32);
65340}
65341#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"]
65343#[doc = "## Safety"]
65344#[doc = " * Neon instrinsic unsafe"]
65345#[inline]
65346#[target_feature(enable = "neon")]
65347#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65348#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65349#[cfg_attr(
65350 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65351 assert_instr(nop, LANE = 0)
65352)]
65353#[rustc_legacy_const_generics(2)]
65354#[cfg_attr(
65355 not(target_arch = "arm"),
65356 stable(feature = "neon_intrinsics", since = "1.59.0")
65357)]
65358#[cfg_attr(
65359 target_arch = "arm",
65360 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65361)]
65362pub unsafe fn vst1_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2_t) {
65363 static_assert_uimm_bits!(LANE, 1);
65364 *a = simd_extract!(b, LANE as u32);
65365}
65366#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"]
65368#[doc = "## Safety"]
65369#[doc = " * Neon instrinsic unsafe"]
65370#[inline]
65371#[target_feature(enable = "neon")]
65372#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65373#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65374#[cfg_attr(
65375 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65376 assert_instr(nop, LANE = 0)
65377)]
65378#[rustc_legacy_const_generics(2)]
65379#[cfg_attr(
65380 not(target_arch = "arm"),
65381 stable(feature = "neon_intrinsics", since = "1.59.0")
65382)]
65383#[cfg_attr(
65384 target_arch = "arm",
65385 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65386)]
65387pub unsafe fn vst1q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4_t) {
65388 static_assert_uimm_bits!(LANE, 2);
65389 *a = simd_extract!(b, LANE as u32);
65390}
65391#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"]
65393#[doc = "## Safety"]
65394#[doc = " * Neon instrinsic unsafe"]
65395#[inline]
65396#[target_feature(enable = "neon")]
65397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65398#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65399#[cfg_attr(
65400 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65401 assert_instr(nop, LANE = 0)
65402)]
65403#[rustc_legacy_const_generics(2)]
65404#[cfg_attr(
65405 not(target_arch = "arm"),
65406 stable(feature = "neon_intrinsics", since = "1.59.0")
65407)]
65408#[cfg_attr(
65409 target_arch = "arm",
65410 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65411)]
65412pub unsafe fn vst1q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2_t) {
65413 static_assert_uimm_bits!(LANE, 1);
65414 *a = simd_extract!(b, LANE as u32);
65415}
65416#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65417#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"]
65418#[doc = "## Safety"]
65419#[doc = " * Neon instrinsic unsafe"]
65420#[inline]
65421#[target_feature(enable = "neon")]
65422#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65423#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65424#[cfg_attr(
65425 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65426 assert_instr(nop, LANE = 0)
65427)]
65428#[rustc_legacy_const_generics(2)]
65429#[cfg_attr(
65430 not(target_arch = "arm"),
65431 stable(feature = "neon_intrinsics", since = "1.59.0")
65432)]
65433#[cfg_attr(
65434 target_arch = "arm",
65435 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65436)]
65437pub unsafe fn vst1_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8_t) {
65438 static_assert_uimm_bits!(LANE, 3);
65439 *a = simd_extract!(b, LANE as u32);
65440}
65441#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"]
65443#[doc = "## Safety"]
65444#[doc = " * Neon instrinsic unsafe"]
65445#[inline]
65446#[target_feature(enable = "neon")]
65447#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65448#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65449#[cfg_attr(
65450 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65451 assert_instr(nop, LANE = 0)
65452)]
65453#[rustc_legacy_const_generics(2)]
65454#[cfg_attr(
65455 not(target_arch = "arm"),
65456 stable(feature = "neon_intrinsics", since = "1.59.0")
65457)]
65458#[cfg_attr(
65459 target_arch = "arm",
65460 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65461)]
65462pub unsafe fn vst1q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16_t) {
65463 static_assert_uimm_bits!(LANE, 4);
65464 *a = simd_extract!(b, LANE as u32);
65465}
65466#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"]
65468#[doc = "## Safety"]
65469#[doc = " * Neon instrinsic unsafe"]
65470#[inline]
65471#[target_feature(enable = "neon")]
65472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65474#[cfg_attr(
65475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65476 assert_instr(nop, LANE = 0)
65477)]
65478#[rustc_legacy_const_generics(2)]
65479#[cfg_attr(
65480 not(target_arch = "arm"),
65481 stable(feature = "neon_intrinsics", since = "1.59.0")
65482)]
65483#[cfg_attr(
65484 target_arch = "arm",
65485 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65486)]
65487pub unsafe fn vst1_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4_t) {
65488 static_assert_uimm_bits!(LANE, 2);
65489 *a = simd_extract!(b, LANE as u32);
65490}
65491#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"]
65493#[doc = "## Safety"]
65494#[doc = " * Neon instrinsic unsafe"]
65495#[inline]
65496#[target_feature(enable = "neon")]
65497#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65498#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65499#[cfg_attr(
65500 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65501 assert_instr(nop, LANE = 0)
65502)]
65503#[rustc_legacy_const_generics(2)]
65504#[cfg_attr(
65505 not(target_arch = "arm"),
65506 stable(feature = "neon_intrinsics", since = "1.59.0")
65507)]
65508#[cfg_attr(
65509 target_arch = "arm",
65510 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65511)]
65512pub unsafe fn vst1q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8_t) {
65513 static_assert_uimm_bits!(LANE, 3);
65514 *a = simd_extract!(b, LANE as u32);
65515}
65516#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"]
65518#[doc = "## Safety"]
65519#[doc = " * Neon instrinsic unsafe"]
65520#[inline]
65521#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65522#[target_feature(enable = "neon,aes")]
65523#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65524#[cfg_attr(
65525 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65526 assert_instr(nop, LANE = 0)
65527)]
65528#[rustc_legacy_const_generics(2)]
65529#[cfg_attr(
65530 not(target_arch = "arm"),
65531 stable(feature = "neon_intrinsics", since = "1.59.0")
65532)]
65533#[cfg_attr(
65534 target_arch = "arm",
65535 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65536)]
65537pub unsafe fn vst1_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1_t) {
65538 static_assert!(LANE == 0);
65539 *a = simd_extract!(b, LANE as u32);
65540}
65541#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"]
65543#[doc = "## Safety"]
65544#[doc = " * Neon instrinsic unsafe"]
65545#[inline]
65546#[target_feature(enable = "neon")]
65547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65548#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65549#[cfg_attr(
65550 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65551 assert_instr(nop, LANE = 0)
65552)]
65553#[rustc_legacy_const_generics(2)]
65554#[cfg_attr(
65555 not(target_arch = "arm"),
65556 stable(feature = "neon_intrinsics", since = "1.59.0")
65557)]
65558#[cfg_attr(
65559 target_arch = "arm",
65560 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65561)]
65562pub unsafe fn vst1_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1_t) {
65563 static_assert!(LANE == 0);
65564 *a = simd_extract!(b, LANE as u32);
65565}
65566#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"]
65568#[doc = "## Safety"]
65569#[doc = " * Neon instrinsic unsafe"]
65570#[inline]
65571#[target_feature(enable = "neon")]
65572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65573#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65574#[cfg_attr(
65575 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65576 assert_instr(nop, LANE = 0)
65577)]
65578#[rustc_legacy_const_generics(2)]
65579#[cfg_attr(
65580 not(target_arch = "arm"),
65581 stable(feature = "neon_intrinsics", since = "1.59.0")
65582)]
65583#[cfg_attr(
65584 target_arch = "arm",
65585 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65586)]
65587pub unsafe fn vst1_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1_t) {
65588 static_assert!(LANE == 0);
65589 *a = simd_extract!(b, LANE as u32);
65590}
65591#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"]
65593#[doc = "## Safety"]
65594#[doc = " * Neon instrinsic unsafe"]
65595#[inline]
65596#[target_feature(enable = "neon,aes")]
65597#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65598#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
65599#[cfg_attr(
65600 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65601 assert_instr(st1)
65602)]
65603#[cfg_attr(
65604 not(target_arch = "arm"),
65605 stable(feature = "neon_intrinsics", since = "1.59.0")
65606)]
65607#[cfg_attr(
65608 target_arch = "arm",
65609 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65610)]
65611pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) {
65612 vst1_s64_x2(transmute(a), transmute(b))
65613}
65614#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"]
65616#[doc = "## Safety"]
65617#[doc = " * Neon instrinsic unsafe"]
65618#[inline]
65619#[target_feature(enable = "neon,aes")]
65620#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65622#[cfg_attr(
65623 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65624 assert_instr(st1)
65625)]
65626#[cfg_attr(
65627 not(target_arch = "arm"),
65628 stable(feature = "neon_intrinsics", since = "1.59.0")
65629)]
65630#[cfg_attr(
65631 target_arch = "arm",
65632 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65633)]
65634pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) {
65635 vst1_s64_x3(transmute(a), transmute(b))
65636}
65637#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"]
65639#[doc = "## Safety"]
65640#[doc = " * Neon instrinsic unsafe"]
65641#[inline]
65642#[target_feature(enable = "neon,aes")]
65643#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65645#[cfg_attr(
65646 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65647 assert_instr(st1)
65648)]
65649#[cfg_attr(
65650 not(target_arch = "arm"),
65651 stable(feature = "neon_intrinsics", since = "1.59.0")
65652)]
65653#[cfg_attr(
65654 target_arch = "arm",
65655 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65656)]
65657pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) {
65658 vst1_s64_x4(transmute(a), transmute(b))
65659}
65660#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"]
65662#[doc = "## Safety"]
65663#[doc = " * Neon instrinsic unsafe"]
65664#[inline]
65665#[target_feature(enable = "neon,aes")]
65666#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65667#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65668#[cfg_attr(
65669 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65670 assert_instr(st1)
65671)]
65672#[cfg_attr(
65673 not(target_arch = "arm"),
65674 stable(feature = "neon_intrinsics", since = "1.59.0")
65675)]
65676#[cfg_attr(
65677 target_arch = "arm",
65678 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65679)]
65680pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) {
65681 vst1q_s64_x2(transmute(a), transmute(b))
65682}
65683#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"]
65685#[doc = "## Safety"]
65686#[doc = " * Neon instrinsic unsafe"]
65687#[inline]
65688#[target_feature(enable = "neon,aes")]
65689#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65690#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65691#[cfg_attr(
65692 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65693 assert_instr(st1)
65694)]
65695#[cfg_attr(
65696 not(target_arch = "arm"),
65697 stable(feature = "neon_intrinsics", since = "1.59.0")
65698)]
65699#[cfg_attr(
65700 target_arch = "arm",
65701 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65702)]
65703pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) {
65704 vst1q_s64_x3(transmute(a), transmute(b))
65705}
65706#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"]
65708#[doc = "## Safety"]
65709#[doc = " * Neon instrinsic unsafe"]
65710#[inline]
65711#[target_feature(enable = "neon,aes")]
65712#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65713#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65714#[cfg_attr(
65715 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65716 assert_instr(st1)
65717)]
65718#[cfg_attr(
65719 not(target_arch = "arm"),
65720 stable(feature = "neon_intrinsics", since = "1.59.0")
65721)]
65722#[cfg_attr(
65723 target_arch = "arm",
65724 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65725)]
65726pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) {
65727 vst1q_s64_x4(transmute(a), transmute(b))
65728}
65729#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
65731#[doc = "## Safety"]
65732#[doc = " * Neon instrinsic unsafe"]
65733#[inline]
65734#[target_feature(enable = "neon")]
65735#[cfg(not(target_arch = "arm"))]
65736#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65737#[cfg_attr(test, assert_instr(st1))]
65738pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
65739 unsafe extern "unadjusted" {
65740 #[cfg_attr(
65741 any(target_arch = "aarch64", target_arch = "arm64ec"),
65742 link_name = "llvm.aarch64.neon.st1x2.v8i8.p0i8"
65743 )]
65744 fn _vst1_s8_x2(a: int8x8_t, b: int8x8_t, ptr: *mut i8);
65745 }
65746 _vst1_s8_x2(b.0, b.1, a)
65747}
65748#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
65750#[doc = "## Safety"]
65751#[doc = " * Neon instrinsic unsafe"]
65752#[inline]
65753#[target_feature(enable = "neon")]
65754#[cfg(not(target_arch = "arm"))]
65755#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65756#[cfg_attr(test, assert_instr(st1))]
65757pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
65758 unsafe extern "unadjusted" {
65759 #[cfg_attr(
65760 any(target_arch = "aarch64", target_arch = "arm64ec"),
65761 link_name = "llvm.aarch64.neon.st1x2.v16i8.p0i8"
65762 )]
65763 fn _vst1q_s8_x2(a: int8x16_t, b: int8x16_t, ptr: *mut i8);
65764 }
65765 _vst1q_s8_x2(b.0, b.1, a)
65766}
65767#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
65769#[doc = "## Safety"]
65770#[doc = " * Neon instrinsic unsafe"]
65771#[inline]
65772#[target_feature(enable = "neon")]
65773#[cfg(not(target_arch = "arm"))]
65774#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65775#[cfg_attr(test, assert_instr(st1))]
65776pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
65777 unsafe extern "unadjusted" {
65778 #[cfg_attr(
65779 any(target_arch = "aarch64", target_arch = "arm64ec"),
65780 link_name = "llvm.aarch64.neon.st1x2.v4i16.p0i16"
65781 )]
65782 fn _vst1_s16_x2(a: int16x4_t, b: int16x4_t, ptr: *mut i16);
65783 }
65784 _vst1_s16_x2(b.0, b.1, a)
65785}
65786#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
65788#[doc = "## Safety"]
65789#[doc = " * Neon instrinsic unsafe"]
65790#[inline]
65791#[target_feature(enable = "neon")]
65792#[cfg(not(target_arch = "arm"))]
65793#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65794#[cfg_attr(test, assert_instr(st1))]
65795pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
65796 unsafe extern "unadjusted" {
65797 #[cfg_attr(
65798 any(target_arch = "aarch64", target_arch = "arm64ec"),
65799 link_name = "llvm.aarch64.neon.st1x2.v8i16.p0i16"
65800 )]
65801 fn _vst1q_s16_x2(a: int16x8_t, b: int16x8_t, ptr: *mut i16);
65802 }
65803 _vst1q_s16_x2(b.0, b.1, a)
65804}
65805#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
65807#[doc = "## Safety"]
65808#[doc = " * Neon instrinsic unsafe"]
65809#[inline]
65810#[target_feature(enable = "neon")]
65811#[cfg(not(target_arch = "arm"))]
65812#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65813#[cfg_attr(test, assert_instr(st1))]
65814pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
65815 unsafe extern "unadjusted" {
65816 #[cfg_attr(
65817 any(target_arch = "aarch64", target_arch = "arm64ec"),
65818 link_name = "llvm.aarch64.neon.st1x2.v2i32.p0i32"
65819 )]
65820 fn _vst1_s32_x2(a: int32x2_t, b: int32x2_t, ptr: *mut i32);
65821 }
65822 _vst1_s32_x2(b.0, b.1, a)
65823}
65824#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
65826#[doc = "## Safety"]
65827#[doc = " * Neon instrinsic unsafe"]
65828#[inline]
65829#[target_feature(enable = "neon")]
65830#[cfg(not(target_arch = "arm"))]
65831#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65832#[cfg_attr(test, assert_instr(st1))]
65833pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
65834 unsafe extern "unadjusted" {
65835 #[cfg_attr(
65836 any(target_arch = "aarch64", target_arch = "arm64ec"),
65837 link_name = "llvm.aarch64.neon.st1x2.v4i32.p0i32"
65838 )]
65839 fn _vst1q_s32_x2(a: int32x4_t, b: int32x4_t, ptr: *mut i32);
65840 }
65841 _vst1q_s32_x2(b.0, b.1, a)
65842}
65843#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
65845#[doc = "## Safety"]
65846#[doc = " * Neon instrinsic unsafe"]
65847#[inline]
65848#[target_feature(enable = "neon")]
65849#[cfg(not(target_arch = "arm"))]
65850#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65851#[cfg_attr(test, assert_instr(st1))]
65852pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
65853 unsafe extern "unadjusted" {
65854 #[cfg_attr(
65855 any(target_arch = "aarch64", target_arch = "arm64ec"),
65856 link_name = "llvm.aarch64.neon.st1x2.v1i64.p0i64"
65857 )]
65858 fn _vst1_s64_x2(a: int64x1_t, b: int64x1_t, ptr: *mut i64);
65859 }
65860 _vst1_s64_x2(b.0, b.1, a)
65861}
65862#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
65864#[doc = "## Safety"]
65865#[doc = " * Neon instrinsic unsafe"]
65866#[inline]
65867#[target_feature(enable = "neon")]
65868#[cfg(not(target_arch = "arm"))]
65869#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65870#[cfg_attr(test, assert_instr(st1))]
65871pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
65872 unsafe extern "unadjusted" {
65873 #[cfg_attr(
65874 any(target_arch = "aarch64", target_arch = "arm64ec"),
65875 link_name = "llvm.aarch64.neon.st1x2.v2i64.p0i64"
65876 )]
65877 fn _vst1q_s64_x2(a: int64x2_t, b: int64x2_t, ptr: *mut i64);
65878 }
65879 _vst1q_s64_x2(b.0, b.1, a)
65880}
65881#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
65883#[doc = "## Safety"]
65884#[doc = " * Neon instrinsic unsafe"]
65885#[inline]
65886#[target_feature(enable = "neon,v7")]
65887#[cfg(target_arch = "arm")]
65888#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65889#[cfg_attr(test, assert_instr(vst1))]
65890pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
65891 unsafe extern "unadjusted" {
65892 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v8i8.p0")]
65893 fn _vst1_s8_x2(ptr: *mut i8, a: int8x8_t, b: int8x8_t);
65894 }
65895 _vst1_s8_x2(a, b.0, b.1)
65896}
65897#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
65899#[doc = "## Safety"]
65900#[doc = " * Neon instrinsic unsafe"]
65901#[inline]
65902#[target_feature(enable = "neon,v7")]
65903#[cfg(target_arch = "arm")]
65904#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65905#[cfg_attr(test, assert_instr(vst1))]
65906pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
65907 unsafe extern "unadjusted" {
65908 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v16i8.p0")]
65909 fn _vst1q_s8_x2(ptr: *mut i8, a: int8x16_t, b: int8x16_t);
65910 }
65911 _vst1q_s8_x2(a, b.0, b.1)
65912}
65913#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
65915#[doc = "## Safety"]
65916#[doc = " * Neon instrinsic unsafe"]
65917#[inline]
65918#[target_feature(enable = "neon,v7")]
65919#[cfg(target_arch = "arm")]
65920#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65921#[cfg_attr(test, assert_instr(vst1))]
65922pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
65923 unsafe extern "unadjusted" {
65924 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4i16.p0")]
65925 fn _vst1_s16_x2(ptr: *mut i16, a: int16x4_t, b: int16x4_t);
65926 }
65927 _vst1_s16_x2(a, b.0, b.1)
65928}
65929#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
65931#[doc = "## Safety"]
65932#[doc = " * Neon instrinsic unsafe"]
65933#[inline]
65934#[target_feature(enable = "neon,v7")]
65935#[cfg(target_arch = "arm")]
65936#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65937#[cfg_attr(test, assert_instr(vst1))]
65938pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
65939 unsafe extern "unadjusted" {
65940 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v8i16.p0")]
65941 fn _vst1q_s16_x2(ptr: *mut i16, a: int16x8_t, b: int16x8_t);
65942 }
65943 _vst1q_s16_x2(a, b.0, b.1)
65944}
65945#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
65947#[doc = "## Safety"]
65948#[doc = " * Neon instrinsic unsafe"]
65949#[inline]
65950#[target_feature(enable = "neon,v7")]
65951#[cfg(target_arch = "arm")]
65952#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65953#[cfg_attr(test, assert_instr(vst1))]
65954pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
65955 unsafe extern "unadjusted" {
65956 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2i32.p0")]
65957 fn _vst1_s32_x2(ptr: *mut i32, a: int32x2_t, b: int32x2_t);
65958 }
65959 _vst1_s32_x2(a, b.0, b.1)
65960}
65961#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
65963#[doc = "## Safety"]
65964#[doc = " * Neon instrinsic unsafe"]
65965#[inline]
65966#[target_feature(enable = "neon,v7")]
65967#[cfg(target_arch = "arm")]
65968#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65969#[cfg_attr(test, assert_instr(vst1))]
65970pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
65971 unsafe extern "unadjusted" {
65972 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4i32.p0")]
65973 fn _vst1q_s32_x2(ptr: *mut i32, a: int32x4_t, b: int32x4_t);
65974 }
65975 _vst1q_s32_x2(a, b.0, b.1)
65976}
65977#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
65979#[doc = "## Safety"]
65980#[doc = " * Neon instrinsic unsafe"]
65981#[inline]
65982#[target_feature(enable = "neon,v7")]
65983#[cfg(target_arch = "arm")]
65984#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65985#[cfg_attr(test, assert_instr(vst1))]
65986pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
65987 unsafe extern "unadjusted" {
65988 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v1i64.p0")]
65989 fn _vst1_s64_x2(ptr: *mut i64, a: int64x1_t, b: int64x1_t);
65990 }
65991 _vst1_s64_x2(a, b.0, b.1)
65992}
65993#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
65995#[doc = "## Safety"]
65996#[doc = " * Neon instrinsic unsafe"]
65997#[inline]
65998#[target_feature(enable = "neon,v7")]
65999#[cfg(target_arch = "arm")]
66000#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66001#[cfg_attr(test, assert_instr(vst1))]
66002pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
66003 unsafe extern "unadjusted" {
66004 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2i64.p0")]
66005 fn _vst1q_s64_x2(ptr: *mut i64, a: int64x2_t, b: int64x2_t);
66006 }
66007 _vst1q_s64_x2(a, b.0, b.1)
66008}
66009#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
66011#[doc = "## Safety"]
66012#[doc = " * Neon instrinsic unsafe"]
66013#[inline]
66014#[target_feature(enable = "neon")]
66015#[cfg(not(target_arch = "arm"))]
66016#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66017#[cfg_attr(test, assert_instr(st1))]
66018pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
66019 unsafe extern "unadjusted" {
66020 #[cfg_attr(
66021 any(target_arch = "aarch64", target_arch = "arm64ec"),
66022 link_name = "llvm.aarch64.neon.st1x3.v8i8.p0i8"
66023 )]
66024 fn _vst1_s8_x3(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8);
66025 }
66026 _vst1_s8_x3(b.0, b.1, b.2, a)
66027}
66028#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
66030#[doc = "## Safety"]
66031#[doc = " * Neon instrinsic unsafe"]
66032#[inline]
66033#[target_feature(enable = "neon")]
66034#[cfg(not(target_arch = "arm"))]
66035#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66036#[cfg_attr(test, assert_instr(st1))]
66037pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
66038 unsafe extern "unadjusted" {
66039 #[cfg_attr(
66040 any(target_arch = "aarch64", target_arch = "arm64ec"),
66041 link_name = "llvm.aarch64.neon.st1x3.v16i8.p0i8"
66042 )]
66043 fn _vst1q_s8_x3(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8);
66044 }
66045 _vst1q_s8_x3(b.0, b.1, b.2, a)
66046}
66047#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
66049#[doc = "## Safety"]
66050#[doc = " * Neon instrinsic unsafe"]
66051#[inline]
66052#[target_feature(enable = "neon")]
66053#[cfg(not(target_arch = "arm"))]
66054#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66055#[cfg_attr(test, assert_instr(st1))]
66056pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
66057 unsafe extern "unadjusted" {
66058 #[cfg_attr(
66059 any(target_arch = "aarch64", target_arch = "arm64ec"),
66060 link_name = "llvm.aarch64.neon.st1x3.v4i16.p0i16"
66061 )]
66062 fn _vst1_s16_x3(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i16);
66063 }
66064 _vst1_s16_x3(b.0, b.1, b.2, a)
66065}
66066#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
66068#[doc = "## Safety"]
66069#[doc = " * Neon instrinsic unsafe"]
66070#[inline]
66071#[target_feature(enable = "neon")]
66072#[cfg(not(target_arch = "arm"))]
66073#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66074#[cfg_attr(test, assert_instr(st1))]
66075pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
66076 unsafe extern "unadjusted" {
66077 #[cfg_attr(
66078 any(target_arch = "aarch64", target_arch = "arm64ec"),
66079 link_name = "llvm.aarch64.neon.st1x3.v8i16.p0i16"
66080 )]
66081 fn _vst1q_s16_x3(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i16);
66082 }
66083 _vst1q_s16_x3(b.0, b.1, b.2, a)
66084}
66085#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66086#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
66087#[doc = "## Safety"]
66088#[doc = " * Neon instrinsic unsafe"]
66089#[inline]
66090#[target_feature(enable = "neon")]
66091#[cfg(not(target_arch = "arm"))]
66092#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66093#[cfg_attr(test, assert_instr(st1))]
66094pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
66095 unsafe extern "unadjusted" {
66096 #[cfg_attr(
66097 any(target_arch = "aarch64", target_arch = "arm64ec"),
66098 link_name = "llvm.aarch64.neon.st1x3.v2i32.p0i32"
66099 )]
66100 fn _vst1_s32_x3(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i32);
66101 }
66102 _vst1_s32_x3(b.0, b.1, b.2, a)
66103}
66104#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
66106#[doc = "## Safety"]
66107#[doc = " * Neon instrinsic unsafe"]
66108#[inline]
66109#[target_feature(enable = "neon")]
66110#[cfg(not(target_arch = "arm"))]
66111#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66112#[cfg_attr(test, assert_instr(st1))]
66113pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
66114 unsafe extern "unadjusted" {
66115 #[cfg_attr(
66116 any(target_arch = "aarch64", target_arch = "arm64ec"),
66117 link_name = "llvm.aarch64.neon.st1x3.v4i32.p0i32"
66118 )]
66119 fn _vst1q_s32_x3(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i32);
66120 }
66121 _vst1q_s32_x3(b.0, b.1, b.2, a)
66122}
66123#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
66125#[doc = "## Safety"]
66126#[doc = " * Neon instrinsic unsafe"]
66127#[inline]
66128#[target_feature(enable = "neon")]
66129#[cfg(not(target_arch = "arm"))]
66130#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66131#[cfg_attr(test, assert_instr(st1))]
66132pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
66133 unsafe extern "unadjusted" {
66134 #[cfg_attr(
66135 any(target_arch = "aarch64", target_arch = "arm64ec"),
66136 link_name = "llvm.aarch64.neon.st1x3.v1i64.p0i64"
66137 )]
66138 fn _vst1_s64_x3(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i64);
66139 }
66140 _vst1_s64_x3(b.0, b.1, b.2, a)
66141}
66142#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
66144#[doc = "## Safety"]
66145#[doc = " * Neon instrinsic unsafe"]
66146#[inline]
66147#[target_feature(enable = "neon")]
66148#[cfg(not(target_arch = "arm"))]
66149#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66150#[cfg_attr(test, assert_instr(st1))]
66151pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
66152 unsafe extern "unadjusted" {
66153 #[cfg_attr(
66154 any(target_arch = "aarch64", target_arch = "arm64ec"),
66155 link_name = "llvm.aarch64.neon.st1x3.v2i64.p0i64"
66156 )]
66157 fn _vst1q_s64_x3(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i64);
66158 }
66159 _vst1q_s64_x3(b.0, b.1, b.2, a)
66160}
66161#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
66163#[doc = "## Safety"]
66164#[doc = " * Neon instrinsic unsafe"]
66165#[inline]
66166#[target_feature(enable = "neon,v7")]
66167#[cfg(target_arch = "arm")]
66168#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66169#[cfg_attr(test, assert_instr(vst1))]
66170pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
66171 unsafe extern "unadjusted" {
66172 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i8.v8i8.p0")]
66173 fn _vst1_s8_x3(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t);
66174 }
66175 _vst1_s8_x3(a, b.0, b.1, b.2)
66176}
66177#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
66179#[doc = "## Safety"]
66180#[doc = " * Neon instrinsic unsafe"]
66181#[inline]
66182#[target_feature(enable = "neon,v7")]
66183#[cfg(target_arch = "arm")]
66184#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66185#[cfg_attr(test, assert_instr(vst1))]
66186pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
66187 unsafe extern "unadjusted" {
66188 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i8.v16i8.p0")]
66189 fn _vst1q_s8_x3(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t);
66190 }
66191 _vst1q_s8_x3(a, b.0, b.1, b.2)
66192}
66193#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
66195#[doc = "## Safety"]
66196#[doc = " * Neon instrinsic unsafe"]
66197#[inline]
66198#[target_feature(enable = "neon,v7")]
66199#[cfg(target_arch = "arm")]
66200#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66201#[cfg_attr(test, assert_instr(vst1))]
66202pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
66203 unsafe extern "unadjusted" {
66204 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i16.v4i16.p0")]
66205 fn _vst1_s16_x3(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t);
66206 }
66207 _vst1_s16_x3(a, b.0, b.1, b.2)
66208}
66209#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
66211#[doc = "## Safety"]
66212#[doc = " * Neon instrinsic unsafe"]
66213#[inline]
66214#[target_feature(enable = "neon,v7")]
66215#[cfg(target_arch = "arm")]
66216#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66217#[cfg_attr(test, assert_instr(vst1))]
66218pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
66219 unsafe extern "unadjusted" {
66220 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i16.v8i16.p0")]
66221 fn _vst1q_s16_x3(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t);
66222 }
66223 _vst1q_s16_x3(a, b.0, b.1, b.2)
66224}
66225#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
66227#[doc = "## Safety"]
66228#[doc = " * Neon instrinsic unsafe"]
66229#[inline]
66230#[target_feature(enable = "neon,v7")]
66231#[cfg(target_arch = "arm")]
66232#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66233#[cfg_attr(test, assert_instr(vst1))]
66234pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
66235 unsafe extern "unadjusted" {
66236 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i32.v2i32.p0")]
66237 fn _vst1_s32_x3(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t);
66238 }
66239 _vst1_s32_x3(a, b.0, b.1, b.2)
66240}
66241#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
66243#[doc = "## Safety"]
66244#[doc = " * Neon instrinsic unsafe"]
66245#[inline]
66246#[target_feature(enable = "neon,v7")]
66247#[cfg(target_arch = "arm")]
66248#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66249#[cfg_attr(test, assert_instr(vst1))]
66250pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
66251 unsafe extern "unadjusted" {
66252 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i32.v4i32.p0")]
66253 fn _vst1q_s32_x3(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t);
66254 }
66255 _vst1q_s32_x3(a, b.0, b.1, b.2)
66256}
66257#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
66259#[doc = "## Safety"]
66260#[doc = " * Neon instrinsic unsafe"]
66261#[inline]
66262#[target_feature(enable = "neon,v7")]
66263#[cfg(target_arch = "arm")]
66264#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66265#[cfg_attr(test, assert_instr(vst1))]
66266pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
66267 unsafe extern "unadjusted" {
66268 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i64.v1i64.p0")]
66269 fn _vst1_s64_x3(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t);
66270 }
66271 _vst1_s64_x3(a, b.0, b.1, b.2)
66272}
66273#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
66275#[doc = "## Safety"]
66276#[doc = " * Neon instrinsic unsafe"]
66277#[inline]
66278#[target_feature(enable = "neon,v7")]
66279#[cfg(target_arch = "arm")]
66280#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66281#[cfg_attr(test, assert_instr(vst1))]
66282pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
66283 unsafe extern "unadjusted" {
66284 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i64.v2i64.p0")]
66285 fn _vst1q_s64_x3(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t);
66286 }
66287 _vst1q_s64_x3(a, b.0, b.1, b.2)
66288}
66289#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
66291#[doc = "## Safety"]
66292#[doc = " * Neon instrinsic unsafe"]
66293#[inline]
66294#[target_feature(enable = "neon")]
66295#[cfg(not(target_arch = "arm"))]
66296#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66297#[cfg_attr(test, assert_instr(st1))]
66298pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
66299 unsafe extern "unadjusted" {
66300 #[cfg_attr(
66301 any(target_arch = "aarch64", target_arch = "arm64ec"),
66302 link_name = "llvm.aarch64.neon.st1x4.v8i8.p0i8"
66303 )]
66304 fn _vst1_s8_x4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8);
66305 }
66306 _vst1_s8_x4(b.0, b.1, b.2, b.3, a)
66307}
66308#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
66310#[doc = "## Safety"]
66311#[doc = " * Neon instrinsic unsafe"]
66312#[inline]
66313#[target_feature(enable = "neon")]
66314#[cfg(not(target_arch = "arm"))]
66315#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66316#[cfg_attr(test, assert_instr(st1))]
66317pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
66318 unsafe extern "unadjusted" {
66319 #[cfg_attr(
66320 any(target_arch = "aarch64", target_arch = "arm64ec"),
66321 link_name = "llvm.aarch64.neon.st1x4.v16i8.p0i8"
66322 )]
66323 fn _vst1q_s8_x4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8);
66324 }
66325 _vst1q_s8_x4(b.0, b.1, b.2, b.3, a)
66326}
66327#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
66329#[doc = "## Safety"]
66330#[doc = " * Neon instrinsic unsafe"]
66331#[inline]
66332#[target_feature(enable = "neon")]
66333#[cfg(not(target_arch = "arm"))]
66334#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66335#[cfg_attr(test, assert_instr(st1))]
66336pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
66337 unsafe extern "unadjusted" {
66338 #[cfg_attr(
66339 any(target_arch = "aarch64", target_arch = "arm64ec"),
66340 link_name = "llvm.aarch64.neon.st1x4.v4i16.p0i16"
66341 )]
66342 fn _vst1_s16_x4(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i16);
66343 }
66344 _vst1_s16_x4(b.0, b.1, b.2, b.3, a)
66345}
66346#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
66348#[doc = "## Safety"]
66349#[doc = " * Neon instrinsic unsafe"]
66350#[inline]
66351#[target_feature(enable = "neon")]
66352#[cfg(not(target_arch = "arm"))]
66353#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66354#[cfg_attr(test, assert_instr(st1))]
66355pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
66356 unsafe extern "unadjusted" {
66357 #[cfg_attr(
66358 any(target_arch = "aarch64", target_arch = "arm64ec"),
66359 link_name = "llvm.aarch64.neon.st1x4.v8i16.p0i16"
66360 )]
66361 fn _vst1q_s16_x4(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i16);
66362 }
66363 _vst1q_s16_x4(b.0, b.1, b.2, b.3, a)
66364}
66365#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
66367#[doc = "## Safety"]
66368#[doc = " * Neon instrinsic unsafe"]
66369#[inline]
66370#[target_feature(enable = "neon")]
66371#[cfg(not(target_arch = "arm"))]
66372#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66373#[cfg_attr(test, assert_instr(st1))]
66374pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
66375 unsafe extern "unadjusted" {
66376 #[cfg_attr(
66377 any(target_arch = "aarch64", target_arch = "arm64ec"),
66378 link_name = "llvm.aarch64.neon.st1x4.v2i32.p0i32"
66379 )]
66380 fn _vst1_s32_x4(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i32);
66381 }
66382 _vst1_s32_x4(b.0, b.1, b.2, b.3, a)
66383}
66384#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
66386#[doc = "## Safety"]
66387#[doc = " * Neon instrinsic unsafe"]
66388#[inline]
66389#[target_feature(enable = "neon")]
66390#[cfg(not(target_arch = "arm"))]
66391#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66392#[cfg_attr(test, assert_instr(st1))]
66393pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
66394 unsafe extern "unadjusted" {
66395 #[cfg_attr(
66396 any(target_arch = "aarch64", target_arch = "arm64ec"),
66397 link_name = "llvm.aarch64.neon.st1x4.v4i32.p0i32"
66398 )]
66399 fn _vst1q_s32_x4(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i32);
66400 }
66401 _vst1q_s32_x4(b.0, b.1, b.2, b.3, a)
66402}
66403#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
66405#[doc = "## Safety"]
66406#[doc = " * Neon instrinsic unsafe"]
66407#[inline]
66408#[target_feature(enable = "neon")]
66409#[cfg(not(target_arch = "arm"))]
66410#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66411#[cfg_attr(test, assert_instr(st1))]
66412pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
66413 unsafe extern "unadjusted" {
66414 #[cfg_attr(
66415 any(target_arch = "aarch64", target_arch = "arm64ec"),
66416 link_name = "llvm.aarch64.neon.st1x4.v1i64.p0i64"
66417 )]
66418 fn _vst1_s64_x4(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i64);
66419 }
66420 _vst1_s64_x4(b.0, b.1, b.2, b.3, a)
66421}
66422#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
66424#[doc = "## Safety"]
66425#[doc = " * Neon instrinsic unsafe"]
66426#[inline]
66427#[target_feature(enable = "neon")]
66428#[cfg(not(target_arch = "arm"))]
66429#[stable(feature = "neon_intrinsics", since = "1.59.0")]
66430#[cfg_attr(test, assert_instr(st1))]
66431pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
66432 unsafe extern "unadjusted" {
66433 #[cfg_attr(
66434 any(target_arch = "aarch64", target_arch = "arm64ec"),
66435 link_name = "llvm.aarch64.neon.st1x4.v2i64.p0i64"
66436 )]
66437 fn _vst1q_s64_x4(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i64);
66438 }
66439 _vst1q_s64_x4(b.0, b.1, b.2, b.3, a)
66440}
66441#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
66443#[doc = "## Safety"]
66444#[doc = " * Neon instrinsic unsafe"]
66445#[inline]
66446#[cfg(target_arch = "arm")]
66447#[target_feature(enable = "neon,v7")]
66448#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66449#[cfg_attr(test, assert_instr(vst1))]
66450pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
66451 unsafe extern "unadjusted" {
66452 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i8.v8i8.p0")]
66453 fn _vst1_s8_x4(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t);
66454 }
66455 _vst1_s8_x4(a, b.0, b.1, b.2, b.3)
66456}
66457#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
66459#[doc = "## Safety"]
66460#[doc = " * Neon instrinsic unsafe"]
66461#[inline]
66462#[cfg(target_arch = "arm")]
66463#[target_feature(enable = "neon,v7")]
66464#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66465#[cfg_attr(test, assert_instr(vst1))]
66466pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
66467 unsafe extern "unadjusted" {
66468 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i8.v16i8.p0")]
66469 fn _vst1q_s8_x4(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t);
66470 }
66471 _vst1q_s8_x4(a, b.0, b.1, b.2, b.3)
66472}
66473#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
66475#[doc = "## Safety"]
66476#[doc = " * Neon instrinsic unsafe"]
66477#[inline]
66478#[cfg(target_arch = "arm")]
66479#[target_feature(enable = "neon,v7")]
66480#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66481#[cfg_attr(test, assert_instr(vst1))]
66482pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
66483 unsafe extern "unadjusted" {
66484 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i16.v4i16.p0")]
66485 fn _vst1_s16_x4(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t);
66486 }
66487 _vst1_s16_x4(a, b.0, b.1, b.2, b.3)
66488}
66489#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
66491#[doc = "## Safety"]
66492#[doc = " * Neon instrinsic unsafe"]
66493#[inline]
66494#[cfg(target_arch = "arm")]
66495#[target_feature(enable = "neon,v7")]
66496#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66497#[cfg_attr(test, assert_instr(vst1))]
66498pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
66499 unsafe extern "unadjusted" {
66500 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i16.v8i16.p0")]
66501 fn _vst1q_s16_x4(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t);
66502 }
66503 _vst1q_s16_x4(a, b.0, b.1, b.2, b.3)
66504}
66505#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
66507#[doc = "## Safety"]
66508#[doc = " * Neon instrinsic unsafe"]
66509#[inline]
66510#[cfg(target_arch = "arm")]
66511#[target_feature(enable = "neon,v7")]
66512#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66513#[cfg_attr(test, assert_instr(vst1))]
66514pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
66515 unsafe extern "unadjusted" {
66516 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i32.v2i32.p0")]
66517 fn _vst1_s32_x4(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t);
66518 }
66519 _vst1_s32_x4(a, b.0, b.1, b.2, b.3)
66520}
66521#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
66523#[doc = "## Safety"]
66524#[doc = " * Neon instrinsic unsafe"]
66525#[inline]
66526#[cfg(target_arch = "arm")]
66527#[target_feature(enable = "neon,v7")]
66528#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66529#[cfg_attr(test, assert_instr(vst1))]
66530pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
66531 unsafe extern "unadjusted" {
66532 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i32.v4i32.p0")]
66533 fn _vst1q_s32_x4(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t);
66534 }
66535 _vst1q_s32_x4(a, b.0, b.1, b.2, b.3)
66536}
66537#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
66539#[doc = "## Safety"]
66540#[doc = " * Neon instrinsic unsafe"]
66541#[inline]
66542#[cfg(target_arch = "arm")]
66543#[target_feature(enable = "neon,v7")]
66544#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66545#[cfg_attr(test, assert_instr(vst1))]
66546pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
66547 unsafe extern "unadjusted" {
66548 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i64.v1i64.p0")]
66549 fn _vst1_s64_x4(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t);
66550 }
66551 _vst1_s64_x4(a, b.0, b.1, b.2, b.3)
66552}
66553#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
66555#[doc = "## Safety"]
66556#[doc = " * Neon instrinsic unsafe"]
66557#[inline]
66558#[cfg(target_arch = "arm")]
66559#[target_feature(enable = "neon,v7")]
66560#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66561#[cfg_attr(test, assert_instr(vst1))]
66562pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
66563 unsafe extern "unadjusted" {
66564 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i64.v2i64.p0")]
66565 fn _vst1q_s64_x4(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t);
66566 }
66567 _vst1q_s64_x4(a, b.0, b.1, b.2, b.3)
66568}
66569#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"]
66571#[doc = "## Safety"]
66572#[doc = " * Neon instrinsic unsafe"]
66573#[inline]
66574#[target_feature(enable = "neon")]
66575#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66576#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66577#[cfg_attr(
66578 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66579 assert_instr(st1)
66580)]
66581#[cfg_attr(
66582 not(target_arch = "arm"),
66583 stable(feature = "neon_intrinsics", since = "1.59.0")
66584)]
66585#[cfg_attr(
66586 target_arch = "arm",
66587 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66588)]
66589pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) {
66590 vst1_s8_x2(transmute(a), transmute(b))
66591}
66592#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"]
66594#[doc = "## Safety"]
66595#[doc = " * Neon instrinsic unsafe"]
66596#[inline]
66597#[target_feature(enable = "neon")]
66598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66599#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66600#[cfg_attr(
66601 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66602 assert_instr(st1)
66603)]
66604#[cfg_attr(
66605 not(target_arch = "arm"),
66606 stable(feature = "neon_intrinsics", since = "1.59.0")
66607)]
66608#[cfg_attr(
66609 target_arch = "arm",
66610 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66611)]
66612pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) {
66613 vst1_s8_x3(transmute(a), transmute(b))
66614}
66615#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"]
66617#[doc = "## Safety"]
66618#[doc = " * Neon instrinsic unsafe"]
66619#[inline]
66620#[target_feature(enable = "neon")]
66621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66622#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66623#[cfg_attr(
66624 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66625 assert_instr(st1)
66626)]
66627#[cfg_attr(
66628 not(target_arch = "arm"),
66629 stable(feature = "neon_intrinsics", since = "1.59.0")
66630)]
66631#[cfg_attr(
66632 target_arch = "arm",
66633 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66634)]
66635pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) {
66636 vst1_s8_x4(transmute(a), transmute(b))
66637}
66638#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"]
66640#[doc = "## Safety"]
66641#[doc = " * Neon instrinsic unsafe"]
66642#[inline]
66643#[target_feature(enable = "neon")]
66644#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66645#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66646#[cfg_attr(
66647 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66648 assert_instr(st1)
66649)]
66650#[cfg_attr(
66651 not(target_arch = "arm"),
66652 stable(feature = "neon_intrinsics", since = "1.59.0")
66653)]
66654#[cfg_attr(
66655 target_arch = "arm",
66656 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66657)]
66658pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) {
66659 vst1q_s8_x2(transmute(a), transmute(b))
66660}
66661#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"]
66663#[doc = "## Safety"]
66664#[doc = " * Neon instrinsic unsafe"]
66665#[inline]
66666#[target_feature(enable = "neon")]
66667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66669#[cfg_attr(
66670 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66671 assert_instr(st1)
66672)]
66673#[cfg_attr(
66674 not(target_arch = "arm"),
66675 stable(feature = "neon_intrinsics", since = "1.59.0")
66676)]
66677#[cfg_attr(
66678 target_arch = "arm",
66679 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66680)]
66681pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) {
66682 vst1q_s8_x3(transmute(a), transmute(b))
66683}
66684#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"]
66686#[doc = "## Safety"]
66687#[doc = " * Neon instrinsic unsafe"]
66688#[inline]
66689#[target_feature(enable = "neon")]
66690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66691#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66692#[cfg_attr(
66693 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66694 assert_instr(st1)
66695)]
66696#[cfg_attr(
66697 not(target_arch = "arm"),
66698 stable(feature = "neon_intrinsics", since = "1.59.0")
66699)]
66700#[cfg_attr(
66701 target_arch = "arm",
66702 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66703)]
66704pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) {
66705 vst1q_s8_x4(transmute(a), transmute(b))
66706}
66707#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"]
66709#[doc = "## Safety"]
66710#[doc = " * Neon instrinsic unsafe"]
66711#[inline]
66712#[target_feature(enable = "neon")]
66713#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66714#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66715#[cfg_attr(
66716 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66717 assert_instr(st1)
66718)]
66719#[cfg_attr(
66720 not(target_arch = "arm"),
66721 stable(feature = "neon_intrinsics", since = "1.59.0")
66722)]
66723#[cfg_attr(
66724 target_arch = "arm",
66725 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66726)]
66727pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) {
66728 vst1_s16_x2(transmute(a), transmute(b))
66729}
66730#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"]
66732#[doc = "## Safety"]
66733#[doc = " * Neon instrinsic unsafe"]
66734#[inline]
66735#[target_feature(enable = "neon")]
66736#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66737#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66738#[cfg_attr(
66739 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66740 assert_instr(st1)
66741)]
66742#[cfg_attr(
66743 not(target_arch = "arm"),
66744 stable(feature = "neon_intrinsics", since = "1.59.0")
66745)]
66746#[cfg_attr(
66747 target_arch = "arm",
66748 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66749)]
66750pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) {
66751 vst1_s16_x3(transmute(a), transmute(b))
66752}
66753#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"]
66755#[doc = "## Safety"]
66756#[doc = " * Neon instrinsic unsafe"]
66757#[inline]
66758#[target_feature(enable = "neon")]
66759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66761#[cfg_attr(
66762 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66763 assert_instr(st1)
66764)]
66765#[cfg_attr(
66766 not(target_arch = "arm"),
66767 stable(feature = "neon_intrinsics", since = "1.59.0")
66768)]
66769#[cfg_attr(
66770 target_arch = "arm",
66771 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66772)]
66773pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) {
66774 vst1_s16_x4(transmute(a), transmute(b))
66775}
66776#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"]
66778#[doc = "## Safety"]
66779#[doc = " * Neon instrinsic unsafe"]
66780#[inline]
66781#[target_feature(enable = "neon")]
66782#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66783#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66784#[cfg_attr(
66785 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66786 assert_instr(st1)
66787)]
66788#[cfg_attr(
66789 not(target_arch = "arm"),
66790 stable(feature = "neon_intrinsics", since = "1.59.0")
66791)]
66792#[cfg_attr(
66793 target_arch = "arm",
66794 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66795)]
66796pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) {
66797 vst1q_s16_x2(transmute(a), transmute(b))
66798}
66799#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"]
66801#[doc = "## Safety"]
66802#[doc = " * Neon instrinsic unsafe"]
66803#[inline]
66804#[target_feature(enable = "neon")]
66805#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66806#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66807#[cfg_attr(
66808 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66809 assert_instr(st1)
66810)]
66811#[cfg_attr(
66812 not(target_arch = "arm"),
66813 stable(feature = "neon_intrinsics", since = "1.59.0")
66814)]
66815#[cfg_attr(
66816 target_arch = "arm",
66817 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66818)]
66819pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) {
66820 vst1q_s16_x3(transmute(a), transmute(b))
66821}
66822#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"]
66824#[doc = "## Safety"]
66825#[doc = " * Neon instrinsic unsafe"]
66826#[inline]
66827#[target_feature(enable = "neon")]
66828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66829#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66830#[cfg_attr(
66831 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66832 assert_instr(st1)
66833)]
66834#[cfg_attr(
66835 not(target_arch = "arm"),
66836 stable(feature = "neon_intrinsics", since = "1.59.0")
66837)]
66838#[cfg_attr(
66839 target_arch = "arm",
66840 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66841)]
66842pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) {
66843 vst1q_s16_x4(transmute(a), transmute(b))
66844}
66845#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"]
66847#[doc = "## Safety"]
66848#[doc = " * Neon instrinsic unsafe"]
66849#[inline]
66850#[target_feature(enable = "neon")]
66851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66852#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66853#[cfg_attr(
66854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66855 assert_instr(st1)
66856)]
66857#[cfg_attr(
66858 not(target_arch = "arm"),
66859 stable(feature = "neon_intrinsics", since = "1.59.0")
66860)]
66861#[cfg_attr(
66862 target_arch = "arm",
66863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66864)]
66865pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) {
66866 vst1_s32_x2(transmute(a), transmute(b))
66867}
66868#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"]
66870#[doc = "## Safety"]
66871#[doc = " * Neon instrinsic unsafe"]
66872#[inline]
66873#[target_feature(enable = "neon")]
66874#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66875#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66876#[cfg_attr(
66877 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66878 assert_instr(st1)
66879)]
66880#[cfg_attr(
66881 not(target_arch = "arm"),
66882 stable(feature = "neon_intrinsics", since = "1.59.0")
66883)]
66884#[cfg_attr(
66885 target_arch = "arm",
66886 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66887)]
66888pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) {
66889 vst1_s32_x3(transmute(a), transmute(b))
66890}
66891#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"]
66893#[doc = "## Safety"]
66894#[doc = " * Neon instrinsic unsafe"]
66895#[inline]
66896#[target_feature(enable = "neon")]
66897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66899#[cfg_attr(
66900 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66901 assert_instr(st1)
66902)]
66903#[cfg_attr(
66904 not(target_arch = "arm"),
66905 stable(feature = "neon_intrinsics", since = "1.59.0")
66906)]
66907#[cfg_attr(
66908 target_arch = "arm",
66909 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66910)]
66911pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) {
66912 vst1_s32_x4(transmute(a), transmute(b))
66913}
66914#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"]
66916#[doc = "## Safety"]
66917#[doc = " * Neon instrinsic unsafe"]
66918#[inline]
66919#[target_feature(enable = "neon")]
66920#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66921#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66922#[cfg_attr(
66923 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66924 assert_instr(st1)
66925)]
66926#[cfg_attr(
66927 not(target_arch = "arm"),
66928 stable(feature = "neon_intrinsics", since = "1.59.0")
66929)]
66930#[cfg_attr(
66931 target_arch = "arm",
66932 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66933)]
66934pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) {
66935 vst1q_s32_x2(transmute(a), transmute(b))
66936}
66937#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"]
66939#[doc = "## Safety"]
66940#[doc = " * Neon instrinsic unsafe"]
66941#[inline]
66942#[target_feature(enable = "neon")]
66943#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66944#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66945#[cfg_attr(
66946 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66947 assert_instr(st1)
66948)]
66949#[cfg_attr(
66950 not(target_arch = "arm"),
66951 stable(feature = "neon_intrinsics", since = "1.59.0")
66952)]
66953#[cfg_attr(
66954 target_arch = "arm",
66955 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66956)]
66957pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) {
66958 vst1q_s32_x3(transmute(a), transmute(b))
66959}
66960#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"]
66962#[doc = "## Safety"]
66963#[doc = " * Neon instrinsic unsafe"]
66964#[inline]
66965#[target_feature(enable = "neon")]
66966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66967#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66968#[cfg_attr(
66969 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66970 assert_instr(st1)
66971)]
66972#[cfg_attr(
66973 not(target_arch = "arm"),
66974 stable(feature = "neon_intrinsics", since = "1.59.0")
66975)]
66976#[cfg_attr(
66977 target_arch = "arm",
66978 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66979)]
66980pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) {
66981 vst1q_s32_x4(transmute(a), transmute(b))
66982}
66983#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"]
66985#[doc = "## Safety"]
66986#[doc = " * Neon instrinsic unsafe"]
66987#[inline]
66988#[target_feature(enable = "neon")]
66989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66991#[cfg_attr(
66992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66993 assert_instr(st1)
66994)]
66995#[cfg_attr(
66996 not(target_arch = "arm"),
66997 stable(feature = "neon_intrinsics", since = "1.59.0")
66998)]
66999#[cfg_attr(
67000 target_arch = "arm",
67001 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67002)]
67003pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) {
67004 vst1_s64_x2(transmute(a), transmute(b))
67005}
67006#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"]
67008#[doc = "## Safety"]
67009#[doc = " * Neon instrinsic unsafe"]
67010#[inline]
67011#[target_feature(enable = "neon")]
67012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67014#[cfg_attr(
67015 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67016 assert_instr(st1)
67017)]
67018#[cfg_attr(
67019 not(target_arch = "arm"),
67020 stable(feature = "neon_intrinsics", since = "1.59.0")
67021)]
67022#[cfg_attr(
67023 target_arch = "arm",
67024 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67025)]
67026pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) {
67027 vst1_s64_x3(transmute(a), transmute(b))
67028}
67029#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"]
67031#[doc = "## Safety"]
67032#[doc = " * Neon instrinsic unsafe"]
67033#[inline]
67034#[target_feature(enable = "neon")]
67035#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67036#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67037#[cfg_attr(
67038 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67039 assert_instr(st1)
67040)]
67041#[cfg_attr(
67042 not(target_arch = "arm"),
67043 stable(feature = "neon_intrinsics", since = "1.59.0")
67044)]
67045#[cfg_attr(
67046 target_arch = "arm",
67047 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67048)]
67049pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) {
67050 vst1_s64_x4(transmute(a), transmute(b))
67051}
67052#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"]
67054#[doc = "## Safety"]
67055#[doc = " * Neon instrinsic unsafe"]
67056#[inline]
67057#[target_feature(enable = "neon")]
67058#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67059#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67060#[cfg_attr(
67061 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67062 assert_instr(st1)
67063)]
67064#[cfg_attr(
67065 not(target_arch = "arm"),
67066 stable(feature = "neon_intrinsics", since = "1.59.0")
67067)]
67068#[cfg_attr(
67069 target_arch = "arm",
67070 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67071)]
67072pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) {
67073 vst1q_s64_x2(transmute(a), transmute(b))
67074}
67075#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"]
67077#[doc = "## Safety"]
67078#[doc = " * Neon instrinsic unsafe"]
67079#[inline]
67080#[target_feature(enable = "neon")]
67081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67083#[cfg_attr(
67084 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67085 assert_instr(st1)
67086)]
67087#[cfg_attr(
67088 not(target_arch = "arm"),
67089 stable(feature = "neon_intrinsics", since = "1.59.0")
67090)]
67091#[cfg_attr(
67092 target_arch = "arm",
67093 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67094)]
67095pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) {
67096 vst1q_s64_x3(transmute(a), transmute(b))
67097}
67098#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"]
67100#[doc = "## Safety"]
67101#[doc = " * Neon instrinsic unsafe"]
67102#[inline]
67103#[target_feature(enable = "neon")]
67104#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67105#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67106#[cfg_attr(
67107 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67108 assert_instr(st1)
67109)]
67110#[cfg_attr(
67111 not(target_arch = "arm"),
67112 stable(feature = "neon_intrinsics", since = "1.59.0")
67113)]
67114#[cfg_attr(
67115 target_arch = "arm",
67116 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67117)]
67118pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) {
67119 vst1q_s64_x4(transmute(a), transmute(b))
67120}
67121#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"]
67123#[doc = "## Safety"]
67124#[doc = " * Neon instrinsic unsafe"]
67125#[inline]
67126#[target_feature(enable = "neon")]
67127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67128#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67129#[cfg_attr(
67130 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67131 assert_instr(st1)
67132)]
67133#[cfg_attr(
67134 not(target_arch = "arm"),
67135 stable(feature = "neon_intrinsics", since = "1.59.0")
67136)]
67137#[cfg_attr(
67138 target_arch = "arm",
67139 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67140)]
67141pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) {
67142 vst1_s8_x2(transmute(a), transmute(b))
67143}
67144#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"]
67146#[doc = "## Safety"]
67147#[doc = " * Neon instrinsic unsafe"]
67148#[inline]
67149#[target_feature(enable = "neon")]
67150#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67151#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67152#[cfg_attr(
67153 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67154 assert_instr(st1)
67155)]
67156#[cfg_attr(
67157 not(target_arch = "arm"),
67158 stable(feature = "neon_intrinsics", since = "1.59.0")
67159)]
67160#[cfg_attr(
67161 target_arch = "arm",
67162 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67163)]
67164pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) {
67165 vst1_s8_x3(transmute(a), transmute(b))
67166}
67167#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"]
67169#[doc = "## Safety"]
67170#[doc = " * Neon instrinsic unsafe"]
67171#[inline]
67172#[target_feature(enable = "neon")]
67173#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67174#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67175#[cfg_attr(
67176 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67177 assert_instr(st1)
67178)]
67179#[cfg_attr(
67180 not(target_arch = "arm"),
67181 stable(feature = "neon_intrinsics", since = "1.59.0")
67182)]
67183#[cfg_attr(
67184 target_arch = "arm",
67185 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67186)]
67187pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) {
67188 vst1_s8_x4(transmute(a), transmute(b))
67189}
67190#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"]
67192#[doc = "## Safety"]
67193#[doc = " * Neon instrinsic unsafe"]
67194#[inline]
67195#[target_feature(enable = "neon")]
67196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67197#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67198#[cfg_attr(
67199 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67200 assert_instr(st1)
67201)]
67202#[cfg_attr(
67203 not(target_arch = "arm"),
67204 stable(feature = "neon_intrinsics", since = "1.59.0")
67205)]
67206#[cfg_attr(
67207 target_arch = "arm",
67208 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67209)]
67210pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) {
67211 vst1q_s8_x2(transmute(a), transmute(b))
67212}
67213#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"]
67215#[doc = "## Safety"]
67216#[doc = " * Neon instrinsic unsafe"]
67217#[inline]
67218#[target_feature(enable = "neon")]
67219#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67220#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67221#[cfg_attr(
67222 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67223 assert_instr(st1)
67224)]
67225#[cfg_attr(
67226 not(target_arch = "arm"),
67227 stable(feature = "neon_intrinsics", since = "1.59.0")
67228)]
67229#[cfg_attr(
67230 target_arch = "arm",
67231 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67232)]
67233pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) {
67234 vst1q_s8_x3(transmute(a), transmute(b))
67235}
67236#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"]
67238#[doc = "## Safety"]
67239#[doc = " * Neon instrinsic unsafe"]
67240#[inline]
67241#[target_feature(enable = "neon")]
67242#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67243#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67244#[cfg_attr(
67245 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67246 assert_instr(st1)
67247)]
67248#[cfg_attr(
67249 not(target_arch = "arm"),
67250 stable(feature = "neon_intrinsics", since = "1.59.0")
67251)]
67252#[cfg_attr(
67253 target_arch = "arm",
67254 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67255)]
67256pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) {
67257 vst1q_s8_x4(transmute(a), transmute(b))
67258}
67259#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"]
67261#[doc = "## Safety"]
67262#[doc = " * Neon instrinsic unsafe"]
67263#[inline]
67264#[target_feature(enable = "neon")]
67265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67266#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67267#[cfg_attr(
67268 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67269 assert_instr(st1)
67270)]
67271#[cfg_attr(
67272 not(target_arch = "arm"),
67273 stable(feature = "neon_intrinsics", since = "1.59.0")
67274)]
67275#[cfg_attr(
67276 target_arch = "arm",
67277 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67278)]
67279pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) {
67280 vst1_s16_x2(transmute(a), transmute(b))
67281}
67282#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"]
67284#[doc = "## Safety"]
67285#[doc = " * Neon instrinsic unsafe"]
67286#[inline]
67287#[target_feature(enable = "neon")]
67288#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67289#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67290#[cfg_attr(
67291 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67292 assert_instr(st1)
67293)]
67294#[cfg_attr(
67295 not(target_arch = "arm"),
67296 stable(feature = "neon_intrinsics", since = "1.59.0")
67297)]
67298#[cfg_attr(
67299 target_arch = "arm",
67300 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67301)]
67302pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) {
67303 vst1_s16_x3(transmute(a), transmute(b))
67304}
67305#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"]
67307#[doc = "## Safety"]
67308#[doc = " * Neon instrinsic unsafe"]
67309#[inline]
67310#[target_feature(enable = "neon")]
67311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67312#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67313#[cfg_attr(
67314 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67315 assert_instr(st1)
67316)]
67317#[cfg_attr(
67318 not(target_arch = "arm"),
67319 stable(feature = "neon_intrinsics", since = "1.59.0")
67320)]
67321#[cfg_attr(
67322 target_arch = "arm",
67323 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67324)]
67325pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) {
67326 vst1_s16_x4(transmute(a), transmute(b))
67327}
67328#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"]
67330#[doc = "## Safety"]
67331#[doc = " * Neon instrinsic unsafe"]
67332#[inline]
67333#[target_feature(enable = "neon")]
67334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67335#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67336#[cfg_attr(
67337 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67338 assert_instr(st1)
67339)]
67340#[cfg_attr(
67341 not(target_arch = "arm"),
67342 stable(feature = "neon_intrinsics", since = "1.59.0")
67343)]
67344#[cfg_attr(
67345 target_arch = "arm",
67346 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67347)]
67348pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) {
67349 vst1q_s16_x2(transmute(a), transmute(b))
67350}
67351#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"]
67353#[doc = "## Safety"]
67354#[doc = " * Neon instrinsic unsafe"]
67355#[inline]
67356#[target_feature(enable = "neon")]
67357#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67358#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67359#[cfg_attr(
67360 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67361 assert_instr(st1)
67362)]
67363#[cfg_attr(
67364 not(target_arch = "arm"),
67365 stable(feature = "neon_intrinsics", since = "1.59.0")
67366)]
67367#[cfg_attr(
67368 target_arch = "arm",
67369 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67370)]
67371pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
67372 vst1q_s16_x3(transmute(a), transmute(b))
67373}
67374#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
67375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"]
67376#[doc = "## Safety"]
67377#[doc = " * Neon instrinsic unsafe"]
67378#[inline]
67379#[target_feature(enable = "neon")]
67380#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67381#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
67382#[cfg_attr(
67383 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67384 assert_instr(st1)
67385)]
67386#[cfg_attr(
67387 not(target_arch = "arm"),
67388 stable(feature = "neon_intrinsics", since = "1.59.0")
67389)]
67390#[cfg_attr(
67391 target_arch = "arm",
67392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67393)]
67394pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) {
67395 vst1q_s16_x4(transmute(a), transmute(b))
67396}
67397#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v1i64)"]
67399#[doc = "## Safety"]
67400#[doc = " * Neon instrinsic unsafe"]
67401#[inline]
67402#[target_feature(enable = "neon")]
67403#[cfg(target_arch = "arm")]
67404#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67405#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67406#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
67407unsafe fn vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32) {
67408 unsafe extern "unadjusted" {
67409 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v1i64.p0")]
67410 fn _vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32);
67411 }
67412 _vst1_v1i64(addr, val, align)
67413}
67414#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2f32)"]
67416#[doc = "## Safety"]
67417#[doc = " * Neon instrinsic unsafe"]
67418#[inline]
67419#[target_feature(enable = "neon")]
67420#[cfg(target_arch = "arm")]
67421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67422#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67423#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67424unsafe fn vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32) {
67425 unsafe extern "unadjusted" {
67426 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2f32.p0")]
67427 fn _vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32);
67428 }
67429 _vst1_v2f32(addr, val, align)
67430}
67431#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2i32)"]
67433#[doc = "## Safety"]
67434#[doc = " * Neon instrinsic unsafe"]
67435#[inline]
67436#[target_feature(enable = "neon")]
67437#[cfg(target_arch = "arm")]
67438#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67439#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67440#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67441unsafe fn vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32) {
67442 unsafe extern "unadjusted" {
67443 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i32.p0")]
67444 fn _vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32);
67445 }
67446 _vst1_v2i32(addr, val, align)
67447}
67448#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4i16)"]
67450#[doc = "## Safety"]
67451#[doc = " * Neon instrinsic unsafe"]
67452#[inline]
67453#[target_feature(enable = "neon")]
67454#[cfg(target_arch = "arm")]
67455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67456#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67457#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67458unsafe fn vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32) {
67459 unsafe extern "unadjusted" {
67460 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i16.p0")]
67461 fn _vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32);
67462 }
67463 _vst1_v4i16(addr, val, align)
67464}
67465#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v8i8)"]
67467#[doc = "## Safety"]
67468#[doc = " * Neon instrinsic unsafe"]
67469#[inline]
67470#[target_feature(enable = "neon")]
67471#[cfg(target_arch = "arm")]
67472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67473#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67474#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
67475unsafe fn vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32) {
67476 unsafe extern "unadjusted" {
67477 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i8.p0")]
67478 fn _vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32);
67479 }
67480 _vst1_v8i8(addr, val, align)
67481}
67482#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v16i8)"]
67484#[doc = "## Safety"]
67485#[doc = " * Neon instrinsic unsafe"]
67486#[inline]
67487#[target_feature(enable = "neon")]
67488#[cfg(target_arch = "arm")]
67489#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67490#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67491#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
67492unsafe fn vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32) {
67493 unsafe extern "unadjusted" {
67494 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v16i8.p0")]
67495 fn _vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32);
67496 }
67497 _vst1q_v16i8(addr, val, align)
67498}
67499#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v2i64)"]
67501#[doc = "## Safety"]
67502#[doc = " * Neon instrinsic unsafe"]
67503#[inline]
67504#[target_feature(enable = "neon")]
67505#[cfg(target_arch = "arm")]
67506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67507#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67508#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
67509unsafe fn vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32) {
67510 unsafe extern "unadjusted" {
67511 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i64.p0")]
67512 fn _vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32);
67513 }
67514 _vst1q_v2i64(addr, val, align)
67515}
67516#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4f32)"]
67518#[doc = "## Safety"]
67519#[doc = " * Neon instrinsic unsafe"]
67520#[inline]
67521#[target_feature(enable = "neon")]
67522#[cfg(target_arch = "arm")]
67523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67524#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67525#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67526unsafe fn vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32) {
67527 unsafe extern "unadjusted" {
67528 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4f32.p0")]
67529 fn _vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32);
67530 }
67531 _vst1q_v4f32(addr, val, align)
67532}
67533#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4i32)"]
67535#[doc = "## Safety"]
67536#[doc = " * Neon instrinsic unsafe"]
67537#[inline]
67538#[target_feature(enable = "neon")]
67539#[cfg(target_arch = "arm")]
67540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67541#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67542#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67543unsafe fn vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32) {
67544 unsafe extern "unadjusted" {
67545 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i32.p0")]
67546 fn _vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32);
67547 }
67548 _vst1q_v4i32(addr, val, align)
67549}
67550#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8i16)"]
67552#[doc = "## Safety"]
67553#[doc = " * Neon instrinsic unsafe"]
67554#[inline]
67555#[target_feature(enable = "neon")]
67556#[cfg(target_arch = "arm")]
67557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67558#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67559#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67560unsafe fn vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32) {
67561 unsafe extern "unadjusted" {
67562 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i16.p0")]
67563 fn _vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32);
67564 }
67565 _vst1q_v8i16(addr, val, align)
67566}
67567#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"]
67569#[doc = "## Safety"]
67570#[doc = " * Neon instrinsic unsafe"]
67571#[inline]
67572#[cfg(target_arch = "arm")]
67573#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67574#[target_feature(enable = "neon,fp16")]
67575#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67576#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67577unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
67578 unsafe extern "unadjusted" {
67579 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4f16.p0")]
67580 fn _vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32);
67581 }
67582 _vst1_v4f16(addr, val, align)
67583}
67584#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"]
67586#[doc = "## Safety"]
67587#[doc = " * Neon instrinsic unsafe"]
67588#[inline]
67589#[cfg(target_arch = "arm")]
67590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67591#[target_feature(enable = "neon,fp16")]
67592#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67593#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67594unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) {
67595 unsafe extern "unadjusted" {
67596 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8f16.p0")]
67597 fn _vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32);
67598 }
67599 _vst1q_v8f16(addr, val, align)
67600}
67601#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
67602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"]
67603#[doc = "## Safety"]
67604#[doc = " * Neon instrinsic unsafe"]
67605#[inline]
67606#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
67607#[target_feature(enable = "neon,aes")]
67608#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
67609#[cfg_attr(
67610 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67611 assert_instr(nop, LANE = 0)
67612)]
67613#[rustc_legacy_const_generics(2)]
67614#[cfg_attr(
67615 not(target_arch = "arm"),
67616 stable(feature = "neon_intrinsics", since = "1.59.0")
67617)]
67618#[cfg_attr(
67619 target_arch = "arm",
67620 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67621)]
67622pub unsafe fn vst1q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2_t) {
67623 static_assert_uimm_bits!(LANE, 1);
67624 *a = simd_extract!(b, LANE as u32);
67625}
67626#[doc = "Store multiple 2-element structures from two registers"]
67627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
67628#[doc = "## Safety"]
67629#[doc = " * Neon instrinsic unsafe"]
67630#[inline]
67631#[cfg(not(target_arch = "arm"))]
67632#[target_feature(enable = "neon,fp16")]
67633#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67634#[cfg_attr(test, assert_instr(st2))]
67635pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
67636 unsafe extern "unadjusted" {
67637 #[cfg_attr(
67638 any(target_arch = "aarch64", target_arch = "arm64ec"),
67639 link_name = "llvm.aarch64.neon.st2.v4f16.p0i8"
67640 )]
67641 fn _vst2_f16(a: float16x4_t, b: float16x4_t, ptr: *mut i8);
67642 }
67643 _vst2_f16(b.0, b.1, a as _)
67644}
67645#[doc = "Store multiple 2-element structures from two registers"]
67646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
67647#[doc = "## Safety"]
67648#[doc = " * Neon instrinsic unsafe"]
67649#[inline]
67650#[cfg(not(target_arch = "arm"))]
67651#[target_feature(enable = "neon,fp16")]
67652#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67653#[cfg_attr(test, assert_instr(st2))]
67654pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
67655 unsafe extern "unadjusted" {
67656 #[cfg_attr(
67657 any(target_arch = "aarch64", target_arch = "arm64ec"),
67658 link_name = "llvm.aarch64.neon.st2.v8f16.p0i8"
67659 )]
67660 fn _vst2q_f16(a: float16x8_t, b: float16x8_t, ptr: *mut i8);
67661 }
67662 _vst2q_f16(b.0, b.1, a as _)
67663}
67664#[doc = "Store multiple 2-element structures from two registers"]
67665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
67666#[doc = "## Safety"]
67667#[doc = " * Neon instrinsic unsafe"]
67668#[inline]
67669#[cfg(target_arch = "arm")]
67670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67671#[target_feature(enable = "neon,fp16")]
67672#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67673#[cfg_attr(test, assert_instr(vst2))]
67674pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
67675 unsafe extern "unadjusted" {
67676 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v4f16")]
67677 fn _vst2_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, size: i32);
67678 }
67679 _vst2_f16(a as _, b.0, b.1, 2)
67680}
67681#[doc = "Store multiple 2-element structures from two registers"]
67682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
67683#[doc = "## Safety"]
67684#[doc = " * Neon instrinsic unsafe"]
67685#[inline]
67686#[cfg(target_arch = "arm")]
67687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67688#[target_feature(enable = "neon,fp16")]
67689#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67690#[cfg_attr(test, assert_instr(vst2))]
67691pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
67692 unsafe extern "unadjusted" {
67693 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v8f16")]
67694 fn _vst2q_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, size: i32);
67695 }
67696 _vst2q_f16(a as _, b.0, b.1, 2)
67697}
67698#[doc = "Store multiple 2-element structures from two registers"]
67699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
67700#[doc = "## Safety"]
67701#[doc = " * Neon instrinsic unsafe"]
67702#[inline]
67703#[target_feature(enable = "neon")]
67704#[cfg(not(target_arch = "arm"))]
67705#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67706#[cfg_attr(test, assert_instr(st2))]
67707pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
67708 unsafe extern "unadjusted" {
67709 #[cfg_attr(
67710 any(target_arch = "aarch64", target_arch = "arm64ec"),
67711 link_name = "llvm.aarch64.neon.st2.v2f32.p0i8"
67712 )]
67713 fn _vst2_f32(a: float32x2_t, b: float32x2_t, ptr: *mut i8);
67714 }
67715 _vst2_f32(b.0, b.1, a as _)
67716}
67717#[doc = "Store multiple 2-element structures from two registers"]
67718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
67719#[doc = "## Safety"]
67720#[doc = " * Neon instrinsic unsafe"]
67721#[inline]
67722#[target_feature(enable = "neon")]
67723#[cfg(not(target_arch = "arm"))]
67724#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67725#[cfg_attr(test, assert_instr(st2))]
67726pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
67727 unsafe extern "unadjusted" {
67728 #[cfg_attr(
67729 any(target_arch = "aarch64", target_arch = "arm64ec"),
67730 link_name = "llvm.aarch64.neon.st2.v4f32.p0i8"
67731 )]
67732 fn _vst2q_f32(a: float32x4_t, b: float32x4_t, ptr: *mut i8);
67733 }
67734 _vst2q_f32(b.0, b.1, a as _)
67735}
67736#[doc = "Store multiple 2-element structures from two registers"]
67737#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
67738#[doc = "## Safety"]
67739#[doc = " * Neon instrinsic unsafe"]
67740#[inline]
67741#[target_feature(enable = "neon")]
67742#[cfg(not(target_arch = "arm"))]
67743#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67744#[cfg_attr(test, assert_instr(st2))]
67745pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
67746 unsafe extern "unadjusted" {
67747 #[cfg_attr(
67748 any(target_arch = "aarch64", target_arch = "arm64ec"),
67749 link_name = "llvm.aarch64.neon.st2.v8i8.p0i8"
67750 )]
67751 fn _vst2_s8(a: int8x8_t, b: int8x8_t, ptr: *mut i8);
67752 }
67753 _vst2_s8(b.0, b.1, a as _)
67754}
67755#[doc = "Store multiple 2-element structures from two registers"]
67756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
67757#[doc = "## Safety"]
67758#[doc = " * Neon instrinsic unsafe"]
67759#[inline]
67760#[target_feature(enable = "neon")]
67761#[cfg(not(target_arch = "arm"))]
67762#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67763#[cfg_attr(test, assert_instr(st2))]
67764pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
67765 unsafe extern "unadjusted" {
67766 #[cfg_attr(
67767 any(target_arch = "aarch64", target_arch = "arm64ec"),
67768 link_name = "llvm.aarch64.neon.st2.v16i8.p0i8"
67769 )]
67770 fn _vst2q_s8(a: int8x16_t, b: int8x16_t, ptr: *mut i8);
67771 }
67772 _vst2q_s8(b.0, b.1, a as _)
67773}
67774#[doc = "Store multiple 2-element structures from two registers"]
67775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
67776#[doc = "## Safety"]
67777#[doc = " * Neon instrinsic unsafe"]
67778#[inline]
67779#[target_feature(enable = "neon")]
67780#[cfg(not(target_arch = "arm"))]
67781#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67782#[cfg_attr(test, assert_instr(st2))]
67783pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
67784 unsafe extern "unadjusted" {
67785 #[cfg_attr(
67786 any(target_arch = "aarch64", target_arch = "arm64ec"),
67787 link_name = "llvm.aarch64.neon.st2.v4i16.p0i8"
67788 )]
67789 fn _vst2_s16(a: int16x4_t, b: int16x4_t, ptr: *mut i8);
67790 }
67791 _vst2_s16(b.0, b.1, a as _)
67792}
67793#[doc = "Store multiple 2-element structures from two registers"]
67794#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
67795#[doc = "## Safety"]
67796#[doc = " * Neon instrinsic unsafe"]
67797#[inline]
67798#[target_feature(enable = "neon")]
67799#[cfg(not(target_arch = "arm"))]
67800#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67801#[cfg_attr(test, assert_instr(st2))]
67802pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
67803 unsafe extern "unadjusted" {
67804 #[cfg_attr(
67805 any(target_arch = "aarch64", target_arch = "arm64ec"),
67806 link_name = "llvm.aarch64.neon.st2.v8i16.p0i8"
67807 )]
67808 fn _vst2q_s16(a: int16x8_t, b: int16x8_t, ptr: *mut i8);
67809 }
67810 _vst2q_s16(b.0, b.1, a as _)
67811}
67812#[doc = "Store multiple 2-element structures from two registers"]
67813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
67814#[doc = "## Safety"]
67815#[doc = " * Neon instrinsic unsafe"]
67816#[inline]
67817#[target_feature(enable = "neon")]
67818#[cfg(not(target_arch = "arm"))]
67819#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67820#[cfg_attr(test, assert_instr(st2))]
67821pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
67822 unsafe extern "unadjusted" {
67823 #[cfg_attr(
67824 any(target_arch = "aarch64", target_arch = "arm64ec"),
67825 link_name = "llvm.aarch64.neon.st2.v2i32.p0i8"
67826 )]
67827 fn _vst2_s32(a: int32x2_t, b: int32x2_t, ptr: *mut i8);
67828 }
67829 _vst2_s32(b.0, b.1, a as _)
67830}
67831#[doc = "Store multiple 2-element structures from two registers"]
67832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
67833#[doc = "## Safety"]
67834#[doc = " * Neon instrinsic unsafe"]
67835#[inline]
67836#[target_feature(enable = "neon")]
67837#[cfg(not(target_arch = "arm"))]
67838#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67839#[cfg_attr(test, assert_instr(st2))]
67840pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
67841 unsafe extern "unadjusted" {
67842 #[cfg_attr(
67843 any(target_arch = "aarch64", target_arch = "arm64ec"),
67844 link_name = "llvm.aarch64.neon.st2.v4i32.p0i8"
67845 )]
67846 fn _vst2q_s32(a: int32x4_t, b: int32x4_t, ptr: *mut i8);
67847 }
67848 _vst2q_s32(b.0, b.1, a as _)
67849}
67850#[doc = "Store multiple 2-element structures from two registers"]
67851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
67852#[doc = "## Safety"]
67853#[doc = " * Neon instrinsic unsafe"]
67854#[inline]
67855#[cfg(target_arch = "arm")]
67856#[target_feature(enable = "neon,v7")]
67857#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67858#[cfg_attr(test, assert_instr(vst2))]
67859pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
67860 unsafe extern "unadjusted" {
67861 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v2f32.p0")]
67862 fn _vst2_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, size: i32);
67863 }
67864 _vst2_f32(a as _, b.0, b.1, 4)
67865}
67866#[doc = "Store multiple 2-element structures from two registers"]
67867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
67868#[doc = "## Safety"]
67869#[doc = " * Neon instrinsic unsafe"]
67870#[inline]
67871#[cfg(target_arch = "arm")]
67872#[target_feature(enable = "neon,v7")]
67873#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67874#[cfg_attr(test, assert_instr(vst2))]
67875pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
67876 unsafe extern "unadjusted" {
67877 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4f32.p0")]
67878 fn _vst2q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, size: i32);
67879 }
67880 _vst2q_f32(a as _, b.0, b.1, 4)
67881}
67882#[doc = "Store multiple 2-element structures from two registers"]
67883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
67884#[doc = "## Safety"]
67885#[doc = " * Neon instrinsic unsafe"]
67886#[inline]
67887#[cfg(target_arch = "arm")]
67888#[target_feature(enable = "neon,v7")]
67889#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67890#[cfg_attr(test, assert_instr(vst2))]
67891pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
67892 unsafe extern "unadjusted" {
67893 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v8i8.p0")]
67894 fn _vst2_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, size: i32);
67895 }
67896 _vst2_s8(a as _, b.0, b.1, 1)
67897}
67898#[doc = "Store multiple 2-element structures from two registers"]
67899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
67900#[doc = "## Safety"]
67901#[doc = " * Neon instrinsic unsafe"]
67902#[inline]
67903#[cfg(target_arch = "arm")]
67904#[target_feature(enable = "neon,v7")]
67905#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67906#[cfg_attr(test, assert_instr(vst2))]
67907pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
67908 unsafe extern "unadjusted" {
67909 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v16i8.p0")]
67910 fn _vst2q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, size: i32);
67911 }
67912 _vst2q_s8(a as _, b.0, b.1, 1)
67913}
67914#[doc = "Store multiple 2-element structures from two registers"]
67915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
67916#[doc = "## Safety"]
67917#[doc = " * Neon instrinsic unsafe"]
67918#[inline]
67919#[cfg(target_arch = "arm")]
67920#[target_feature(enable = "neon,v7")]
67921#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67922#[cfg_attr(test, assert_instr(vst2))]
67923pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
67924 unsafe extern "unadjusted" {
67925 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4i16.p0")]
67926 fn _vst2_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, size: i32);
67927 }
67928 _vst2_s16(a as _, b.0, b.1, 2)
67929}
67930#[doc = "Store multiple 2-element structures from two registers"]
67931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
67932#[doc = "## Safety"]
67933#[doc = " * Neon instrinsic unsafe"]
67934#[inline]
67935#[cfg(target_arch = "arm")]
67936#[target_feature(enable = "neon,v7")]
67937#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67938#[cfg_attr(test, assert_instr(vst2))]
67939pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
67940 unsafe extern "unadjusted" {
67941 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v8i16.p0")]
67942 fn _vst2q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, size: i32);
67943 }
67944 _vst2q_s16(a as _, b.0, b.1, 2)
67945}
67946#[doc = "Store multiple 2-element structures from two registers"]
67947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
67948#[doc = "## Safety"]
67949#[doc = " * Neon instrinsic unsafe"]
67950#[inline]
67951#[cfg(target_arch = "arm")]
67952#[target_feature(enable = "neon,v7")]
67953#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67954#[cfg_attr(test, assert_instr(vst2))]
67955pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
67956 unsafe extern "unadjusted" {
67957 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v2i32.p0")]
67958 fn _vst2_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, size: i32);
67959 }
67960 _vst2_s32(a as _, b.0, b.1, 4)
67961}
67962#[doc = "Store multiple 2-element structures from two registers"]
67963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
67964#[doc = "## Safety"]
67965#[doc = " * Neon instrinsic unsafe"]
67966#[inline]
67967#[cfg(target_arch = "arm")]
67968#[target_feature(enable = "neon,v7")]
67969#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67970#[cfg_attr(test, assert_instr(vst2))]
67971pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
67972 unsafe extern "unadjusted" {
67973 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4i32.p0")]
67974 fn _vst2q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, size: i32);
67975 }
67976 _vst2q_s32(a as _, b.0, b.1, 4)
67977}
67978#[doc = "Store multiple 2-element structures from two registers"]
67979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
67980#[doc = "## Safety"]
67981#[doc = " * Neon instrinsic unsafe"]
67982#[inline]
67983#[cfg(not(target_arch = "arm"))]
67984#[rustc_legacy_const_generics(2)]
67985#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67986#[target_feature(enable = "neon,fp16")]
67987#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67988pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
67989 static_assert_uimm_bits!(LANE, 2);
67990 unsafe extern "unadjusted" {
67991 #[cfg_attr(
67992 any(target_arch = "aarch64", target_arch = "arm64ec"),
67993 link_name = "llvm.aarch64.neon.st2lane.v4f16.p0i8"
67994 )]
67995 fn _vst2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *mut i8);
67996 }
67997 _vst2_lane_f16(b.0, b.1, LANE as i64, a as _)
67998}
67999#[doc = "Store multiple 2-element structures from two registers"]
68000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
68001#[doc = "## Safety"]
68002#[doc = " * Neon instrinsic unsafe"]
68003#[inline]
68004#[cfg(not(target_arch = "arm"))]
68005#[rustc_legacy_const_generics(2)]
68006#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68007#[target_feature(enable = "neon,fp16")]
68008#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68009pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
68010 static_assert_uimm_bits!(LANE, 3);
68011 unsafe extern "unadjusted" {
68012 #[cfg_attr(
68013 any(target_arch = "aarch64", target_arch = "arm64ec"),
68014 link_name = "llvm.aarch64.neon.st2lane.v8f16.p0i8"
68015 )]
68016 fn _vst2q_lane_f16(a: float16x8_t, b: float16x8_t, n: i64, ptr: *mut i8);
68017 }
68018 _vst2q_lane_f16(b.0, b.1, LANE as i64, a as _)
68019}
68020#[doc = "Store multiple 2-element structures from two registers"]
68021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
68022#[doc = "## Safety"]
68023#[doc = " * Neon instrinsic unsafe"]
68024#[inline]
68025#[cfg(target_arch = "arm")]
68026#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68027#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68028#[rustc_legacy_const_generics(2)]
68029#[target_feature(enable = "neon,fp16")]
68030#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68031pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
68032 static_assert_uimm_bits!(LANE, 2);
68033 unsafe extern "unadjusted" {
68034 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4f16")]
68035 fn _vst2_lane_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, n: i32, size: i32);
68036 }
68037 _vst2_lane_f16(a as _, b.0, b.1, LANE, 2)
68038}
68039#[doc = "Store multiple 2-element structures from two registers"]
68040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
68041#[doc = "## Safety"]
68042#[doc = " * Neon instrinsic unsafe"]
68043#[inline]
68044#[cfg(target_arch = "arm")]
68045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68046#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68047#[rustc_legacy_const_generics(2)]
68048#[target_feature(enable = "neon,fp16")]
68049#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68050pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
68051 static_assert_uimm_bits!(LANE, 1);
68052 unsafe extern "unadjusted" {
68053 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v8f16")]
68054 fn _vst2q_lane_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, n: i32, size: i32);
68055 }
68056 _vst2q_lane_f16(a as _, b.0, b.1, LANE, 2)
68057}
68058#[doc = "Store multiple 2-element structures from two registers"]
68059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
68060#[doc = "## Safety"]
68061#[doc = " * Neon instrinsic unsafe"]
68062#[inline]
68063#[target_feature(enable = "neon")]
68064#[cfg(not(target_arch = "arm"))]
68065#[rustc_legacy_const_generics(2)]
68066#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68067#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68068pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
68069 static_assert_uimm_bits!(LANE, 1);
68070 unsafe extern "unadjusted" {
68071 #[cfg_attr(
68072 any(target_arch = "aarch64", target_arch = "arm64ec"),
68073 link_name = "llvm.aarch64.neon.st2lane.v2f32.p0i8"
68074 )]
68075 fn _vst2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *mut i8);
68076 }
68077 _vst2_lane_f32(b.0, b.1, LANE as i64, a as _)
68078}
68079#[doc = "Store multiple 2-element structures from two registers"]
68080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
68081#[doc = "## Safety"]
68082#[doc = " * Neon instrinsic unsafe"]
68083#[inline]
68084#[target_feature(enable = "neon")]
68085#[cfg(not(target_arch = "arm"))]
68086#[rustc_legacy_const_generics(2)]
68087#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68088#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68089pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
68090 static_assert_uimm_bits!(LANE, 2);
68091 unsafe extern "unadjusted" {
68092 #[cfg_attr(
68093 any(target_arch = "aarch64", target_arch = "arm64ec"),
68094 link_name = "llvm.aarch64.neon.st2lane.v4f32.p0i8"
68095 )]
68096 fn _vst2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *mut i8);
68097 }
68098 _vst2q_lane_f32(b.0, b.1, LANE as i64, a as _)
68099}
68100#[doc = "Store multiple 2-element structures from two registers"]
68101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
68102#[doc = "## Safety"]
68103#[doc = " * Neon instrinsic unsafe"]
68104#[inline]
68105#[target_feature(enable = "neon")]
68106#[cfg(not(target_arch = "arm"))]
68107#[rustc_legacy_const_generics(2)]
68108#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68109#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68110pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
68111 static_assert_uimm_bits!(LANE, 3);
68112 unsafe extern "unadjusted" {
68113 #[cfg_attr(
68114 any(target_arch = "aarch64", target_arch = "arm64ec"),
68115 link_name = "llvm.aarch64.neon.st2lane.v8i8.p0i8"
68116 )]
68117 fn _vst2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *mut i8);
68118 }
68119 _vst2_lane_s8(b.0, b.1, LANE as i64, a as _)
68120}
68121#[doc = "Store multiple 2-element structures from two registers"]
68122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
68123#[doc = "## Safety"]
68124#[doc = " * Neon instrinsic unsafe"]
68125#[inline]
68126#[target_feature(enable = "neon")]
68127#[cfg(not(target_arch = "arm"))]
68128#[rustc_legacy_const_generics(2)]
68129#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68130#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68131pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
68132 static_assert_uimm_bits!(LANE, 2);
68133 unsafe extern "unadjusted" {
68134 #[cfg_attr(
68135 any(target_arch = "aarch64", target_arch = "arm64ec"),
68136 link_name = "llvm.aarch64.neon.st2lane.v4i16.p0i8"
68137 )]
68138 fn _vst2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *mut i8);
68139 }
68140 _vst2_lane_s16(b.0, b.1, LANE as i64, a as _)
68141}
68142#[doc = "Store multiple 2-element structures from two registers"]
68143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
68144#[doc = "## Safety"]
68145#[doc = " * Neon instrinsic unsafe"]
68146#[inline]
68147#[target_feature(enable = "neon")]
68148#[cfg(not(target_arch = "arm"))]
68149#[rustc_legacy_const_generics(2)]
68150#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68151#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68152pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
68153 static_assert_uimm_bits!(LANE, 3);
68154 unsafe extern "unadjusted" {
68155 #[cfg_attr(
68156 any(target_arch = "aarch64", target_arch = "arm64ec"),
68157 link_name = "llvm.aarch64.neon.st2lane.v8i16.p0i8"
68158 )]
68159 fn _vst2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *mut i8);
68160 }
68161 _vst2q_lane_s16(b.0, b.1, LANE as i64, a as _)
68162}
68163#[doc = "Store multiple 2-element structures from two registers"]
68164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
68165#[doc = "## Safety"]
68166#[doc = " * Neon instrinsic unsafe"]
68167#[inline]
68168#[target_feature(enable = "neon")]
68169#[cfg(not(target_arch = "arm"))]
68170#[rustc_legacy_const_generics(2)]
68171#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68172#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68173pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
68174 static_assert_uimm_bits!(LANE, 1);
68175 unsafe extern "unadjusted" {
68176 #[cfg_attr(
68177 any(target_arch = "aarch64", target_arch = "arm64ec"),
68178 link_name = "llvm.aarch64.neon.st2lane.v2i32.p0i8"
68179 )]
68180 fn _vst2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *mut i8);
68181 }
68182 _vst2_lane_s32(b.0, b.1, LANE as i64, a as _)
68183}
68184#[doc = "Store multiple 2-element structures from two registers"]
68185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
68186#[doc = "## Safety"]
68187#[doc = " * Neon instrinsic unsafe"]
68188#[inline]
68189#[target_feature(enable = "neon")]
68190#[cfg(not(target_arch = "arm"))]
68191#[rustc_legacy_const_generics(2)]
68192#[cfg_attr(test, assert_instr(st2, LANE = 0))]
68193#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68194pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
68195 static_assert_uimm_bits!(LANE, 2);
68196 unsafe extern "unadjusted" {
68197 #[cfg_attr(
68198 any(target_arch = "aarch64", target_arch = "arm64ec"),
68199 link_name = "llvm.aarch64.neon.st2lane.v4i32.p0i8"
68200 )]
68201 fn _vst2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *mut i8);
68202 }
68203 _vst2q_lane_s32(b.0, b.1, LANE as i64, a as _)
68204}
68205#[doc = "Store multiple 2-element structures from two registers"]
68206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
68207#[doc = "## Safety"]
68208#[doc = " * Neon instrinsic unsafe"]
68209#[inline]
68210#[cfg(target_arch = "arm")]
68211#[target_feature(enable = "neon,v7")]
68212#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68213#[rustc_legacy_const_generics(2)]
68214#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68215pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
68216 static_assert_uimm_bits!(LANE, 1);
68217 unsafe extern "unadjusted" {
68218 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v2f32.p0")]
68219 fn _vst2_lane_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, n: i32, size: i32);
68220 }
68221 _vst2_lane_f32(a as _, b.0, b.1, LANE, 4)
68222}
68223#[doc = "Store multiple 2-element structures from two registers"]
68224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
68225#[doc = "## Safety"]
68226#[doc = " * Neon instrinsic unsafe"]
68227#[inline]
68228#[cfg(target_arch = "arm")]
68229#[target_feature(enable = "neon,v7")]
68230#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68231#[rustc_legacy_const_generics(2)]
68232#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68233pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
68234 static_assert_uimm_bits!(LANE, 2);
68235 unsafe extern "unadjusted" {
68236 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4f32.p0")]
68237 fn _vst2q_lane_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, n: i32, size: i32);
68238 }
68239 _vst2q_lane_f32(a as _, b.0, b.1, LANE, 4)
68240}
68241#[doc = "Store multiple 2-element structures from two registers"]
68242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
68243#[doc = "## Safety"]
68244#[doc = " * Neon instrinsic unsafe"]
68245#[inline]
68246#[cfg(target_arch = "arm")]
68247#[target_feature(enable = "neon,v7")]
68248#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68249#[rustc_legacy_const_generics(2)]
68250#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68251pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
68252 static_assert_uimm_bits!(LANE, 3);
68253 unsafe extern "unadjusted" {
68254 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v8i8.p0")]
68255 fn _vst2_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32);
68256 }
68257 _vst2_lane_s8(a as _, b.0, b.1, LANE, 1)
68258}
68259#[doc = "Store multiple 2-element structures from two registers"]
68260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
68261#[doc = "## Safety"]
68262#[doc = " * Neon instrinsic unsafe"]
68263#[inline]
68264#[cfg(target_arch = "arm")]
68265#[target_feature(enable = "neon,v7")]
68266#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68267#[rustc_legacy_const_generics(2)]
68268#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68269pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
68270 static_assert_uimm_bits!(LANE, 2);
68271 unsafe extern "unadjusted" {
68272 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4i16.p0")]
68273 fn _vst2_lane_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, n: i32, size: i32);
68274 }
68275 _vst2_lane_s16(a as _, b.0, b.1, LANE, 2)
68276}
68277#[doc = "Store multiple 2-element structures from two registers"]
68278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
68279#[doc = "## Safety"]
68280#[doc = " * Neon instrinsic unsafe"]
68281#[inline]
68282#[cfg(target_arch = "arm")]
68283#[target_feature(enable = "neon,v7")]
68284#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68285#[rustc_legacy_const_generics(2)]
68286#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68287pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
68288 static_assert_uimm_bits!(LANE, 3);
68289 unsafe extern "unadjusted" {
68290 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v8i16.p0")]
68291 fn _vst2q_lane_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, n: i32, size: i32);
68292 }
68293 _vst2q_lane_s16(a as _, b.0, b.1, LANE, 2)
68294}
68295#[doc = "Store multiple 2-element structures from two registers"]
68296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
68297#[doc = "## Safety"]
68298#[doc = " * Neon instrinsic unsafe"]
68299#[inline]
68300#[cfg(target_arch = "arm")]
68301#[target_feature(enable = "neon,v7")]
68302#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68303#[rustc_legacy_const_generics(2)]
68304#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68305pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
68306 static_assert_uimm_bits!(LANE, 1);
68307 unsafe extern "unadjusted" {
68308 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v2i32.p0")]
68309 fn _vst2_lane_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, n: i32, size: i32);
68310 }
68311 _vst2_lane_s32(a as _, b.0, b.1, LANE, 4)
68312}
68313#[doc = "Store multiple 2-element structures from two registers"]
68314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
68315#[doc = "## Safety"]
68316#[doc = " * Neon instrinsic unsafe"]
68317#[inline]
68318#[cfg(target_arch = "arm")]
68319#[target_feature(enable = "neon,v7")]
68320#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
68321#[rustc_legacy_const_generics(2)]
68322#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68323pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
68324 static_assert_uimm_bits!(LANE, 2);
68325 unsafe extern "unadjusted" {
68326 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4i32.p0")]
68327 fn _vst2q_lane_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, n: i32, size: i32);
68328 }
68329 _vst2q_lane_s32(a as _, b.0, b.1, LANE, 4)
68330}
68331#[doc = "Store multiple 2-element structures from two registers"]
68332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"]
68333#[doc = "## Safety"]
68334#[doc = " * Neon instrinsic unsafe"]
68335#[inline]
68336#[target_feature(enable = "neon")]
68337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68339#[cfg_attr(
68340 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68341 assert_instr(st2, LANE = 0)
68342)]
68343#[rustc_legacy_const_generics(2)]
68344#[cfg_attr(
68345 not(target_arch = "arm"),
68346 stable(feature = "neon_intrinsics", since = "1.59.0")
68347)]
68348#[cfg_attr(
68349 target_arch = "arm",
68350 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68351)]
68352pub unsafe fn vst2_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x2_t) {
68353 static_assert_uimm_bits!(LANE, 3);
68354 vst2_lane_s8::<LANE>(transmute(a), transmute(b))
68355}
68356#[doc = "Store multiple 2-element structures from two registers"]
68357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"]
68358#[doc = "## Safety"]
68359#[doc = " * Neon instrinsic unsafe"]
68360#[inline]
68361#[target_feature(enable = "neon")]
68362#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68363#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68364#[cfg_attr(
68365 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68366 assert_instr(st2, LANE = 0)
68367)]
68368#[rustc_legacy_const_generics(2)]
68369#[cfg_attr(
68370 not(target_arch = "arm"),
68371 stable(feature = "neon_intrinsics", since = "1.59.0")
68372)]
68373#[cfg_attr(
68374 target_arch = "arm",
68375 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68376)]
68377pub unsafe fn vst2_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x2_t) {
68378 static_assert_uimm_bits!(LANE, 2);
68379 vst2_lane_s16::<LANE>(transmute(a), transmute(b))
68380}
68381#[doc = "Store multiple 2-element structures from two registers"]
68382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"]
68383#[doc = "## Safety"]
68384#[doc = " * Neon instrinsic unsafe"]
68385#[inline]
68386#[target_feature(enable = "neon")]
68387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68389#[cfg_attr(
68390 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68391 assert_instr(st2, LANE = 0)
68392)]
68393#[rustc_legacy_const_generics(2)]
68394#[cfg_attr(
68395 not(target_arch = "arm"),
68396 stable(feature = "neon_intrinsics", since = "1.59.0")
68397)]
68398#[cfg_attr(
68399 target_arch = "arm",
68400 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68401)]
68402pub unsafe fn vst2q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x2_t) {
68403 static_assert_uimm_bits!(LANE, 3);
68404 vst2q_lane_s16::<LANE>(transmute(a), transmute(b))
68405}
68406#[doc = "Store multiple 2-element structures from two registers"]
68407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"]
68408#[doc = "## Safety"]
68409#[doc = " * Neon instrinsic unsafe"]
68410#[inline]
68411#[target_feature(enable = "neon")]
68412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68413#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68414#[cfg_attr(
68415 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68416 assert_instr(st2, LANE = 0)
68417)]
68418#[rustc_legacy_const_generics(2)]
68419#[cfg_attr(
68420 not(target_arch = "arm"),
68421 stable(feature = "neon_intrinsics", since = "1.59.0")
68422)]
68423#[cfg_attr(
68424 target_arch = "arm",
68425 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68426)]
68427pub unsafe fn vst2_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x2_t) {
68428 static_assert_uimm_bits!(LANE, 1);
68429 vst2_lane_s32::<LANE>(transmute(a), transmute(b))
68430}
68431#[doc = "Store multiple 2-element structures from two registers"]
68432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"]
68433#[doc = "## Safety"]
68434#[doc = " * Neon instrinsic unsafe"]
68435#[inline]
68436#[target_feature(enable = "neon")]
68437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68438#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68439#[cfg_attr(
68440 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68441 assert_instr(st2, LANE = 0)
68442)]
68443#[rustc_legacy_const_generics(2)]
68444#[cfg_attr(
68445 not(target_arch = "arm"),
68446 stable(feature = "neon_intrinsics", since = "1.59.0")
68447)]
68448#[cfg_attr(
68449 target_arch = "arm",
68450 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68451)]
68452pub unsafe fn vst2q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x2_t) {
68453 static_assert_uimm_bits!(LANE, 2);
68454 vst2q_lane_s32::<LANE>(transmute(a), transmute(b))
68455}
68456#[doc = "Store multiple 2-element structures from two registers"]
68457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"]
68458#[doc = "## Safety"]
68459#[doc = " * Neon instrinsic unsafe"]
68460#[inline]
68461#[target_feature(enable = "neon")]
68462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68464#[cfg_attr(
68465 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68466 assert_instr(st2, LANE = 0)
68467)]
68468#[rustc_legacy_const_generics(2)]
68469#[cfg_attr(
68470 not(target_arch = "arm"),
68471 stable(feature = "neon_intrinsics", since = "1.59.0")
68472)]
68473#[cfg_attr(
68474 target_arch = "arm",
68475 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68476)]
68477pub unsafe fn vst2_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x2_t) {
68478 static_assert_uimm_bits!(LANE, 3);
68479 vst2_lane_s8::<LANE>(transmute(a), transmute(b))
68480}
68481#[doc = "Store multiple 2-element structures from two registers"]
68482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"]
68483#[doc = "## Safety"]
68484#[doc = " * Neon instrinsic unsafe"]
68485#[inline]
68486#[target_feature(enable = "neon")]
68487#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68488#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68489#[cfg_attr(
68490 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68491 assert_instr(st2, LANE = 0)
68492)]
68493#[rustc_legacy_const_generics(2)]
68494#[cfg_attr(
68495 not(target_arch = "arm"),
68496 stable(feature = "neon_intrinsics", since = "1.59.0")
68497)]
68498#[cfg_attr(
68499 target_arch = "arm",
68500 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68501)]
68502pub unsafe fn vst2_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x2_t) {
68503 static_assert_uimm_bits!(LANE, 2);
68504 vst2_lane_s16::<LANE>(transmute(a), transmute(b))
68505}
68506#[doc = "Store multiple 2-element structures from two registers"]
68507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"]
68508#[doc = "## Safety"]
68509#[doc = " * Neon instrinsic unsafe"]
68510#[inline]
68511#[target_feature(enable = "neon")]
68512#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68513#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68514#[cfg_attr(
68515 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68516 assert_instr(st2, LANE = 0)
68517)]
68518#[rustc_legacy_const_generics(2)]
68519#[cfg_attr(
68520 not(target_arch = "arm"),
68521 stable(feature = "neon_intrinsics", since = "1.59.0")
68522)]
68523#[cfg_attr(
68524 target_arch = "arm",
68525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68526)]
68527pub unsafe fn vst2q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x2_t) {
68528 static_assert_uimm_bits!(LANE, 3);
68529 vst2q_lane_s16::<LANE>(transmute(a), transmute(b))
68530}
68531#[doc = "Store multiple 2-element structures from two registers"]
68532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"]
68533#[doc = "## Safety"]
68534#[doc = " * Neon instrinsic unsafe"]
68535#[inline]
68536#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
68537#[target_feature(enable = "neon,aes")]
68538#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
68539#[cfg_attr(
68540 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68541 assert_instr(nop)
68542)]
68543#[cfg_attr(
68544 not(target_arch = "arm"),
68545 stable(feature = "neon_intrinsics", since = "1.59.0")
68546)]
68547#[cfg_attr(
68548 target_arch = "arm",
68549 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68550)]
68551pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) {
68552 vst2_s64(transmute(a), transmute(b))
68553}
68554#[doc = "Store multiple 2-element structures from two registers"]
68555#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
68556#[doc = "## Safety"]
68557#[doc = " * Neon instrinsic unsafe"]
68558#[inline]
68559#[cfg(target_arch = "arm")]
68560#[target_feature(enable = "neon,v7")]
68561#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68562#[cfg_attr(test, assert_instr(nop))]
68563pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
68564 unsafe extern "unadjusted" {
68565 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v1i64.p0")]
68566 fn _vst2_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, size: i32);
68567 }
68568 _vst2_s64(a as _, b.0, b.1, 8)
68569}
68570#[doc = "Store multiple 2-element structures from two registers"]
68571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
68572#[doc = "## Safety"]
68573#[doc = " * Neon instrinsic unsafe"]
68574#[inline]
68575#[target_feature(enable = "neon")]
68576#[cfg(not(target_arch = "arm"))]
68577#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68578#[cfg_attr(test, assert_instr(nop))]
68579pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
68580 unsafe extern "unadjusted" {
68581 #[cfg_attr(
68582 any(target_arch = "aarch64", target_arch = "arm64ec"),
68583 link_name = "llvm.aarch64.neon.st2.v1i64.p0i8"
68584 )]
68585 fn _vst2_s64(a: int64x1_t, b: int64x1_t, ptr: *mut i8);
68586 }
68587 _vst2_s64(b.0, b.1, a as _)
68588}
68589#[doc = "Store multiple 2-element structures from two registers"]
68590#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"]
68591#[doc = "## Safety"]
68592#[doc = " * Neon instrinsic unsafe"]
68593#[inline]
68594#[target_feature(enable = "neon")]
68595#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68596#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
68597#[cfg_attr(
68598 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68599 assert_instr(nop)
68600)]
68601#[cfg_attr(
68602 not(target_arch = "arm"),
68603 stable(feature = "neon_intrinsics", since = "1.59.0")
68604)]
68605#[cfg_attr(
68606 target_arch = "arm",
68607 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68608)]
68609pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) {
68610 vst2_s64(transmute(a), transmute(b))
68611}
68612#[doc = "Store multiple 2-element structures from two registers"]
68613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"]
68614#[doc = "## Safety"]
68615#[doc = " * Neon instrinsic unsafe"]
68616#[inline]
68617#[target_feature(enable = "neon")]
68618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68619#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68620#[cfg_attr(
68621 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68622 assert_instr(st2)
68623)]
68624#[cfg_attr(
68625 not(target_arch = "arm"),
68626 stable(feature = "neon_intrinsics", since = "1.59.0")
68627)]
68628#[cfg_attr(
68629 target_arch = "arm",
68630 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68631)]
68632pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) {
68633 vst2_s8(transmute(a), transmute(b))
68634}
68635#[doc = "Store multiple 2-element structures from two registers"]
68636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"]
68637#[doc = "## Safety"]
68638#[doc = " * Neon instrinsic unsafe"]
68639#[inline]
68640#[target_feature(enable = "neon")]
68641#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68642#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68643#[cfg_attr(
68644 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68645 assert_instr(st2)
68646)]
68647#[cfg_attr(
68648 not(target_arch = "arm"),
68649 stable(feature = "neon_intrinsics", since = "1.59.0")
68650)]
68651#[cfg_attr(
68652 target_arch = "arm",
68653 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68654)]
68655pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) {
68656 vst2q_s8(transmute(a), transmute(b))
68657}
68658#[doc = "Store multiple 2-element structures from two registers"]
68659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"]
68660#[doc = "## Safety"]
68661#[doc = " * Neon instrinsic unsafe"]
68662#[inline]
68663#[target_feature(enable = "neon")]
68664#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68665#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68666#[cfg_attr(
68667 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68668 assert_instr(st2)
68669)]
68670#[cfg_attr(
68671 not(target_arch = "arm"),
68672 stable(feature = "neon_intrinsics", since = "1.59.0")
68673)]
68674#[cfg_attr(
68675 target_arch = "arm",
68676 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68677)]
68678pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) {
68679 vst2_s16(transmute(a), transmute(b))
68680}
68681#[doc = "Store multiple 2-element structures from two registers"]
68682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"]
68683#[doc = "## Safety"]
68684#[doc = " * Neon instrinsic unsafe"]
68685#[inline]
68686#[target_feature(enable = "neon")]
68687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68689#[cfg_attr(
68690 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68691 assert_instr(st2)
68692)]
68693#[cfg_attr(
68694 not(target_arch = "arm"),
68695 stable(feature = "neon_intrinsics", since = "1.59.0")
68696)]
68697#[cfg_attr(
68698 target_arch = "arm",
68699 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68700)]
68701pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) {
68702 vst2q_s16(transmute(a), transmute(b))
68703}
68704#[doc = "Store multiple 2-element structures from two registers"]
68705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"]
68706#[doc = "## Safety"]
68707#[doc = " * Neon instrinsic unsafe"]
68708#[inline]
68709#[target_feature(enable = "neon")]
68710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68711#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68712#[cfg_attr(
68713 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68714 assert_instr(st2)
68715)]
68716#[cfg_attr(
68717 not(target_arch = "arm"),
68718 stable(feature = "neon_intrinsics", since = "1.59.0")
68719)]
68720#[cfg_attr(
68721 target_arch = "arm",
68722 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68723)]
68724pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) {
68725 vst2_s32(transmute(a), transmute(b))
68726}
68727#[doc = "Store multiple 2-element structures from two registers"]
68728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"]
68729#[doc = "## Safety"]
68730#[doc = " * Neon instrinsic unsafe"]
68731#[inline]
68732#[target_feature(enable = "neon")]
68733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68734#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68735#[cfg_attr(
68736 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68737 assert_instr(st2)
68738)]
68739#[cfg_attr(
68740 not(target_arch = "arm"),
68741 stable(feature = "neon_intrinsics", since = "1.59.0")
68742)]
68743#[cfg_attr(
68744 target_arch = "arm",
68745 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68746)]
68747pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) {
68748 vst2q_s32(transmute(a), transmute(b))
68749}
68750#[doc = "Store multiple 2-element structures from two registers"]
68751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"]
68752#[doc = "## Safety"]
68753#[doc = " * Neon instrinsic unsafe"]
68754#[inline]
68755#[target_feature(enable = "neon")]
68756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68758#[cfg_attr(
68759 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68760 assert_instr(st2)
68761)]
68762#[cfg_attr(
68763 not(target_arch = "arm"),
68764 stable(feature = "neon_intrinsics", since = "1.59.0")
68765)]
68766#[cfg_attr(
68767 target_arch = "arm",
68768 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68769)]
68770pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) {
68771 vst2_s8(transmute(a), transmute(b))
68772}
68773#[doc = "Store multiple 2-element structures from two registers"]
68774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"]
68775#[doc = "## Safety"]
68776#[doc = " * Neon instrinsic unsafe"]
68777#[inline]
68778#[target_feature(enable = "neon")]
68779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68781#[cfg_attr(
68782 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68783 assert_instr(st2)
68784)]
68785#[cfg_attr(
68786 not(target_arch = "arm"),
68787 stable(feature = "neon_intrinsics", since = "1.59.0")
68788)]
68789#[cfg_attr(
68790 target_arch = "arm",
68791 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68792)]
68793pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) {
68794 vst2q_s8(transmute(a), transmute(b))
68795}
68796#[doc = "Store multiple 2-element structures from two registers"]
68797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"]
68798#[doc = "## Safety"]
68799#[doc = " * Neon instrinsic unsafe"]
68800#[inline]
68801#[target_feature(enable = "neon")]
68802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68803#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68804#[cfg_attr(
68805 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68806 assert_instr(st2)
68807)]
68808#[cfg_attr(
68809 not(target_arch = "arm"),
68810 stable(feature = "neon_intrinsics", since = "1.59.0")
68811)]
68812#[cfg_attr(
68813 target_arch = "arm",
68814 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68815)]
68816pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) {
68817 vst2_s16(transmute(a), transmute(b))
68818}
68819#[doc = "Store multiple 2-element structures from two registers"]
68820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"]
68821#[doc = "## Safety"]
68822#[doc = " * Neon instrinsic unsafe"]
68823#[inline]
68824#[target_feature(enable = "neon")]
68825#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68826#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68827#[cfg_attr(
68828 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68829 assert_instr(st2)
68830)]
68831#[cfg_attr(
68832 not(target_arch = "arm"),
68833 stable(feature = "neon_intrinsics", since = "1.59.0")
68834)]
68835#[cfg_attr(
68836 target_arch = "arm",
68837 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68838)]
68839pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) {
68840 vst2q_s16(transmute(a), transmute(b))
68841}
68842#[doc = "Store multiple 3-element structures from three registers"]
68843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
68844#[doc = "## Safety"]
68845#[doc = " * Neon instrinsic unsafe"]
68846#[inline]
68847#[cfg(target_arch = "arm")]
68848#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68849#[target_feature(enable = "neon,fp16")]
68850#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68851#[cfg_attr(test, assert_instr(vst3))]
68852pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
68853 unsafe extern "unadjusted" {
68854 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4f16")]
68855 fn _vst3_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, c: float16x4_t, size: i32);
68856 }
68857 _vst3_f16(a as _, b.0, b.1, b.2, 2)
68858}
68859#[doc = "Store multiple 3-element structures from three registers"]
68860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
68861#[doc = "## Safety"]
68862#[doc = " * Neon instrinsic unsafe"]
68863#[inline]
68864#[cfg(target_arch = "arm")]
68865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68866#[target_feature(enable = "neon,fp16")]
68867#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68868#[cfg_attr(test, assert_instr(vst3))]
68869pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
68870 unsafe extern "unadjusted" {
68871 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8f16")]
68872 fn _vst3q_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, c: float16x8_t, size: i32);
68873 }
68874 _vst3q_f16(a as _, b.0, b.1, b.2, 2)
68875}
68876#[doc = "Store multiple 3-element structures from three registers"]
68877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
68878#[doc = "## Safety"]
68879#[doc = " * Neon instrinsic unsafe"]
68880#[inline]
68881#[cfg(not(target_arch = "arm"))]
68882#[target_feature(enable = "neon,fp16")]
68883#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68884#[cfg_attr(test, assert_instr(st3))]
68885pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
68886 unsafe extern "unadjusted" {
68887 #[cfg_attr(
68888 any(target_arch = "aarch64", target_arch = "arm64ec"),
68889 link_name = "llvm.aarch64.neon.st3.v4f16.p0i8"
68890 )]
68891 fn _vst3_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, ptr: *mut i8);
68892 }
68893 _vst3_f16(b.0, b.1, b.2, a as _)
68894}
68895#[doc = "Store multiple 3-element structures from three registers"]
68896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
68897#[doc = "## Safety"]
68898#[doc = " * Neon instrinsic unsafe"]
68899#[inline]
68900#[cfg(not(target_arch = "arm"))]
68901#[target_feature(enable = "neon,fp16")]
68902#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68903#[cfg_attr(test, assert_instr(st3))]
68904pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
68905 unsafe extern "unadjusted" {
68906 #[cfg_attr(
68907 any(target_arch = "aarch64", target_arch = "arm64ec"),
68908 link_name = "llvm.aarch64.neon.st3.v8f16.p0i8"
68909 )]
68910 fn _vst3q_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, ptr: *mut i8);
68911 }
68912 _vst3q_f16(b.0, b.1, b.2, a as _)
68913}
68914#[doc = "Store multiple 3-element structures from three registers"]
68915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
68916#[doc = "## Safety"]
68917#[doc = " * Neon instrinsic unsafe"]
68918#[inline]
68919#[cfg(target_arch = "arm")]
68920#[target_feature(enable = "neon,v7")]
68921#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68922#[cfg_attr(test, assert_instr(vst3))]
68923pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
68924 unsafe extern "unadjusted" {
68925 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v2f32")]
68926 fn _vst3_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, size: i32);
68927 }
68928 _vst3_f32(a as _, b.0, b.1, b.2, 4)
68929}
68930#[doc = "Store multiple 3-element structures from three registers"]
68931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
68932#[doc = "## Safety"]
68933#[doc = " * Neon instrinsic unsafe"]
68934#[inline]
68935#[cfg(target_arch = "arm")]
68936#[target_feature(enable = "neon,v7")]
68937#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68938#[cfg_attr(test, assert_instr(vst3))]
68939pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
68940 unsafe extern "unadjusted" {
68941 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4f32")]
68942 fn _vst3q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, size: i32);
68943 }
68944 _vst3q_f32(a as _, b.0, b.1, b.2, 4)
68945}
68946#[doc = "Store multiple 3-element structures from three registers"]
68947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
68948#[doc = "## Safety"]
68949#[doc = " * Neon instrinsic unsafe"]
68950#[inline]
68951#[cfg(target_arch = "arm")]
68952#[target_feature(enable = "neon,v7")]
68953#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68954#[cfg_attr(test, assert_instr(vst3))]
68955pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
68956 unsafe extern "unadjusted" {
68957 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8i8")]
68958 fn _vst3_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, size: i32);
68959 }
68960 _vst3_s8(a as _, b.0, b.1, b.2, 1)
68961}
68962#[doc = "Store multiple 3-element structures from three registers"]
68963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
68964#[doc = "## Safety"]
68965#[doc = " * Neon instrinsic unsafe"]
68966#[inline]
68967#[cfg(target_arch = "arm")]
68968#[target_feature(enable = "neon,v7")]
68969#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68970#[cfg_attr(test, assert_instr(vst3))]
68971pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
68972 unsafe extern "unadjusted" {
68973 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v16i8")]
68974 fn _vst3q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, size: i32);
68975 }
68976 _vst3q_s8(a as _, b.0, b.1, b.2, 1)
68977}
68978#[doc = "Store multiple 3-element structures from three registers"]
68979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
68980#[doc = "## Safety"]
68981#[doc = " * Neon instrinsic unsafe"]
68982#[inline]
68983#[cfg(target_arch = "arm")]
68984#[target_feature(enable = "neon,v7")]
68985#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68986#[cfg_attr(test, assert_instr(vst3))]
68987pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
68988 unsafe extern "unadjusted" {
68989 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4i16")]
68990 fn _vst3_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, size: i32);
68991 }
68992 _vst3_s16(a as _, b.0, b.1, b.2, 2)
68993}
68994#[doc = "Store multiple 3-element structures from three registers"]
68995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
68996#[doc = "## Safety"]
68997#[doc = " * Neon instrinsic unsafe"]
68998#[inline]
68999#[cfg(target_arch = "arm")]
69000#[target_feature(enable = "neon,v7")]
69001#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69002#[cfg_attr(test, assert_instr(vst3))]
69003pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
69004 unsafe extern "unadjusted" {
69005 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8i16")]
69006 fn _vst3q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, size: i32);
69007 }
69008 _vst3q_s16(a as _, b.0, b.1, b.2, 2)
69009}
69010#[doc = "Store multiple 3-element structures from three registers"]
69011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
69012#[doc = "## Safety"]
69013#[doc = " * Neon instrinsic unsafe"]
69014#[inline]
69015#[cfg(target_arch = "arm")]
69016#[target_feature(enable = "neon,v7")]
69017#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69018#[cfg_attr(test, assert_instr(vst3))]
69019pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
69020 unsafe extern "unadjusted" {
69021 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v2i32")]
69022 fn _vst3_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, size: i32);
69023 }
69024 _vst3_s32(a as _, b.0, b.1, b.2, 4)
69025}
69026#[doc = "Store multiple 3-element structures from three registers"]
69027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
69028#[doc = "## Safety"]
69029#[doc = " * Neon instrinsic unsafe"]
69030#[inline]
69031#[cfg(target_arch = "arm")]
69032#[target_feature(enable = "neon,v7")]
69033#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69034#[cfg_attr(test, assert_instr(vst3))]
69035pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
69036 unsafe extern "unadjusted" {
69037 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4i32")]
69038 fn _vst3q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, size: i32);
69039 }
69040 _vst3q_s32(a as _, b.0, b.1, b.2, 4)
69041}
69042#[doc = "Store multiple 3-element structures from three registers"]
69043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
69044#[doc = "## Safety"]
69045#[doc = " * Neon instrinsic unsafe"]
69046#[inline]
69047#[target_feature(enable = "neon")]
69048#[cfg(not(target_arch = "arm"))]
69049#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69050#[cfg_attr(test, assert_instr(st3))]
69051pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
69052 unsafe extern "unadjusted" {
69053 #[cfg_attr(
69054 any(target_arch = "aarch64", target_arch = "arm64ec"),
69055 link_name = "llvm.aarch64.neon.st3.v2f32.p0i8"
69056 )]
69057 fn _vst3_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut i8);
69058 }
69059 _vst3_f32(b.0, b.1, b.2, a as _)
69060}
69061#[doc = "Store multiple 3-element structures from three registers"]
69062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
69063#[doc = "## Safety"]
69064#[doc = " * Neon instrinsic unsafe"]
69065#[inline]
69066#[target_feature(enable = "neon")]
69067#[cfg(not(target_arch = "arm"))]
69068#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69069#[cfg_attr(test, assert_instr(st3))]
69070pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
69071 unsafe extern "unadjusted" {
69072 #[cfg_attr(
69073 any(target_arch = "aarch64", target_arch = "arm64ec"),
69074 link_name = "llvm.aarch64.neon.st3.v4f32.p0i8"
69075 )]
69076 fn _vst3q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut i8);
69077 }
69078 _vst3q_f32(b.0, b.1, b.2, a as _)
69079}
69080#[doc = "Store multiple 3-element structures from three registers"]
69081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
69082#[doc = "## Safety"]
69083#[doc = " * Neon instrinsic unsafe"]
69084#[inline]
69085#[target_feature(enable = "neon")]
69086#[cfg(not(target_arch = "arm"))]
69087#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69088#[cfg_attr(test, assert_instr(st3))]
69089pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
69090 unsafe extern "unadjusted" {
69091 #[cfg_attr(
69092 any(target_arch = "aarch64", target_arch = "arm64ec"),
69093 link_name = "llvm.aarch64.neon.st3.v8i8.p0i8"
69094 )]
69095 fn _vst3_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8);
69096 }
69097 _vst3_s8(b.0, b.1, b.2, a as _)
69098}
69099#[doc = "Store multiple 3-element structures from three registers"]
69100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
69101#[doc = "## Safety"]
69102#[doc = " * Neon instrinsic unsafe"]
69103#[inline]
69104#[target_feature(enable = "neon")]
69105#[cfg(not(target_arch = "arm"))]
69106#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69107#[cfg_attr(test, assert_instr(st3))]
69108pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
69109 unsafe extern "unadjusted" {
69110 #[cfg_attr(
69111 any(target_arch = "aarch64", target_arch = "arm64ec"),
69112 link_name = "llvm.aarch64.neon.st3.v16i8.p0i8"
69113 )]
69114 fn _vst3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8);
69115 }
69116 _vst3q_s8(b.0, b.1, b.2, a as _)
69117}
69118#[doc = "Store multiple 3-element structures from three registers"]
69119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
69120#[doc = "## Safety"]
69121#[doc = " * Neon instrinsic unsafe"]
69122#[inline]
69123#[target_feature(enable = "neon")]
69124#[cfg(not(target_arch = "arm"))]
69125#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69126#[cfg_attr(test, assert_instr(st3))]
69127pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
69128 unsafe extern "unadjusted" {
69129 #[cfg_attr(
69130 any(target_arch = "aarch64", target_arch = "arm64ec"),
69131 link_name = "llvm.aarch64.neon.st3.v4i16.p0i8"
69132 )]
69133 fn _vst3_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i8);
69134 }
69135 _vst3_s16(b.0, b.1, b.2, a as _)
69136}
69137#[doc = "Store multiple 3-element structures from three registers"]
69138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
69139#[doc = "## Safety"]
69140#[doc = " * Neon instrinsic unsafe"]
69141#[inline]
69142#[target_feature(enable = "neon")]
69143#[cfg(not(target_arch = "arm"))]
69144#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69145#[cfg_attr(test, assert_instr(st3))]
69146pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
69147 unsafe extern "unadjusted" {
69148 #[cfg_attr(
69149 any(target_arch = "aarch64", target_arch = "arm64ec"),
69150 link_name = "llvm.aarch64.neon.st3.v8i16.p0i8"
69151 )]
69152 fn _vst3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i8);
69153 }
69154 _vst3q_s16(b.0, b.1, b.2, a as _)
69155}
69156#[doc = "Store multiple 3-element structures from three registers"]
69157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
69158#[doc = "## Safety"]
69159#[doc = " * Neon instrinsic unsafe"]
69160#[inline]
69161#[target_feature(enable = "neon")]
69162#[cfg(not(target_arch = "arm"))]
69163#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69164#[cfg_attr(test, assert_instr(st3))]
69165pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
69166 unsafe extern "unadjusted" {
69167 #[cfg_attr(
69168 any(target_arch = "aarch64", target_arch = "arm64ec"),
69169 link_name = "llvm.aarch64.neon.st3.v2i32.p0i8"
69170 )]
69171 fn _vst3_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i8);
69172 }
69173 _vst3_s32(b.0, b.1, b.2, a as _)
69174}
69175#[doc = "Store multiple 3-element structures from three registers"]
69176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
69177#[doc = "## Safety"]
69178#[doc = " * Neon instrinsic unsafe"]
69179#[inline]
69180#[target_feature(enable = "neon")]
69181#[cfg(not(target_arch = "arm"))]
69182#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69183#[cfg_attr(test, assert_instr(st3))]
69184pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
69185 unsafe extern "unadjusted" {
69186 #[cfg_attr(
69187 any(target_arch = "aarch64", target_arch = "arm64ec"),
69188 link_name = "llvm.aarch64.neon.st3.v4i32.p0i8"
69189 )]
69190 fn _vst3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i8);
69191 }
69192 _vst3q_s32(b.0, b.1, b.2, a as _)
69193}
69194#[doc = "Store multiple 3-element structures from three registers"]
69195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
69196#[doc = "## Safety"]
69197#[doc = " * Neon instrinsic unsafe"]
69198#[inline]
69199#[cfg(target_arch = "arm")]
69200#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69201#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69202#[rustc_legacy_const_generics(2)]
69203#[target_feature(enable = "neon,fp16")]
69204#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69205pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
69206 static_assert_uimm_bits!(LANE, 2);
69207 unsafe extern "unadjusted" {
69208 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4f16")]
69209 fn _vst3_lane_f16(
69210 ptr: *mut i8,
69211 a: float16x4_t,
69212 b: float16x4_t,
69213 c: float16x4_t,
69214 n: i32,
69215 size: i32,
69216 );
69217 }
69218 _vst3_lane_f16(a as _, b.0, b.1, b.2, LANE, 4)
69219}
69220#[doc = "Store multiple 3-element structures from three registers"]
69221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
69222#[doc = "## Safety"]
69223#[doc = " * Neon instrinsic unsafe"]
69224#[inline]
69225#[cfg(target_arch = "arm")]
69226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69227#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69228#[rustc_legacy_const_generics(2)]
69229#[target_feature(enable = "neon,fp16")]
69230#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69231pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
69232 static_assert_uimm_bits!(LANE, 3);
69233 unsafe extern "unadjusted" {
69234 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8f16")]
69235 fn _vst3q_lane_f16(
69236 ptr: *mut i8,
69237 a: float16x8_t,
69238 b: float16x8_t,
69239 c: float16x8_t,
69240 n: i32,
69241 size: i32,
69242 );
69243 }
69244 _vst3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 4)
69245}
69246#[doc = "Store multiple 3-element structures from three registers"]
69247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
69248#[doc = "## Safety"]
69249#[doc = " * Neon instrinsic unsafe"]
69250#[inline]
69251#[cfg(not(target_arch = "arm"))]
69252#[rustc_legacy_const_generics(2)]
69253#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69254#[target_feature(enable = "neon,fp16")]
69255#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69256pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
69257 static_assert_uimm_bits!(LANE, 2);
69258 unsafe extern "unadjusted" {
69259 #[cfg_attr(
69260 any(target_arch = "aarch64", target_arch = "arm64ec"),
69261 link_name = "llvm.aarch64.neon.st3lane.v4f16.p0i8"
69262 )]
69263 fn _vst3_lane_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, n: i64, ptr: *mut i8);
69264 }
69265 _vst3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
69266}
69267#[doc = "Store multiple 3-element structures from three registers"]
69268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
69269#[doc = "## Safety"]
69270#[doc = " * Neon instrinsic unsafe"]
69271#[inline]
69272#[cfg(not(target_arch = "arm"))]
69273#[rustc_legacy_const_generics(2)]
69274#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69275#[target_feature(enable = "neon,fp16")]
69276#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69277pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
69278 static_assert_uimm_bits!(LANE, 3);
69279 unsafe extern "unadjusted" {
69280 #[cfg_attr(
69281 any(target_arch = "aarch64", target_arch = "arm64ec"),
69282 link_name = "llvm.aarch64.neon.st3lane.v8f16.p0i8"
69283 )]
69284 fn _vst3q_lane_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, n: i64, ptr: *mut i8);
69285 }
69286 _vst3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
69287}
69288#[doc = "Store multiple 3-element structures from three registers"]
69289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
69290#[doc = "## Safety"]
69291#[doc = " * Neon instrinsic unsafe"]
69292#[inline]
69293#[cfg(target_arch = "arm")]
69294#[target_feature(enable = "neon,v7")]
69295#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69296#[rustc_legacy_const_generics(2)]
69297#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69298pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
69299 static_assert_uimm_bits!(LANE, 1);
69300 unsafe extern "unadjusted" {
69301 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v2f32")]
69302 fn _vst3_lane_f32(
69303 ptr: *mut i8,
69304 a: float32x2_t,
69305 b: float32x2_t,
69306 c: float32x2_t,
69307 n: i32,
69308 size: i32,
69309 );
69310 }
69311 _vst3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
69312}
69313#[doc = "Store multiple 3-element structures from three registers"]
69314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
69315#[doc = "## Safety"]
69316#[doc = " * Neon instrinsic unsafe"]
69317#[inline]
69318#[cfg(target_arch = "arm")]
69319#[target_feature(enable = "neon,v7")]
69320#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69321#[rustc_legacy_const_generics(2)]
69322#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69323pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
69324 static_assert_uimm_bits!(LANE, 2);
69325 unsafe extern "unadjusted" {
69326 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4f32")]
69327 fn _vst3q_lane_f32(
69328 ptr: *mut i8,
69329 a: float32x4_t,
69330 b: float32x4_t,
69331 c: float32x4_t,
69332 n: i32,
69333 size: i32,
69334 );
69335 }
69336 _vst3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
69337}
69338#[doc = "Store multiple 3-element structures from three registers"]
69339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
69340#[doc = "## Safety"]
69341#[doc = " * Neon instrinsic unsafe"]
69342#[inline]
69343#[cfg(target_arch = "arm")]
69344#[target_feature(enable = "neon,v7")]
69345#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69346#[rustc_legacy_const_generics(2)]
69347#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69348pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
69349 static_assert_uimm_bits!(LANE, 3);
69350 unsafe extern "unadjusted" {
69351 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i8")]
69352 fn _vst3_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i32, size: i32);
69353 }
69354 _vst3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1)
69355}
69356#[doc = "Store multiple 3-element structures from three registers"]
69357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
69358#[doc = "## Safety"]
69359#[doc = " * Neon instrinsic unsafe"]
69360#[inline]
69361#[cfg(target_arch = "arm")]
69362#[target_feature(enable = "neon,v7")]
69363#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69364#[rustc_legacy_const_generics(2)]
69365#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69366pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
69367 static_assert_uimm_bits!(LANE, 2);
69368 unsafe extern "unadjusted" {
69369 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4i16")]
69370 fn _vst3_lane_s16(
69371 ptr: *mut i8,
69372 a: int16x4_t,
69373 b: int16x4_t,
69374 c: int16x4_t,
69375 n: i32,
69376 size: i32,
69377 );
69378 }
69379 _vst3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
69380}
69381#[doc = "Store multiple 3-element structures from three registers"]
69382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
69383#[doc = "## Safety"]
69384#[doc = " * Neon instrinsic unsafe"]
69385#[inline]
69386#[cfg(target_arch = "arm")]
69387#[target_feature(enable = "neon,v7")]
69388#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69389#[rustc_legacy_const_generics(2)]
69390#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69391pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
69392 static_assert_uimm_bits!(LANE, 3);
69393 unsafe extern "unadjusted" {
69394 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i16")]
69395 fn _vst3q_lane_s16(
69396 ptr: *mut i8,
69397 a: int16x8_t,
69398 b: int16x8_t,
69399 c: int16x8_t,
69400 n: i32,
69401 size: i32,
69402 );
69403 }
69404 _vst3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
69405}
69406#[doc = "Store multiple 3-element structures from three registers"]
69407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
69408#[doc = "## Safety"]
69409#[doc = " * Neon instrinsic unsafe"]
69410#[inline]
69411#[cfg(target_arch = "arm")]
69412#[target_feature(enable = "neon,v7")]
69413#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69414#[rustc_legacy_const_generics(2)]
69415#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69416pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
69417 static_assert_uimm_bits!(LANE, 1);
69418 unsafe extern "unadjusted" {
69419 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v2i32")]
69420 fn _vst3_lane_s32(
69421 ptr: *mut i8,
69422 a: int32x2_t,
69423 b: int32x2_t,
69424 c: int32x2_t,
69425 n: i32,
69426 size: i32,
69427 );
69428 }
69429 _vst3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
69430}
69431#[doc = "Store multiple 3-element structures from three registers"]
69432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
69433#[doc = "## Safety"]
69434#[doc = " * Neon instrinsic unsafe"]
69435#[inline]
69436#[cfg(target_arch = "arm")]
69437#[target_feature(enable = "neon,v7")]
69438#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69439#[rustc_legacy_const_generics(2)]
69440#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69441pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
69442 static_assert_uimm_bits!(LANE, 2);
69443 unsafe extern "unadjusted" {
69444 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4i32")]
69445 fn _vst3q_lane_s32(
69446 ptr: *mut i8,
69447 a: int32x4_t,
69448 b: int32x4_t,
69449 c: int32x4_t,
69450 n: i32,
69451 size: i32,
69452 );
69453 }
69454 _vst3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
69455}
69456#[doc = "Store multiple 3-element structures from three registers"]
69457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
69458#[doc = "## Safety"]
69459#[doc = " * Neon instrinsic unsafe"]
69460#[inline]
69461#[target_feature(enable = "neon")]
69462#[cfg(not(target_arch = "arm"))]
69463#[rustc_legacy_const_generics(2)]
69464#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69465#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69466pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
69467 static_assert_uimm_bits!(LANE, 1);
69468 unsafe extern "unadjusted" {
69469 #[cfg_attr(
69470 any(target_arch = "aarch64", target_arch = "arm64ec"),
69471 link_name = "llvm.aarch64.neon.st3lane.v2f32.p0i8"
69472 )]
69473 fn _vst3_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, n: i64, ptr: *mut i8);
69474 }
69475 _vst3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
69476}
69477#[doc = "Store multiple 3-element structures from three registers"]
69478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
69479#[doc = "## Safety"]
69480#[doc = " * Neon instrinsic unsafe"]
69481#[inline]
69482#[target_feature(enable = "neon")]
69483#[cfg(not(target_arch = "arm"))]
69484#[rustc_legacy_const_generics(2)]
69485#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69486#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69487pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
69488 static_assert_uimm_bits!(LANE, 2);
69489 unsafe extern "unadjusted" {
69490 #[cfg_attr(
69491 any(target_arch = "aarch64", target_arch = "arm64ec"),
69492 link_name = "llvm.aarch64.neon.st3lane.v4f32.p0i8"
69493 )]
69494 fn _vst3q_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, n: i64, ptr: *mut i8);
69495 }
69496 _vst3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
69497}
69498#[doc = "Store multiple 3-element structures from three registers"]
69499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
69500#[doc = "## Safety"]
69501#[doc = " * Neon instrinsic unsafe"]
69502#[inline]
69503#[target_feature(enable = "neon")]
69504#[cfg(not(target_arch = "arm"))]
69505#[rustc_legacy_const_generics(2)]
69506#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69507#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69508pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
69509 static_assert_uimm_bits!(LANE, 3);
69510 unsafe extern "unadjusted" {
69511 #[cfg_attr(
69512 any(target_arch = "aarch64", target_arch = "arm64ec"),
69513 link_name = "llvm.aarch64.neon.st3lane.v8i8.p0i8"
69514 )]
69515 fn _vst3_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i64, ptr: *mut i8);
69516 }
69517 _vst3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
69518}
69519#[doc = "Store multiple 3-element structures from three registers"]
69520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
69521#[doc = "## Safety"]
69522#[doc = " * Neon instrinsic unsafe"]
69523#[inline]
69524#[target_feature(enable = "neon")]
69525#[cfg(not(target_arch = "arm"))]
69526#[rustc_legacy_const_generics(2)]
69527#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69528#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69529pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
69530 static_assert_uimm_bits!(LANE, 2);
69531 unsafe extern "unadjusted" {
69532 #[cfg_attr(
69533 any(target_arch = "aarch64", target_arch = "arm64ec"),
69534 link_name = "llvm.aarch64.neon.st3lane.v4i16.p0i8"
69535 )]
69536 fn _vst3_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, n: i64, ptr: *mut i8);
69537 }
69538 _vst3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
69539}
69540#[doc = "Store multiple 3-element structures from three registers"]
69541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
69542#[doc = "## Safety"]
69543#[doc = " * Neon instrinsic unsafe"]
69544#[inline]
69545#[target_feature(enable = "neon")]
69546#[cfg(not(target_arch = "arm"))]
69547#[rustc_legacy_const_generics(2)]
69548#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69549#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69550pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
69551 static_assert_uimm_bits!(LANE, 3);
69552 unsafe extern "unadjusted" {
69553 #[cfg_attr(
69554 any(target_arch = "aarch64", target_arch = "arm64ec"),
69555 link_name = "llvm.aarch64.neon.st3lane.v8i16.p0i8"
69556 )]
69557 fn _vst3q_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, n: i64, ptr: *mut i8);
69558 }
69559 _vst3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
69560}
69561#[doc = "Store multiple 3-element structures from three registers"]
69562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
69563#[doc = "## Safety"]
69564#[doc = " * Neon instrinsic unsafe"]
69565#[inline]
69566#[target_feature(enable = "neon")]
69567#[cfg(not(target_arch = "arm"))]
69568#[rustc_legacy_const_generics(2)]
69569#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69570#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69571pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
69572 static_assert_uimm_bits!(LANE, 1);
69573 unsafe extern "unadjusted" {
69574 #[cfg_attr(
69575 any(target_arch = "aarch64", target_arch = "arm64ec"),
69576 link_name = "llvm.aarch64.neon.st3lane.v2i32.p0i8"
69577 )]
69578 fn _vst3_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, n: i64, ptr: *mut i8);
69579 }
69580 _vst3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
69581}
69582#[doc = "Store multiple 3-element structures from three registers"]
69583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
69584#[doc = "## Safety"]
69585#[doc = " * Neon instrinsic unsafe"]
69586#[inline]
69587#[target_feature(enable = "neon")]
69588#[cfg(not(target_arch = "arm"))]
69589#[rustc_legacy_const_generics(2)]
69590#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69591#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69592pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
69593 static_assert_uimm_bits!(LANE, 2);
69594 unsafe extern "unadjusted" {
69595 #[cfg_attr(
69596 any(target_arch = "aarch64", target_arch = "arm64ec"),
69597 link_name = "llvm.aarch64.neon.st3lane.v4i32.p0i8"
69598 )]
69599 fn _vst3q_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, n: i64, ptr: *mut i8);
69600 }
69601 _vst3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
69602}
69603#[doc = "Store multiple 3-element structures from three registers"]
69604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"]
69605#[doc = "## Safety"]
69606#[doc = " * Neon instrinsic unsafe"]
69607#[inline]
69608#[target_feature(enable = "neon")]
69609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69611#[cfg_attr(
69612 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69613 assert_instr(st3, LANE = 0)
69614)]
69615#[rustc_legacy_const_generics(2)]
69616#[cfg_attr(
69617 not(target_arch = "arm"),
69618 stable(feature = "neon_intrinsics", since = "1.59.0")
69619)]
69620#[cfg_attr(
69621 target_arch = "arm",
69622 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69623)]
69624pub unsafe fn vst3_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x3_t) {
69625 static_assert_uimm_bits!(LANE, 3);
69626 vst3_lane_s8::<LANE>(transmute(a), transmute(b))
69627}
69628#[doc = "Store multiple 3-element structures from three registers"]
69629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"]
69630#[doc = "## Safety"]
69631#[doc = " * Neon instrinsic unsafe"]
69632#[inline]
69633#[target_feature(enable = "neon")]
69634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69636#[cfg_attr(
69637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69638 assert_instr(st3, LANE = 0)
69639)]
69640#[rustc_legacy_const_generics(2)]
69641#[cfg_attr(
69642 not(target_arch = "arm"),
69643 stable(feature = "neon_intrinsics", since = "1.59.0")
69644)]
69645#[cfg_attr(
69646 target_arch = "arm",
69647 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69648)]
69649pub unsafe fn vst3_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x3_t) {
69650 static_assert_uimm_bits!(LANE, 2);
69651 vst3_lane_s16::<LANE>(transmute(a), transmute(b))
69652}
69653#[doc = "Store multiple 3-element structures from three registers"]
69654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"]
69655#[doc = "## Safety"]
69656#[doc = " * Neon instrinsic unsafe"]
69657#[inline]
69658#[target_feature(enable = "neon")]
69659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69660#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69661#[cfg_attr(
69662 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69663 assert_instr(st3, LANE = 0)
69664)]
69665#[rustc_legacy_const_generics(2)]
69666#[cfg_attr(
69667 not(target_arch = "arm"),
69668 stable(feature = "neon_intrinsics", since = "1.59.0")
69669)]
69670#[cfg_attr(
69671 target_arch = "arm",
69672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69673)]
69674pub unsafe fn vst3q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x3_t) {
69675 static_assert_uimm_bits!(LANE, 3);
69676 vst3q_lane_s16::<LANE>(transmute(a), transmute(b))
69677}
69678#[doc = "Store multiple 3-element structures from three registers"]
69679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"]
69680#[doc = "## Safety"]
69681#[doc = " * Neon instrinsic unsafe"]
69682#[inline]
69683#[target_feature(enable = "neon")]
69684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69685#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69686#[cfg_attr(
69687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69688 assert_instr(st3, LANE = 0)
69689)]
69690#[rustc_legacy_const_generics(2)]
69691#[cfg_attr(
69692 not(target_arch = "arm"),
69693 stable(feature = "neon_intrinsics", since = "1.59.0")
69694)]
69695#[cfg_attr(
69696 target_arch = "arm",
69697 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69698)]
69699pub unsafe fn vst3_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x3_t) {
69700 static_assert_uimm_bits!(LANE, 1);
69701 vst3_lane_s32::<LANE>(transmute(a), transmute(b))
69702}
69703#[doc = "Store multiple 3-element structures from three registers"]
69704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"]
69705#[doc = "## Safety"]
69706#[doc = " * Neon instrinsic unsafe"]
69707#[inline]
69708#[target_feature(enable = "neon")]
69709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69711#[cfg_attr(
69712 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69713 assert_instr(st3, LANE = 0)
69714)]
69715#[rustc_legacy_const_generics(2)]
69716#[cfg_attr(
69717 not(target_arch = "arm"),
69718 stable(feature = "neon_intrinsics", since = "1.59.0")
69719)]
69720#[cfg_attr(
69721 target_arch = "arm",
69722 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69723)]
69724pub unsafe fn vst3q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x3_t) {
69725 static_assert_uimm_bits!(LANE, 2);
69726 vst3q_lane_s32::<LANE>(transmute(a), transmute(b))
69727}
69728#[doc = "Store multiple 3-element structures from three registers"]
69729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"]
69730#[doc = "## Safety"]
69731#[doc = " * Neon instrinsic unsafe"]
69732#[inline]
69733#[target_feature(enable = "neon")]
69734#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69735#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69736#[cfg_attr(
69737 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69738 assert_instr(st3, LANE = 0)
69739)]
69740#[rustc_legacy_const_generics(2)]
69741#[cfg_attr(
69742 not(target_arch = "arm"),
69743 stable(feature = "neon_intrinsics", since = "1.59.0")
69744)]
69745#[cfg_attr(
69746 target_arch = "arm",
69747 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69748)]
69749pub unsafe fn vst3_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x3_t) {
69750 static_assert_uimm_bits!(LANE, 3);
69751 vst3_lane_s8::<LANE>(transmute(a), transmute(b))
69752}
69753#[doc = "Store multiple 3-element structures from three registers"]
69754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"]
69755#[doc = "## Safety"]
69756#[doc = " * Neon instrinsic unsafe"]
69757#[inline]
69758#[target_feature(enable = "neon")]
69759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69761#[cfg_attr(
69762 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69763 assert_instr(st3, LANE = 0)
69764)]
69765#[rustc_legacy_const_generics(2)]
69766#[cfg_attr(
69767 not(target_arch = "arm"),
69768 stable(feature = "neon_intrinsics", since = "1.59.0")
69769)]
69770#[cfg_attr(
69771 target_arch = "arm",
69772 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69773)]
69774pub unsafe fn vst3_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x3_t) {
69775 static_assert_uimm_bits!(LANE, 2);
69776 vst3_lane_s16::<LANE>(transmute(a), transmute(b))
69777}
69778#[doc = "Store multiple 3-element structures from three registers"]
69779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"]
69780#[doc = "## Safety"]
69781#[doc = " * Neon instrinsic unsafe"]
69782#[inline]
69783#[target_feature(enable = "neon")]
69784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69785#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69786#[cfg_attr(
69787 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69788 assert_instr(st3, LANE = 0)
69789)]
69790#[rustc_legacy_const_generics(2)]
69791#[cfg_attr(
69792 not(target_arch = "arm"),
69793 stable(feature = "neon_intrinsics", since = "1.59.0")
69794)]
69795#[cfg_attr(
69796 target_arch = "arm",
69797 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69798)]
69799pub unsafe fn vst3q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x3_t) {
69800 static_assert_uimm_bits!(LANE, 3);
69801 vst3q_lane_s16::<LANE>(transmute(a), transmute(b))
69802}
69803#[doc = "Store multiple 3-element structures from three registers"]
69804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"]
69805#[doc = "## Safety"]
69806#[doc = " * Neon instrinsic unsafe"]
69807#[inline]
69808#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
69809#[target_feature(enable = "neon,aes")]
69810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
69811#[cfg_attr(
69812 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69813 assert_instr(nop)
69814)]
69815#[cfg_attr(
69816 not(target_arch = "arm"),
69817 stable(feature = "neon_intrinsics", since = "1.59.0")
69818)]
69819#[cfg_attr(
69820 target_arch = "arm",
69821 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69822)]
69823pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) {
69824 vst3_s64(transmute(a), transmute(b))
69825}
69826#[doc = "Store multiple 3-element structures from three registers"]
69827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
69828#[doc = "## Safety"]
69829#[doc = " * Neon instrinsic unsafe"]
69830#[inline]
69831#[target_feature(enable = "neon")]
69832#[cfg(not(target_arch = "arm"))]
69833#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69834#[cfg_attr(test, assert_instr(nop))]
69835pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
69836 unsafe extern "unadjusted" {
69837 #[cfg_attr(
69838 any(target_arch = "aarch64", target_arch = "arm64ec"),
69839 link_name = "llvm.aarch64.neon.st3.v1i64.p0i8"
69840 )]
69841 fn _vst3_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i8);
69842 }
69843 _vst3_s64(b.0, b.1, b.2, a as _)
69844}
69845#[doc = "Store multiple 3-element structures from three registers"]
69846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
69847#[doc = "## Safety"]
69848#[doc = " * Neon instrinsic unsafe"]
69849#[inline]
69850#[cfg(target_arch = "arm")]
69851#[target_feature(enable = "neon,v7")]
69852#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69853#[cfg_attr(test, assert_instr(nop))]
69854pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
69855 unsafe extern "unadjusted" {
69856 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v1i64")]
69857 fn _vst3_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, c: int64x1_t, size: i32);
69858 }
69859 _vst3_s64(a as _, b.0, b.1, b.2, 8)
69860}
69861#[doc = "Store multiple 3-element structures from three registers"]
69862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"]
69863#[doc = "## Safety"]
69864#[doc = " * Neon instrinsic unsafe"]
69865#[inline]
69866#[target_feature(enable = "neon")]
69867#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69868#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
69869#[cfg_attr(
69870 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69871 assert_instr(nop)
69872)]
69873#[cfg_attr(
69874 not(target_arch = "arm"),
69875 stable(feature = "neon_intrinsics", since = "1.59.0")
69876)]
69877#[cfg_attr(
69878 target_arch = "arm",
69879 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69880)]
69881pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) {
69882 vst3_s64(transmute(a), transmute(b))
69883}
69884#[doc = "Store multiple 3-element structures from three registers"]
69885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"]
69886#[doc = "## Safety"]
69887#[doc = " * Neon instrinsic unsafe"]
69888#[inline]
69889#[target_feature(enable = "neon")]
69890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69892#[cfg_attr(
69893 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69894 assert_instr(st3)
69895)]
69896#[cfg_attr(
69897 not(target_arch = "arm"),
69898 stable(feature = "neon_intrinsics", since = "1.59.0")
69899)]
69900#[cfg_attr(
69901 target_arch = "arm",
69902 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69903)]
69904pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) {
69905 vst3_s8(transmute(a), transmute(b))
69906}
69907#[doc = "Store multiple 3-element structures from three registers"]
69908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"]
69909#[doc = "## Safety"]
69910#[doc = " * Neon instrinsic unsafe"]
69911#[inline]
69912#[target_feature(enable = "neon")]
69913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69914#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69915#[cfg_attr(
69916 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69917 assert_instr(st3)
69918)]
69919#[cfg_attr(
69920 not(target_arch = "arm"),
69921 stable(feature = "neon_intrinsics", since = "1.59.0")
69922)]
69923#[cfg_attr(
69924 target_arch = "arm",
69925 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69926)]
69927pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) {
69928 vst3q_s8(transmute(a), transmute(b))
69929}
69930#[doc = "Store multiple 3-element structures from three registers"]
69931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"]
69932#[doc = "## Safety"]
69933#[doc = " * Neon instrinsic unsafe"]
69934#[inline]
69935#[target_feature(enable = "neon")]
69936#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69938#[cfg_attr(
69939 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69940 assert_instr(st3)
69941)]
69942#[cfg_attr(
69943 not(target_arch = "arm"),
69944 stable(feature = "neon_intrinsics", since = "1.59.0")
69945)]
69946#[cfg_attr(
69947 target_arch = "arm",
69948 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69949)]
69950pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) {
69951 vst3_s16(transmute(a), transmute(b))
69952}
69953#[doc = "Store multiple 3-element structures from three registers"]
69954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"]
69955#[doc = "## Safety"]
69956#[doc = " * Neon instrinsic unsafe"]
69957#[inline]
69958#[target_feature(enable = "neon")]
69959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69960#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69961#[cfg_attr(
69962 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69963 assert_instr(st3)
69964)]
69965#[cfg_attr(
69966 not(target_arch = "arm"),
69967 stable(feature = "neon_intrinsics", since = "1.59.0")
69968)]
69969#[cfg_attr(
69970 target_arch = "arm",
69971 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69972)]
69973pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) {
69974 vst3q_s16(transmute(a), transmute(b))
69975}
69976#[doc = "Store multiple 3-element structures from three registers"]
69977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"]
69978#[doc = "## Safety"]
69979#[doc = " * Neon instrinsic unsafe"]
69980#[inline]
69981#[target_feature(enable = "neon")]
69982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69983#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69984#[cfg_attr(
69985 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69986 assert_instr(st3)
69987)]
69988#[cfg_attr(
69989 not(target_arch = "arm"),
69990 stable(feature = "neon_intrinsics", since = "1.59.0")
69991)]
69992#[cfg_attr(
69993 target_arch = "arm",
69994 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69995)]
69996pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) {
69997 vst3_s32(transmute(a), transmute(b))
69998}
69999#[doc = "Store multiple 3-element structures from three registers"]
70000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"]
70001#[doc = "## Safety"]
70002#[doc = " * Neon instrinsic unsafe"]
70003#[inline]
70004#[target_feature(enable = "neon")]
70005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70007#[cfg_attr(
70008 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70009 assert_instr(st3)
70010)]
70011#[cfg_attr(
70012 not(target_arch = "arm"),
70013 stable(feature = "neon_intrinsics", since = "1.59.0")
70014)]
70015#[cfg_attr(
70016 target_arch = "arm",
70017 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70018)]
70019pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) {
70020 vst3q_s32(transmute(a), transmute(b))
70021}
70022#[doc = "Store multiple 3-element structures from three registers"]
70023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"]
70024#[doc = "## Safety"]
70025#[doc = " * Neon instrinsic unsafe"]
70026#[inline]
70027#[target_feature(enable = "neon")]
70028#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70029#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70030#[cfg_attr(
70031 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70032 assert_instr(st3)
70033)]
70034#[cfg_attr(
70035 not(target_arch = "arm"),
70036 stable(feature = "neon_intrinsics", since = "1.59.0")
70037)]
70038#[cfg_attr(
70039 target_arch = "arm",
70040 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70041)]
70042pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) {
70043 vst3_s8(transmute(a), transmute(b))
70044}
70045#[doc = "Store multiple 3-element structures from three registers"]
70046#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"]
70047#[doc = "## Safety"]
70048#[doc = " * Neon instrinsic unsafe"]
70049#[inline]
70050#[target_feature(enable = "neon")]
70051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70053#[cfg_attr(
70054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70055 assert_instr(st3)
70056)]
70057#[cfg_attr(
70058 not(target_arch = "arm"),
70059 stable(feature = "neon_intrinsics", since = "1.59.0")
70060)]
70061#[cfg_attr(
70062 target_arch = "arm",
70063 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70064)]
70065pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) {
70066 vst3q_s8(transmute(a), transmute(b))
70067}
70068#[doc = "Store multiple 3-element structures from three registers"]
70069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"]
70070#[doc = "## Safety"]
70071#[doc = " * Neon instrinsic unsafe"]
70072#[inline]
70073#[target_feature(enable = "neon")]
70074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70076#[cfg_attr(
70077 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70078 assert_instr(st3)
70079)]
70080#[cfg_attr(
70081 not(target_arch = "arm"),
70082 stable(feature = "neon_intrinsics", since = "1.59.0")
70083)]
70084#[cfg_attr(
70085 target_arch = "arm",
70086 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70087)]
70088pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) {
70089 vst3_s16(transmute(a), transmute(b))
70090}
70091#[doc = "Store multiple 3-element structures from three registers"]
70092#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"]
70093#[doc = "## Safety"]
70094#[doc = " * Neon instrinsic unsafe"]
70095#[inline]
70096#[target_feature(enable = "neon")]
70097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
70099#[cfg_attr(
70100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70101 assert_instr(st3)
70102)]
70103#[cfg_attr(
70104 not(target_arch = "arm"),
70105 stable(feature = "neon_intrinsics", since = "1.59.0")
70106)]
70107#[cfg_attr(
70108 target_arch = "arm",
70109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70110)]
70111pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) {
70112 vst3q_s16(transmute(a), transmute(b))
70113}
70114#[doc = "Store multiple 4-element structures from four registers"]
70115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
70116#[doc = "## Safety"]
70117#[doc = " * Neon instrinsic unsafe"]
70118#[inline]
70119#[cfg(target_arch = "arm")]
70120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70121#[target_feature(enable = "neon,fp16")]
70122#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70123#[cfg_attr(test, assert_instr(vst4))]
70124pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
70125 unsafe extern "unadjusted" {
70126 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4f16")]
70127 fn _vst4_f16(
70128 ptr: *mut i8,
70129 a: float16x4_t,
70130 b: float16x4_t,
70131 c: float16x4_t,
70132 d: float16x4_t,
70133 size: i32,
70134 );
70135 }
70136 _vst4_f16(a as _, b.0, b.1, b.2, b.3, 2)
70137}
70138#[doc = "Store multiple 4-element structures from four registers"]
70139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
70140#[doc = "## Safety"]
70141#[doc = " * Neon instrinsic unsafe"]
70142#[inline]
70143#[cfg(target_arch = "arm")]
70144#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70145#[target_feature(enable = "neon,fp16")]
70146#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70147#[cfg_attr(test, assert_instr(vst4))]
70148pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
70149 unsafe extern "unadjusted" {
70150 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8f16")]
70151 fn _vst4q_f16(
70152 ptr: *mut i8,
70153 a: float16x8_t,
70154 b: float16x8_t,
70155 c: float16x8_t,
70156 d: float16x8_t,
70157 size: i32,
70158 );
70159 }
70160 _vst4q_f16(a as _, b.0, b.1, b.2, b.3, 2)
70161}
70162#[doc = "Store multiple 4-element structures from four registers"]
70163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
70164#[doc = "## Safety"]
70165#[doc = " * Neon instrinsic unsafe"]
70166#[inline]
70167#[cfg(not(target_arch = "arm"))]
70168#[target_feature(enable = "neon,fp16")]
70169#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70170#[cfg_attr(test, assert_instr(st4))]
70171pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
70172 unsafe extern "unadjusted" {
70173 #[cfg_attr(
70174 any(target_arch = "aarch64", target_arch = "arm64ec"),
70175 link_name = "llvm.aarch64.neon.st4.v4f16.p0i8"
70176 )]
70177 fn _vst4_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, d: float16x4_t, ptr: *mut i8);
70178 }
70179 _vst4_f16(b.0, b.1, b.2, b.3, a as _)
70180}
70181#[doc = "Store multiple 4-element structures from four registers"]
70182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
70183#[doc = "## Safety"]
70184#[doc = " * Neon instrinsic unsafe"]
70185#[inline]
70186#[cfg(not(target_arch = "arm"))]
70187#[target_feature(enable = "neon,fp16")]
70188#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70189#[cfg_attr(test, assert_instr(st4))]
70190pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
70191 unsafe extern "unadjusted" {
70192 #[cfg_attr(
70193 any(target_arch = "aarch64", target_arch = "arm64ec"),
70194 link_name = "llvm.aarch64.neon.st4.v8f16.p0i8"
70195 )]
70196 fn _vst4q_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, d: float16x8_t, ptr: *mut i8);
70197 }
70198 _vst4q_f16(b.0, b.1, b.2, b.3, a as _)
70199}
70200#[doc = "Store multiple 4-element structures from four registers"]
70201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
70202#[doc = "## Safety"]
70203#[doc = " * Neon instrinsic unsafe"]
70204#[inline]
70205#[cfg(target_arch = "arm")]
70206#[target_feature(enable = "neon,v7")]
70207#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70208#[cfg_attr(test, assert_instr(vst4))]
70209pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
70210 unsafe extern "unadjusted" {
70211 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v2f32")]
70212 fn _vst4_f32(
70213 ptr: *mut i8,
70214 a: float32x2_t,
70215 b: float32x2_t,
70216 c: float32x2_t,
70217 d: float32x2_t,
70218 size: i32,
70219 );
70220 }
70221 _vst4_f32(a as _, b.0, b.1, b.2, b.3, 4)
70222}
70223#[doc = "Store multiple 4-element structures from four registers"]
70224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
70225#[doc = "## Safety"]
70226#[doc = " * Neon instrinsic unsafe"]
70227#[inline]
70228#[cfg(target_arch = "arm")]
70229#[target_feature(enable = "neon,v7")]
70230#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70231#[cfg_attr(test, assert_instr(vst4))]
70232pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
70233 unsafe extern "unadjusted" {
70234 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4f32")]
70235 fn _vst4q_f32(
70236 ptr: *mut i8,
70237 a: float32x4_t,
70238 b: float32x4_t,
70239 c: float32x4_t,
70240 d: float32x4_t,
70241 size: i32,
70242 );
70243 }
70244 _vst4q_f32(a as _, b.0, b.1, b.2, b.3, 4)
70245}
70246#[doc = "Store multiple 4-element structures from four registers"]
70247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
70248#[doc = "## Safety"]
70249#[doc = " * Neon instrinsic unsafe"]
70250#[inline]
70251#[cfg(target_arch = "arm")]
70252#[target_feature(enable = "neon,v7")]
70253#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70254#[cfg_attr(test, assert_instr(vst4))]
70255pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
70256 unsafe extern "unadjusted" {
70257 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8i8")]
70258 fn _vst4_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, size: i32);
70259 }
70260 _vst4_s8(a as _, b.0, b.1, b.2, b.3, 1)
70261}
70262#[doc = "Store multiple 4-element structures from four registers"]
70263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
70264#[doc = "## Safety"]
70265#[doc = " * Neon instrinsic unsafe"]
70266#[inline]
70267#[cfg(target_arch = "arm")]
70268#[target_feature(enable = "neon,v7")]
70269#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70270#[cfg_attr(test, assert_instr(vst4))]
70271pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
70272 unsafe extern "unadjusted" {
70273 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v16i8")]
70274 fn _vst4q_s8(
70275 ptr: *mut i8,
70276 a: int8x16_t,
70277 b: int8x16_t,
70278 c: int8x16_t,
70279 d: int8x16_t,
70280 size: i32,
70281 );
70282 }
70283 _vst4q_s8(a as _, b.0, b.1, b.2, b.3, 1)
70284}
70285#[doc = "Store multiple 4-element structures from four registers"]
70286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
70287#[doc = "## Safety"]
70288#[doc = " * Neon instrinsic unsafe"]
70289#[inline]
70290#[cfg(target_arch = "arm")]
70291#[target_feature(enable = "neon,v7")]
70292#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70293#[cfg_attr(test, assert_instr(vst4))]
70294pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
70295 unsafe extern "unadjusted" {
70296 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4i16")]
70297 fn _vst4_s16(
70298 ptr: *mut i8,
70299 a: int16x4_t,
70300 b: int16x4_t,
70301 c: int16x4_t,
70302 d: int16x4_t,
70303 size: i32,
70304 );
70305 }
70306 _vst4_s16(a as _, b.0, b.1, b.2, b.3, 2)
70307}
70308#[doc = "Store multiple 4-element structures from four registers"]
70309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
70310#[doc = "## Safety"]
70311#[doc = " * Neon instrinsic unsafe"]
70312#[inline]
70313#[cfg(target_arch = "arm")]
70314#[target_feature(enable = "neon,v7")]
70315#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70316#[cfg_attr(test, assert_instr(vst4))]
70317pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
70318 unsafe extern "unadjusted" {
70319 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8i16")]
70320 fn _vst4q_s16(
70321 ptr: *mut i8,
70322 a: int16x8_t,
70323 b: int16x8_t,
70324 c: int16x8_t,
70325 d: int16x8_t,
70326 size: i32,
70327 );
70328 }
70329 _vst4q_s16(a as _, b.0, b.1, b.2, b.3, 2)
70330}
70331#[doc = "Store multiple 4-element structures from four registers"]
70332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
70333#[doc = "## Safety"]
70334#[doc = " * Neon instrinsic unsafe"]
70335#[inline]
70336#[cfg(target_arch = "arm")]
70337#[target_feature(enable = "neon,v7")]
70338#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70339#[cfg_attr(test, assert_instr(vst4))]
70340pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
70341 unsafe extern "unadjusted" {
70342 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v2i32")]
70343 fn _vst4_s32(
70344 ptr: *mut i8,
70345 a: int32x2_t,
70346 b: int32x2_t,
70347 c: int32x2_t,
70348 d: int32x2_t,
70349 size: i32,
70350 );
70351 }
70352 _vst4_s32(a as _, b.0, b.1, b.2, b.3, 4)
70353}
70354#[doc = "Store multiple 4-element structures from four registers"]
70355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
70356#[doc = "## Safety"]
70357#[doc = " * Neon instrinsic unsafe"]
70358#[inline]
70359#[cfg(target_arch = "arm")]
70360#[target_feature(enable = "neon,v7")]
70361#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70362#[cfg_attr(test, assert_instr(vst4))]
70363pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
70364 unsafe extern "unadjusted" {
70365 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4i32")]
70366 fn _vst4q_s32(
70367 ptr: *mut i8,
70368 a: int32x4_t,
70369 b: int32x4_t,
70370 c: int32x4_t,
70371 d: int32x4_t,
70372 size: i32,
70373 );
70374 }
70375 _vst4q_s32(a as _, b.0, b.1, b.2, b.3, 4)
70376}
70377#[doc = "Store multiple 4-element structures from four registers"]
70378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
70379#[doc = "## Safety"]
70380#[doc = " * Neon instrinsic unsafe"]
70381#[inline]
70382#[target_feature(enable = "neon")]
70383#[cfg(not(target_arch = "arm"))]
70384#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70385#[cfg_attr(test, assert_instr(st4))]
70386pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
70387 unsafe extern "unadjusted" {
70388 #[cfg_attr(
70389 any(target_arch = "aarch64", target_arch = "arm64ec"),
70390 link_name = "llvm.aarch64.neon.st4.v2f32.p0i8"
70391 )]
70392 fn _vst4_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, ptr: *mut i8);
70393 }
70394 _vst4_f32(b.0, b.1, b.2, b.3, a as _)
70395}
70396#[doc = "Store multiple 4-element structures from four registers"]
70397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
70398#[doc = "## Safety"]
70399#[doc = " * Neon instrinsic unsafe"]
70400#[inline]
70401#[target_feature(enable = "neon")]
70402#[cfg(not(target_arch = "arm"))]
70403#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70404#[cfg_attr(test, assert_instr(st4))]
70405pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
70406 unsafe extern "unadjusted" {
70407 #[cfg_attr(
70408 any(target_arch = "aarch64", target_arch = "arm64ec"),
70409 link_name = "llvm.aarch64.neon.st4.v4f32.p0i8"
70410 )]
70411 fn _vst4q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, ptr: *mut i8);
70412 }
70413 _vst4q_f32(b.0, b.1, b.2, b.3, a as _)
70414}
70415#[doc = "Store multiple 4-element structures from four registers"]
70416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
70417#[doc = "## Safety"]
70418#[doc = " * Neon instrinsic unsafe"]
70419#[inline]
70420#[target_feature(enable = "neon")]
70421#[cfg(not(target_arch = "arm"))]
70422#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70423#[cfg_attr(test, assert_instr(st4))]
70424pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
70425 unsafe extern "unadjusted" {
70426 #[cfg_attr(
70427 any(target_arch = "aarch64", target_arch = "arm64ec"),
70428 link_name = "llvm.aarch64.neon.st4.v8i8.p0i8"
70429 )]
70430 fn _vst4_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8);
70431 }
70432 _vst4_s8(b.0, b.1, b.2, b.3, a as _)
70433}
70434#[doc = "Store multiple 4-element structures from four registers"]
70435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
70436#[doc = "## Safety"]
70437#[doc = " * Neon instrinsic unsafe"]
70438#[inline]
70439#[target_feature(enable = "neon")]
70440#[cfg(not(target_arch = "arm"))]
70441#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70442#[cfg_attr(test, assert_instr(st4))]
70443pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
70444 unsafe extern "unadjusted" {
70445 #[cfg_attr(
70446 any(target_arch = "aarch64", target_arch = "arm64ec"),
70447 link_name = "llvm.aarch64.neon.st4.v16i8.p0i8"
70448 )]
70449 fn _vst4q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8);
70450 }
70451 _vst4q_s8(b.0, b.1, b.2, b.3, a as _)
70452}
70453#[doc = "Store multiple 4-element structures from four registers"]
70454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
70455#[doc = "## Safety"]
70456#[doc = " * Neon instrinsic unsafe"]
70457#[inline]
70458#[target_feature(enable = "neon")]
70459#[cfg(not(target_arch = "arm"))]
70460#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70461#[cfg_attr(test, assert_instr(st4))]
70462pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
70463 unsafe extern "unadjusted" {
70464 #[cfg_attr(
70465 any(target_arch = "aarch64", target_arch = "arm64ec"),
70466 link_name = "llvm.aarch64.neon.st4.v4i16.p0i8"
70467 )]
70468 fn _vst4_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i8);
70469 }
70470 _vst4_s16(b.0, b.1, b.2, b.3, a as _)
70471}
70472#[doc = "Store multiple 4-element structures from four registers"]
70473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
70474#[doc = "## Safety"]
70475#[doc = " * Neon instrinsic unsafe"]
70476#[inline]
70477#[target_feature(enable = "neon")]
70478#[cfg(not(target_arch = "arm"))]
70479#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70480#[cfg_attr(test, assert_instr(st4))]
70481pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
70482 unsafe extern "unadjusted" {
70483 #[cfg_attr(
70484 any(target_arch = "aarch64", target_arch = "arm64ec"),
70485 link_name = "llvm.aarch64.neon.st4.v8i16.p0i8"
70486 )]
70487 fn _vst4q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i8);
70488 }
70489 _vst4q_s16(b.0, b.1, b.2, b.3, a as _)
70490}
70491#[doc = "Store multiple 4-element structures from four registers"]
70492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
70493#[doc = "## Safety"]
70494#[doc = " * Neon instrinsic unsafe"]
70495#[inline]
70496#[target_feature(enable = "neon")]
70497#[cfg(not(target_arch = "arm"))]
70498#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70499#[cfg_attr(test, assert_instr(st4))]
70500pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
70501 unsafe extern "unadjusted" {
70502 #[cfg_attr(
70503 any(target_arch = "aarch64", target_arch = "arm64ec"),
70504 link_name = "llvm.aarch64.neon.st4.v2i32.p0i8"
70505 )]
70506 fn _vst4_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i8);
70507 }
70508 _vst4_s32(b.0, b.1, b.2, b.3, a as _)
70509}
70510#[doc = "Store multiple 4-element structures from four registers"]
70511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
70512#[doc = "## Safety"]
70513#[doc = " * Neon instrinsic unsafe"]
70514#[inline]
70515#[target_feature(enable = "neon")]
70516#[cfg(not(target_arch = "arm"))]
70517#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70518#[cfg_attr(test, assert_instr(st4))]
70519pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
70520 unsafe extern "unadjusted" {
70521 #[cfg_attr(
70522 any(target_arch = "aarch64", target_arch = "arm64ec"),
70523 link_name = "llvm.aarch64.neon.st4.v4i32.p0i8"
70524 )]
70525 fn _vst4q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i8);
70526 }
70527 _vst4q_s32(b.0, b.1, b.2, b.3, a as _)
70528}
70529#[doc = "Store multiple 4-element structures from four registers"]
70530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
70531#[doc = "## Safety"]
70532#[doc = " * Neon instrinsic unsafe"]
70533#[inline]
70534#[cfg(target_arch = "arm")]
70535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70536#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70537#[rustc_legacy_const_generics(2)]
70538#[target_feature(enable = "neon,fp16")]
70539#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70540pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
70541 static_assert_uimm_bits!(LANE, 2);
70542 unsafe extern "unadjusted" {
70543 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4f16")]
70544 fn _vst4_lane_f16(
70545 ptr: *mut i8,
70546 a: float16x4_t,
70547 b: float16x4_t,
70548 c: float16x4_t,
70549 d: float16x4_t,
70550 n: i32,
70551 size: i32,
70552 );
70553 }
70554 _vst4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70555}
70556#[doc = "Store multiple 4-element structures from four registers"]
70557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
70558#[doc = "## Safety"]
70559#[doc = " * Neon instrinsic unsafe"]
70560#[inline]
70561#[cfg(target_arch = "arm")]
70562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70563#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70564#[rustc_legacy_const_generics(2)]
70565#[target_feature(enable = "neon,fp16")]
70566#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70567pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
70568 static_assert_uimm_bits!(LANE, 3);
70569 unsafe extern "unadjusted" {
70570 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8f16")]
70571 fn _vst4q_lane_f16(
70572 ptr: *mut i8,
70573 a: float16x8_t,
70574 b: float16x8_t,
70575 c: float16x8_t,
70576 d: float16x8_t,
70577 n: i32,
70578 size: i32,
70579 );
70580 }
70581 _vst4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70582}
70583#[doc = "Store multiple 4-element structures from four registers"]
70584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
70585#[doc = "## Safety"]
70586#[doc = " * Neon instrinsic unsafe"]
70587#[inline]
70588#[cfg(not(target_arch = "arm"))]
70589#[rustc_legacy_const_generics(2)]
70590#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70591#[target_feature(enable = "neon,fp16")]
70592#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70593pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
70594 static_assert_uimm_bits!(LANE, 2);
70595 unsafe extern "unadjusted" {
70596 #[cfg_attr(
70597 any(target_arch = "aarch64", target_arch = "arm64ec"),
70598 link_name = "llvm.aarch64.neon.st4lane.v4f16.p0i8"
70599 )]
70600 fn _vst4_lane_f16(
70601 a: float16x4_t,
70602 b: float16x4_t,
70603 c: float16x4_t,
70604 d: float16x4_t,
70605 n: i64,
70606 ptr: *mut i8,
70607 );
70608 }
70609 _vst4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70610}
70611#[doc = "Store multiple 4-element structures from four registers"]
70612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
70613#[doc = "## Safety"]
70614#[doc = " * Neon instrinsic unsafe"]
70615#[inline]
70616#[cfg(not(target_arch = "arm"))]
70617#[rustc_legacy_const_generics(2)]
70618#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70619#[target_feature(enable = "neon,fp16")]
70620#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70621pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
70622 static_assert_uimm_bits!(LANE, 3);
70623 unsafe extern "unadjusted" {
70624 #[cfg_attr(
70625 any(target_arch = "aarch64", target_arch = "arm64ec"),
70626 link_name = "llvm.aarch64.neon.st4lane.v8f16.p0i8"
70627 )]
70628 fn _vst4q_lane_f16(
70629 a: float16x8_t,
70630 b: float16x8_t,
70631 c: float16x8_t,
70632 d: float16x8_t,
70633 n: i64,
70634 ptr: *mut i8,
70635 );
70636 }
70637 _vst4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70638}
70639#[doc = "Store multiple 4-element structures from four registers"]
70640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
70641#[doc = "## Safety"]
70642#[doc = " * Neon instrinsic unsafe"]
70643#[inline]
70644#[cfg(target_arch = "arm")]
70645#[target_feature(enable = "neon,v7")]
70646#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70647#[rustc_legacy_const_generics(2)]
70648#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70649pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
70650 static_assert_uimm_bits!(LANE, 1);
70651 unsafe extern "unadjusted" {
70652 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v2f32")]
70653 fn _vst4_lane_f32(
70654 ptr: *mut i8,
70655 a: float32x2_t,
70656 b: float32x2_t,
70657 c: float32x2_t,
70658 d: float32x2_t,
70659 n: i32,
70660 size: i32,
70661 );
70662 }
70663 _vst4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70664}
70665#[doc = "Store multiple 4-element structures from four registers"]
70666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
70667#[doc = "## Safety"]
70668#[doc = " * Neon instrinsic unsafe"]
70669#[inline]
70670#[cfg(target_arch = "arm")]
70671#[target_feature(enable = "neon,v7")]
70672#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70673#[rustc_legacy_const_generics(2)]
70674#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70675pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
70676 static_assert_uimm_bits!(LANE, 2);
70677 unsafe extern "unadjusted" {
70678 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4f32")]
70679 fn _vst4q_lane_f32(
70680 ptr: *mut i8,
70681 a: float32x4_t,
70682 b: float32x4_t,
70683 c: float32x4_t,
70684 d: float32x4_t,
70685 n: i32,
70686 size: i32,
70687 );
70688 }
70689 _vst4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70690}
70691#[doc = "Store multiple 4-element structures from four registers"]
70692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
70693#[doc = "## Safety"]
70694#[doc = " * Neon instrinsic unsafe"]
70695#[inline]
70696#[cfg(target_arch = "arm")]
70697#[target_feature(enable = "neon,v7")]
70698#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70699#[rustc_legacy_const_generics(2)]
70700#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70701pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
70702 static_assert_uimm_bits!(LANE, 3);
70703 unsafe extern "unadjusted" {
70704 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8i8")]
70705 fn _vst4_lane_s8(
70706 ptr: *mut i8,
70707 a: int8x8_t,
70708 b: int8x8_t,
70709 c: int8x8_t,
70710 d: int8x8_t,
70711 n: i32,
70712 size: i32,
70713 );
70714 }
70715 _vst4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
70716}
70717#[doc = "Store multiple 4-element structures from four registers"]
70718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
70719#[doc = "## Safety"]
70720#[doc = " * Neon instrinsic unsafe"]
70721#[inline]
70722#[cfg(target_arch = "arm")]
70723#[target_feature(enable = "neon,v7")]
70724#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70725#[rustc_legacy_const_generics(2)]
70726#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70727pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
70728 static_assert_uimm_bits!(LANE, 2);
70729 unsafe extern "unadjusted" {
70730 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4i16")]
70731 fn _vst4_lane_s16(
70732 ptr: *mut i8,
70733 a: int16x4_t,
70734 b: int16x4_t,
70735 c: int16x4_t,
70736 d: int16x4_t,
70737 n: i32,
70738 size: i32,
70739 );
70740 }
70741 _vst4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70742}
70743#[doc = "Store multiple 4-element structures from four registers"]
70744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
70745#[doc = "## Safety"]
70746#[doc = " * Neon instrinsic unsafe"]
70747#[inline]
70748#[cfg(target_arch = "arm")]
70749#[target_feature(enable = "neon,v7")]
70750#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70751#[rustc_legacy_const_generics(2)]
70752#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70753pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
70754 static_assert_uimm_bits!(LANE, 3);
70755 unsafe extern "unadjusted" {
70756 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8i16")]
70757 fn _vst4q_lane_s16(
70758 ptr: *mut i8,
70759 a: int16x8_t,
70760 b: int16x8_t,
70761 c: int16x8_t,
70762 d: int16x8_t,
70763 n: i32,
70764 size: i32,
70765 );
70766 }
70767 _vst4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70768}
70769#[doc = "Store multiple 4-element structures from four registers"]
70770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
70771#[doc = "## Safety"]
70772#[doc = " * Neon instrinsic unsafe"]
70773#[inline]
70774#[cfg(target_arch = "arm")]
70775#[target_feature(enable = "neon,v7")]
70776#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70777#[rustc_legacy_const_generics(2)]
70778#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70779pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
70780 static_assert_uimm_bits!(LANE, 1);
70781 unsafe extern "unadjusted" {
70782 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v2i32")]
70783 fn _vst4_lane_s32(
70784 ptr: *mut i8,
70785 a: int32x2_t,
70786 b: int32x2_t,
70787 c: int32x2_t,
70788 d: int32x2_t,
70789 n: i32,
70790 size: i32,
70791 );
70792 }
70793 _vst4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70794}
70795#[doc = "Store multiple 4-element structures from four registers"]
70796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
70797#[doc = "## Safety"]
70798#[doc = " * Neon instrinsic unsafe"]
70799#[inline]
70800#[cfg(target_arch = "arm")]
70801#[target_feature(enable = "neon,v7")]
70802#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70803#[rustc_legacy_const_generics(2)]
70804#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70805pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
70806 static_assert_uimm_bits!(LANE, 2);
70807 unsafe extern "unadjusted" {
70808 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4i32")]
70809 fn _vst4q_lane_s32(
70810 ptr: *mut i8,
70811 a: int32x4_t,
70812 b: int32x4_t,
70813 c: int32x4_t,
70814 d: int32x4_t,
70815 n: i32,
70816 size: i32,
70817 );
70818 }
70819 _vst4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70820}
70821#[doc = "Store multiple 4-element structures from four registers"]
70822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
70823#[doc = "## Safety"]
70824#[doc = " * Neon instrinsic unsafe"]
70825#[inline]
70826#[target_feature(enable = "neon")]
70827#[cfg(not(target_arch = "arm"))]
70828#[rustc_legacy_const_generics(2)]
70829#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70830#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70831pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
70832 static_assert_uimm_bits!(LANE, 1);
70833 unsafe extern "unadjusted" {
70834 #[cfg_attr(
70835 any(target_arch = "aarch64", target_arch = "arm64ec"),
70836 link_name = "llvm.aarch64.neon.st4lane.v2f32.p0i8"
70837 )]
70838 fn _vst4_lane_f32(
70839 a: float32x2_t,
70840 b: float32x2_t,
70841 c: float32x2_t,
70842 d: float32x2_t,
70843 n: i64,
70844 ptr: *mut i8,
70845 );
70846 }
70847 _vst4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70848}
70849#[doc = "Store multiple 4-element structures from four registers"]
70850#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
70851#[doc = "## Safety"]
70852#[doc = " * Neon instrinsic unsafe"]
70853#[inline]
70854#[target_feature(enable = "neon")]
70855#[cfg(not(target_arch = "arm"))]
70856#[rustc_legacy_const_generics(2)]
70857#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70858#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70859pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
70860 static_assert_uimm_bits!(LANE, 2);
70861 unsafe extern "unadjusted" {
70862 #[cfg_attr(
70863 any(target_arch = "aarch64", target_arch = "arm64ec"),
70864 link_name = "llvm.aarch64.neon.st4lane.v4f32.p0i8"
70865 )]
70866 fn _vst4q_lane_f32(
70867 a: float32x4_t,
70868 b: float32x4_t,
70869 c: float32x4_t,
70870 d: float32x4_t,
70871 n: i64,
70872 ptr: *mut i8,
70873 );
70874 }
70875 _vst4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70876}
70877#[doc = "Store multiple 4-element structures from four registers"]
70878#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
70879#[doc = "## Safety"]
70880#[doc = " * Neon instrinsic unsafe"]
70881#[inline]
70882#[target_feature(enable = "neon")]
70883#[cfg(not(target_arch = "arm"))]
70884#[rustc_legacy_const_generics(2)]
70885#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70886#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70887pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
70888 static_assert_uimm_bits!(LANE, 3);
70889 unsafe extern "unadjusted" {
70890 #[cfg_attr(
70891 any(target_arch = "aarch64", target_arch = "arm64ec"),
70892 link_name = "llvm.aarch64.neon.st4lane.v8i8.p0i8"
70893 )]
70894 fn _vst4_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *mut i8);
70895 }
70896 _vst4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70897}
70898#[doc = "Store multiple 4-element structures from four registers"]
70899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
70900#[doc = "## Safety"]
70901#[doc = " * Neon instrinsic unsafe"]
70902#[inline]
70903#[target_feature(enable = "neon")]
70904#[cfg(not(target_arch = "arm"))]
70905#[rustc_legacy_const_generics(2)]
70906#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70907#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70908pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
70909 static_assert_uimm_bits!(LANE, 2);
70910 unsafe extern "unadjusted" {
70911 #[cfg_attr(
70912 any(target_arch = "aarch64", target_arch = "arm64ec"),
70913 link_name = "llvm.aarch64.neon.st4lane.v4i16.p0i8"
70914 )]
70915 fn _vst4_lane_s16(
70916 a: int16x4_t,
70917 b: int16x4_t,
70918 c: int16x4_t,
70919 d: int16x4_t,
70920 n: i64,
70921 ptr: *mut i8,
70922 );
70923 }
70924 _vst4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70925}
70926#[doc = "Store multiple 4-element structures from four registers"]
70927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
70928#[doc = "## Safety"]
70929#[doc = " * Neon instrinsic unsafe"]
70930#[inline]
70931#[target_feature(enable = "neon")]
70932#[cfg(not(target_arch = "arm"))]
70933#[rustc_legacy_const_generics(2)]
70934#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70935#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70936pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
70937 static_assert_uimm_bits!(LANE, 3);
70938 unsafe extern "unadjusted" {
70939 #[cfg_attr(
70940 any(target_arch = "aarch64", target_arch = "arm64ec"),
70941 link_name = "llvm.aarch64.neon.st4lane.v8i16.p0i8"
70942 )]
70943 fn _vst4q_lane_s16(
70944 a: int16x8_t,
70945 b: int16x8_t,
70946 c: int16x8_t,
70947 d: int16x8_t,
70948 n: i64,
70949 ptr: *mut i8,
70950 );
70951 }
70952 _vst4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70953}
70954#[doc = "Store multiple 4-element structures from four registers"]
70955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
70956#[doc = "## Safety"]
70957#[doc = " * Neon instrinsic unsafe"]
70958#[inline]
70959#[target_feature(enable = "neon")]
70960#[cfg(not(target_arch = "arm"))]
70961#[rustc_legacy_const_generics(2)]
70962#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70963#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70964pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
70965 static_assert_uimm_bits!(LANE, 1);
70966 unsafe extern "unadjusted" {
70967 #[cfg_attr(
70968 any(target_arch = "aarch64", target_arch = "arm64ec"),
70969 link_name = "llvm.aarch64.neon.st4lane.v2i32.p0i8"
70970 )]
70971 fn _vst4_lane_s32(
70972 a: int32x2_t,
70973 b: int32x2_t,
70974 c: int32x2_t,
70975 d: int32x2_t,
70976 n: i64,
70977 ptr: *mut i8,
70978 );
70979 }
70980 _vst4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70981}
70982#[doc = "Store multiple 4-element structures from four registers"]
70983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
70984#[doc = "## Safety"]
70985#[doc = " * Neon instrinsic unsafe"]
70986#[inline]
70987#[target_feature(enable = "neon")]
70988#[cfg(not(target_arch = "arm"))]
70989#[rustc_legacy_const_generics(2)]
70990#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70991#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70992pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
70993 static_assert_uimm_bits!(LANE, 2);
70994 unsafe extern "unadjusted" {
70995 #[cfg_attr(
70996 any(target_arch = "aarch64", target_arch = "arm64ec"),
70997 link_name = "llvm.aarch64.neon.st4lane.v4i32.p0i8"
70998 )]
70999 fn _vst4q_lane_s32(
71000 a: int32x4_t,
71001 b: int32x4_t,
71002 c: int32x4_t,
71003 d: int32x4_t,
71004 n: i64,
71005 ptr: *mut i8,
71006 );
71007 }
71008 _vst4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
71009}
71010#[doc = "Store multiple 4-element structures from four registers"]
71011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"]
71012#[doc = "## Safety"]
71013#[doc = " * Neon instrinsic unsafe"]
71014#[inline]
71015#[target_feature(enable = "neon")]
71016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71017#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71018#[cfg_attr(
71019 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71020 assert_instr(st4, LANE = 0)
71021)]
71022#[rustc_legacy_const_generics(2)]
71023#[cfg_attr(
71024 not(target_arch = "arm"),
71025 stable(feature = "neon_intrinsics", since = "1.59.0")
71026)]
71027#[cfg_attr(
71028 target_arch = "arm",
71029 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71030)]
71031pub unsafe fn vst4_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x4_t) {
71032 static_assert_uimm_bits!(LANE, 3);
71033 vst4_lane_s8::<LANE>(transmute(a), transmute(b))
71034}
71035#[doc = "Store multiple 4-element structures from four registers"]
71036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"]
71037#[doc = "## Safety"]
71038#[doc = " * Neon instrinsic unsafe"]
71039#[inline]
71040#[target_feature(enable = "neon")]
71041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71043#[cfg_attr(
71044 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71045 assert_instr(st4, LANE = 0)
71046)]
71047#[rustc_legacy_const_generics(2)]
71048#[cfg_attr(
71049 not(target_arch = "arm"),
71050 stable(feature = "neon_intrinsics", since = "1.59.0")
71051)]
71052#[cfg_attr(
71053 target_arch = "arm",
71054 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71055)]
71056pub unsafe fn vst4_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x4_t) {
71057 static_assert_uimm_bits!(LANE, 2);
71058 vst4_lane_s16::<LANE>(transmute(a), transmute(b))
71059}
71060#[doc = "Store multiple 4-element structures from four registers"]
71061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"]
71062#[doc = "## Safety"]
71063#[doc = " * Neon instrinsic unsafe"]
71064#[inline]
71065#[target_feature(enable = "neon")]
71066#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71067#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71068#[cfg_attr(
71069 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71070 assert_instr(st4, LANE = 0)
71071)]
71072#[rustc_legacy_const_generics(2)]
71073#[cfg_attr(
71074 not(target_arch = "arm"),
71075 stable(feature = "neon_intrinsics", since = "1.59.0")
71076)]
71077#[cfg_attr(
71078 target_arch = "arm",
71079 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71080)]
71081pub unsafe fn vst4q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x4_t) {
71082 static_assert_uimm_bits!(LANE, 3);
71083 vst4q_lane_s16::<LANE>(transmute(a), transmute(b))
71084}
71085#[doc = "Store multiple 4-element structures from four registers"]
71086#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"]
71087#[doc = "## Safety"]
71088#[doc = " * Neon instrinsic unsafe"]
71089#[inline]
71090#[target_feature(enable = "neon")]
71091#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71092#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71093#[cfg_attr(
71094 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71095 assert_instr(st4, LANE = 0)
71096)]
71097#[rustc_legacy_const_generics(2)]
71098#[cfg_attr(
71099 not(target_arch = "arm"),
71100 stable(feature = "neon_intrinsics", since = "1.59.0")
71101)]
71102#[cfg_attr(
71103 target_arch = "arm",
71104 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71105)]
71106pub unsafe fn vst4_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x4_t) {
71107 static_assert_uimm_bits!(LANE, 1);
71108 vst4_lane_s32::<LANE>(transmute(a), transmute(b))
71109}
71110#[doc = "Store multiple 4-element structures from four registers"]
71111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"]
71112#[doc = "## Safety"]
71113#[doc = " * Neon instrinsic unsafe"]
71114#[inline]
71115#[target_feature(enable = "neon")]
71116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71118#[cfg_attr(
71119 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71120 assert_instr(st4, LANE = 0)
71121)]
71122#[rustc_legacy_const_generics(2)]
71123#[cfg_attr(
71124 not(target_arch = "arm"),
71125 stable(feature = "neon_intrinsics", since = "1.59.0")
71126)]
71127#[cfg_attr(
71128 target_arch = "arm",
71129 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71130)]
71131pub unsafe fn vst4q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x4_t) {
71132 static_assert_uimm_bits!(LANE, 2);
71133 vst4q_lane_s32::<LANE>(transmute(a), transmute(b))
71134}
71135#[doc = "Store multiple 4-element structures from four registers"]
71136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"]
71137#[doc = "## Safety"]
71138#[doc = " * Neon instrinsic unsafe"]
71139#[inline]
71140#[target_feature(enable = "neon")]
71141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71143#[cfg_attr(
71144 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71145 assert_instr(st4, LANE = 0)
71146)]
71147#[rustc_legacy_const_generics(2)]
71148#[cfg_attr(
71149 not(target_arch = "arm"),
71150 stable(feature = "neon_intrinsics", since = "1.59.0")
71151)]
71152#[cfg_attr(
71153 target_arch = "arm",
71154 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71155)]
71156pub unsafe fn vst4_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x4_t) {
71157 static_assert_uimm_bits!(LANE, 3);
71158 vst4_lane_s8::<LANE>(transmute(a), transmute(b))
71159}
71160#[doc = "Store multiple 4-element structures from four registers"]
71161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"]
71162#[doc = "## Safety"]
71163#[doc = " * Neon instrinsic unsafe"]
71164#[inline]
71165#[target_feature(enable = "neon")]
71166#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71167#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71168#[cfg_attr(
71169 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71170 assert_instr(st4, LANE = 0)
71171)]
71172#[rustc_legacy_const_generics(2)]
71173#[cfg_attr(
71174 not(target_arch = "arm"),
71175 stable(feature = "neon_intrinsics", since = "1.59.0")
71176)]
71177#[cfg_attr(
71178 target_arch = "arm",
71179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71180)]
71181pub unsafe fn vst4_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x4_t) {
71182 static_assert_uimm_bits!(LANE, 2);
71183 vst4_lane_s16::<LANE>(transmute(a), transmute(b))
71184}
71185#[doc = "Store multiple 4-element structures from four registers"]
71186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"]
71187#[doc = "## Safety"]
71188#[doc = " * Neon instrinsic unsafe"]
71189#[inline]
71190#[target_feature(enable = "neon")]
71191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71192#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
71193#[cfg_attr(
71194 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71195 assert_instr(st4, LANE = 0)
71196)]
71197#[rustc_legacy_const_generics(2)]
71198#[cfg_attr(
71199 not(target_arch = "arm"),
71200 stable(feature = "neon_intrinsics", since = "1.59.0")
71201)]
71202#[cfg_attr(
71203 target_arch = "arm",
71204 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71205)]
71206pub unsafe fn vst4q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x4_t) {
71207 static_assert_uimm_bits!(LANE, 3);
71208 vst4q_lane_s16::<LANE>(transmute(a), transmute(b))
71209}
71210#[doc = "Store multiple 4-element structures from four registers"]
71211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"]
71212#[doc = "## Safety"]
71213#[doc = " * Neon instrinsic unsafe"]
71214#[inline]
71215#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
71216#[target_feature(enable = "neon,aes")]
71217#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
71218#[cfg_attr(
71219 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71220 assert_instr(nop)
71221)]
71222#[cfg_attr(
71223 not(target_arch = "arm"),
71224 stable(feature = "neon_intrinsics", since = "1.59.0")
71225)]
71226#[cfg_attr(
71227 target_arch = "arm",
71228 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71229)]
71230pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) {
71231 vst4_s64(transmute(a), transmute(b))
71232}
71233#[doc = "Store multiple 4-element structures from four registers"]
71234#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
71235#[doc = "## Safety"]
71236#[doc = " * Neon instrinsic unsafe"]
71237#[inline]
71238#[cfg(target_arch = "arm")]
71239#[target_feature(enable = "neon,v7")]
71240#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
71241#[cfg_attr(test, assert_instr(nop))]
71242pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
71243 unsafe extern "unadjusted" {
71244 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v1i64")]
71245 fn _vst4_s64(
71246 ptr: *mut i8,
71247 a: int64x1_t,
71248 b: int64x1_t,
71249 c: int64x1_t,
71250 d: int64x1_t,
71251 size: i32,
71252 );
71253 }
71254 _vst4_s64(a as _, b.0, b.1, b.2, b.3, 8)
71255}
71256#[doc = "Store multiple 4-element structures from four registers"]
71257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
71258#[doc = "## Safety"]
71259#[doc = " * Neon instrinsic unsafe"]
71260#[inline]
71261#[target_feature(enable = "neon")]
71262#[cfg(not(target_arch = "arm"))]
71263#[stable(feature = "neon_intrinsics", since = "1.59.0")]
71264#[cfg_attr(test, assert_instr(nop))]
71265pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
71266 unsafe extern "unadjusted" {
71267 #[cfg_attr(
71268 any(target_arch = "aarch64", target_arch = "arm64ec"),
71269 link_name = "llvm.aarch64.neon.st4.v1i64.p0i8"
71270 )]
71271 fn _vst4_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i8);
71272 }
71273 _vst4_s64(b.0, b.1, b.2, b.3, a as _)
71274}
71275#[doc = "Store multiple 4-element structures from four registers"]
71276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"]
71277#[doc = "## Safety"]
71278#[doc = " * Neon instrinsic unsafe"]
71279#[inline]
71280#[target_feature(enable = "neon")]
71281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
71283#[cfg_attr(
71284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71285 assert_instr(nop)
71286)]
71287#[cfg_attr(
71288 not(target_arch = "arm"),
71289 stable(feature = "neon_intrinsics", since = "1.59.0")
71290)]
71291#[cfg_attr(
71292 target_arch = "arm",
71293 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71294)]
71295pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) {
71296 vst4_s64(transmute(a), transmute(b))
71297}
71298#[doc = "Store multiple 4-element structures from four registers"]
71299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"]
71300#[doc = "## Safety"]
71301#[doc = " * Neon instrinsic unsafe"]
71302#[inline]
71303#[target_feature(enable = "neon")]
71304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71305#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71306#[cfg_attr(
71307 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71308 assert_instr(st4)
71309)]
71310#[cfg_attr(
71311 not(target_arch = "arm"),
71312 stable(feature = "neon_intrinsics", since = "1.59.0")
71313)]
71314#[cfg_attr(
71315 target_arch = "arm",
71316 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71317)]
71318pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) {
71319 vst4_s8(transmute(a), transmute(b))
71320}
71321#[doc = "Store multiple 4-element structures from four registers"]
71322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"]
71323#[doc = "## Safety"]
71324#[doc = " * Neon instrinsic unsafe"]
71325#[inline]
71326#[target_feature(enable = "neon")]
71327#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71328#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71329#[cfg_attr(
71330 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71331 assert_instr(st4)
71332)]
71333#[cfg_attr(
71334 not(target_arch = "arm"),
71335 stable(feature = "neon_intrinsics", since = "1.59.0")
71336)]
71337#[cfg_attr(
71338 target_arch = "arm",
71339 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71340)]
71341pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) {
71342 vst4q_s8(transmute(a), transmute(b))
71343}
71344#[doc = "Store multiple 4-element structures from four registers"]
71345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"]
71346#[doc = "## Safety"]
71347#[doc = " * Neon instrinsic unsafe"]
71348#[inline]
71349#[target_feature(enable = "neon")]
71350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71351#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71352#[cfg_attr(
71353 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71354 assert_instr(st4)
71355)]
71356#[cfg_attr(
71357 not(target_arch = "arm"),
71358 stable(feature = "neon_intrinsics", since = "1.59.0")
71359)]
71360#[cfg_attr(
71361 target_arch = "arm",
71362 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71363)]
71364pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) {
71365 vst4_s16(transmute(a), transmute(b))
71366}
71367#[doc = "Store multiple 4-element structures from four registers"]
71368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"]
71369#[doc = "## Safety"]
71370#[doc = " * Neon instrinsic unsafe"]
71371#[inline]
71372#[target_feature(enable = "neon")]
71373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71375#[cfg_attr(
71376 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71377 assert_instr(st4)
71378)]
71379#[cfg_attr(
71380 not(target_arch = "arm"),
71381 stable(feature = "neon_intrinsics", since = "1.59.0")
71382)]
71383#[cfg_attr(
71384 target_arch = "arm",
71385 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71386)]
71387pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) {
71388 vst4q_s16(transmute(a), transmute(b))
71389}
71390#[doc = "Store multiple 4-element structures from four registers"]
71391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"]
71392#[doc = "## Safety"]
71393#[doc = " * Neon instrinsic unsafe"]
71394#[inline]
71395#[target_feature(enable = "neon")]
71396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71398#[cfg_attr(
71399 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71400 assert_instr(st4)
71401)]
71402#[cfg_attr(
71403 not(target_arch = "arm"),
71404 stable(feature = "neon_intrinsics", since = "1.59.0")
71405)]
71406#[cfg_attr(
71407 target_arch = "arm",
71408 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71409)]
71410pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) {
71411 vst4_s32(transmute(a), transmute(b))
71412}
71413#[doc = "Store multiple 4-element structures from four registers"]
71414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"]
71415#[doc = "## Safety"]
71416#[doc = " * Neon instrinsic unsafe"]
71417#[inline]
71418#[target_feature(enable = "neon")]
71419#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71420#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71421#[cfg_attr(
71422 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71423 assert_instr(st4)
71424)]
71425#[cfg_attr(
71426 not(target_arch = "arm"),
71427 stable(feature = "neon_intrinsics", since = "1.59.0")
71428)]
71429#[cfg_attr(
71430 target_arch = "arm",
71431 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71432)]
71433pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) {
71434 vst4q_s32(transmute(a), transmute(b))
71435}
71436#[doc = "Store multiple 4-element structures from four registers"]
71437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"]
71438#[doc = "## Safety"]
71439#[doc = " * Neon instrinsic unsafe"]
71440#[inline]
71441#[target_feature(enable = "neon")]
71442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71444#[cfg_attr(
71445 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71446 assert_instr(st4)
71447)]
71448#[cfg_attr(
71449 not(target_arch = "arm"),
71450 stable(feature = "neon_intrinsics", since = "1.59.0")
71451)]
71452#[cfg_attr(
71453 target_arch = "arm",
71454 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71455)]
71456pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) {
71457 vst4_s8(transmute(a), transmute(b))
71458}
71459#[doc = "Store multiple 4-element structures from four registers"]
71460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"]
71461#[doc = "## Safety"]
71462#[doc = " * Neon instrinsic unsafe"]
71463#[inline]
71464#[target_feature(enable = "neon")]
71465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71467#[cfg_attr(
71468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71469 assert_instr(st4)
71470)]
71471#[cfg_attr(
71472 not(target_arch = "arm"),
71473 stable(feature = "neon_intrinsics", since = "1.59.0")
71474)]
71475#[cfg_attr(
71476 target_arch = "arm",
71477 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71478)]
71479pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) {
71480 vst4q_s8(transmute(a), transmute(b))
71481}
71482#[doc = "Store multiple 4-element structures from four registers"]
71483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"]
71484#[doc = "## Safety"]
71485#[doc = " * Neon instrinsic unsafe"]
71486#[inline]
71487#[target_feature(enable = "neon")]
71488#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71489#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71490#[cfg_attr(
71491 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71492 assert_instr(st4)
71493)]
71494#[cfg_attr(
71495 not(target_arch = "arm"),
71496 stable(feature = "neon_intrinsics", since = "1.59.0")
71497)]
71498#[cfg_attr(
71499 target_arch = "arm",
71500 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71501)]
71502pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) {
71503 vst4_s16(transmute(a), transmute(b))
71504}
71505#[doc = "Store multiple 4-element structures from four registers"]
71506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"]
71507#[doc = "## Safety"]
71508#[doc = " * Neon instrinsic unsafe"]
71509#[inline]
71510#[target_feature(enable = "neon")]
71511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71513#[cfg_attr(
71514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71515 assert_instr(st4)
71516)]
71517#[cfg_attr(
71518 not(target_arch = "arm"),
71519 stable(feature = "neon_intrinsics", since = "1.59.0")
71520)]
71521#[cfg_attr(
71522 target_arch = "arm",
71523 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71524)]
71525pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) {
71526 vst4q_s16(transmute(a), transmute(b))
71527}
71528#[doc = "Store SIMD&FP register (immediate offset)"]
71529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"]
71530#[doc = "## Safety"]
71531#[doc = " * Neon instrinsic unsafe"]
71532#[inline]
71533#[target_feature(enable = "neon")]
71534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
71536#[cfg_attr(
71537 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71538 assert_instr(nop)
71539)]
71540#[cfg_attr(
71541 not(target_arch = "arm"),
71542 stable(feature = "neon_intrinsics", since = "1.59.0")
71543)]
71544#[cfg_attr(
71545 target_arch = "arm",
71546 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71547)]
71548pub unsafe fn vstrq_p128(a: *mut p128, b: p128) {
71549 *a = b
71550}
71551#[doc = "Subtract"]
71552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"]
71553#[inline]
71554#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
71555#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
71556#[cfg_attr(
71557 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71558 assert_instr(fsub)
71559)]
71560#[target_feature(enable = "neon,fp16")]
71561#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
71562pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
71563 unsafe { simd_sub(a, b) }
71564}
71565#[doc = "Subtract"]
71566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"]
71567#[inline]
71568#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
71569#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
71570#[cfg_attr(
71571 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71572 assert_instr(fsub)
71573)]
71574#[target_feature(enable = "neon,fp16")]
71575#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
71576pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
71577 unsafe { simd_sub(a, b) }
71578}
71579#[doc = "Subtract"]
71580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"]
71581#[inline]
71582#[target_feature(enable = "neon")]
71583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71584#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
71585#[cfg_attr(
71586 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71587 assert_instr(fsub)
71588)]
71589#[cfg_attr(
71590 not(target_arch = "arm"),
71591 stable(feature = "neon_intrinsics", since = "1.59.0")
71592)]
71593#[cfg_attr(
71594 target_arch = "arm",
71595 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71596)]
71597pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
71598 unsafe { simd_sub(a, b) }
71599}
71600#[doc = "Subtract"]
71601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"]
71602#[inline]
71603#[target_feature(enable = "neon")]
71604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71605#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
71606#[cfg_attr(
71607 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71608 assert_instr(fsub)
71609)]
71610#[cfg_attr(
71611 not(target_arch = "arm"),
71612 stable(feature = "neon_intrinsics", since = "1.59.0")
71613)]
71614#[cfg_attr(
71615 target_arch = "arm",
71616 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71617)]
71618pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
71619 unsafe { simd_sub(a, b) }
71620}
71621#[doc = "Subtract"]
71622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"]
71623#[inline]
71624#[target_feature(enable = "neon")]
71625#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71626#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71627#[cfg_attr(
71628 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71629 assert_instr(sub)
71630)]
71631#[cfg_attr(
71632 not(target_arch = "arm"),
71633 stable(feature = "neon_intrinsics", since = "1.59.0")
71634)]
71635#[cfg_attr(
71636 target_arch = "arm",
71637 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71638)]
71639pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
71640 unsafe { simd_sub(a, b) }
71641}
71642#[doc = "Subtract"]
71643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"]
71644#[inline]
71645#[target_feature(enable = "neon")]
71646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71647#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71648#[cfg_attr(
71649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71650 assert_instr(sub)
71651)]
71652#[cfg_attr(
71653 not(target_arch = "arm"),
71654 stable(feature = "neon_intrinsics", since = "1.59.0")
71655)]
71656#[cfg_attr(
71657 target_arch = "arm",
71658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71659)]
71660pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
71661 unsafe { simd_sub(a, b) }
71662}
71663#[doc = "Subtract"]
71664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"]
71665#[inline]
71666#[target_feature(enable = "neon")]
71667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71668#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71669#[cfg_attr(
71670 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71671 assert_instr(sub)
71672)]
71673#[cfg_attr(
71674 not(target_arch = "arm"),
71675 stable(feature = "neon_intrinsics", since = "1.59.0")
71676)]
71677#[cfg_attr(
71678 target_arch = "arm",
71679 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71680)]
71681pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
71682 unsafe { simd_sub(a, b) }
71683}
71684#[doc = "Subtract"]
71685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"]
71686#[inline]
71687#[target_feature(enable = "neon")]
71688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71689#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71690#[cfg_attr(
71691 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71692 assert_instr(sub)
71693)]
71694#[cfg_attr(
71695 not(target_arch = "arm"),
71696 stable(feature = "neon_intrinsics", since = "1.59.0")
71697)]
71698#[cfg_attr(
71699 target_arch = "arm",
71700 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71701)]
71702pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
71703 unsafe { simd_sub(a, b) }
71704}
71705#[doc = "Subtract"]
71706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"]
71707#[inline]
71708#[target_feature(enable = "neon")]
71709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71710#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71711#[cfg_attr(
71712 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71713 assert_instr(sub)
71714)]
71715#[cfg_attr(
71716 not(target_arch = "arm"),
71717 stable(feature = "neon_intrinsics", since = "1.59.0")
71718)]
71719#[cfg_attr(
71720 target_arch = "arm",
71721 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71722)]
71723pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
71724 unsafe { simd_sub(a, b) }
71725}
71726#[doc = "Subtract"]
71727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"]
71728#[inline]
71729#[target_feature(enable = "neon")]
71730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71731#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71732#[cfg_attr(
71733 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71734 assert_instr(sub)
71735)]
71736#[cfg_attr(
71737 not(target_arch = "arm"),
71738 stable(feature = "neon_intrinsics", since = "1.59.0")
71739)]
71740#[cfg_attr(
71741 target_arch = "arm",
71742 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71743)]
71744pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
71745 unsafe { simd_sub(a, b) }
71746}
71747#[doc = "Subtract"]
71748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"]
71749#[inline]
71750#[target_feature(enable = "neon")]
71751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71752#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71753#[cfg_attr(
71754 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71755 assert_instr(sub)
71756)]
71757#[cfg_attr(
71758 not(target_arch = "arm"),
71759 stable(feature = "neon_intrinsics", since = "1.59.0")
71760)]
71761#[cfg_attr(
71762 target_arch = "arm",
71763 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71764)]
71765pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
71766 unsafe { simd_sub(a, b) }
71767}
71768#[doc = "Subtract"]
71769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"]
71770#[inline]
71771#[target_feature(enable = "neon")]
71772#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71773#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71774#[cfg_attr(
71775 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71776 assert_instr(sub)
71777)]
71778#[cfg_attr(
71779 not(target_arch = "arm"),
71780 stable(feature = "neon_intrinsics", since = "1.59.0")
71781)]
71782#[cfg_attr(
71783 target_arch = "arm",
71784 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71785)]
71786pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
71787 unsafe { simd_sub(a, b) }
71788}
71789#[doc = "Subtract"]
71790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"]
71791#[inline]
71792#[target_feature(enable = "neon")]
71793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71794#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71795#[cfg_attr(
71796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71797 assert_instr(sub)
71798)]
71799#[cfg_attr(
71800 not(target_arch = "arm"),
71801 stable(feature = "neon_intrinsics", since = "1.59.0")
71802)]
71803#[cfg_attr(
71804 target_arch = "arm",
71805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71806)]
71807pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
71808 unsafe { simd_sub(a, b) }
71809}
71810#[doc = "Subtract"]
71811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"]
71812#[inline]
71813#[target_feature(enable = "neon")]
71814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71815#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71816#[cfg_attr(
71817 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71818 assert_instr(sub)
71819)]
71820#[cfg_attr(
71821 not(target_arch = "arm"),
71822 stable(feature = "neon_intrinsics", since = "1.59.0")
71823)]
71824#[cfg_attr(
71825 target_arch = "arm",
71826 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71827)]
71828pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
71829 unsafe { simd_sub(a, b) }
71830}
71831#[doc = "Subtract"]
71832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"]
71833#[inline]
71834#[target_feature(enable = "neon")]
71835#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71836#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71837#[cfg_attr(
71838 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71839 assert_instr(sub)
71840)]
71841#[cfg_attr(
71842 not(target_arch = "arm"),
71843 stable(feature = "neon_intrinsics", since = "1.59.0")
71844)]
71845#[cfg_attr(
71846 target_arch = "arm",
71847 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71848)]
71849pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
71850 unsafe { simd_sub(a, b) }
71851}
71852#[doc = "Subtract"]
71853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"]
71854#[inline]
71855#[target_feature(enable = "neon")]
71856#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71857#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71858#[cfg_attr(
71859 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71860 assert_instr(sub)
71861)]
71862#[cfg_attr(
71863 not(target_arch = "arm"),
71864 stable(feature = "neon_intrinsics", since = "1.59.0")
71865)]
71866#[cfg_attr(
71867 target_arch = "arm",
71868 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71869)]
71870pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
71871 unsafe { simd_sub(a, b) }
71872}
71873#[doc = "Subtract"]
71874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"]
71875#[inline]
71876#[target_feature(enable = "neon")]
71877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71878#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71879#[cfg_attr(
71880 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71881 assert_instr(sub)
71882)]
71883#[cfg_attr(
71884 not(target_arch = "arm"),
71885 stable(feature = "neon_intrinsics", since = "1.59.0")
71886)]
71887#[cfg_attr(
71888 target_arch = "arm",
71889 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71890)]
71891pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
71892 unsafe { simd_sub(a, b) }
71893}
71894#[doc = "Subtract"]
71895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"]
71896#[inline]
71897#[target_feature(enable = "neon")]
71898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71899#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71900#[cfg_attr(
71901 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71902 assert_instr(sub)
71903)]
71904#[cfg_attr(
71905 not(target_arch = "arm"),
71906 stable(feature = "neon_intrinsics", since = "1.59.0")
71907)]
71908#[cfg_attr(
71909 target_arch = "arm",
71910 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71911)]
71912pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
71913 unsafe { simd_sub(a, b) }
71914}
71915#[doc = "Subtract"]
71916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"]
71917#[inline]
71918#[target_feature(enable = "neon")]
71919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71920#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71921#[cfg_attr(
71922 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71923 assert_instr(sub)
71924)]
71925#[cfg_attr(
71926 not(target_arch = "arm"),
71927 stable(feature = "neon_intrinsics", since = "1.59.0")
71928)]
71929#[cfg_attr(
71930 target_arch = "arm",
71931 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71932)]
71933pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
71934 unsafe { simd_sub(a, b) }
71935}
71936#[doc = "Subtract"]
71937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"]
71938#[inline]
71939#[target_feature(enable = "neon")]
71940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71941#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71942#[cfg_attr(
71943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71944 assert_instr(sub)
71945)]
71946#[cfg_attr(
71947 not(target_arch = "arm"),
71948 stable(feature = "neon_intrinsics", since = "1.59.0")
71949)]
71950#[cfg_attr(
71951 target_arch = "arm",
71952 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71953)]
71954pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
71955 unsafe { simd_sub(a, b) }
71956}
71957#[doc = "Subtract returning high narrow"]
71958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"]
71959#[inline]
71960#[target_feature(enable = "neon")]
71961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71962#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71963#[cfg_attr(
71964 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71965 assert_instr(subhn2)
71966)]
71967#[cfg_attr(
71968 not(target_arch = "arm"),
71969 stable(feature = "neon_intrinsics", since = "1.59.0")
71970)]
71971#[cfg_attr(
71972 target_arch = "arm",
71973 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71974)]
71975pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
71976 let d: int8x8_t = vsubhn_s16(b, c);
71977 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
71978}
71979#[doc = "Subtract returning high narrow"]
71980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"]
71981#[inline]
71982#[target_feature(enable = "neon")]
71983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71985#[cfg_attr(
71986 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71987 assert_instr(subhn2)
71988)]
71989#[cfg_attr(
71990 not(target_arch = "arm"),
71991 stable(feature = "neon_intrinsics", since = "1.59.0")
71992)]
71993#[cfg_attr(
71994 target_arch = "arm",
71995 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71996)]
71997pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
71998 let d: int16x4_t = vsubhn_s32(b, c);
71999 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
72000}
72001#[doc = "Subtract returning high narrow"]
72002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"]
72003#[inline]
72004#[target_feature(enable = "neon")]
72005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72007#[cfg_attr(
72008 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72009 assert_instr(subhn2)
72010)]
72011#[cfg_attr(
72012 not(target_arch = "arm"),
72013 stable(feature = "neon_intrinsics", since = "1.59.0")
72014)]
72015#[cfg_attr(
72016 target_arch = "arm",
72017 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72018)]
72019pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
72020 let d: int32x2_t = vsubhn_s64(b, c);
72021 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
72022}
72023#[doc = "Subtract returning high narrow"]
72024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"]
72025#[inline]
72026#[target_feature(enable = "neon")]
72027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72029#[cfg_attr(
72030 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72031 assert_instr(subhn2)
72032)]
72033#[cfg_attr(
72034 not(target_arch = "arm"),
72035 stable(feature = "neon_intrinsics", since = "1.59.0")
72036)]
72037#[cfg_attr(
72038 target_arch = "arm",
72039 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72040)]
72041pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
72042 let d: uint8x8_t = vsubhn_u16(b, c);
72043 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
72044}
72045#[doc = "Subtract returning high narrow"]
72046#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"]
72047#[inline]
72048#[target_feature(enable = "neon")]
72049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72050#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72051#[cfg_attr(
72052 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72053 assert_instr(subhn2)
72054)]
72055#[cfg_attr(
72056 not(target_arch = "arm"),
72057 stable(feature = "neon_intrinsics", since = "1.59.0")
72058)]
72059#[cfg_attr(
72060 target_arch = "arm",
72061 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72062)]
72063pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
72064 let d: uint16x4_t = vsubhn_u32(b, c);
72065 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
72066}
72067#[doc = "Subtract returning high narrow"]
72068#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"]
72069#[inline]
72070#[target_feature(enable = "neon")]
72071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72072#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72073#[cfg_attr(
72074 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72075 assert_instr(subhn2)
72076)]
72077#[cfg_attr(
72078 not(target_arch = "arm"),
72079 stable(feature = "neon_intrinsics", since = "1.59.0")
72080)]
72081#[cfg_attr(
72082 target_arch = "arm",
72083 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72084)]
72085pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
72086 let d: uint32x2_t = vsubhn_u64(b, c);
72087 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
72088}
72089#[doc = "Subtract returning high narrow"]
72090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"]
72091#[inline]
72092#[target_feature(enable = "neon")]
72093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72094#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72095#[cfg_attr(
72096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72097 assert_instr(subhn)
72098)]
72099#[cfg_attr(
72100 not(target_arch = "arm"),
72101 stable(feature = "neon_intrinsics", since = "1.59.0")
72102)]
72103#[cfg_attr(
72104 target_arch = "arm",
72105 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72106)]
72107pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
72108 let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8);
72109 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72110}
72111#[doc = "Subtract returning high narrow"]
72112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"]
72113#[inline]
72114#[target_feature(enable = "neon")]
72115#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72116#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72117#[cfg_attr(
72118 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72119 assert_instr(subhn)
72120)]
72121#[cfg_attr(
72122 not(target_arch = "arm"),
72123 stable(feature = "neon_intrinsics", since = "1.59.0")
72124)]
72125#[cfg_attr(
72126 target_arch = "arm",
72127 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72128)]
72129pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
72130 let c: i32x4 = i32x4::new(16, 16, 16, 16);
72131 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72132}
72133#[doc = "Subtract returning high narrow"]
72134#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"]
72135#[inline]
72136#[target_feature(enable = "neon")]
72137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72138#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72139#[cfg_attr(
72140 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72141 assert_instr(subhn)
72142)]
72143#[cfg_attr(
72144 not(target_arch = "arm"),
72145 stable(feature = "neon_intrinsics", since = "1.59.0")
72146)]
72147#[cfg_attr(
72148 target_arch = "arm",
72149 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72150)]
72151pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
72152 let c: i64x2 = i64x2::new(32, 32);
72153 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72154}
72155#[doc = "Subtract returning high narrow"]
72156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"]
72157#[inline]
72158#[target_feature(enable = "neon")]
72159#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72160#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72161#[cfg_attr(
72162 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72163 assert_instr(subhn)
72164)]
72165#[cfg_attr(
72166 not(target_arch = "arm"),
72167 stable(feature = "neon_intrinsics", since = "1.59.0")
72168)]
72169#[cfg_attr(
72170 target_arch = "arm",
72171 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72172)]
72173pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
72174 let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8);
72175 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72176}
72177#[doc = "Subtract returning high narrow"]
72178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"]
72179#[inline]
72180#[target_feature(enable = "neon")]
72181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72182#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72183#[cfg_attr(
72184 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72185 assert_instr(subhn)
72186)]
72187#[cfg_attr(
72188 not(target_arch = "arm"),
72189 stable(feature = "neon_intrinsics", since = "1.59.0")
72190)]
72191#[cfg_attr(
72192 target_arch = "arm",
72193 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72194)]
72195pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
72196 let c: u32x4 = u32x4::new(16, 16, 16, 16);
72197 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72198}
72199#[doc = "Subtract returning high narrow"]
72200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"]
72201#[inline]
72202#[target_feature(enable = "neon")]
72203#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72204#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
72205#[cfg_attr(
72206 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72207 assert_instr(subhn)
72208)]
72209#[cfg_attr(
72210 not(target_arch = "arm"),
72211 stable(feature = "neon_intrinsics", since = "1.59.0")
72212)]
72213#[cfg_attr(
72214 target_arch = "arm",
72215 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72216)]
72217pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
72218 let c: u64x2 = u64x2::new(32, 32);
72219 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
72220}
72221#[doc = "Signed Subtract Long"]
72222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"]
72223#[inline]
72224#[target_feature(enable = "neon")]
72225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72226#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72227#[cfg_attr(
72228 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72229 assert_instr(ssubl)
72230)]
72231#[cfg_attr(
72232 not(target_arch = "arm"),
72233 stable(feature = "neon_intrinsics", since = "1.59.0")
72234)]
72235#[cfg_attr(
72236 target_arch = "arm",
72237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72238)]
72239pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
72240 unsafe {
72241 let c: int16x8_t = simd_cast(a);
72242 let d: int16x8_t = simd_cast(b);
72243 simd_sub(c, d)
72244 }
72245}
72246#[doc = "Signed Subtract Long"]
72247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"]
72248#[inline]
72249#[target_feature(enable = "neon")]
72250#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72251#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72252#[cfg_attr(
72253 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72254 assert_instr(ssubl)
72255)]
72256#[cfg_attr(
72257 not(target_arch = "arm"),
72258 stable(feature = "neon_intrinsics", since = "1.59.0")
72259)]
72260#[cfg_attr(
72261 target_arch = "arm",
72262 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72263)]
72264pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
72265 unsafe {
72266 let c: int32x4_t = simd_cast(a);
72267 let d: int32x4_t = simd_cast(b);
72268 simd_sub(c, d)
72269 }
72270}
72271#[doc = "Signed Subtract Long"]
72272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"]
72273#[inline]
72274#[target_feature(enable = "neon")]
72275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72276#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72277#[cfg_attr(
72278 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72279 assert_instr(ssubl)
72280)]
72281#[cfg_attr(
72282 not(target_arch = "arm"),
72283 stable(feature = "neon_intrinsics", since = "1.59.0")
72284)]
72285#[cfg_attr(
72286 target_arch = "arm",
72287 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72288)]
72289pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
72290 unsafe {
72291 let c: int64x2_t = simd_cast(a);
72292 let d: int64x2_t = simd_cast(b);
72293 simd_sub(c, d)
72294 }
72295}
72296#[doc = "Unsigned Subtract Long"]
72297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"]
72298#[inline]
72299#[target_feature(enable = "neon")]
72300#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72301#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72302#[cfg_attr(
72303 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72304 assert_instr(usubl)
72305)]
72306#[cfg_attr(
72307 not(target_arch = "arm"),
72308 stable(feature = "neon_intrinsics", since = "1.59.0")
72309)]
72310#[cfg_attr(
72311 target_arch = "arm",
72312 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72313)]
72314pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
72315 unsafe {
72316 let c: uint16x8_t = simd_cast(a);
72317 let d: uint16x8_t = simd_cast(b);
72318 simd_sub(c, d)
72319 }
72320}
72321#[doc = "Unsigned Subtract Long"]
72322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"]
72323#[inline]
72324#[target_feature(enable = "neon")]
72325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72327#[cfg_attr(
72328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72329 assert_instr(usubl)
72330)]
72331#[cfg_attr(
72332 not(target_arch = "arm"),
72333 stable(feature = "neon_intrinsics", since = "1.59.0")
72334)]
72335#[cfg_attr(
72336 target_arch = "arm",
72337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72338)]
72339pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
72340 unsafe {
72341 let c: uint32x4_t = simd_cast(a);
72342 let d: uint32x4_t = simd_cast(b);
72343 simd_sub(c, d)
72344 }
72345}
72346#[doc = "Unsigned Subtract Long"]
72347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"]
72348#[inline]
72349#[target_feature(enable = "neon")]
72350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72351#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
72352#[cfg_attr(
72353 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72354 assert_instr(usubl)
72355)]
72356#[cfg_attr(
72357 not(target_arch = "arm"),
72358 stable(feature = "neon_intrinsics", since = "1.59.0")
72359)]
72360#[cfg_attr(
72361 target_arch = "arm",
72362 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72363)]
72364pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
72365 unsafe {
72366 let c: uint64x2_t = simd_cast(a);
72367 let d: uint64x2_t = simd_cast(b);
72368 simd_sub(c, d)
72369 }
72370}
72371#[doc = "Signed Subtract Wide"]
72372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"]
72373#[inline]
72374#[target_feature(enable = "neon")]
72375#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72376#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72377#[cfg_attr(
72378 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72379 assert_instr(ssubw)
72380)]
72381#[cfg_attr(
72382 not(target_arch = "arm"),
72383 stable(feature = "neon_intrinsics", since = "1.59.0")
72384)]
72385#[cfg_attr(
72386 target_arch = "arm",
72387 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72388)]
72389pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
72390 unsafe { simd_sub(a, simd_cast(b)) }
72391}
72392#[doc = "Signed Subtract Wide"]
72393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"]
72394#[inline]
72395#[target_feature(enable = "neon")]
72396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72398#[cfg_attr(
72399 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72400 assert_instr(ssubw)
72401)]
72402#[cfg_attr(
72403 not(target_arch = "arm"),
72404 stable(feature = "neon_intrinsics", since = "1.59.0")
72405)]
72406#[cfg_attr(
72407 target_arch = "arm",
72408 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72409)]
72410pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
72411 unsafe { simd_sub(a, simd_cast(b)) }
72412}
72413#[doc = "Signed Subtract Wide"]
72414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"]
72415#[inline]
72416#[target_feature(enable = "neon")]
72417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72419#[cfg_attr(
72420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72421 assert_instr(ssubw)
72422)]
72423#[cfg_attr(
72424 not(target_arch = "arm"),
72425 stable(feature = "neon_intrinsics", since = "1.59.0")
72426)]
72427#[cfg_attr(
72428 target_arch = "arm",
72429 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72430)]
72431pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
72432 unsafe { simd_sub(a, simd_cast(b)) }
72433}
72434#[doc = "Unsigned Subtract Wide"]
72435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"]
72436#[inline]
72437#[target_feature(enable = "neon")]
72438#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72439#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72440#[cfg_attr(
72441 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72442 assert_instr(usubw)
72443)]
72444#[cfg_attr(
72445 not(target_arch = "arm"),
72446 stable(feature = "neon_intrinsics", since = "1.59.0")
72447)]
72448#[cfg_attr(
72449 target_arch = "arm",
72450 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72451)]
72452pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
72453 unsafe { simd_sub(a, simd_cast(b)) }
72454}
72455#[doc = "Unsigned Subtract Wide"]
72456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"]
72457#[inline]
72458#[target_feature(enable = "neon")]
72459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72461#[cfg_attr(
72462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72463 assert_instr(usubw)
72464)]
72465#[cfg_attr(
72466 not(target_arch = "arm"),
72467 stable(feature = "neon_intrinsics", since = "1.59.0")
72468)]
72469#[cfg_attr(
72470 target_arch = "arm",
72471 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72472)]
72473pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
72474 unsafe { simd_sub(a, simd_cast(b)) }
72475}
72476#[doc = "Unsigned Subtract Wide"]
72477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"]
72478#[inline]
72479#[target_feature(enable = "neon")]
72480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72482#[cfg_attr(
72483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72484 assert_instr(usubw)
72485)]
72486#[cfg_attr(
72487 not(target_arch = "arm"),
72488 stable(feature = "neon_intrinsics", since = "1.59.0")
72489)]
72490#[cfg_attr(
72491 target_arch = "arm",
72492 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72493)]
72494pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
72495 unsafe { simd_sub(a, simd_cast(b)) }
72496}
72497#[doc = "Dot product index form with signed and unsigned integers"]
72498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
72499#[inline]
72500#[target_feature(enable = "neon,i8mm")]
72501#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
72502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
72503#[cfg_attr(
72504 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72505 assert_instr(sudot, LANE = 0)
72506)]
72507#[rustc_legacy_const_generics(3)]
72508#[cfg_attr(
72509 not(target_arch = "arm"),
72510 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
72511)]
72512#[cfg_attr(
72513 target_arch = "arm",
72514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72515)]
72516pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
72517 static_assert_uimm_bits!(LANE, 1);
72518 unsafe {
72519 let c: uint32x2_t = transmute(c);
72520 let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
72521 vusdot_s32(a, transmute(c), b)
72522 }
72523}
72524#[doc = "Dot product index form with signed and unsigned integers"]
72525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
72526#[inline]
72527#[target_feature(enable = "neon,i8mm")]
72528#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
72529#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
72530#[cfg_attr(
72531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72532 assert_instr(sudot, LANE = 0)
72533)]
72534#[rustc_legacy_const_generics(3)]
72535#[cfg_attr(
72536 not(target_arch = "arm"),
72537 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
72538)]
72539#[cfg_attr(
72540 target_arch = "arm",
72541 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72542)]
72543pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
72544 static_assert_uimm_bits!(LANE, 1);
72545 unsafe {
72546 let c: uint32x2_t = transmute(c);
72547 let c: uint32x4_t =
72548 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
72549 vusdotq_s32(a, transmute(c), b)
72550 }
72551}
72552#[doc = "Table look-up"]
72553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"]
72554#[inline]
72555#[target_feature(enable = "neon")]
72556#[cfg(target_arch = "arm")]
72557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72558#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72559#[cfg_attr(test, assert_instr(vtbl))]
72560fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t {
72561 unsafe extern "unadjusted" {
72562 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl1")]
72563 fn _vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t;
72564 }
72565 unsafe { _vtbl1(a, b) }
72566}
72567#[doc = "Table look-up"]
72568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
72569#[inline]
72570#[target_feature(enable = "neon")]
72571#[cfg(target_arch = "arm")]
72572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72573#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72574#[cfg_attr(test, assert_instr(vtbl))]
72575pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
72576 vtbl1(a, b)
72577}
72578#[doc = "Table look-up"]
72579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
72580#[inline]
72581#[cfg(target_endian = "little")]
72582#[target_feature(enable = "neon")]
72583#[cfg(target_arch = "arm")]
72584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72585#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72586#[cfg_attr(test, assert_instr(vtbl))]
72587pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
72588 unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
72589}
72590#[doc = "Table look-up"]
72591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
72592#[inline]
72593#[cfg(target_endian = "big")]
72594#[target_feature(enable = "neon")]
72595#[cfg(target_arch = "arm")]
72596#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72597#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72598#[cfg_attr(test, assert_instr(vtbl))]
72599pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
72600 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72601 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72602 unsafe {
72603 let ret_val: uint8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
72604 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72605 }
72606}
72607#[doc = "Table look-up"]
72608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
72609#[inline]
72610#[cfg(target_endian = "little")]
72611#[target_feature(enable = "neon")]
72612#[cfg(target_arch = "arm")]
72613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72614#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72615#[cfg_attr(test, assert_instr(vtbl))]
72616pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
72617 unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
72618}
72619#[doc = "Table look-up"]
72620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
72621#[inline]
72622#[cfg(target_endian = "big")]
72623#[target_feature(enable = "neon")]
72624#[cfg(target_arch = "arm")]
72625#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72626#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72627#[cfg_attr(test, assert_instr(vtbl))]
72628pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
72629 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72630 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72631 unsafe {
72632 let ret_val: poly8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
72633 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72634 }
72635}
72636#[doc = "Table look-up"]
72637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"]
72638#[inline]
72639#[target_feature(enable = "neon")]
72640#[cfg(target_arch = "arm")]
72641#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72642#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72643#[cfg_attr(test, assert_instr(vtbl))]
72644fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72645 unsafe extern "unadjusted" {
72646 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl2")]
72647 fn _vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
72648 }
72649 unsafe { _vtbl2(a, b, c) }
72650}
72651#[doc = "Table look-up"]
72652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
72653#[inline]
72654#[target_feature(enable = "neon")]
72655#[cfg(target_arch = "arm")]
72656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72657#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72658#[cfg_attr(test, assert_instr(vtbl))]
72659pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
72660 vtbl2(a.0, a.1, b)
72661}
72662#[doc = "Table look-up"]
72663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
72664#[inline]
72665#[cfg(target_endian = "little")]
72666#[target_feature(enable = "neon")]
72667#[cfg(target_arch = "arm")]
72668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72669#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72670#[cfg_attr(test, assert_instr(vtbl))]
72671pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
72672 unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
72673}
72674#[doc = "Table look-up"]
72675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
72676#[inline]
72677#[cfg(target_endian = "big")]
72678#[target_feature(enable = "neon")]
72679#[cfg(target_arch = "arm")]
72680#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72681#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72682#[cfg_attr(test, assert_instr(vtbl))]
72683pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
72684 let mut a: uint8x8x2_t = a;
72685 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72686 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72687 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72688 unsafe {
72689 let ret_val: uint8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
72690 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72691 }
72692}
72693#[doc = "Table look-up"]
72694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
72695#[inline]
72696#[cfg(target_endian = "little")]
72697#[target_feature(enable = "neon")]
72698#[cfg(target_arch = "arm")]
72699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72700#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72701#[cfg_attr(test, assert_instr(vtbl))]
72702pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
72703 unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
72704}
72705#[doc = "Table look-up"]
72706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
72707#[inline]
72708#[cfg(target_endian = "big")]
72709#[target_feature(enable = "neon")]
72710#[cfg(target_arch = "arm")]
72711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72712#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72713#[cfg_attr(test, assert_instr(vtbl))]
72714pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
72715 let mut a: poly8x8x2_t = a;
72716 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72717 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72718 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72719 unsafe {
72720 let ret_val: poly8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
72721 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72722 }
72723}
72724#[doc = "Table look-up"]
72725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"]
72726#[inline]
72727#[target_feature(enable = "neon")]
72728#[cfg(target_arch = "arm")]
72729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72730#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72731#[cfg_attr(test, assert_instr(vtbl))]
72732fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
72733 unsafe extern "unadjusted" {
72734 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl3")]
72735 fn _vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
72736 }
72737 unsafe { _vtbl3(a, b, c, d) }
72738}
72739#[doc = "Table look-up"]
72740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
72741#[inline]
72742#[target_feature(enable = "neon")]
72743#[cfg(target_arch = "arm")]
72744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72745#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72746#[cfg_attr(test, assert_instr(vtbl))]
72747pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
72748 vtbl3(a.0, a.1, a.2, b)
72749}
72750#[doc = "Table look-up"]
72751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
72752#[inline]
72753#[cfg(target_endian = "little")]
72754#[target_feature(enable = "neon")]
72755#[cfg(target_arch = "arm")]
72756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72757#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72758#[cfg_attr(test, assert_instr(vtbl))]
72759pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
72760 unsafe {
72761 transmute(vtbl3(
72762 transmute(a.0),
72763 transmute(a.1),
72764 transmute(a.2),
72765 transmute(b),
72766 ))
72767 }
72768}
72769#[doc = "Table look-up"]
72770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
72771#[inline]
72772#[cfg(target_endian = "big")]
72773#[target_feature(enable = "neon")]
72774#[cfg(target_arch = "arm")]
72775#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72776#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72777#[cfg_attr(test, assert_instr(vtbl))]
72778pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
72779 let mut a: uint8x8x3_t = a;
72780 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72781 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72782 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72783 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72784 unsafe {
72785 let ret_val: uint8x8_t = transmute(vtbl3(
72786 transmute(a.0),
72787 transmute(a.1),
72788 transmute(a.2),
72789 transmute(b),
72790 ));
72791 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72792 }
72793}
72794#[doc = "Table look-up"]
72795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
72796#[inline]
72797#[cfg(target_endian = "little")]
72798#[target_feature(enable = "neon")]
72799#[cfg(target_arch = "arm")]
72800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72801#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72802#[cfg_attr(test, assert_instr(vtbl))]
72803pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
72804 unsafe {
72805 transmute(vtbl3(
72806 transmute(a.0),
72807 transmute(a.1),
72808 transmute(a.2),
72809 transmute(b),
72810 ))
72811 }
72812}
72813#[doc = "Table look-up"]
72814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
72815#[inline]
72816#[cfg(target_endian = "big")]
72817#[target_feature(enable = "neon")]
72818#[cfg(target_arch = "arm")]
72819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72820#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72821#[cfg_attr(test, assert_instr(vtbl))]
72822pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
72823 let mut a: poly8x8x3_t = a;
72824 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72825 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72826 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72827 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72828 unsafe {
72829 let ret_val: poly8x8_t = transmute(vtbl3(
72830 transmute(a.0),
72831 transmute(a.1),
72832 transmute(a.2),
72833 transmute(b),
72834 ));
72835 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72836 }
72837}
72838#[doc = "Table look-up"]
72839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"]
72840#[inline]
72841#[target_feature(enable = "neon")]
72842#[cfg(target_arch = "arm")]
72843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72844#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72845#[cfg_attr(test, assert_instr(vtbl))]
72846fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t {
72847 unsafe extern "unadjusted" {
72848 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl4")]
72849 fn _vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t;
72850 }
72851 unsafe { _vtbl4(a, b, c, d, e) }
72852}
72853#[doc = "Table look-up"]
72854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
72855#[inline]
72856#[target_feature(enable = "neon")]
72857#[cfg(target_arch = "arm")]
72858#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72859#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72860#[cfg_attr(test, assert_instr(vtbl))]
72861pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
72862 vtbl4(a.0, a.1, a.2, a.3, b)
72863}
72864#[doc = "Table look-up"]
72865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
72866#[inline]
72867#[cfg(target_endian = "little")]
72868#[target_feature(enable = "neon")]
72869#[cfg(target_arch = "arm")]
72870#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72871#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72872#[cfg_attr(test, assert_instr(vtbl))]
72873pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
72874 unsafe {
72875 transmute(vtbl4(
72876 transmute(a.0),
72877 transmute(a.1),
72878 transmute(a.2),
72879 transmute(a.3),
72880 transmute(b),
72881 ))
72882 }
72883}
72884#[doc = "Table look-up"]
72885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
72886#[inline]
72887#[cfg(target_endian = "big")]
72888#[target_feature(enable = "neon")]
72889#[cfg(target_arch = "arm")]
72890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72891#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72892#[cfg_attr(test, assert_instr(vtbl))]
72893pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
72894 let mut a: uint8x8x4_t = a;
72895 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72896 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72897 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72898 a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
72899 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72900 unsafe {
72901 let ret_val: uint8x8_t = transmute(vtbl4(
72902 transmute(a.0),
72903 transmute(a.1),
72904 transmute(a.2),
72905 transmute(a.3),
72906 transmute(b),
72907 ));
72908 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72909 }
72910}
72911#[doc = "Table look-up"]
72912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
72913#[inline]
72914#[cfg(target_endian = "little")]
72915#[target_feature(enable = "neon")]
72916#[cfg(target_arch = "arm")]
72917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72918#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72919#[cfg_attr(test, assert_instr(vtbl))]
72920pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
72921 unsafe {
72922 transmute(vtbl4(
72923 transmute(a.0),
72924 transmute(a.1),
72925 transmute(a.2),
72926 transmute(a.3),
72927 transmute(b),
72928 ))
72929 }
72930}
72931#[doc = "Table look-up"]
72932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
72933#[inline]
72934#[cfg(target_endian = "big")]
72935#[target_feature(enable = "neon")]
72936#[cfg(target_arch = "arm")]
72937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72938#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72939#[cfg_attr(test, assert_instr(vtbl))]
72940pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
72941 let mut a: poly8x8x4_t = a;
72942 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72943 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72944 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72945 a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
72946 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72947 unsafe {
72948 let ret_val: poly8x8_t = transmute(vtbl4(
72949 transmute(a.0),
72950 transmute(a.1),
72951 transmute(a.2),
72952 transmute(a.3),
72953 transmute(b),
72954 ));
72955 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72956 }
72957}
72958#[doc = "Extended table look-up"]
72959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"]
72960#[inline]
72961#[target_feature(enable = "neon,v7")]
72962#[cfg(target_arch = "arm")]
72963#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72964#[cfg_attr(test, assert_instr(vtbx))]
72965fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72966 unsafe extern "unadjusted" {
72967 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx1")]
72968 fn _vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
72969 }
72970 unsafe { _vtbx1(a, b, c) }
72971}
72972#[doc = "Extended table look-up"]
72973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
72974#[inline]
72975#[target_feature(enable = "neon,v7")]
72976#[cfg(target_arch = "arm")]
72977#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72978#[cfg_attr(test, assert_instr(vtbx))]
72979pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72980 vtbx1(a, b, c)
72981}
72982#[doc = "Extended table look-up"]
72983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
72984#[inline]
72985#[cfg(target_endian = "little")]
72986#[target_feature(enable = "neon,v7")]
72987#[cfg(target_arch = "arm")]
72988#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72989#[cfg_attr(test, assert_instr(vtbx))]
72990pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
72991 unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
72992}
72993#[doc = "Extended table look-up"]
72994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
72995#[inline]
72996#[cfg(target_endian = "big")]
72997#[target_feature(enable = "neon,v7")]
72998#[cfg(target_arch = "arm")]
72999#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73000#[cfg_attr(test, assert_instr(vtbx))]
73001pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
73002 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73003 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
73004 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73005 unsafe {
73006 let ret_val: uint8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
73007 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73008 }
73009}
73010#[doc = "Extended table look-up"]
73011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
73012#[inline]
73013#[cfg(target_endian = "little")]
73014#[target_feature(enable = "neon,v7")]
73015#[cfg(target_arch = "arm")]
73016#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73017#[cfg_attr(test, assert_instr(vtbx))]
73018pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
73019 unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
73020}
73021#[doc = "Extended table look-up"]
73022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
73023#[inline]
73024#[cfg(target_endian = "big")]
73025#[target_feature(enable = "neon,v7")]
73026#[cfg(target_arch = "arm")]
73027#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73028#[cfg_attr(test, assert_instr(vtbx))]
73029pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
73030 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73031 let b: poly8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
73032 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73033 unsafe {
73034 let ret_val: poly8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
73035 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73036 }
73037}
73038#[doc = "Extended table look-up"]
73039#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"]
73040#[inline]
73041#[target_feature(enable = "neon,v7")]
73042#[cfg(target_arch = "arm")]
73043#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73044#[cfg_attr(test, assert_instr(vtbx))]
73045fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
73046 unsafe extern "unadjusted" {
73047 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx2")]
73048 fn _vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
73049 }
73050 unsafe { _vtbx2(a, b, c, d) }
73051}
73052#[doc = "Extended table look-up"]
73053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
73054#[inline]
73055#[target_feature(enable = "neon,v7")]
73056#[cfg(target_arch = "arm")]
73057#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73058#[cfg_attr(test, assert_instr(vtbx))]
73059pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
73060 vtbx2(a, b.0, b.1, c)
73061}
73062#[doc = "Extended table look-up"]
73063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
73064#[inline]
73065#[cfg(target_endian = "little")]
73066#[target_feature(enable = "neon,v7")]
73067#[cfg(target_arch = "arm")]
73068#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73069#[cfg_attr(test, assert_instr(vtbx))]
73070pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
73071 unsafe {
73072 transmute(vtbx2(
73073 transmute(a),
73074 transmute(b.0),
73075 transmute(b.1),
73076 transmute(c),
73077 ))
73078 }
73079}
73080#[doc = "Extended table look-up"]
73081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
73082#[inline]
73083#[cfg(target_endian = "big")]
73084#[target_feature(enable = "neon,v7")]
73085#[cfg(target_arch = "arm")]
73086#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73087#[cfg_attr(test, assert_instr(vtbx))]
73088pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
73089 let mut b: uint8x8x2_t = b;
73090 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73091 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73092 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73093 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73094 unsafe {
73095 let ret_val: uint8x8_t = transmute(vtbx2(
73096 transmute(a),
73097 transmute(b.0),
73098 transmute(b.1),
73099 transmute(c),
73100 ));
73101 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73102 }
73103}
73104#[doc = "Extended table look-up"]
73105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
73106#[inline]
73107#[cfg(target_endian = "little")]
73108#[target_feature(enable = "neon,v7")]
73109#[cfg(target_arch = "arm")]
73110#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73111#[cfg_attr(test, assert_instr(vtbx))]
73112pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
73113 unsafe {
73114 transmute(vtbx2(
73115 transmute(a),
73116 transmute(b.0),
73117 transmute(b.1),
73118 transmute(c),
73119 ))
73120 }
73121}
73122#[doc = "Extended table look-up"]
73123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
73124#[inline]
73125#[cfg(target_endian = "big")]
73126#[target_feature(enable = "neon,v7")]
73127#[cfg(target_arch = "arm")]
73128#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73129#[cfg_attr(test, assert_instr(vtbx))]
73130pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
73131 let mut b: poly8x8x2_t = b;
73132 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73133 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73134 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73135 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73136 unsafe {
73137 let ret_val: poly8x8_t = transmute(vtbx2(
73138 transmute(a),
73139 transmute(b.0),
73140 transmute(b.1),
73141 transmute(c),
73142 ));
73143 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73144 }
73145}
73146#[doc = "Extended table look-up"]
73147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"]
73148#[inline]
73149#[target_feature(enable = "neon,v7")]
73150#[cfg(target_arch = "arm")]
73151#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73152#[cfg_attr(test, assert_instr(vtbx))]
73153fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t {
73154 unsafe extern "unadjusted" {
73155 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx3")]
73156 fn _vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t;
73157 }
73158 unsafe { _vtbx3(a, b, c, d, e) }
73159}
73160#[doc = "Extended table look-up"]
73161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
73162#[inline]
73163#[target_feature(enable = "neon,v7")]
73164#[cfg(target_arch = "arm")]
73165#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73166#[cfg_attr(test, assert_instr(vtbx))]
73167pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
73168 vtbx3(a, b.0, b.1, b.2, c)
73169}
73170#[doc = "Extended table look-up"]
73171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
73172#[inline]
73173#[cfg(target_endian = "little")]
73174#[target_feature(enable = "neon,v7")]
73175#[cfg(target_arch = "arm")]
73176#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73177#[cfg_attr(test, assert_instr(vtbx))]
73178pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
73179 unsafe {
73180 transmute(vtbx3(
73181 transmute(a),
73182 transmute(b.0),
73183 transmute(b.1),
73184 transmute(b.2),
73185 transmute(c),
73186 ))
73187 }
73188}
73189#[doc = "Extended table look-up"]
73190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
73191#[inline]
73192#[cfg(target_endian = "big")]
73193#[target_feature(enable = "neon,v7")]
73194#[cfg(target_arch = "arm")]
73195#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73196#[cfg_attr(test, assert_instr(vtbx))]
73197pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
73198 let mut b: uint8x8x3_t = b;
73199 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73200 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73201 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73202 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73203 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73204 unsafe {
73205 let ret_val: uint8x8_t = transmute(vtbx3(
73206 transmute(a),
73207 transmute(b.0),
73208 transmute(b.1),
73209 transmute(b.2),
73210 transmute(c),
73211 ));
73212 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73213 }
73214}
73215#[doc = "Extended table look-up"]
73216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
73217#[inline]
73218#[cfg(target_endian = "little")]
73219#[target_feature(enable = "neon,v7")]
73220#[cfg(target_arch = "arm")]
73221#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73222#[cfg_attr(test, assert_instr(vtbx))]
73223pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
73224 unsafe {
73225 transmute(vtbx3(
73226 transmute(a),
73227 transmute(b.0),
73228 transmute(b.1),
73229 transmute(b.2),
73230 transmute(c),
73231 ))
73232 }
73233}
73234#[doc = "Extended table look-up"]
73235#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
73236#[inline]
73237#[cfg(target_endian = "big")]
73238#[target_feature(enable = "neon,v7")]
73239#[cfg(target_arch = "arm")]
73240#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73241#[cfg_attr(test, assert_instr(vtbx))]
73242pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
73243 let mut b: poly8x8x3_t = b;
73244 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73245 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73246 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73247 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73248 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73249 unsafe {
73250 let ret_val: poly8x8_t = transmute(vtbx3(
73251 transmute(a),
73252 transmute(b.0),
73253 transmute(b.1),
73254 transmute(b.2),
73255 transmute(c),
73256 ));
73257 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73258 }
73259}
73260#[doc = "Extended table look-up"]
73261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"]
73262#[inline]
73263#[target_feature(enable = "neon,v7")]
73264#[cfg(target_arch = "arm")]
73265#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73266#[cfg_attr(test, assert_instr(vtbx))]
73267fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int8x8_t) -> int8x8_t {
73268 unsafe extern "unadjusted" {
73269 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx4")]
73270 fn _vtbx4(
73271 a: int8x8_t,
73272 b: int8x8_t,
73273 c: int8x8_t,
73274 d: int8x8_t,
73275 e: int8x8_t,
73276 f: int8x8_t,
73277 ) -> int8x8_t;
73278 }
73279 unsafe { _vtbx4(a, b, c, d, e, f) }
73280}
73281#[doc = "Extended table look-up"]
73282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
73283#[inline]
73284#[cfg(target_endian = "little")]
73285#[target_feature(enable = "neon,v7")]
73286#[cfg(target_arch = "arm")]
73287#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73288#[cfg_attr(test, assert_instr(vtbx))]
73289pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
73290 unsafe {
73291 vtbx4(
73292 a,
73293 transmute(b.0),
73294 transmute(b.1),
73295 transmute(b.2),
73296 transmute(b.3),
73297 c,
73298 )
73299 }
73300}
73301#[doc = "Extended table look-up"]
73302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
73303#[inline]
73304#[cfg(target_endian = "big")]
73305#[target_feature(enable = "neon,v7")]
73306#[cfg(target_arch = "arm")]
73307#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73308#[cfg_attr(test, assert_instr(vtbx))]
73309pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
73310 let mut b: int8x8x4_t = b;
73311 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73312 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73313 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73314 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73315 b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
73316 let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73317 unsafe {
73318 let ret_val: int8x8_t = vtbx4(
73319 a,
73320 transmute(b.0),
73321 transmute(b.1),
73322 transmute(b.2),
73323 transmute(b.3),
73324 c,
73325 );
73326 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73327 }
73328}
73329#[doc = "Extended table look-up"]
73330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
73331#[inline]
73332#[cfg(target_endian = "little")]
73333#[target_feature(enable = "neon,v7")]
73334#[cfg(target_arch = "arm")]
73335#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73336#[cfg_attr(test, assert_instr(vtbx))]
73337pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
73338 unsafe {
73339 transmute(vtbx4(
73340 transmute(a),
73341 transmute(b.0),
73342 transmute(b.1),
73343 transmute(b.2),
73344 transmute(b.3),
73345 transmute(c),
73346 ))
73347 }
73348}
73349#[doc = "Extended table look-up"]
73350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
73351#[inline]
73352#[cfg(target_endian = "big")]
73353#[target_feature(enable = "neon,v7")]
73354#[cfg(target_arch = "arm")]
73355#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73356#[cfg_attr(test, assert_instr(vtbx))]
73357pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
73358 let mut b: uint8x8x4_t = b;
73359 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73360 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73361 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73362 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73363 b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
73364 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73365 unsafe {
73366 let ret_val: uint8x8_t = transmute(vtbx4(
73367 transmute(a),
73368 transmute(b.0),
73369 transmute(b.1),
73370 transmute(b.2),
73371 transmute(b.3),
73372 transmute(c),
73373 ));
73374 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73375 }
73376}
73377#[doc = "Extended table look-up"]
73378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
73379#[inline]
73380#[cfg(target_endian = "little")]
73381#[target_feature(enable = "neon,v7")]
73382#[cfg(target_arch = "arm")]
73383#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73384#[cfg_attr(test, assert_instr(vtbx))]
73385pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
73386 unsafe {
73387 transmute(vtbx4(
73388 transmute(a),
73389 transmute(b.0),
73390 transmute(b.1),
73391 transmute(b.2),
73392 transmute(b.3),
73393 transmute(c),
73394 ))
73395 }
73396}
73397#[doc = "Extended table look-up"]
73398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
73399#[inline]
73400#[cfg(target_endian = "big")]
73401#[target_feature(enable = "neon,v7")]
73402#[cfg(target_arch = "arm")]
73403#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
73404#[cfg_attr(test, assert_instr(vtbx))]
73405pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
73406 let mut b: poly8x8x4_t = b;
73407 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
73408 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
73409 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
73410 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
73411 b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
73412 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
73413 unsafe {
73414 let ret_val: poly8x8_t = transmute(vtbx4(
73415 transmute(a),
73416 transmute(b.0),
73417 transmute(b.1),
73418 transmute(b.2),
73419 transmute(b.3),
73420 transmute(c),
73421 ));
73422 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
73423 }
73424}
73425#[doc = "Transpose elements"]
73426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"]
73427#[inline]
73428#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73429#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73430#[cfg_attr(
73431 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73432 assert_instr(trn)
73433)]
73434#[target_feature(enable = "neon,fp16")]
73435#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
73436pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
73437 unsafe {
73438 let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73439 let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73440 transmute((a1, b1))
73441 }
73442}
73443#[doc = "Transpose elements"]
73444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"]
73445#[inline]
73446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73447#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73448#[cfg_attr(
73449 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73450 assert_instr(trn)
73451)]
73452#[target_feature(enable = "neon,fp16")]
73453#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
73454pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
73455 unsafe {
73456 let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73457 let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73458 transmute((a1, b1))
73459 }
73460}
73461#[doc = "Transpose elements"]
73462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"]
73463#[inline]
73464#[target_feature(enable = "neon")]
73465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73467#[cfg_attr(
73468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73469 assert_instr(zip)
73470)]
73471#[cfg_attr(
73472 not(target_arch = "arm"),
73473 stable(feature = "neon_intrinsics", since = "1.59.0")
73474)]
73475#[cfg_attr(
73476 target_arch = "arm",
73477 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73478)]
73479pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
73480 unsafe {
73481 let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]);
73482 let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]);
73483 transmute((a1, b1))
73484 }
73485}
73486#[doc = "Transpose elements"]
73487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"]
73488#[inline]
73489#[target_feature(enable = "neon")]
73490#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73491#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73492#[cfg_attr(
73493 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73494 assert_instr(zip)
73495)]
73496#[cfg_attr(
73497 not(target_arch = "arm"),
73498 stable(feature = "neon_intrinsics", since = "1.59.0")
73499)]
73500#[cfg_attr(
73501 target_arch = "arm",
73502 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73503)]
73504pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
73505 unsafe {
73506 let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]);
73507 let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]);
73508 transmute((a1, b1))
73509 }
73510}
73511#[doc = "Transpose elements"]
73512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"]
73513#[inline]
73514#[target_feature(enable = "neon")]
73515#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73516#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73517#[cfg_attr(
73518 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73519 assert_instr(zip)
73520)]
73521#[cfg_attr(
73522 not(target_arch = "arm"),
73523 stable(feature = "neon_intrinsics", since = "1.59.0")
73524)]
73525#[cfg_attr(
73526 target_arch = "arm",
73527 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73528)]
73529pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
73530 unsafe {
73531 let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
73532 let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
73533 transmute((a1, b1))
73534 }
73535}
73536#[doc = "Transpose elements"]
73537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"]
73538#[inline]
73539#[target_feature(enable = "neon")]
73540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73541#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73542#[cfg_attr(
73543 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73544 assert_instr(trn)
73545)]
73546#[cfg_attr(
73547 not(target_arch = "arm"),
73548 stable(feature = "neon_intrinsics", since = "1.59.0")
73549)]
73550#[cfg_attr(
73551 target_arch = "arm",
73552 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73553)]
73554pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
73555 unsafe {
73556 let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73557 let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73558 transmute((a1, b1))
73559 }
73560}
73561#[doc = "Transpose elements"]
73562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"]
73563#[inline]
73564#[target_feature(enable = "neon")]
73565#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73566#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73567#[cfg_attr(
73568 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73569 assert_instr(trn)
73570)]
73571#[cfg_attr(
73572 not(target_arch = "arm"),
73573 stable(feature = "neon_intrinsics", since = "1.59.0")
73574)]
73575#[cfg_attr(
73576 target_arch = "arm",
73577 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73578)]
73579pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
73580 unsafe {
73581 let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73582 let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73583 transmute((a1, b1))
73584 }
73585}
73586#[doc = "Transpose elements"]
73587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"]
73588#[inline]
73589#[target_feature(enable = "neon")]
73590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73591#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73592#[cfg_attr(
73593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73594 assert_instr(trn)
73595)]
73596#[cfg_attr(
73597 not(target_arch = "arm"),
73598 stable(feature = "neon_intrinsics", since = "1.59.0")
73599)]
73600#[cfg_attr(
73601 target_arch = "arm",
73602 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73603)]
73604pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
73605 unsafe {
73606 let a1: int8x16_t = simd_shuffle!(
73607 a,
73608 b,
73609 [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73610 );
73611 let b1: int8x16_t = simd_shuffle!(
73612 a,
73613 b,
73614 [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73615 );
73616 transmute((a1, b1))
73617 }
73618}
73619#[doc = "Transpose elements"]
73620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"]
73621#[inline]
73622#[target_feature(enable = "neon")]
73623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73624#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73625#[cfg_attr(
73626 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73627 assert_instr(trn)
73628)]
73629#[cfg_attr(
73630 not(target_arch = "arm"),
73631 stable(feature = "neon_intrinsics", since = "1.59.0")
73632)]
73633#[cfg_attr(
73634 target_arch = "arm",
73635 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73636)]
73637pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
73638 unsafe {
73639 let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73640 let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73641 transmute((a1, b1))
73642 }
73643}
73644#[doc = "Transpose elements"]
73645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"]
73646#[inline]
73647#[target_feature(enable = "neon")]
73648#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73649#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73650#[cfg_attr(
73651 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73652 assert_instr(trn)
73653)]
73654#[cfg_attr(
73655 not(target_arch = "arm"),
73656 stable(feature = "neon_intrinsics", since = "1.59.0")
73657)]
73658#[cfg_attr(
73659 target_arch = "arm",
73660 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73661)]
73662pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
73663 unsafe {
73664 let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73665 let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73666 transmute((a1, b1))
73667 }
73668}
73669#[doc = "Transpose elements"]
73670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"]
73671#[inline]
73672#[target_feature(enable = "neon")]
73673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73674#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73675#[cfg_attr(
73676 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73677 assert_instr(trn)
73678)]
73679#[cfg_attr(
73680 not(target_arch = "arm"),
73681 stable(feature = "neon_intrinsics", since = "1.59.0")
73682)]
73683#[cfg_attr(
73684 target_arch = "arm",
73685 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73686)]
73687pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
73688 unsafe {
73689 let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73690 let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73691 transmute((a1, b1))
73692 }
73693}
73694#[doc = "Transpose elements"]
73695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"]
73696#[inline]
73697#[target_feature(enable = "neon")]
73698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73699#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73700#[cfg_attr(
73701 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73702 assert_instr(trn)
73703)]
73704#[cfg_attr(
73705 not(target_arch = "arm"),
73706 stable(feature = "neon_intrinsics", since = "1.59.0")
73707)]
73708#[cfg_attr(
73709 target_arch = "arm",
73710 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73711)]
73712pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
73713 unsafe {
73714 let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73715 let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73716 transmute((a1, b1))
73717 }
73718}
73719#[doc = "Transpose elements"]
73720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"]
73721#[inline]
73722#[target_feature(enable = "neon")]
73723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73724#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73725#[cfg_attr(
73726 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73727 assert_instr(trn)
73728)]
73729#[cfg_attr(
73730 not(target_arch = "arm"),
73731 stable(feature = "neon_intrinsics", since = "1.59.0")
73732)]
73733#[cfg_attr(
73734 target_arch = "arm",
73735 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73736)]
73737pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
73738 unsafe {
73739 let a1: uint8x16_t = simd_shuffle!(
73740 a,
73741 b,
73742 [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73743 );
73744 let b1: uint8x16_t = simd_shuffle!(
73745 a,
73746 b,
73747 [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73748 );
73749 transmute((a1, b1))
73750 }
73751}
73752#[doc = "Transpose elements"]
73753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"]
73754#[inline]
73755#[target_feature(enable = "neon")]
73756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73758#[cfg_attr(
73759 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73760 assert_instr(trn)
73761)]
73762#[cfg_attr(
73763 not(target_arch = "arm"),
73764 stable(feature = "neon_intrinsics", since = "1.59.0")
73765)]
73766#[cfg_attr(
73767 target_arch = "arm",
73768 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73769)]
73770pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
73771 unsafe {
73772 let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73773 let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73774 transmute((a1, b1))
73775 }
73776}
73777#[doc = "Transpose elements"]
73778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"]
73779#[inline]
73780#[target_feature(enable = "neon")]
73781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73783#[cfg_attr(
73784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73785 assert_instr(trn)
73786)]
73787#[cfg_attr(
73788 not(target_arch = "arm"),
73789 stable(feature = "neon_intrinsics", since = "1.59.0")
73790)]
73791#[cfg_attr(
73792 target_arch = "arm",
73793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73794)]
73795pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
73796 unsafe {
73797 let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73798 let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73799 transmute((a1, b1))
73800 }
73801}
73802#[doc = "Transpose elements"]
73803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"]
73804#[inline]
73805#[target_feature(enable = "neon")]
73806#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73807#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73808#[cfg_attr(
73809 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73810 assert_instr(trn)
73811)]
73812#[cfg_attr(
73813 not(target_arch = "arm"),
73814 stable(feature = "neon_intrinsics", since = "1.59.0")
73815)]
73816#[cfg_attr(
73817 target_arch = "arm",
73818 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73819)]
73820pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
73821 unsafe {
73822 let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73823 let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73824 transmute((a1, b1))
73825 }
73826}
73827#[doc = "Transpose elements"]
73828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"]
73829#[inline]
73830#[target_feature(enable = "neon")]
73831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73832#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73833#[cfg_attr(
73834 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73835 assert_instr(trn)
73836)]
73837#[cfg_attr(
73838 not(target_arch = "arm"),
73839 stable(feature = "neon_intrinsics", since = "1.59.0")
73840)]
73841#[cfg_attr(
73842 target_arch = "arm",
73843 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73844)]
73845pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
73846 unsafe {
73847 let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73848 let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73849 transmute((a1, b1))
73850 }
73851}
73852#[doc = "Transpose elements"]
73853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"]
73854#[inline]
73855#[target_feature(enable = "neon")]
73856#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73857#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73858#[cfg_attr(
73859 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73860 assert_instr(trn)
73861)]
73862#[cfg_attr(
73863 not(target_arch = "arm"),
73864 stable(feature = "neon_intrinsics", since = "1.59.0")
73865)]
73866#[cfg_attr(
73867 target_arch = "arm",
73868 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73869)]
73870pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
73871 unsafe {
73872 let a1: poly8x16_t = simd_shuffle!(
73873 a,
73874 b,
73875 [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73876 );
73877 let b1: poly8x16_t = simd_shuffle!(
73878 a,
73879 b,
73880 [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73881 );
73882 transmute((a1, b1))
73883 }
73884}
73885#[doc = "Transpose elements"]
73886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"]
73887#[inline]
73888#[target_feature(enable = "neon")]
73889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73890#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73891#[cfg_attr(
73892 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73893 assert_instr(trn)
73894)]
73895#[cfg_attr(
73896 not(target_arch = "arm"),
73897 stable(feature = "neon_intrinsics", since = "1.59.0")
73898)]
73899#[cfg_attr(
73900 target_arch = "arm",
73901 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73902)]
73903pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
73904 unsafe {
73905 let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73906 let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73907 transmute((a1, b1))
73908 }
73909}
73910#[doc = "Transpose elements"]
73911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"]
73912#[inline]
73913#[target_feature(enable = "neon")]
73914#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73915#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73916#[cfg_attr(
73917 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73918 assert_instr(trn)
73919)]
73920#[cfg_attr(
73921 not(target_arch = "arm"),
73922 stable(feature = "neon_intrinsics", since = "1.59.0")
73923)]
73924#[cfg_attr(
73925 target_arch = "arm",
73926 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73927)]
73928pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
73929 unsafe {
73930 let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73931 let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73932 transmute((a1, b1))
73933 }
73934}
73935#[doc = "Signed compare bitwise Test bits nonzero"]
73936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"]
73937#[inline]
73938#[target_feature(enable = "neon")]
73939#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73940#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73941#[cfg_attr(
73942 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73943 assert_instr(cmtst)
73944)]
73945#[cfg_attr(
73946 not(target_arch = "arm"),
73947 stable(feature = "neon_intrinsics", since = "1.59.0")
73948)]
73949#[cfg_attr(
73950 target_arch = "arm",
73951 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73952)]
73953pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
73954 unsafe {
73955 let c: int8x8_t = simd_and(a, b);
73956 let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
73957 simd_ne(c, transmute(d))
73958 }
73959}
73960#[doc = "Signed compare bitwise Test bits nonzero"]
73961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"]
73962#[inline]
73963#[target_feature(enable = "neon")]
73964#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73965#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73966#[cfg_attr(
73967 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73968 assert_instr(cmtst)
73969)]
73970#[cfg_attr(
73971 not(target_arch = "arm"),
73972 stable(feature = "neon_intrinsics", since = "1.59.0")
73973)]
73974#[cfg_attr(
73975 target_arch = "arm",
73976 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73977)]
73978pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
73979 unsafe {
73980 let c: int8x16_t = simd_and(a, b);
73981 let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
73982 simd_ne(c, transmute(d))
73983 }
73984}
73985#[doc = "Signed compare bitwise Test bits nonzero"]
73986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"]
73987#[inline]
73988#[target_feature(enable = "neon")]
73989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73991#[cfg_attr(
73992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73993 assert_instr(cmtst)
73994)]
73995#[cfg_attr(
73996 not(target_arch = "arm"),
73997 stable(feature = "neon_intrinsics", since = "1.59.0")
73998)]
73999#[cfg_attr(
74000 target_arch = "arm",
74001 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74002)]
74003pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
74004 unsafe {
74005 let c: int16x4_t = simd_and(a, b);
74006 let d: i16x4 = i16x4::new(0, 0, 0, 0);
74007 simd_ne(c, transmute(d))
74008 }
74009}
74010#[doc = "Signed compare bitwise Test bits nonzero"]
74011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"]
74012#[inline]
74013#[target_feature(enable = "neon")]
74014#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74015#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74016#[cfg_attr(
74017 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74018 assert_instr(cmtst)
74019)]
74020#[cfg_attr(
74021 not(target_arch = "arm"),
74022 stable(feature = "neon_intrinsics", since = "1.59.0")
74023)]
74024#[cfg_attr(
74025 target_arch = "arm",
74026 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74027)]
74028pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
74029 unsafe {
74030 let c: int16x8_t = simd_and(a, b);
74031 let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74032 simd_ne(c, transmute(d))
74033 }
74034}
74035#[doc = "Signed compare bitwise Test bits nonzero"]
74036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"]
74037#[inline]
74038#[target_feature(enable = "neon")]
74039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74041#[cfg_attr(
74042 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74043 assert_instr(cmtst)
74044)]
74045#[cfg_attr(
74046 not(target_arch = "arm"),
74047 stable(feature = "neon_intrinsics", since = "1.59.0")
74048)]
74049#[cfg_attr(
74050 target_arch = "arm",
74051 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74052)]
74053pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
74054 unsafe {
74055 let c: int32x2_t = simd_and(a, b);
74056 let d: i32x2 = i32x2::new(0, 0);
74057 simd_ne(c, transmute(d))
74058 }
74059}
74060#[doc = "Signed compare bitwise Test bits nonzero"]
74061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"]
74062#[inline]
74063#[target_feature(enable = "neon")]
74064#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74065#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74066#[cfg_attr(
74067 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74068 assert_instr(cmtst)
74069)]
74070#[cfg_attr(
74071 not(target_arch = "arm"),
74072 stable(feature = "neon_intrinsics", since = "1.59.0")
74073)]
74074#[cfg_attr(
74075 target_arch = "arm",
74076 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74077)]
74078pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
74079 unsafe {
74080 let c: int32x4_t = simd_and(a, b);
74081 let d: i32x4 = i32x4::new(0, 0, 0, 0);
74082 simd_ne(c, transmute(d))
74083 }
74084}
74085#[doc = "Signed compare bitwise Test bits nonzero"]
74086#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"]
74087#[inline]
74088#[target_feature(enable = "neon")]
74089#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74090#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74091#[cfg_attr(
74092 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74093 assert_instr(cmtst)
74094)]
74095#[cfg_attr(
74096 not(target_arch = "arm"),
74097 stable(feature = "neon_intrinsics", since = "1.59.0")
74098)]
74099#[cfg_attr(
74100 target_arch = "arm",
74101 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74102)]
74103pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
74104 unsafe {
74105 let c: poly8x8_t = simd_and(a, b);
74106 let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74107 simd_ne(c, transmute(d))
74108 }
74109}
74110#[doc = "Signed compare bitwise Test bits nonzero"]
74111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"]
74112#[inline]
74113#[target_feature(enable = "neon")]
74114#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74115#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74116#[cfg_attr(
74117 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74118 assert_instr(cmtst)
74119)]
74120#[cfg_attr(
74121 not(target_arch = "arm"),
74122 stable(feature = "neon_intrinsics", since = "1.59.0")
74123)]
74124#[cfg_attr(
74125 target_arch = "arm",
74126 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74127)]
74128pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
74129 unsafe {
74130 let c: poly8x16_t = simd_and(a, b);
74131 let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
74132 simd_ne(c, transmute(d))
74133 }
74134}
74135#[doc = "Signed compare bitwise Test bits nonzero"]
74136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"]
74137#[inline]
74138#[target_feature(enable = "neon")]
74139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74140#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74141#[cfg_attr(
74142 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74143 assert_instr(cmtst)
74144)]
74145#[cfg_attr(
74146 not(target_arch = "arm"),
74147 stable(feature = "neon_intrinsics", since = "1.59.0")
74148)]
74149#[cfg_attr(
74150 target_arch = "arm",
74151 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74152)]
74153pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t {
74154 unsafe {
74155 let c: poly16x4_t = simd_and(a, b);
74156 let d: i16x4 = i16x4::new(0, 0, 0, 0);
74157 simd_ne(c, transmute(d))
74158 }
74159}
74160#[doc = "Signed compare bitwise Test bits nonzero"]
74161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"]
74162#[inline]
74163#[target_feature(enable = "neon")]
74164#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74165#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74166#[cfg_attr(
74167 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74168 assert_instr(cmtst)
74169)]
74170#[cfg_attr(
74171 not(target_arch = "arm"),
74172 stable(feature = "neon_intrinsics", since = "1.59.0")
74173)]
74174#[cfg_attr(
74175 target_arch = "arm",
74176 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74177)]
74178pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t {
74179 unsafe {
74180 let c: poly16x8_t = simd_and(a, b);
74181 let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74182 simd_ne(c, transmute(d))
74183 }
74184}
74185#[doc = "Unsigned compare bitwise Test bits nonzero"]
74186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"]
74187#[inline]
74188#[target_feature(enable = "neon")]
74189#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74190#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74191#[cfg_attr(
74192 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74193 assert_instr(cmtst)
74194)]
74195#[cfg_attr(
74196 not(target_arch = "arm"),
74197 stable(feature = "neon_intrinsics", since = "1.59.0")
74198)]
74199#[cfg_attr(
74200 target_arch = "arm",
74201 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74202)]
74203pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
74204 unsafe {
74205 let c: uint8x8_t = simd_and(a, b);
74206 let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74207 simd_ne(c, transmute(d))
74208 }
74209}
74210#[doc = "Unsigned compare bitwise Test bits nonzero"]
74211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"]
74212#[inline]
74213#[target_feature(enable = "neon")]
74214#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74215#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74216#[cfg_attr(
74217 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74218 assert_instr(cmtst)
74219)]
74220#[cfg_attr(
74221 not(target_arch = "arm"),
74222 stable(feature = "neon_intrinsics", since = "1.59.0")
74223)]
74224#[cfg_attr(
74225 target_arch = "arm",
74226 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74227)]
74228pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
74229 unsafe {
74230 let c: uint8x16_t = simd_and(a, b);
74231 let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
74232 simd_ne(c, transmute(d))
74233 }
74234}
74235#[doc = "Unsigned compare bitwise Test bits nonzero"]
74236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"]
74237#[inline]
74238#[target_feature(enable = "neon")]
74239#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74240#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74241#[cfg_attr(
74242 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74243 assert_instr(cmtst)
74244)]
74245#[cfg_attr(
74246 not(target_arch = "arm"),
74247 stable(feature = "neon_intrinsics", since = "1.59.0")
74248)]
74249#[cfg_attr(
74250 target_arch = "arm",
74251 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74252)]
74253pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
74254 unsafe {
74255 let c: uint16x4_t = simd_and(a, b);
74256 let d: u16x4 = u16x4::new(0, 0, 0, 0);
74257 simd_ne(c, transmute(d))
74258 }
74259}
74260#[doc = "Unsigned compare bitwise Test bits nonzero"]
74261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"]
74262#[inline]
74263#[target_feature(enable = "neon")]
74264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74266#[cfg_attr(
74267 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74268 assert_instr(cmtst)
74269)]
74270#[cfg_attr(
74271 not(target_arch = "arm"),
74272 stable(feature = "neon_intrinsics", since = "1.59.0")
74273)]
74274#[cfg_attr(
74275 target_arch = "arm",
74276 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74277)]
74278pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
74279 unsafe {
74280 let c: uint16x8_t = simd_and(a, b);
74281 let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
74282 simd_ne(c, transmute(d))
74283 }
74284}
74285#[doc = "Unsigned compare bitwise Test bits nonzero"]
74286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"]
74287#[inline]
74288#[target_feature(enable = "neon")]
74289#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74290#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74291#[cfg_attr(
74292 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74293 assert_instr(cmtst)
74294)]
74295#[cfg_attr(
74296 not(target_arch = "arm"),
74297 stable(feature = "neon_intrinsics", since = "1.59.0")
74298)]
74299#[cfg_attr(
74300 target_arch = "arm",
74301 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74302)]
74303pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
74304 unsafe {
74305 let c: uint32x2_t = simd_and(a, b);
74306 let d: u32x2 = u32x2::new(0, 0);
74307 simd_ne(c, transmute(d))
74308 }
74309}
74310#[doc = "Unsigned compare bitwise Test bits nonzero"]
74311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"]
74312#[inline]
74313#[target_feature(enable = "neon")]
74314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74315#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
74316#[cfg_attr(
74317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74318 assert_instr(cmtst)
74319)]
74320#[cfg_attr(
74321 not(target_arch = "arm"),
74322 stable(feature = "neon_intrinsics", since = "1.59.0")
74323)]
74324#[cfg_attr(
74325 target_arch = "arm",
74326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74327)]
74328pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
74329 unsafe {
74330 let c: uint32x4_t = simd_and(a, b);
74331 let d: u32x4 = u32x4::new(0, 0, 0, 0);
74332 simd_ne(c, transmute(d))
74333 }
74334}
74335#[doc = "Dot product index form with unsigned and signed integers"]
74336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
74337#[inline]
74338#[target_feature(enable = "neon,i8mm")]
74339#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
74341#[cfg_attr(
74342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74343 assert_instr(usdot, LANE = 0)
74344)]
74345#[rustc_legacy_const_generics(3)]
74346#[cfg_attr(
74347 not(target_arch = "arm"),
74348 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74349)]
74350#[cfg_attr(
74351 target_arch = "arm",
74352 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74353)]
74354pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
74355 static_assert_uimm_bits!(LANE, 1);
74356 unsafe {
74357 let c: int32x2_t = transmute(c);
74358 let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
74359 vusdot_s32(a, b, transmute(c))
74360 }
74361}
74362#[doc = "Dot product index form with unsigned and signed integers"]
74363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
74364#[inline]
74365#[target_feature(enable = "neon,i8mm")]
74366#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74367#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
74368#[cfg_attr(
74369 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74370 assert_instr(usdot, LANE = 0)
74371)]
74372#[rustc_legacy_const_generics(3)]
74373#[cfg_attr(
74374 not(target_arch = "arm"),
74375 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74376)]
74377#[cfg_attr(
74378 target_arch = "arm",
74379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74380)]
74381pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
74382 static_assert_uimm_bits!(LANE, 1);
74383 unsafe {
74384 let c: int32x2_t = transmute(c);
74385 let c: int32x4_t =
74386 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
74387 vusdotq_s32(a, b, transmute(c))
74388 }
74389}
74390#[doc = "Dot product vector form with unsigned and signed integers"]
74391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"]
74392#[inline]
74393#[target_feature(enable = "neon,i8mm")]
74394#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74395#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
74396#[cfg_attr(
74397 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74398 assert_instr(usdot)
74399)]
74400#[cfg_attr(
74401 not(target_arch = "arm"),
74402 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74403)]
74404#[cfg_attr(
74405 target_arch = "arm",
74406 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74407)]
74408pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
74409 unsafe extern "unadjusted" {
74410 #[cfg_attr(
74411 any(target_arch = "aarch64", target_arch = "arm64ec"),
74412 link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8"
74413 )]
74414 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")]
74415 fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t;
74416 }
74417 unsafe { _vusdot_s32(a, b, c) }
74418}
74419#[doc = "Dot product vector form with unsigned and signed integers"]
74420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"]
74421#[inline]
74422#[target_feature(enable = "neon,i8mm")]
74423#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74424#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
74425#[cfg_attr(
74426 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74427 assert_instr(usdot)
74428)]
74429#[cfg_attr(
74430 not(target_arch = "arm"),
74431 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74432)]
74433#[cfg_attr(
74434 target_arch = "arm",
74435 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74436)]
74437pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
74438 unsafe extern "unadjusted" {
74439 #[cfg_attr(
74440 any(target_arch = "aarch64", target_arch = "arm64ec"),
74441 link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8"
74442 )]
74443 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")]
74444 fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t;
74445 }
74446 unsafe { _vusdotq_s32(a, b, c) }
74447}
74448#[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"]
74449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"]
74450#[inline]
74451#[target_feature(enable = "neon,i8mm")]
74452#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74453#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
74454#[cfg_attr(
74455 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74456 assert_instr(usmmla)
74457)]
74458#[cfg_attr(
74459 not(target_arch = "arm"),
74460 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74461)]
74462#[cfg_attr(
74463 target_arch = "arm",
74464 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74465)]
74466pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
74467 unsafe extern "unadjusted" {
74468 #[cfg_attr(
74469 any(target_arch = "aarch64", target_arch = "arm64ec"),
74470 link_name = "llvm.aarch64.neon.usmmla.v4i32.v16i8"
74471 )]
74472 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usmmla.v4i32.v16i8")]
74473 fn _vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t;
74474 }
74475 unsafe { _vusmmlaq_s32(a, b, c) }
74476}
74477#[doc = "Unzip vectors"]
74478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"]
74479#[inline]
74480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74482#[cfg_attr(
74483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74484 assert_instr(uzp)
74485)]
74486#[target_feature(enable = "neon,fp16")]
74487#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74488pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
74489 unsafe {
74490 let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74491 let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74492 transmute((a0, b0))
74493 }
74494}
74495#[doc = "Unzip vectors"]
74496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"]
74497#[inline]
74498#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74499#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74500#[cfg_attr(
74501 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74502 assert_instr(uzp)
74503)]
74504#[target_feature(enable = "neon,fp16")]
74505#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74506pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
74507 unsafe {
74508 let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74509 let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74510 transmute((a0, b0))
74511 }
74512}
74513#[doc = "Unzip vectors"]
74514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"]
74515#[inline]
74516#[target_feature(enable = "neon")]
74517#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74518#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74519#[cfg_attr(
74520 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74521 assert_instr(zip)
74522)]
74523#[cfg_attr(
74524 not(target_arch = "arm"),
74525 stable(feature = "neon_intrinsics", since = "1.59.0")
74526)]
74527#[cfg_attr(
74528 target_arch = "arm",
74529 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74530)]
74531pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
74532 unsafe {
74533 let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]);
74534 let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]);
74535 transmute((a0, b0))
74536 }
74537}
74538#[doc = "Unzip vectors"]
74539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"]
74540#[inline]
74541#[target_feature(enable = "neon")]
74542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74544#[cfg_attr(
74545 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74546 assert_instr(zip)
74547)]
74548#[cfg_attr(
74549 not(target_arch = "arm"),
74550 stable(feature = "neon_intrinsics", since = "1.59.0")
74551)]
74552#[cfg_attr(
74553 target_arch = "arm",
74554 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74555)]
74556pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
74557 unsafe {
74558 let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]);
74559 let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]);
74560 transmute((a0, b0))
74561 }
74562}
74563#[doc = "Unzip vectors"]
74564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"]
74565#[inline]
74566#[target_feature(enable = "neon")]
74567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74568#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74569#[cfg_attr(
74570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74571 assert_instr(zip)
74572)]
74573#[cfg_attr(
74574 not(target_arch = "arm"),
74575 stable(feature = "neon_intrinsics", since = "1.59.0")
74576)]
74577#[cfg_attr(
74578 target_arch = "arm",
74579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74580)]
74581pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
74582 unsafe {
74583 let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
74584 let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
74585 transmute((a0, b0))
74586 }
74587}
74588#[doc = "Unzip vectors"]
74589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"]
74590#[inline]
74591#[target_feature(enable = "neon")]
74592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74594#[cfg_attr(
74595 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74596 assert_instr(uzp)
74597)]
74598#[cfg_attr(
74599 not(target_arch = "arm"),
74600 stable(feature = "neon_intrinsics", since = "1.59.0")
74601)]
74602#[cfg_attr(
74603 target_arch = "arm",
74604 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74605)]
74606pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
74607 unsafe {
74608 let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74609 let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74610 transmute((a0, b0))
74611 }
74612}
74613#[doc = "Unzip vectors"]
74614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"]
74615#[inline]
74616#[target_feature(enable = "neon")]
74617#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74618#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74619#[cfg_attr(
74620 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74621 assert_instr(uzp)
74622)]
74623#[cfg_attr(
74624 not(target_arch = "arm"),
74625 stable(feature = "neon_intrinsics", since = "1.59.0")
74626)]
74627#[cfg_attr(
74628 target_arch = "arm",
74629 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74630)]
74631pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
74632 unsafe {
74633 let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74634 let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74635 transmute((a0, b0))
74636 }
74637}
74638#[doc = "Unzip vectors"]
74639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"]
74640#[inline]
74641#[target_feature(enable = "neon")]
74642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74643#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74644#[cfg_attr(
74645 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74646 assert_instr(uzp)
74647)]
74648#[cfg_attr(
74649 not(target_arch = "arm"),
74650 stable(feature = "neon_intrinsics", since = "1.59.0")
74651)]
74652#[cfg_attr(
74653 target_arch = "arm",
74654 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74655)]
74656pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
74657 unsafe {
74658 let a0: int8x16_t = simd_shuffle!(
74659 a,
74660 b,
74661 [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74662 );
74663 let b0: int8x16_t = simd_shuffle!(
74664 a,
74665 b,
74666 [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74667 );
74668 transmute((a0, b0))
74669 }
74670}
74671#[doc = "Unzip vectors"]
74672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"]
74673#[inline]
74674#[target_feature(enable = "neon")]
74675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74676#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74677#[cfg_attr(
74678 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74679 assert_instr(uzp)
74680)]
74681#[cfg_attr(
74682 not(target_arch = "arm"),
74683 stable(feature = "neon_intrinsics", since = "1.59.0")
74684)]
74685#[cfg_attr(
74686 target_arch = "arm",
74687 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74688)]
74689pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
74690 unsafe {
74691 let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74692 let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74693 transmute((a0, b0))
74694 }
74695}
74696#[doc = "Unzip vectors"]
74697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"]
74698#[inline]
74699#[target_feature(enable = "neon")]
74700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74701#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74702#[cfg_attr(
74703 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74704 assert_instr(uzp)
74705)]
74706#[cfg_attr(
74707 not(target_arch = "arm"),
74708 stable(feature = "neon_intrinsics", since = "1.59.0")
74709)]
74710#[cfg_attr(
74711 target_arch = "arm",
74712 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74713)]
74714pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
74715 unsafe {
74716 let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74717 let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74718 transmute((a0, b0))
74719 }
74720}
74721#[doc = "Unzip vectors"]
74722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"]
74723#[inline]
74724#[target_feature(enable = "neon")]
74725#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74726#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74727#[cfg_attr(
74728 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74729 assert_instr(uzp)
74730)]
74731#[cfg_attr(
74732 not(target_arch = "arm"),
74733 stable(feature = "neon_intrinsics", since = "1.59.0")
74734)]
74735#[cfg_attr(
74736 target_arch = "arm",
74737 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74738)]
74739pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
74740 unsafe {
74741 let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74742 let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74743 transmute((a0, b0))
74744 }
74745}
74746#[doc = "Unzip vectors"]
74747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"]
74748#[inline]
74749#[target_feature(enable = "neon")]
74750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74751#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74752#[cfg_attr(
74753 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74754 assert_instr(uzp)
74755)]
74756#[cfg_attr(
74757 not(target_arch = "arm"),
74758 stable(feature = "neon_intrinsics", since = "1.59.0")
74759)]
74760#[cfg_attr(
74761 target_arch = "arm",
74762 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74763)]
74764pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
74765 unsafe {
74766 let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74767 let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74768 transmute((a0, b0))
74769 }
74770}
74771#[doc = "Unzip vectors"]
74772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"]
74773#[inline]
74774#[target_feature(enable = "neon")]
74775#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74776#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74777#[cfg_attr(
74778 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74779 assert_instr(uzp)
74780)]
74781#[cfg_attr(
74782 not(target_arch = "arm"),
74783 stable(feature = "neon_intrinsics", since = "1.59.0")
74784)]
74785#[cfg_attr(
74786 target_arch = "arm",
74787 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74788)]
74789pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
74790 unsafe {
74791 let a0: uint8x16_t = simd_shuffle!(
74792 a,
74793 b,
74794 [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74795 );
74796 let b0: uint8x16_t = simd_shuffle!(
74797 a,
74798 b,
74799 [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74800 );
74801 transmute((a0, b0))
74802 }
74803}
74804#[doc = "Unzip vectors"]
74805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"]
74806#[inline]
74807#[target_feature(enable = "neon")]
74808#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74809#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74810#[cfg_attr(
74811 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74812 assert_instr(uzp)
74813)]
74814#[cfg_attr(
74815 not(target_arch = "arm"),
74816 stable(feature = "neon_intrinsics", since = "1.59.0")
74817)]
74818#[cfg_attr(
74819 target_arch = "arm",
74820 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74821)]
74822pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
74823 unsafe {
74824 let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74825 let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74826 transmute((a0, b0))
74827 }
74828}
74829#[doc = "Unzip vectors"]
74830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"]
74831#[inline]
74832#[target_feature(enable = "neon")]
74833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74834#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74835#[cfg_attr(
74836 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74837 assert_instr(uzp)
74838)]
74839#[cfg_attr(
74840 not(target_arch = "arm"),
74841 stable(feature = "neon_intrinsics", since = "1.59.0")
74842)]
74843#[cfg_attr(
74844 target_arch = "arm",
74845 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74846)]
74847pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
74848 unsafe {
74849 let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74850 let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74851 transmute((a0, b0))
74852 }
74853}
74854#[doc = "Unzip vectors"]
74855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"]
74856#[inline]
74857#[target_feature(enable = "neon")]
74858#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74859#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74860#[cfg_attr(
74861 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74862 assert_instr(uzp)
74863)]
74864#[cfg_attr(
74865 not(target_arch = "arm"),
74866 stable(feature = "neon_intrinsics", since = "1.59.0")
74867)]
74868#[cfg_attr(
74869 target_arch = "arm",
74870 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74871)]
74872pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
74873 unsafe {
74874 let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74875 let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74876 transmute((a0, b0))
74877 }
74878}
74879#[doc = "Unzip vectors"]
74880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"]
74881#[inline]
74882#[target_feature(enable = "neon")]
74883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74885#[cfg_attr(
74886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74887 assert_instr(uzp)
74888)]
74889#[cfg_attr(
74890 not(target_arch = "arm"),
74891 stable(feature = "neon_intrinsics", since = "1.59.0")
74892)]
74893#[cfg_attr(
74894 target_arch = "arm",
74895 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74896)]
74897pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
74898 unsafe {
74899 let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74900 let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74901 transmute((a0, b0))
74902 }
74903}
74904#[doc = "Unzip vectors"]
74905#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"]
74906#[inline]
74907#[target_feature(enable = "neon")]
74908#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74909#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74910#[cfg_attr(
74911 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74912 assert_instr(uzp)
74913)]
74914#[cfg_attr(
74915 not(target_arch = "arm"),
74916 stable(feature = "neon_intrinsics", since = "1.59.0")
74917)]
74918#[cfg_attr(
74919 target_arch = "arm",
74920 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74921)]
74922pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
74923 unsafe {
74924 let a0: poly8x16_t = simd_shuffle!(
74925 a,
74926 b,
74927 [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74928 );
74929 let b0: poly8x16_t = simd_shuffle!(
74930 a,
74931 b,
74932 [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74933 );
74934 transmute((a0, b0))
74935 }
74936}
74937#[doc = "Unzip vectors"]
74938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"]
74939#[inline]
74940#[target_feature(enable = "neon")]
74941#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74942#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74943#[cfg_attr(
74944 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74945 assert_instr(uzp)
74946)]
74947#[cfg_attr(
74948 not(target_arch = "arm"),
74949 stable(feature = "neon_intrinsics", since = "1.59.0")
74950)]
74951#[cfg_attr(
74952 target_arch = "arm",
74953 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74954)]
74955pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
74956 unsafe {
74957 let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74958 let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74959 transmute((a0, b0))
74960 }
74961}
74962#[doc = "Unzip vectors"]
74963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"]
74964#[inline]
74965#[target_feature(enable = "neon")]
74966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74967#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74968#[cfg_attr(
74969 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74970 assert_instr(uzp)
74971)]
74972#[cfg_attr(
74973 not(target_arch = "arm"),
74974 stable(feature = "neon_intrinsics", since = "1.59.0")
74975)]
74976#[cfg_attr(
74977 target_arch = "arm",
74978 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74979)]
74980pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
74981 unsafe {
74982 let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74983 let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74984 transmute((a0, b0))
74985 }
74986}
74987#[doc = "Zip vectors"]
74988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"]
74989#[inline]
74990#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74991#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
74992#[cfg_attr(
74993 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74994 assert_instr(zip)
74995)]
74996#[target_feature(enable = "neon,fp16")]
74997#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74998pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
74999 unsafe {
75000 let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75001 let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75002 transmute((a0, b0))
75003 }
75004}
75005#[doc = "Zip vectors"]
75006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"]
75007#[inline]
75008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75009#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
75010#[cfg_attr(
75011 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75012 assert_instr(zip)
75013)]
75014#[target_feature(enable = "neon,fp16")]
75015#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
75016pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
75017 unsafe {
75018 let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75019 let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75020 transmute((a0, b0))
75021 }
75022}
75023#[doc = "Zip vectors"]
75024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"]
75025#[inline]
75026#[target_feature(enable = "neon")]
75027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
75029#[cfg_attr(
75030 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75031 assert_instr(zip)
75032)]
75033#[cfg_attr(
75034 not(target_arch = "arm"),
75035 stable(feature = "neon_intrinsics", since = "1.59.0")
75036)]
75037#[cfg_attr(
75038 target_arch = "arm",
75039 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75040)]
75041pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
75042 unsafe {
75043 let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]);
75044 let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]);
75045 transmute((a0, b0))
75046 }
75047}
75048#[doc = "Zip vectors"]
75049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"]
75050#[inline]
75051#[target_feature(enable = "neon")]
75052#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75053#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
75054#[cfg_attr(
75055 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75056 assert_instr(zip)
75057)]
75058#[cfg_attr(
75059 not(target_arch = "arm"),
75060 stable(feature = "neon_intrinsics", since = "1.59.0")
75061)]
75062#[cfg_attr(
75063 target_arch = "arm",
75064 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75065)]
75066pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
75067 unsafe {
75068 let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]);
75069 let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]);
75070 transmute((a0, b0))
75071 }
75072}
75073#[doc = "Zip vectors"]
75074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"]
75075#[inline]
75076#[target_feature(enable = "neon")]
75077#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75078#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
75079#[cfg_attr(
75080 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75081 assert_instr(zip)
75082)]
75083#[cfg_attr(
75084 not(target_arch = "arm"),
75085 stable(feature = "neon_intrinsics", since = "1.59.0")
75086)]
75087#[cfg_attr(
75088 target_arch = "arm",
75089 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75090)]
75091pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
75092 unsafe {
75093 let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
75094 let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
75095 transmute((a0, b0))
75096 }
75097}
75098#[doc = "Zip vectors"]
75099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"]
75100#[inline]
75101#[target_feature(enable = "neon")]
75102#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75103#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75104#[cfg_attr(
75105 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75106 assert_instr(zip)
75107)]
75108#[cfg_attr(
75109 not(target_arch = "arm"),
75110 stable(feature = "neon_intrinsics", since = "1.59.0")
75111)]
75112#[cfg_attr(
75113 target_arch = "arm",
75114 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75115)]
75116pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
75117 unsafe {
75118 let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75119 let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75120 transmute((a0, b0))
75121 }
75122}
75123#[doc = "Zip vectors"]
75124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"]
75125#[inline]
75126#[target_feature(enable = "neon")]
75127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75128#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75129#[cfg_attr(
75130 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75131 assert_instr(zip)
75132)]
75133#[cfg_attr(
75134 not(target_arch = "arm"),
75135 stable(feature = "neon_intrinsics", since = "1.59.0")
75136)]
75137#[cfg_attr(
75138 target_arch = "arm",
75139 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75140)]
75141pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
75142 unsafe {
75143 let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75144 let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75145 transmute((a0, b0))
75146 }
75147}
75148#[doc = "Zip vectors"]
75149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"]
75150#[inline]
75151#[target_feature(enable = "neon")]
75152#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75153#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75154#[cfg_attr(
75155 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75156 assert_instr(zip)
75157)]
75158#[cfg_attr(
75159 not(target_arch = "arm"),
75160 stable(feature = "neon_intrinsics", since = "1.59.0")
75161)]
75162#[cfg_attr(
75163 target_arch = "arm",
75164 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75165)]
75166pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
75167 unsafe {
75168 let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75169 let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75170 transmute((a0, b0))
75171 }
75172}
75173#[doc = "Zip vectors"]
75174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"]
75175#[inline]
75176#[target_feature(enable = "neon")]
75177#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75178#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75179#[cfg_attr(
75180 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75181 assert_instr(zip)
75182)]
75183#[cfg_attr(
75184 not(target_arch = "arm"),
75185 stable(feature = "neon_intrinsics", since = "1.59.0")
75186)]
75187#[cfg_attr(
75188 target_arch = "arm",
75189 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75190)]
75191pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
75192 unsafe {
75193 let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75194 let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75195 transmute((a0, b0))
75196 }
75197}
75198#[doc = "Zip vectors"]
75199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"]
75200#[inline]
75201#[target_feature(enable = "neon")]
75202#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75203#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75204#[cfg_attr(
75205 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75206 assert_instr(zip)
75207)]
75208#[cfg_attr(
75209 not(target_arch = "arm"),
75210 stable(feature = "neon_intrinsics", since = "1.59.0")
75211)]
75212#[cfg_attr(
75213 target_arch = "arm",
75214 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75215)]
75216pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
75217 unsafe {
75218 let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75219 let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75220 transmute((a0, b0))
75221 }
75222}
75223#[doc = "Zip vectors"]
75224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"]
75225#[inline]
75226#[target_feature(enable = "neon")]
75227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
75229#[cfg_attr(
75230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75231 assert_instr(zip)
75232)]
75233#[cfg_attr(
75234 not(target_arch = "arm"),
75235 stable(feature = "neon_intrinsics", since = "1.59.0")
75236)]
75237#[cfg_attr(
75238 target_arch = "arm",
75239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75240)]
75241pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
75242 unsafe {
75243 let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75244 let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75245 transmute((a0, b0))
75246 }
75247}
75248#[doc = "Zip vectors"]
75249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"]
75250#[inline]
75251#[target_feature(enable = "neon")]
75252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75254#[cfg_attr(
75255 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75256 assert_instr(zip)
75257)]
75258#[cfg_attr(
75259 not(target_arch = "arm"),
75260 stable(feature = "neon_intrinsics", since = "1.59.0")
75261)]
75262#[cfg_attr(
75263 target_arch = "arm",
75264 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75265)]
75266pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
75267 unsafe {
75268 let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75269 let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75270 transmute((a0, b0))
75271 }
75272}
75273#[doc = "Zip vectors"]
75274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"]
75275#[inline]
75276#[target_feature(enable = "neon")]
75277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75278#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75279#[cfg_attr(
75280 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75281 assert_instr(zip)
75282)]
75283#[cfg_attr(
75284 not(target_arch = "arm"),
75285 stable(feature = "neon_intrinsics", since = "1.59.0")
75286)]
75287#[cfg_attr(
75288 target_arch = "arm",
75289 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75290)]
75291pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
75292 unsafe {
75293 let a0: int8x16_t = simd_shuffle!(
75294 a,
75295 b,
75296 [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75297 );
75298 let b0: int8x16_t = simd_shuffle!(
75299 a,
75300 b,
75301 [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75302 );
75303 transmute((a0, b0))
75304 }
75305}
75306#[doc = "Zip vectors"]
75307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"]
75308#[inline]
75309#[target_feature(enable = "neon")]
75310#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75311#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75312#[cfg_attr(
75313 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75314 assert_instr(zip)
75315)]
75316#[cfg_attr(
75317 not(target_arch = "arm"),
75318 stable(feature = "neon_intrinsics", since = "1.59.0")
75319)]
75320#[cfg_attr(
75321 target_arch = "arm",
75322 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75323)]
75324pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
75325 unsafe {
75326 let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75327 let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75328 transmute((a0, b0))
75329 }
75330}
75331#[doc = "Zip vectors"]
75332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"]
75333#[inline]
75334#[target_feature(enable = "neon")]
75335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75336#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75337#[cfg_attr(
75338 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75339 assert_instr(zip)
75340)]
75341#[cfg_attr(
75342 not(target_arch = "arm"),
75343 stable(feature = "neon_intrinsics", since = "1.59.0")
75344)]
75345#[cfg_attr(
75346 target_arch = "arm",
75347 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75348)]
75349pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
75350 unsafe {
75351 let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75352 let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75353 transmute((a0, b0))
75354 }
75355}
75356#[doc = "Zip vectors"]
75357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"]
75358#[inline]
75359#[target_feature(enable = "neon")]
75360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75361#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75362#[cfg_attr(
75363 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75364 assert_instr(zip)
75365)]
75366#[cfg_attr(
75367 not(target_arch = "arm"),
75368 stable(feature = "neon_intrinsics", since = "1.59.0")
75369)]
75370#[cfg_attr(
75371 target_arch = "arm",
75372 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75373)]
75374pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
75375 unsafe {
75376 let a0: uint8x16_t = simd_shuffle!(
75377 a,
75378 b,
75379 [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75380 );
75381 let b0: uint8x16_t = simd_shuffle!(
75382 a,
75383 b,
75384 [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75385 );
75386 transmute((a0, b0))
75387 }
75388}
75389#[doc = "Zip vectors"]
75390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"]
75391#[inline]
75392#[target_feature(enable = "neon")]
75393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75395#[cfg_attr(
75396 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75397 assert_instr(zip)
75398)]
75399#[cfg_attr(
75400 not(target_arch = "arm"),
75401 stable(feature = "neon_intrinsics", since = "1.59.0")
75402)]
75403#[cfg_attr(
75404 target_arch = "arm",
75405 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75406)]
75407pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
75408 unsafe {
75409 let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75410 let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75411 transmute((a0, b0))
75412 }
75413}
75414#[doc = "Zip vectors"]
75415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"]
75416#[inline]
75417#[target_feature(enable = "neon")]
75418#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75419#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75420#[cfg_attr(
75421 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75422 assert_instr(zip)
75423)]
75424#[cfg_attr(
75425 not(target_arch = "arm"),
75426 stable(feature = "neon_intrinsics", since = "1.59.0")
75427)]
75428#[cfg_attr(
75429 target_arch = "arm",
75430 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75431)]
75432pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
75433 unsafe {
75434 let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75435 let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75436 transmute((a0, b0))
75437 }
75438}
75439#[doc = "Zip vectors"]
75440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"]
75441#[inline]
75442#[target_feature(enable = "neon")]
75443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75445#[cfg_attr(
75446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75447 assert_instr(zip)
75448)]
75449#[cfg_attr(
75450 not(target_arch = "arm"),
75451 stable(feature = "neon_intrinsics", since = "1.59.0")
75452)]
75453#[cfg_attr(
75454 target_arch = "arm",
75455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75456)]
75457pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
75458 unsafe {
75459 let a0: poly8x16_t = simd_shuffle!(
75460 a,
75461 b,
75462 [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75463 );
75464 let b0: poly8x16_t = simd_shuffle!(
75465 a,
75466 b,
75467 [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75468 );
75469 transmute((a0, b0))
75470 }
75471}
75472#[doc = "Zip vectors"]
75473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"]
75474#[inline]
75475#[target_feature(enable = "neon")]
75476#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75477#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75478#[cfg_attr(
75479 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75480 assert_instr(zip)
75481)]
75482#[cfg_attr(
75483 not(target_arch = "arm"),
75484 stable(feature = "neon_intrinsics", since = "1.59.0")
75485)]
75486#[cfg_attr(
75487 target_arch = "arm",
75488 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75489)]
75490pub fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
75491 unsafe {
75492 let a0: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75493 let b0: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75494 transmute((a0, b0))
75495 }
75496}